* [PATCH] drm/i915: Use GGTT batchbuffer selector
@ 2014-09-10 9:26 Chris Wilson
2014-09-10 9:46 ` Chris Wilson
2014-09-10 10:30 ` Ville Syrjälä
0 siblings, 2 replies; 8+ messages in thread
From: Chris Wilson @ 2014-09-10 9:26 UTC (permalink / raw)
To: intel-gfx
gen6 and earlier conflate address space selection (ppgtt vs ggtt) with
the security bit (i.e. only privileged batches were allowed to run from
ggtt). From Haswell onwards, you are able to select the security bit
separate from the address space - and we always requested to use ppgtt.
This breaks the golden render state batch execution as that is only
present in the global GTT and so we need to disable the use of the ppgtt
selector bit, or else we hang immediately upon boot and thence after
every GPU reset...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++--
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 1a0611bb576b..8ff448dc8be4 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1260,7 +1260,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
if (!file->is_master || !capable(CAP_SYS_ADMIN))
return -EPERM;
- flags |= I915_DISPATCH_SECURE;
+ flags |= I915_DISPATCH_SECURE | I915_DISPATCH_GGTT;
}
if (args->flags & I915_EXEC_IS_PINNED)
flags |= I915_DISPATCH_PINNED;
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index a9a62d75aa57..a158d610720b 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -165,7 +165,7 @@ int i915_gem_render_state_init(struct intel_engine_cs *ring)
ret = ring->dispatch_execbuffer(ring,
so.ggtt_offset,
so.rodata->batch_items * 4,
- I915_DISPATCH_SECURE);
+ I915_DISPATCH_GGTT);
if (ret)
goto out;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 109de2eeb9a8..d053819407da 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2174,7 +2174,7 @@ gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
u64 offset, u32 len,
unsigned flags)
{
- bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
+ bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_GGTT);
int ret;
ret = intel_ring_begin(ring, 4);
@@ -2203,7 +2203,8 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
return ret;
intel_ring_emit(ring,
- MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
+ MI_BATCH_BUFFER_START |
+ (flags & I915_DISPATCH_GGTT ? 0 : MI_BATCH_PPGTT_HSW) |
(flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
/* bit0-7 is the length on GEN6+ */
intel_ring_emit(ring, offset);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 96479c89f4bd..755585a6fcc7 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -169,8 +169,9 @@ struct intel_engine_cs {
int (*dispatch_execbuffer)(struct intel_engine_cs *ring,
u64 offset, u32 length,
unsigned flags);
-#define I915_DISPATCH_SECURE 0x1
-#define I915_DISPATCH_PINNED 0x2
+#define I915_DISPATCH_GGTT 0x1
+#define I915_DISPATCH_SECURE 0x2
+#define I915_DISPATCH_PINNED 0x4
void (*cleanup)(struct intel_engine_cs *ring);
/* GEN8 signal/wait table - never trust comments!
--
2.1.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: Use GGTT batchbuffer selector
2014-09-10 9:26 [PATCH] drm/i915: Use GGTT batchbuffer selector Chris Wilson
@ 2014-09-10 9:46 ` Chris Wilson
2014-09-10 10:30 ` Ville Syrjälä
1 sibling, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2014-09-10 9:46 UTC (permalink / raw)
To: intel-gfx
On Wed, Sep 10, 2014 at 10:26:54AM +0100, Chris Wilson wrote:
> gen6 and earlier conflate address space selection (ppgtt vs ggtt) with
> the security bit (i.e. only privileged batches were allowed to run from
> ggtt). From Haswell onwards, you are able to select the security bit
> separate from the address space - and we always requested to use ppgtt.
> This breaks the golden render state batch execution as that is only
> present in the global GTT and so we need to disable the use of the ppgtt
> selector bit, or else we hang immediately upon boot and thence after
> every GPU reset...
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
> drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++--
> 4 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 1a0611bb576b..8ff448dc8be4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1260,7 +1260,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
> if (!file->is_master || !capable(CAP_SYS_ADMIN))
> return -EPERM;
>
> - flags |= I915_DISPATCH_SECURE;
> + flags |= I915_DISPATCH_SECURE | I915_DISPATCH_GGTT;
> }
> if (args->flags & I915_EXEC_IS_PINNED)
> flags |= I915_DISPATCH_PINNED;
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index a9a62d75aa57..a158d610720b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -165,7 +165,7 @@ int i915_gem_render_state_init(struct intel_engine_cs *ring)
> ret = ring->dispatch_execbuffer(ring,
> so.ggtt_offset,
> so.rodata->batch_items * 4,
> - I915_DISPATCH_SECURE);
> + I915_DISPATCH_GGTT);
> if (ret)
> goto out;
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 109de2eeb9a8..d053819407da 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2174,7 +2174,7 @@ gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
> u64 offset, u32 len,
> unsigned flags)
> {
> - bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
> + bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_GGTT);
> int ret;
>
> ret = intel_ring_begin(ring, 4);
> @@ -2203,7 +2203,8 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
> return ret;
>
> intel_ring_emit(ring,
> - MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
> + MI_BATCH_BUFFER_START |
> + (flags & I915_DISPATCH_GGTT ? 0 : MI_BATCH_PPGTT_HSW) |
> (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
> /* bit0-7 is the length on GEN6+ */
> intel_ring_emit(ring, offset);
I thought I had also fixed up gen6 like:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0231144d5ef1..ce90f43cecd0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1761,7 +1761,7 @@ gen6_emit_batchbuffer(struct i915_gem_request *rq,
intel_ring_emit(ring,
MI_BATCH_BUFFER_START |
- (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
+ ((flags & I915_DISPATCH_SECURE | I915_DISPATCH_GTT) ? 0 : MI_BATCH_NON_SECURE_I965));
/* bit0-7 is the length on GEN6+ */
intel_ring_emit(ring, offset);
intel_ring_advance(ring);
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: Use GGTT batchbuffer selector
2014-09-10 9:26 [PATCH] drm/i915: Use GGTT batchbuffer selector Chris Wilson
2014-09-10 9:46 ` Chris Wilson
@ 2014-09-10 10:30 ` Ville Syrjälä
2014-09-10 10:50 ` Chris Wilson
2014-09-10 11:18 ` [PATCH] drm/i915: HSW always use GGTT selector for secure batches Chris Wilson
1 sibling, 2 replies; 8+ messages in thread
From: Ville Syrjälä @ 2014-09-10 10:30 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Wed, Sep 10, 2014 at 10:26:54AM +0100, Chris Wilson wrote:
> gen6 and earlier conflate address space selection (ppgtt vs ggtt) with
> the security bit (i.e. only privileged batches were allowed to run from
> ggtt). From Haswell onwards,
Not onwards unfortunately. BDW went back to the single bit approach.
> you are able to select the security bit
> separate from the address space - and we always requested to use ppgtt.
> This breaks the golden render state batch execution as that is only
> present in the global GTT and so we need to disable the use of the ppgtt
> selector bit, or else we hang immediately upon boot and thence after
> every GPU reset...
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
> drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++--
> 4 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 1a0611bb576b..8ff448dc8be4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1260,7 +1260,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
> if (!file->is_master || !capable(CAP_SYS_ADMIN))
> return -EPERM;
>
> - flags |= I915_DISPATCH_SECURE;
> + flags |= I915_DISPATCH_SECURE | I915_DISPATCH_GGTT;
> }
> if (args->flags & I915_EXEC_IS_PINNED)
> flags |= I915_DISPATCH_PINNED;
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index a9a62d75aa57..a158d610720b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -165,7 +165,7 @@ int i915_gem_render_state_init(struct intel_engine_cs *ring)
> ret = ring->dispatch_execbuffer(ring,
> so.ggtt_offset,
> so.rodata->batch_items * 4,
> - I915_DISPATCH_SECURE);
> + I915_DISPATCH_GGTT);
> if (ret)
> goto out;
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 109de2eeb9a8..d053819407da 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2174,7 +2174,7 @@ gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
> u64 offset, u32 len,
> unsigned flags)
> {
> - bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
> + bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_GGTT);
> int ret;
>
> ret = intel_ring_begin(ring, 4);
> @@ -2203,7 +2203,8 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
> return ret;
>
> intel_ring_emit(ring,
> - MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
> + MI_BATCH_BUFFER_START |
> + (flags & I915_DISPATCH_GGTT ? 0 : MI_BATCH_PPGTT_HSW) |
> (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
Do we actually want to make a distinction between GGTT and secure given
that HSW is the only one where it makes any difference? Why not just
set both GGGT and secure bits on HSW when I915_DISPATCH_SECURE is set?
> /* bit0-7 is the length on GEN6+ */
> intel_ring_emit(ring, offset);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 96479c89f4bd..755585a6fcc7 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -169,8 +169,9 @@ struct intel_engine_cs {
> int (*dispatch_execbuffer)(struct intel_engine_cs *ring,
> u64 offset, u32 length,
> unsigned flags);
> -#define I915_DISPATCH_SECURE 0x1
> -#define I915_DISPATCH_PINNED 0x2
> +#define I915_DISPATCH_GGTT 0x1
> +#define I915_DISPATCH_SECURE 0x2
> +#define I915_DISPATCH_PINNED 0x4
> void (*cleanup)(struct intel_engine_cs *ring);
>
> /* GEN8 signal/wait table - never trust comments!
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: Use GGTT batchbuffer selector
2014-09-10 10:30 ` Ville Syrjälä
@ 2014-09-10 10:50 ` Chris Wilson
2014-09-10 11:18 ` [PATCH] drm/i915: HSW always use GGTT selector for secure batches Chris Wilson
1 sibling, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2014-09-10 10:50 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Sep 10, 2014 at 01:30:45PM +0300, Ville Syrjälä wrote:
> Do we actually want to make a distinction between GGTT and secure given
> that HSW is the only one where it makes any difference? Why not just
> set both GGGT and secure bits on HSW when I915_DISPATCH_SECURE is set?
If it is only HSW, then the distinction is moot indeed.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] drm/i915: HSW always use GGTT selector for secure batches
2014-09-10 10:30 ` Ville Syrjälä
2014-09-10 10:50 ` Chris Wilson
@ 2014-09-10 11:18 ` Chris Wilson
2014-09-10 11:21 ` Chris Wilson
1 sibling, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2014-09-10 11:18 UTC (permalink / raw)
To: intel-gfx
gen6 and earlier conflate address space selection (ppgtt vs ggtt) with
the security bit (i.e. only privileged batches were allowed to run from
ggtt). From Haswell onwards, you are able to select the security bit
separate from the address space - and we always requested to use ppgtt.
This breaks the golden render state batch execution with full-ppgtt as
that is only present in the global GTT and more generally any secure
batch that is not colocated in the ppgtt and ggtt. So we need to
disable the use of the ppgtt selector bit for secure batches, or else we
hang immediately upon boot and thence after every GPU reset...
v2: Only HSW differentiates between secure dispatch and ggtt, so simply
ignore the differentiation and always use secure==ggtt.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 109de2eeb9a8..25795f2efdcb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2203,8 +2203,9 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
return ret;
intel_ring_emit(ring,
- MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
- (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
+ MI_BATCH_BUFFER_START |
+ (flags & I915_DISPATCH_SECURE ?
+ 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
/* bit0-7 is the length on GEN6+ */
intel_ring_emit(ring, offset);
intel_ring_advance(ring);
--
2.1.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: HSW always use GGTT selector for secure batches
2014-09-10 11:18 ` [PATCH] drm/i915: HSW always use GGTT selector for secure batches Chris Wilson
@ 2014-09-10 11:21 ` Chris Wilson
2014-09-10 12:00 ` Ville Syrjälä
0 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2014-09-10 11:21 UTC (permalink / raw)
To: intel-gfx
On Wed, Sep 10, 2014 at 12:18:27PM +0100, Chris Wilson wrote:
> gen6 and earlier conflate address space selection (ppgtt vs ggtt) with
> the security bit (i.e. only privileged batches were allowed to run from
> ggtt). From Haswell onwards, you are able to select the security bit
ggtt). For Haswell only, you are able to select the security bit
> separate from the address space - and we always requested to use ppgtt.
> This breaks the golden render state batch execution with full-ppgtt as
> that is only present in the global GTT and more generally any secure
> batch that is not colocated in the ppgtt and ggtt. So we need to
> disable the use of the ppgtt selector bit for secure batches, or else we
> hang immediately upon boot and thence after every GPU reset...
>
> v2: Only HSW differentiates between secure dispatch and ggtt, so simply
> ignore the differentiation and always use secure==ggtt.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 109de2eeb9a8..25795f2efdcb 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2203,8 +2203,9 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
> return ret;
>
> intel_ring_emit(ring,
> - MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
> - (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
> + MI_BATCH_BUFFER_START |
> + (flags & I915_DISPATCH_SECURE ?
> + 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
> /* bit0-7 is the length on GEN6+ */
> intel_ring_emit(ring, offset);
> intel_ring_advance(ring);
> --
> 2.1.0
>
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: HSW always use GGTT selector for secure batches
2014-09-10 11:21 ` Chris Wilson
@ 2014-09-10 12:00 ` Ville Syrjälä
2014-09-10 12:16 ` Daniel Vetter
0 siblings, 1 reply; 8+ messages in thread
From: Ville Syrjälä @ 2014-09-10 12:00 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On Wed, Sep 10, 2014 at 12:21:43PM +0100, Chris Wilson wrote:
> On Wed, Sep 10, 2014 at 12:18:27PM +0100, Chris Wilson wrote:
> > gen6 and earlier conflate address space selection (ppgtt vs ggtt) with
> > the security bit (i.e. only privileged batches were allowed to run from
> > ggtt). From Haswell onwards, you are able to select the security bit
>
> ggtt). For Haswell only, you are able to select the security bit
>
> > separate from the address space - and we always requested to use ppgtt.
> > This breaks the golden render state batch execution with full-ppgtt as
> > that is only present in the global GTT and more generally any secure
> > batch that is not colocated in the ppgtt and ggtt. So we need to
> > disable the use of the ppgtt selector bit for secure batches, or else we
> > hang immediately upon boot and thence after every GPU reset...
> >
> > v2: Only HSW differentiates between secure dispatch and ggtt, so simply
> > ignore the differentiation and always use secure==ggtt.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 109de2eeb9a8..25795f2efdcb 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -2203,8 +2203,9 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
> > return ret;
> >
> > intel_ring_emit(ring,
> > - MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
> > - (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
> > + MI_BATCH_BUFFER_START |
> > + (flags & I915_DISPATCH_SECURE ?
> > + 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
> > /* bit0-7 is the length on GEN6+ */
> > intel_ring_emit(ring, offset);
> > intel_ring_advance(ring);
> > --
> > 2.1.0
> >
>
> --
> Chris Wilson, Intel Open Source Technology Centre
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: HSW always use GGTT selector for secure batches
2014-09-10 12:00 ` Ville Syrjälä
@ 2014-09-10 12:16 ` Daniel Vetter
0 siblings, 0 replies; 8+ messages in thread
From: Daniel Vetter @ 2014-09-10 12:16 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Sep 10, 2014 at 03:00:03PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 10, 2014 at 12:21:43PM +0100, Chris Wilson wrote:
> > On Wed, Sep 10, 2014 at 12:18:27PM +0100, Chris Wilson wrote:
> > > gen6 and earlier conflate address space selection (ppgtt vs ggtt) with
> > > the security bit (i.e. only privileged batches were allowed to run from
> > > ggtt). From Haswell onwards, you are able to select the security bit
> >
> > ggtt). For Haswell only, you are able to select the security bit
Rectified.
> > > separate from the address space - and we always requested to use ppgtt.
> > > This breaks the golden render state batch execution with full-ppgtt as
> > > that is only present in the global GTT and more generally any secure
> > > batch that is not colocated in the ppgtt and ggtt. So we need to
> > > disable the use of the ppgtt selector bit for secure batches, or else we
> > > hang immediately upon boot and thence after every GPU reset...
> > >
> > > v2: Only HSW differentiates between secure dispatch and ggtt, so simply
> > > ignore the differentiation and always use secure==ggtt.
> > >
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2014-09-10 12:16 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-09-10 9:26 [PATCH] drm/i915: Use GGTT batchbuffer selector Chris Wilson
2014-09-10 9:46 ` Chris Wilson
2014-09-10 10:30 ` Ville Syrjälä
2014-09-10 10:50 ` Chris Wilson
2014-09-10 11:18 ` [PATCH] drm/i915: HSW always use GGTT selector for secure batches Chris Wilson
2014-09-10 11:21 ` Chris Wilson
2014-09-10 12:00 ` Ville Syrjälä
2014-09-10 12:16 ` Daniel Vetter
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.