* PCIe PASID (Process Address Space ID) and iommu code
@ 2014-10-15 23:44 Kallol Biswas
[not found] ` <CA+QbAV6-C9wxPttEx0uDn_K5Y1LaGt8pxDWc8RJmN4DqR+NHtQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Kallol Biswas @ 2014-10-15 23:44 UTC (permalink / raw)
To: linux-kernel
Resending, as message got bounced for html content.
--------------------------------------------
Hi,
PCIe has introduced PASID TLP Prefix. There are two ECNs on this.
It seems that AMD iommu code makes use of PASID. Is there a device that
utilizes this TLP prefix?
PASID allocation and management within a device is not clear to me. How
does device know which PASID to issue for which virtual address? Who makes
the association? Must be software/OS, but how? There is no table for this
like MSI-X table.
Any pointer/documentation will be appreciated.
Regards,
^ permalink raw reply [flat|nested] 6+ messages in thread[parent not found: <CA+QbAV6-C9wxPttEx0uDn_K5Y1LaGt8pxDWc8RJmN4DqR+NHtQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: PCIe PASID (Process Address Space ID) and iommu code 2014-10-15 23:44 PCIe PASID (Process Address Space ID) and iommu code Kallol Biswas @ 2014-10-16 3:50 ` Bjorn Helgaas 0 siblings, 0 replies; 6+ messages in thread From: Bjorn Helgaas @ 2014-10-16 3:50 UTC (permalink / raw) To: Kallol Biswas Cc: Jay Cornwall, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, open list:INTEL IOMMU (VT-d) [+cc Joerg, Suravee, Jay, iommu list, linux-pci] On Wed, Oct 15, 2014 at 5:44 PM, Kallol Biswas <nucleodyne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > Resending, as message got bounced for html content. > -------------------------------------------- > Hi, > PCIe has introduced PASID TLP Prefix. There are two ECNs on this. > > It seems that AMD iommu code makes use of PASID. Is there a device that > utilizes this TLP prefix? > > PASID allocation and management within a device is not clear to me. How > does device know which PASID to issue for which virtual address? Who makes > the association? Must be software/OS, but how? There is no table for this > like MSI-X table. > > Any pointer/documentation will be appreciated. > > Regards, > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: PCIe PASID (Process Address Space ID) and iommu code @ 2014-10-16 3:50 ` Bjorn Helgaas 0 siblings, 0 replies; 6+ messages in thread From: Bjorn Helgaas @ 2014-10-16 3:50 UTC (permalink / raw) To: Kallol Biswas Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Joerg Roedel, open list:INTEL IOMMU (VT-d), Suravee Suthikulpanit, Jay Cornwall [+cc Joerg, Suravee, Jay, iommu list, linux-pci] On Wed, Oct 15, 2014 at 5:44 PM, Kallol Biswas <nucleodyne@gmail.com> wrote: > Resending, as message got bounced for html content. > -------------------------------------------- > Hi, > PCIe has introduced PASID TLP Prefix. There are two ECNs on this. > > It seems that AMD iommu code makes use of PASID. Is there a device that > utilizes this TLP prefix? > > PASID allocation and management within a device is not clear to me. How > does device know which PASID to issue for which virtual address? Who makes > the association? Must be software/OS, but how? There is no table for this > like MSI-X table. > > Any pointer/documentation will be appreciated. > > Regards, > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ ^ permalink raw reply [flat|nested] 6+ messages in thread
[parent not found: <CAErSpo5YXZ8YRzhg0xvbHGCr22o+_+yi7HrCCBYBM9Ke42okJQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: PCIe PASID (Process Address Space ID) and iommu code 2014-10-16 3:50 ` Bjorn Helgaas @ 2014-10-16 9:14 ` Joerg Roedel -1 siblings, 0 replies; 6+ messages in thread From: Joerg Roedel @ 2014-10-16 9:14 UTC (permalink / raw) To: Bjorn Helgaas Cc: Jay Cornwall, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, open list:INTEL IOMMU (VT-d), Kallol Biswas On Wed, Oct 15, 2014 at 09:50:58PM -0600, Bjorn Helgaas wrote: > [+cc Joerg, Suravee, Jay, iommu list, linux-pci] > > On Wed, Oct 15, 2014 at 5:44 PM, Kallol Biswas <nucleodyne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > > Resending, as message got bounced for html content. > > -------------------------------------------- > > Hi, > > PCIe has introduced PASID TLP Prefix. There are two ECNs on this. > > > > It seems that AMD iommu code makes use of PASID. Is there a device that > > utilizes this TLP prefix? Yes, recent radeon GPUs can make use of the TLP prefix. > > PASID allocation and management within a device is not clear to me. How > > does device know which PASID to issue for which virtual address? Who makes > > the association? Must be software/OS, but how? There is no table for this > > like MSI-X table. The setup of the PASIDs is device specific, so there is no standard for setting up PASID address spaces on devices. HTH, Joerg ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: PCIe PASID (Process Address Space ID) and iommu code @ 2014-10-16 9:14 ` Joerg Roedel 0 siblings, 0 replies; 6+ messages in thread From: Joerg Roedel @ 2014-10-16 9:14 UTC (permalink / raw) To: Bjorn Helgaas Cc: Kallol Biswas, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, open list:INTEL IOMMU (VT-d), Suravee Suthikulpanit, Jay Cornwall On Wed, Oct 15, 2014 at 09:50:58PM -0600, Bjorn Helgaas wrote: > [+cc Joerg, Suravee, Jay, iommu list, linux-pci] > > On Wed, Oct 15, 2014 at 5:44 PM, Kallol Biswas <nucleodyne@gmail.com> wrote: > > Resending, as message got bounced for html content. > > -------------------------------------------- > > Hi, > > PCIe has introduced PASID TLP Prefix. There are two ECNs on this. > > > > It seems that AMD iommu code makes use of PASID. Is there a device that > > utilizes this TLP prefix? Yes, recent radeon GPUs can make use of the TLP prefix. > > PASID allocation and management within a device is not clear to me. How > > does device know which PASID to issue for which virtual address? Who makes > > the association? Must be software/OS, but how? There is no table for this > > like MSI-X table. The setup of the PASIDs is device specific, so there is no standard for setting up PASID address spaces on devices. HTH, Joerg ^ permalink raw reply [flat|nested] 6+ messages in thread
[parent not found: <CA+QbAV40LRnqghVzpUy4MqbjP2+tfsXWcBfot+TA2S+F5wsvng@mail.gmail.com>]
* Re: PCIe PASID (Process Address Space ID) and iommu code [not found] <CA+QbAV40LRnqghVzpUy4MqbjP2+tfsXWcBfot+TA2S+F5wsvng@mail.gmail.com> @ 2014-10-15 23:32 ` Kallol Biswas 0 siblings, 0 replies; 6+ messages in thread From: Kallol Biswas @ 2014-10-15 23:32 UTC (permalink / raw) To: linux-kernel Hi, PCIe has introduced PASID TLP Prefix. There are two ECNs on this. It seems that AMD iommu code makes use of PASID. Is there a device that utilizes this TLP prefix? PASID allocation and management within a device is not clear to me. How does device know which PASID to issue for with virtual address? Who makes the association? Must be software/OS, but how? There is no table for this like MSI-X table. Any pointer/documentation will be appreciated. Regards, ^ permalink raw reply [flat|nested] 6+ messages in thread
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2014-10-15 23:44 PCIe PASID (Process Address Space ID) and iommu code Kallol Biswas
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2014-10-16 3:50 ` Bjorn Helgaas
2014-10-16 3:50 ` Bjorn Helgaas
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2014-10-16 9:14 ` Joerg Roedel
2014-10-16 9:14 ` Joerg Roedel
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2014-10-15 23:32 ` Kallol Biswas
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