Re: [PATCH v2 04/17] drm/tegra: dsi: Add ganged mode support

[Thierry Reding <thierry.reding@gmail.com>]

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On Mon, Nov 03, 2014 at 01:30:38PM -0500, Sean Paul wrote:
> On Mon, Nov 3, 2014 at 4:27 AM, Thierry Reding <thierry.reding@gmail.com> wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > Implement ganged mode support for the Tegra DSI driver. The DSI host
> > controller to gang up with is specified via a phandle in the device tree
> > and the resolved DSI host controller used for the programming of the
> > ganged-mode registers.
> >
> 
> There's a lot in here that is not specifically ganging-support, such
> as adding the transfer callback and command mode, as well as pulling
> out functionality into helper functions. It might make things a little
> clearer to split this up into a few patches. I'll leave that up to
> you.

I think I tried to do that a while back, but things got really
complicated so I abandonned that effort. I'll give it another shot and
see what I can come up with.

> > diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
[...]
> > -static int tegra_output_dsi_enable(struct tegra_output *output)
> > +static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
> > +                                   unsigned int size)
> > +{
> > +       u32 value;
> > +
> > +       tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
> > +       tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
> 
> You might want to add "size = size & 0xFFFF;" before performing this write.

Actually according to register documentation the mask even needs to be
0x1fff, so that's a good idea. Alternatively I guess we could check the
size earlier to make sure that we can actually support it.

Thierry

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