From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/4] arm64: dts: fix PMU IRQ ordering for Juno
Date: Thu, 5 Feb 2015 11:54:16 +0000 [thread overview]
Message-ID: <20150205115416.GE23241@arm.com> (raw)
In-Reply-To: <20150205114642.GG11344@leverpostej>
On Thu, Feb 05, 2015 at 11:46:42AM +0000, Mark Rutland wrote:
> On Mon, Jan 26, 2015 at 05:54:15PM +0000, Will Deacon wrote:
> > diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
> > index cb3073e4e7a8..4ed9287aaef1 100644
> > --- a/arch/arm64/boot/dts/arm/juno.dts
> > +++ b/arch/arm64/boot/dts/arm/juno.dts
> > @@ -107,11 +107,11 @@
> > pmu {
> > compatible = "arm,armv8-pmuv3";
> > interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
> > + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> > };
>
> I am very much not keen on this. While this may get things working
> today, it completely relies on Linux-internal details (the order of CPU
> bringup, which in this case is different from the order of entries in
> /cpus).
>
> In all other dts that I am aware of, the order of entries in /cpus
> aligns with the order of interrupts in the PMU node, and the first entry
> is the boot CPU.
>
> I think that we should ensure that the ordering of CPU nodes matches the
> order of interrupts here. That way we can fall back to that ordering (if
> not explicitly overridden), and even after an arbitrary logical
> renumbering (e.g. after a kexec) the relationship should stay intact.
There are a few problems with reordering the CPU nodes:
(1) It breaks any existing users of taskset to pin on big/little
clusters.
(2) It's not generally possible if, for example, the bootloader decides
to boot Linux on a different CPU then we have no choice but to
change the PMU interrupt order.
(3) I didn't think that the ordering of CPU nodes was guaranteed to be
preserved by dtc, whereas the order of the interrupts will be.
> This DT has clearly never worked (nor been tested), and I think having
> this as an intermediary step only adds to the long term support burden
> by having the juno dts arbitrarily different to all other dts files (by
> relying on a logical order that's different to the /cpus order).
>
> Longer term we must ensure we have a more explicit ordering, as with
> your later patches.
Agreed. This is intended as something simpler for -stable.
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
To: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: [PATCH 1/4] arm64: dts: fix PMU IRQ ordering for Juno
Date: Thu, 5 Feb 2015 11:54:16 +0000 [thread overview]
Message-ID: <20150205115416.GE23241@arm.com> (raw)
In-Reply-To: <20150205114642.GG11344@leverpostej>
On Thu, Feb 05, 2015 at 11:46:42AM +0000, Mark Rutland wrote:
> On Mon, Jan 26, 2015 at 05:54:15PM +0000, Will Deacon wrote:
> > diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
> > index cb3073e4e7a8..4ed9287aaef1 100644
> > --- a/arch/arm64/boot/dts/arm/juno.dts
> > +++ b/arch/arm64/boot/dts/arm/juno.dts
> > @@ -107,11 +107,11 @@
> > pmu {
> > compatible = "arm,armv8-pmuv3";
> > interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
> > + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> > };
>
> I am very much not keen on this. While this may get things working
> today, it completely relies on Linux-internal details (the order of CPU
> bringup, which in this case is different from the order of entries in
> /cpus).
>
> In all other dts that I am aware of, the order of entries in /cpus
> aligns with the order of interrupts in the PMU node, and the first entry
> is the boot CPU.
>
> I think that we should ensure that the ordering of CPU nodes matches the
> order of interrupts here. That way we can fall back to that ordering (if
> not explicitly overridden), and even after an arbitrary logical
> renumbering (e.g. after a kexec) the relationship should stay intact.
There are a few problems with reordering the CPU nodes:
(1) It breaks any existing users of taskset to pin on big/little
clusters.
(2) It's not generally possible if, for example, the bootloader decides
to boot Linux on a different CPU then we have no choice but to
change the PMU interrupt order.
(3) I didn't think that the ordering of CPU nodes was guaranteed to be
preserved by dtc, whereas the order of the interrupts will be.
> This DT has clearly never worked (nor been tested), and I think having
> this as an intermediary step only adds to the long term support burden
> by having the juno dts arbitrarily different to all other dts files (by
> relying on a logical order that's different to the /cpus order).
>
> Longer term we must ensure we have a more explicit ordering, as with
> your later patches.
Agreed. This is intended as something simpler for -stable.
Will
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2015-02-05 11:54 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-26 17:54 [PATCH 1/4] arm64: dts: fix PMU IRQ ordering for Juno Will Deacon
2015-01-26 17:54 ` Will Deacon
2015-01-26 17:54 ` [PATCH 2/4] arm64: pmu: add support for interrupt-affinity property Will Deacon
2015-01-26 17:54 ` Will Deacon
2015-02-05 11:56 ` Mark Rutland
2015-02-05 11:56 ` Mark Rutland
2015-02-05 12:12 ` Will Deacon
2015-02-05 12:12 ` Will Deacon
2015-02-05 12:23 ` Mark Rutland
2015-02-05 12:23 ` Mark Rutland
2015-01-26 17:54 ` [PATCH 3/4] ARM: " Will Deacon
2015-01-26 17:54 ` Will Deacon
2015-01-26 17:54 ` [PATCH 4/4] arm64: dts: add interrupt-affinity property to pmu node for juno Will Deacon
2015-01-26 17:54 ` Will Deacon
2015-02-05 11:46 ` [PATCH 1/4] arm64: dts: fix PMU IRQ ordering for Juno Mark Rutland
2015-02-05 11:46 ` Mark Rutland
2015-02-05 11:54 ` Will Deacon [this message]
2015-02-05 11:54 ` Will Deacon
2015-02-05 11:59 ` Mark Rutland
2015-02-05 11:59 ` Mark Rutland
2015-02-05 12:09 ` Will Deacon
2015-02-05 12:09 ` Will Deacon
2015-02-05 12:20 ` Mark Rutland
2015-02-05 12:20 ` Mark Rutland
2015-02-05 12:48 ` David Gibson
2015-02-05 12:48 ` David Gibson
2015-02-05 14:33 ` Jon Loeliger
2015-02-05 14:33 ` Jon Loeliger
2015-02-05 15:38 ` Mark Rutland
2015-02-05 15:38 ` Mark Rutland
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150205115416.GE23241@arm.com \
--to=will.deacon@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.