[U-Boot] [RESEND PATCH 5/6] usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's

[Marek Vasut <marex@denx.de>]

On Wednesday, April 01, 2015 at 11:54:22 AM, Sanchayan Maity wrote:

The commit message is missing, please fix in v2.

> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>

[...]

> +#define USB_NC_REG_OFFSET				0x00000800
> +#define USBCx_CTRL_OFFSET				0x00000000
> +#define USBCx_PHY_CTRL_OFFSET			0x00000018

Please define the register offsets using the regular struct {} method,
see for example struct mxs_usbphy_regs and it's usage in ehci-mxs.c .

> +#define USBPHY_CTRL						0x00000030
> +#define USBPHY_CTRL_SET					0x00000034
> +#define USBPHY_CTRL_CLR					0x00000038
> +#define USBPHY_CTRL_TOG					0x0000003c
> +
> +#define USBPHY_PWD						0x00000000
> +#define USBPHY_TX						0x00000010
> +#define USBPHY_RX						0x00000020
> +#define USBPHY_DEBUG					0x00000050
> +#define USBPHY_CTRL_SFTRST				0x80000000
> +#define USBPHY_CTRL_CLKGATE				0x40000000
> +#define USBPHY_CTRL_ENUTMILEVEL3		0x00008000
> +#define USBPHY_CTRL_ENUTMILEVEL2		0x00004000
> +#define USBPHY_CTRL_OTG_ID				0x08000000
> +
> +#define ANADIG_PLL_CTRL_BYPASS			0x00010000
> +#define ANADIG_PLL_CTRL_ENABLE			0x00002000
> +#define ANADIG_PLL_CTRL_POWER			0x00001000
> +#define ANADIG_PLL_CTRL_EN_USB_CLKS		0x00000040
> +
> +#define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
> +#define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection
> */ +
> +/* USBCMD */
> +#define UCMD_RUN_STOP		(1 << 0) /* controller run/stop */
> +#define UCMD_RESET			(1 << 1) /* controller reset */

This looks very much like the USB PHY used on MX28 , can you double-check this
please ?

Best regards,
Marek Vasut