* [PATCH 1/2] drm/i915/skl: Remove of the DC5 code
@ 2015-06-29 16:44 Damien Lespiau
2015-06-29 16:44 ` [PATCH 2/2] drm/i915/skl: Don't try to disable DC6 if the DMC firwmare isn't loaded Damien Lespiau
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Damien Lespiau @ 2015-06-29 16:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Suketu Shah
This code is all dead code since we want to go up to DC6, always.
Cc: A.Sunil Kamath <sunil.kamath@intel.com>
Cc: Suketu Shah <suketu.j.shah@intel.com>
Cc Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 99 +++++----------------------------
1 file changed, 13 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a472012..ae80ffa 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -49,7 +49,6 @@
* present for a given platform.
*/
-#define GEN9_ENABLE_DC5(dev) 0
#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
#define for_each_power_well(i, power_well, domain_mask, power_domains) \
@@ -455,71 +454,6 @@ static void gen9_set_dc_state_debugmask_memory_up(
}
}
-static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
-{
- struct drm_device *dev = dev_priv->dev;
- bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
- SKL_DISP_PW_2);
-
- WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
- WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
- WARN(pg2_enabled, "PG2 not disabled to enable DC5.\n");
-
- WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
- "DC5 already programmed to be enabled.\n");
- WARN(dev_priv->pm.suspended,
- "DC5 cannot be enabled, if platform is runtime-suspended.\n");
-
- assert_csr_loaded(dev_priv);
-}
-
-static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
-{
- bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
- SKL_DISP_PW_2);
- /*
- * During initialization, the firmware may not be loaded yet.
- * We still want to make sure that the DC enabling flag is cleared.
- */
- if (dev_priv->power_domains.initializing)
- return;
-
- WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
- WARN(dev_priv->pm.suspended,
- "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
-}
-
-static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
-{
- uint32_t val;
-
- assert_can_enable_dc5(dev_priv);
-
- DRM_DEBUG_KMS("Enabling DC5\n");
-
- gen9_set_dc_state_debugmask_memory_up(dev_priv);
-
- val = I915_READ(DC_STATE_EN);
- val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
- val |= DC_STATE_EN_UPTO_DC5;
- I915_WRITE(DC_STATE_EN, val);
- POSTING_READ(DC_STATE_EN);
-}
-
-static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
-{
- uint32_t val;
-
- assert_can_disable_dc5(dev_priv);
-
- DRM_DEBUG_KMS("Disabling DC5\n");
-
- val = I915_READ(DC_STATE_EN);
- val &= ~DC_STATE_EN_UPTO_DC5;
- I915_WRITE(DC_STATE_EN, val);
- POSTING_READ(DC_STATE_EN);
-}
-
static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
@@ -626,20 +560,16 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
!I915_READ(HSW_PWR_WELL_BIOS),
"Invalid for power well status to be enabled, unless done by the BIOS, \
when request is to disable!\n");
- if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
- power_well->data == SKL_DISP_PW_2) {
- if (SKL_ENABLE_DC6(dev)) {
- skl_disable_dc6(dev_priv);
- /*
- * DDI buffer programming unnecessary during driver-load/resume
- * as it's already done during modeset initialization then.
- * It's also invalid here as encoder list is still uninitialized.
- */
- if (!dev_priv->power_domains.initializing)
- intel_prepare_ddi(dev);
- } else {
- gen9_disable_dc5(dev_priv);
- }
+ if (SKL_ENABLE_DC6(dev) &&
+ power_well->data == SKL_DISP_PW_2) {
+ skl_disable_dc6(dev_priv);
+ /*
+ * DDI buffer programming unnecessary during driver-load/resume
+ * as it's already done during modeset initialization then.
+ * It's also invalid here as encoder list is still uninitialized.
+ */
+ if (!dev_priv->power_domains.initializing)
+ intel_prepare_ddi(dev);
}
I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
}
@@ -658,8 +588,8 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
POSTING_READ(HSW_PWR_WELL_DRIVER);
DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
- if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
- power_well->data == SKL_DISP_PW_2) {
+ if (SKL_ENABLE_DC6(dev) &&
+ power_well->data == SKL_DISP_PW_2) {
enum csr_state state;
/* TODO: wait for a completion event or
* similar here instead of busy
@@ -671,10 +601,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
DRM_ERROR("CSR firmware not ready (%d)\n",
state);
else
- if (SKL_ENABLE_DC6(dev))
- skl_enable_dc6(dev_priv);
- else
- gen9_enable_dc5(dev_priv);
+ skl_enable_dc6(dev_priv);
}
}
}
--
2.1.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/2] drm/i915/skl: Don't try to disable DC6 if the DMC firwmare isn't loaded
2015-06-29 16:44 [PATCH 1/2] drm/i915/skl: Remove of the DC5 code Damien Lespiau
@ 2015-06-29 16:44 ` Damien Lespiau
2015-06-30 9:38 ` shuang.he
2015-06-29 16:54 ` [PATCH 1/2] drm/i915/skl: Remove of the DC5 code Imre Deak
2015-06-29 17:15 ` Kamath, Sunil
2 siblings, 1 reply; 8+ messages in thread
From: Damien Lespiau @ 2015-06-29 16:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Suketu Shah
Currently, when the firwmare isn't loaded, we don't enable DC6
(obviously!) but the disable path tries unconditionally to disable DC6.
[drm:i915_power_well_enable] enabling power well 1
[drm:i915_power_well_enable] enabling MISC IO power well
[drm:i915_power_well_enable] enabling power well 2
------------[ cut here ]------------
WARNING: CPU: 2 PID: 1935 at drivers/gpu/drm/i915/intel_csr.c:466 assert_csr_loaded+0xa9/0x100 [i915]()
CSR is not loaded.
Hardware name: Intel Corporation Skylake Client platform/Skylake Y LPDDR3 RVP3, BIOS SKLSE2P1.86C.X060.R00.1411120819 11/12/2014
ffffffffa01b3540 ffff88003f6ffa58 ffffffff8178875c 0000000000000000
ffff88003f6ffaa8 ffff88003f6ffa98 ffffffff8109425a ffff88003f965af0
ffff8801469e0000 ffff8801469e0340 0000000000000002 0000000030000003
Call Trace:
[<ffffffff8178875c>] dump_stack+0x45/0x57
[<ffffffff8109425a>] warn_slowpath_common+0x8a/0xc0
[<ffffffff810942d6>] warn_slowpath_fmt+0x46/0x50
[<ffffffffa00f73c9>] assert_csr_loaded+0xa9/0x100 [i915]
[<ffffffffa00f5edb>] skl_set_power_well+0x75b/0xae0 [i915]
[<ffffffffa00f6293>] skl_power_well_enable+0x13/0x20 [i915]
[<ffffffffa00f43d8>] i915_power_well_enable+0x28/0x50 [i915]
[<ffffffffa00f65d3>] intel_display_power_get+0xa3/0xd0 [i915]
[<ffffffffa017e131>] intel_dp_detect+0xa1/0x4e0 [i915]
[<ffffffffa00c8cb0>] drm_helper_probe_single_connector_modes_merge_bits+0x300/0x4c0 [drm_kms_helper]
[<ffffffffa006dd1e>] ? drm_mode_getconnector+0x8e/0x400 [drm]
[<ffffffffa00c8e83>] drm_helper_probe_single_connector_modes+0x13/0x20 [drm_kms_helper]
[<ffffffffa006dff9>] drm_mode_getconnector+0x369/0x400 [drm]
[<ffffffff811d6fe2>] ? might_fault+0x42/0xa0
[<ffffffffa005edd9>] drm_ioctl+0x359/0x690 [drm]
[<ffffffffa006dc90>] ? drm_mode_getcrtc+0x150/0x150 [drm]
[<ffffffff81239a08>] do_vfs_ioctl+0x318/0x570
[<ffffffff81245201>] ? expand_files+0x221/0x260
[<ffffffff8133794b>] ? selinux_file_ioctl+0x5b/0x110
[<ffffffff81239ce1>] SyS_ioctl+0x81/0xa0
[<ffffffff817917ee>] system_call_fastpath+0x12/0x76
Cc: A.Sunil Kamath <sunil.kamath@intel.com>
Cc: Suketu Shah <suketu.j.shah@intel.com>
Cc Animesh Manna <animesh.manna@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90461
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ae80ffa..0d5a166 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -503,6 +503,9 @@ static void skl_disable_dc6(struct drm_i915_private *dev_priv)
{
uint32_t val;
+ if (intel_csr_load_status_get(dev_priv) != FW_LOADED)
+ return;
+
assert_can_disable_dc6(dev_priv);
DRM_DEBUG_KMS("Disabling DC6\n");
--
2.1.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 1/2] drm/i915/skl: Remove of the DC5 code
2015-06-29 16:44 [PATCH 1/2] drm/i915/skl: Remove of the DC5 code Damien Lespiau
2015-06-29 16:44 ` [PATCH 2/2] drm/i915/skl: Don't try to disable DC6 if the DMC firwmare isn't loaded Damien Lespiau
@ 2015-06-29 16:54 ` Imre Deak
2015-06-29 16:59 ` Damien Lespiau
2015-06-29 17:15 ` Kamath, Sunil
2 siblings, 1 reply; 8+ messages in thread
From: Imre Deak @ 2015-06-29 16:54 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Suketu Shah, intel-gfx
On Mon, 2015-06-29 at 17:44 +0100, Damien Lespiau wrote:
> This code is all dead code since we want to go up to DC6, always.
On BXT DC6 is not available, so we can only go to DC5. It's disabled on
BXT atm, since runtime PM isn't enabled either.
> Cc: A.Sunil Kamath <sunil.kamath@intel.com>
> Cc: Suketu Shah <suketu.j.shah@intel.com>
> Cc Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 99 +++++----------------------------
> 1 file changed, 13 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index a472012..ae80ffa 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -49,7 +49,6 @@
> * present for a given platform.
> */
>
> -#define GEN9_ENABLE_DC5(dev) 0
> #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
>
> #define for_each_power_well(i, power_well, domain_mask, power_domains) \
> @@ -455,71 +454,6 @@ static void gen9_set_dc_state_debugmask_memory_up(
> }
> }
>
> -static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
> -{
> - struct drm_device *dev = dev_priv->dev;
> - bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
> - SKL_DISP_PW_2);
> -
> - WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
> - WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
> - WARN(pg2_enabled, "PG2 not disabled to enable DC5.\n");
> -
> - WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
> - "DC5 already programmed to be enabled.\n");
> - WARN(dev_priv->pm.suspended,
> - "DC5 cannot be enabled, if platform is runtime-suspended.\n");
> -
> - assert_csr_loaded(dev_priv);
> -}
> -
> -static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
> -{
> - bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
> - SKL_DISP_PW_2);
> - /*
> - * During initialization, the firmware may not be loaded yet.
> - * We still want to make sure that the DC enabling flag is cleared.
> - */
> - if (dev_priv->power_domains.initializing)
> - return;
> -
> - WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
> - WARN(dev_priv->pm.suspended,
> - "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
> -}
> -
> -static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> -{
> - uint32_t val;
> -
> - assert_can_enable_dc5(dev_priv);
> -
> - DRM_DEBUG_KMS("Enabling DC5\n");
> -
> - gen9_set_dc_state_debugmask_memory_up(dev_priv);
> -
> - val = I915_READ(DC_STATE_EN);
> - val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
> - val |= DC_STATE_EN_UPTO_DC5;
> - I915_WRITE(DC_STATE_EN, val);
> - POSTING_READ(DC_STATE_EN);
> -}
> -
> -static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
> -{
> - uint32_t val;
> -
> - assert_can_disable_dc5(dev_priv);
> -
> - DRM_DEBUG_KMS("Disabling DC5\n");
> -
> - val = I915_READ(DC_STATE_EN);
> - val &= ~DC_STATE_EN_UPTO_DC5;
> - I915_WRITE(DC_STATE_EN, val);
> - POSTING_READ(DC_STATE_EN);
> -}
> -
> static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> {
> struct drm_device *dev = dev_priv->dev;
> @@ -626,20 +560,16 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> !I915_READ(HSW_PWR_WELL_BIOS),
> "Invalid for power well status to be enabled, unless done by the BIOS, \
> when request is to disable!\n");
> - if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
> - power_well->data == SKL_DISP_PW_2) {
> - if (SKL_ENABLE_DC6(dev)) {
> - skl_disable_dc6(dev_priv);
> - /*
> - * DDI buffer programming unnecessary during driver-load/resume
> - * as it's already done during modeset initialization then.
> - * It's also invalid here as encoder list is still uninitialized.
> - */
> - if (!dev_priv->power_domains.initializing)
> - intel_prepare_ddi(dev);
> - } else {
> - gen9_disable_dc5(dev_priv);
> - }
> + if (SKL_ENABLE_DC6(dev) &&
> + power_well->data == SKL_DISP_PW_2) {
> + skl_disable_dc6(dev_priv);
> + /*
> + * DDI buffer programming unnecessary during driver-load/resume
> + * as it's already done during modeset initialization then.
> + * It's also invalid here as encoder list is still uninitialized.
> + */
> + if (!dev_priv->power_domains.initializing)
> + intel_prepare_ddi(dev);
> }
> I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
> }
> @@ -658,8 +588,8 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> POSTING_READ(HSW_PWR_WELL_DRIVER);
> DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
>
> - if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
> - power_well->data == SKL_DISP_PW_2) {
> + if (SKL_ENABLE_DC6(dev) &&
> + power_well->data == SKL_DISP_PW_2) {
> enum csr_state state;
> /* TODO: wait for a completion event or
> * similar here instead of busy
> @@ -671,10 +601,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> DRM_ERROR("CSR firmware not ready (%d)\n",
> state);
> else
> - if (SKL_ENABLE_DC6(dev))
> - skl_enable_dc6(dev_priv);
> - else
> - gen9_enable_dc5(dev_priv);
> + skl_enable_dc6(dev_priv);
> }
> }
> }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/2] drm/i915/skl: Remove of the DC5 code
2015-06-29 16:54 ` [PATCH 1/2] drm/i915/skl: Remove of the DC5 code Imre Deak
@ 2015-06-29 16:59 ` Damien Lespiau
2015-06-29 17:08 ` Imre Deak
0 siblings, 1 reply; 8+ messages in thread
From: Damien Lespiau @ 2015-06-29 16:59 UTC (permalink / raw)
To: Imre Deak; +Cc: Suketu Shah, intel-gfx
On Mon, Jun 29, 2015 at 07:54:42PM +0300, Imre Deak wrote:
> On Mon, 2015-06-29 at 17:44 +0100, Damien Lespiau wrote:
> > This code is all dead code since we want to go up to DC6, always.
>
> On BXT DC6 is not available, so we can only go to DC5. It's disabled on
> BXT atm, since runtime PM isn't enabled either.
I knew there was a catch!
That code is pretty convoluted btw, it would make sense to have proper
pre_disable/post_enabled hooks on power wells?
--
Damien
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915/skl: Remove of the DC5 code
2015-06-29 16:59 ` Damien Lespiau
@ 2015-06-29 17:08 ` Imre Deak
2015-06-29 17:19 ` Damien Lespiau
0 siblings, 1 reply; 8+ messages in thread
From: Imre Deak @ 2015-06-29 17:08 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Suketu Shah, intel-gfx
On Mon, 2015-06-29 at 17:59 +0100, Damien Lespiau wrote:
> On Mon, Jun 29, 2015 at 07:54:42PM +0300, Imre Deak wrote:
> > On Mon, 2015-06-29 at 17:44 +0100, Damien Lespiau wrote:
> > > This code is all dead code since we want to go up to DC6, always.
> >
> > On BXT DC6 is not available, so we can only go to DC5. It's disabled on
> > BXT atm, since runtime PM isn't enabled either.
>
> I knew there was a catch!
>
> That code is pretty convoluted btw, it would make sense to have proper
> pre_disable/post_enabled hooks on power wells?
Yes, it would make sense to simplify the code. I haven't thought about
adding new hooks, not sure how useful they would be on other platforms.
But to me it seems that the enable/disable parts in skl_set_power_well()
could be split out to the existing skl_power_well_{enable,disable}, have
you looked into that already?
--Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/2] drm/i915/skl: Remove of the DC5 code
2015-06-29 17:08 ` Imre Deak
@ 2015-06-29 17:19 ` Damien Lespiau
0 siblings, 0 replies; 8+ messages in thread
From: Damien Lespiau @ 2015-06-29 17:19 UTC (permalink / raw)
To: Imre Deak; +Cc: Suketu Shah, intel-gfx
On Mon, Jun 29, 2015 at 08:08:59PM +0300, Imre Deak wrote:
> On Mon, 2015-06-29 at 17:59 +0100, Damien Lespiau wrote:
> > On Mon, Jun 29, 2015 at 07:54:42PM +0300, Imre Deak wrote:
> > > On Mon, 2015-06-29 at 17:44 +0100, Damien Lespiau wrote:
> > > > This code is all dead code since we want to go up to DC6, always.
> > >
> > > On BXT DC6 is not available, so we can only go to DC5. It's disabled on
> > > BXT atm, since runtime PM isn't enabled either.
> >
> > I knew there was a catch!
> >
> > That code is pretty convoluted btw, it would make sense to have proper
> > pre_disable/post_enabled hooks on power wells?
>
> Yes, it would make sense to simplify the code. I haven't thought about
> adding new hooks, not sure how useful they would be on other platforms.
> But to me it seems that the enable/disable parts in skl_set_power_well()
> could be split out to the existing skl_power_well_{enable,disable}, have
> you looked into that already?
Nop, I haven't, but that's indeed a nice middle ground.
--
Damien
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915/skl: Remove of the DC5 code
2015-06-29 16:44 [PATCH 1/2] drm/i915/skl: Remove of the DC5 code Damien Lespiau
2015-06-29 16:44 ` [PATCH 2/2] drm/i915/skl: Don't try to disable DC6 if the DMC firwmare isn't loaded Damien Lespiau
2015-06-29 16:54 ` [PATCH 1/2] drm/i915/skl: Remove of the DC5 code Imre Deak
@ 2015-06-29 17:15 ` Kamath, Sunil
2 siblings, 0 replies; 8+ messages in thread
From: Kamath, Sunil @ 2015-06-29 17:15 UTC (permalink / raw)
To: Lespiau, Damien, intel-gfx@lists.freedesktop.org; +Cc: Shah, Suketu J
But DC5 needed for BXT
- Sunil
>-----Original Message-----
>From: Lespiau, Damien
>Sent: Monday, June 29, 2015 10:15 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Kamath, Sunil; Shah, Suketu J
>Subject: [PATCH 1/2] drm/i915/skl: Remove of the DC5 code
>
>This code is all dead code since we want to go up to DC6, always.
>
>Cc: A.Sunil Kamath <sunil.kamath@intel.com>
>Cc: Suketu Shah <suketu.j.shah@intel.com> Cc Animesh Manna <animesh.manna@intel.com>
>Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>
>Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>---
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2015-06-30 9:38 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-06-29 16:44 [PATCH 1/2] drm/i915/skl: Remove of the DC5 code Damien Lespiau
2015-06-29 16:44 ` [PATCH 2/2] drm/i915/skl: Don't try to disable DC6 if the DMC firwmare isn't loaded Damien Lespiau
2015-06-30 9:38 ` shuang.he
2015-06-29 16:54 ` [PATCH 1/2] drm/i915/skl: Remove of the DC5 code Imre Deak
2015-06-29 16:59 ` Damien Lespiau
2015-06-29 17:08 ` Imre Deak
2015-06-29 17:19 ` Damien Lespiau
2015-06-29 17:15 ` Kamath, Sunil
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.