From: Joerg Roedel <jroedel-l3A5Bk7waGM@public.gmane.org>
To: Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
David Woodhouse <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
Gregor Dick <gdick-s/n/eUQHGBpZroRs9YW3xA@public.gmane.org>
Subject: Re: [PATCH v2 01/11] iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth
Date: Mon, 27 Jul 2015 15:08:10 +0200 [thread overview]
Message-ID: <20150727130810.GG27614@suse.de> (raw)
In-Reply-To: <20150721001357.28145.83631.stgit-1RhO1Y9PlrlHTL0Zs8A6p/gx64E7kk8eUsxypvmhUTTZJqsBc5GL+g@public.gmane.org>
On Mon, Jul 20, 2015 at 07:13:57PM -0500, Bjorn Helgaas wrote:
> We check the ATS state (enabled/disabled) and fetch the PCI ATS Invalidate
> Queue Depth in performance-sensitive paths. It's easy to cache these,
> which removes dependencies on PCI.
>
> Remember the ATS enabled state. When enabling, read the queue depth once
> and cache it in the device_domain_info struct. This is similar to what
> amd_iommu.c does.
>
> Signed-off-by: Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/iommu/intel-iommu.c | 26 ++++++++++++++++----------
> 1 file changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
> index a98a7b2..50832f1 100644
> --- a/drivers/iommu/intel-iommu.c
> +++ b/drivers/iommu/intel-iommu.c
> @@ -408,6 +408,10 @@ struct device_domain_info {
> struct list_head global; /* link to global list */
> u8 bus; /* PCI bus number */
> u8 devfn; /* PCI devfn number */
> + struct {
> + int enabled:1;
> + u8 qdep;
> + } ats; /* ATS state */
> struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
> struct intel_iommu *iommu; /* IOMMU used by this device */
> struct dmar_domain *domain; /* pointer to domain */
> @@ -1391,19 +1395,26 @@ iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
>
> static void iommu_enable_dev_iotlb(struct device_domain_info *info)
> {
> + struct pci_dev *pdev;
> +
> if (!info || !dev_is_pci(info->dev))
> return;
>
> - pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT);
> + pdev = to_pci_dev(info->dev);
> + if (pci_enable_ats(pdev, VTD_PAGE_SHIFT))
> + return;
> +
> + info->ats.enabled = 1;
> + info->ats.qdep = pci_ats_queue_depth(pdev);
Hmm, this is a place where the relaxed error handling in
pci_enable_ats() can get problematic. If ATS is (by accident or a bug
elsewhere) already enabled an the function returns -EINVAL, the IOMMU
driver considers ATS disabled and doesn't flush the IO/TLBs of the
device. This can cause data corruption later on, so we should make sure
that info->ats.enabled is consistent with pdev->ats_enabled.
Joerg
WARNING: multiple messages have this Message-ID (diff)
From: Joerg Roedel <jroedel@suse.de>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org, David Woodhouse <dwmw2@infradead.org>,
iommu@lists.linux-foundation.org,
Gregor Dick <gdick@solarflare.com>
Subject: Re: [PATCH v2 01/11] iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth
Date: Mon, 27 Jul 2015 15:08:10 +0200 [thread overview]
Message-ID: <20150727130810.GG27614@suse.de> (raw)
In-Reply-To: <20150721001357.28145.83631.stgit@bhelgaas-glaptop2.roam.corp.google.com>
On Mon, Jul 20, 2015 at 07:13:57PM -0500, Bjorn Helgaas wrote:
> We check the ATS state (enabled/disabled) and fetch the PCI ATS Invalidate
> Queue Depth in performance-sensitive paths. It's easy to cache these,
> which removes dependencies on PCI.
>
> Remember the ATS enabled state. When enabling, read the queue depth once
> and cache it in the device_domain_info struct. This is similar to what
> amd_iommu.c does.
>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/iommu/intel-iommu.c | 26 ++++++++++++++++----------
> 1 file changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
> index a98a7b2..50832f1 100644
> --- a/drivers/iommu/intel-iommu.c
> +++ b/drivers/iommu/intel-iommu.c
> @@ -408,6 +408,10 @@ struct device_domain_info {
> struct list_head global; /* link to global list */
> u8 bus; /* PCI bus number */
> u8 devfn; /* PCI devfn number */
> + struct {
> + int enabled:1;
> + u8 qdep;
> + } ats; /* ATS state */
> struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
> struct intel_iommu *iommu; /* IOMMU used by this device */
> struct dmar_domain *domain; /* pointer to domain */
> @@ -1391,19 +1395,26 @@ iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
>
> static void iommu_enable_dev_iotlb(struct device_domain_info *info)
> {
> + struct pci_dev *pdev;
> +
> if (!info || !dev_is_pci(info->dev))
> return;
>
> - pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT);
> + pdev = to_pci_dev(info->dev);
> + if (pci_enable_ats(pdev, VTD_PAGE_SHIFT))
> + return;
> +
> + info->ats.enabled = 1;
> + info->ats.qdep = pci_ats_queue_depth(pdev);
Hmm, this is a place where the relaxed error handling in
pci_enable_ats() can get problematic. If ATS is (by accident or a bug
elsewhere) already enabled an the function returns -EINVAL, the IOMMU
driver considers ATS disabled and doesn't flush the IO/TLBs of the
device. This can cause data corruption later on, so we should make sure
that info->ats.enabled is consistent with pdev->ats_enabled.
Joerg
next prev parent reply other threads:[~2015-07-27 13:08 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-21 0:13 [PATCH v2 00/11] PCI: Fix ATS deadlock Bjorn Helgaas
2015-07-21 0:13 ` [PATCH v2 01/11] iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth Bjorn Helgaas
[not found] ` <20150721001357.28145.83631.stgit-1RhO1Y9PlrlHTL0Zs8A6p/gx64E7kk8eUsxypvmhUTTZJqsBc5GL+g@public.gmane.org>
2015-07-27 13:08 ` Joerg Roedel [this message]
2015-07-27 13:08 ` Joerg Roedel
2015-07-27 22:54 ` Bjorn Helgaas
[not found] ` <20150727225453.GB24401-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
2015-07-28 7:14 ` Joerg Roedel
2015-07-28 7:14 ` Joerg Roedel
2015-07-21 0:14 ` [PATCH v2 02/11] PCI: Allocate ATS struct during enumeration Bjorn Helgaas
2015-07-27 12:40 ` Joerg Roedel
2015-07-21 0:14 ` [PATCH v2 03/11] PCI: Embed ATS info directly into struct pci_dev Bjorn Helgaas
[not found] ` <20150721001413.28145.38246.stgit-1RhO1Y9PlrlHTL0Zs8A6p/gx64E7kk8eUsxypvmhUTTZJqsBc5GL+g@public.gmane.org>
2015-07-27 12:45 ` Joerg Roedel
2015-07-27 12:45 ` Joerg Roedel
2015-07-21 0:14 ` [PATCH v2 05/11] PCI: Rationalize pci_ats_queue_depth() error checking Bjorn Helgaas
2015-07-21 0:14 ` [PATCH v2 06/11] PCI: Inline the ATS setup code into pci_ats_init() Bjorn Helgaas
[not found] ` <20150721001243.28145.81610.stgit-1RhO1Y9PlrlHTL0Zs8A6p/gx64E7kk8eUsxypvmhUTTZJqsBc5GL+g@public.gmane.org>
2015-07-21 0:14 ` [PATCH v2 04/11] PCI: Reduce size of ATS structure elements Bjorn Helgaas
2015-07-21 0:14 ` Bjorn Helgaas
2015-07-21 0:14 ` [PATCH v2 07/11] PCI: Use pci_physfn() rather than looking up physfn by hand Bjorn Helgaas
2015-07-21 0:14 ` Bjorn Helgaas
2015-07-21 0:14 ` [PATCH v2 08/11] PCI: Clean up ATS error handling Bjorn Helgaas
2015-07-21 0:14 ` Bjorn Helgaas
2015-07-27 12:56 ` Joerg Roedel
2015-07-29 16:07 ` [PATCH v2 00/11] PCI: Fix ATS deadlock Bjorn Helgaas
2015-07-29 16:07 ` Bjorn Helgaas
2015-08-06 16:03 ` Yinghai Lu
2015-08-07 1:06 ` Yinghai Lu
2015-08-10 17:33 ` Bjorn Helgaas
2015-08-10 22:54 ` Yinghai Lu
2015-07-21 0:15 ` [PATCH v2 09/11] PCI: Move ATS declarations to linux/pci.h so they're all together Bjorn Helgaas
2015-07-21 0:15 ` [PATCH v2 10/11] PCI: Stop caching ATS Invalidate Queue Depth Bjorn Helgaas
2015-07-27 12:57 ` Joerg Roedel
2015-07-27 14:00 ` Don Dutile
2015-07-27 22:27 ` Bjorn Helgaas
2015-07-27 23:13 ` Don Dutile
2015-07-21 0:15 ` [PATCH v2 11/11] PCI: Remove pci_ats_enabled() Bjorn Helgaas
[not found] ` <20150721001519.28145.73458.stgit-1RhO1Y9PlrlHTL0Zs8A6p/gx64E7kk8eUsxypvmhUTTZJqsBc5GL+g@public.gmane.org>
2015-07-27 12:58 ` Joerg Roedel
2015-07-27 12:58 ` Joerg Roedel
2015-07-28 15:16 ` [PATCH v2 00/11] PCI: Fix ATS deadlock Joerg Roedel
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