From: shawnguo@kernel.org (Shawn Guo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes
Date: Wed, 5 Aug 2015 19:57:02 +0800 [thread overview]
Message-ID: <20150805115702.GI12927@tiger> (raw)
In-Reply-To: <1438094636-20421-2-git-send-email-claudiu.manoil@freescale.com>
On Tue, Jul 28, 2015 at 05:43:55PM +0300, Claudiu Manoil wrote:
> Add basic support for all the eTSEC controllers on the
> ls1021a SoC. Second interrupt group register blocks
> and their corresponding Rx/Tx/Err interrupt sources are
> included as well for each eTSEC node.
>
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Applied both with a minor change below.
> ---
> v2: various findings, added 2nd interrupt group;
> v3: addressed findings from Shawn Guo -
> - initial patch split in soc, boards and bindings patches;
> - removed redundant all zero local-mac-address;
> - subject prefix;
>
> arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 1b306c7..0638cda 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
> serial3 = &lpuart3;
> serial4 = &lpuart4;
> serial5 = &lpuart5;
> + ethernet0 = &enet0;
> + ethernet1 = &enet1;
> + ethernet2 = &enet2;
I moved these above serial to keep them sort alphabetically.
Shawn
> sysclk = &sysclk;
> };
>
> @@ -391,6 +394,91 @@
> reg = <0x0 0x2d24000 0x0 0x4000>;
> };
>
> + enet0: ethernet at 2d10000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + fsl,magic-packet;
> + ranges;
> +
> + queue-group at 2d10000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d10000 0x0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group at 2d14000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d14000 0x0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet1: ethernet at 2d50000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + ranges;
> +
> + queue-group at 2d50000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d50000 0x0 0x1000>;
> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group at 2d54000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d54000 0x0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet2: ethernet at 2d90000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + ranges;
> +
> + queue-group at 2d90000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d90000 0x0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group at 2d94000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d94000 0x0 0x1000>;
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> usb at 8600000 {
> compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> reg = <0x0 0x8600000 0x0 0x1000>;
> --
> 1.7.11.7
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Claudiu Manoil <claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Alison Wang <alison.wang-KZfg59tc24xl57MIdRCFDg@public.gmane.org>,
shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
Subject: Re: [PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes
Date: Wed, 5 Aug 2015 19:57:02 +0800 [thread overview]
Message-ID: <20150805115702.GI12927@tiger> (raw)
In-Reply-To: <1438094636-20421-2-git-send-email-claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
On Tue, Jul 28, 2015 at 05:43:55PM +0300, Claudiu Manoil wrote:
> Add basic support for all the eTSEC controllers on the
> ls1021a SoC. Second interrupt group register blocks
> and their corresponding Rx/Tx/Err interrupt sources are
> included as well for each eTSEC node.
>
> Signed-off-by: Alison Wang <alison.wang-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Claudiu Manoil <claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Applied both with a minor change below.
> ---
> v2: various findings, added 2nd interrupt group;
> v3: addressed findings from Shawn Guo -
> - initial patch split in soc, boards and bindings patches;
> - removed redundant all zero local-mac-address;
> - subject prefix;
>
> arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 1b306c7..0638cda 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
> serial3 = &lpuart3;
> serial4 = &lpuart4;
> serial5 = &lpuart5;
> + ethernet0 = &enet0;
> + ethernet1 = &enet1;
> + ethernet2 = &enet2;
I moved these above serial to keep them sort alphabetically.
Shawn
> sysclk = &sysclk;
> };
>
> @@ -391,6 +394,91 @@
> reg = <0x0 0x2d24000 0x0 0x4000>;
> };
>
> + enet0: ethernet@2d10000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + fsl,magic-packet;
> + ranges;
> +
> + queue-group@2d10000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d10000 0x0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d14000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d14000 0x0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet1: ethernet@2d50000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + ranges;
> +
> + queue-group@2d50000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d50000 0x0 0x1000>;
> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d54000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d54000 0x0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet2: ethernet@2d90000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + ranges;
> +
> + queue-group@2d90000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d90000 0x0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d94000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d94000 0x0 0x1000>;
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> usb@8600000 {
> compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> reg = <0x0 0x8600000 0x0 0x1000>;
> --
> 1.7.11.7
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
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WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Claudiu Manoil <claudiu.manoil@freescale.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Alison Wang <alison.wang@freescale.com>,
shawn.guo@linaro.org, galak@codeaurora.org
Subject: Re: [PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes
Date: Wed, 5 Aug 2015 19:57:02 +0800 [thread overview]
Message-ID: <20150805115702.GI12927@tiger> (raw)
In-Reply-To: <1438094636-20421-2-git-send-email-claudiu.manoil@freescale.com>
On Tue, Jul 28, 2015 at 05:43:55PM +0300, Claudiu Manoil wrote:
> Add basic support for all the eTSEC controllers on the
> ls1021a SoC. Second interrupt group register blocks
> and their corresponding Rx/Tx/Err interrupt sources are
> included as well for each eTSEC node.
>
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Applied both with a minor change below.
> ---
> v2: various findings, added 2nd interrupt group;
> v3: addressed findings from Shawn Guo -
> - initial patch split in soc, boards and bindings patches;
> - removed redundant all zero local-mac-address;
> - subject prefix;
>
> arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 1b306c7..0638cda 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
> serial3 = &lpuart3;
> serial4 = &lpuart4;
> serial5 = &lpuart5;
> + ethernet0 = &enet0;
> + ethernet1 = &enet1;
> + ethernet2 = &enet2;
I moved these above serial to keep them sort alphabetically.
Shawn
> sysclk = &sysclk;
> };
>
> @@ -391,6 +394,91 @@
> reg = <0x0 0x2d24000 0x0 0x4000>;
> };
>
> + enet0: ethernet@2d10000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + fsl,magic-packet;
> + ranges;
> +
> + queue-group@2d10000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d10000 0x0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d14000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d14000 0x0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet1: ethernet@2d50000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + ranges;
> +
> + queue-group@2d50000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d50000 0x0 0x1000>;
> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d54000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d54000 0x0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet2: ethernet@2d90000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + ranges;
> +
> + queue-group@2d90000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d90000 0x0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d94000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d94000 0x0 0x1000>;
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> usb@8600000 {
> compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> reg = <0x0 0x8600000 0x0 0x1000>;
> --
> 1.7.11.7
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
next prev parent reply other threads:[~2015-08-05 11:57 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-25 6:24 [PATCH] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2 Alison Wang
2015-06-25 6:24 ` Alison Wang
2015-06-25 6:24 ` Alison Wang
2015-07-12 6:51 ` Shawn Guo
2015-07-12 6:51 ` Shawn Guo
2015-07-13 10:47 ` Manoil Claudiu
2015-07-13 10:47 ` Manoil Claudiu
2015-07-13 10:47 ` Manoil Claudiu
2015-07-13 13:31 ` Shawn Guo
2015-07-13 13:31 ` Shawn Guo
2015-07-13 13:31 ` Shawn Guo
2015-07-13 15:08 ` Manoil Claudiu
2015-07-13 15:08 ` Manoil Claudiu
2015-07-13 15:08 ` Manoil Claudiu
2015-07-14 15:46 ` [PATCH v2] " Claudiu Manoil
2015-07-14 15:46 ` Claudiu Manoil
2015-07-14 15:46 ` Claudiu Manoil
2015-07-14 15:57 ` Fabio Estevam
2015-07-14 15:57 ` Fabio Estevam
2015-07-14 15:57 ` Fabio Estevam
2015-07-14 16:13 ` Manoil Claudiu
2015-07-14 16:13 ` Manoil Claudiu
2015-07-14 16:13 ` Manoil Claudiu
2015-07-14 16:17 ` Fabio Estevam
2015-07-14 16:17 ` Fabio Estevam
2015-07-14 16:17 ` Fabio Estevam
2015-07-27 14:28 ` Shawn Guo
2015-07-27 14:28 ` Shawn Guo
2015-07-27 16:09 ` Manoil Claudiu
2015-07-27 16:09 ` Manoil Claudiu
2015-07-27 16:09 ` Manoil Claudiu
2015-07-28 14:43 ` [PATCH,v3 1/3] doc: dt: Update eTSEC bindings doc Claudiu Manoil
2015-07-28 14:43 ` Claudiu Manoil
2015-07-28 14:43 ` Claudiu Manoil
2015-07-28 14:43 ` [PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes Claudiu Manoil
2015-07-28 14:43 ` Claudiu Manoil
2015-07-28 14:43 ` Claudiu Manoil
2015-08-05 11:57 ` Shawn Guo [this message]
2015-08-05 11:57 ` Shawn Guo
2015-08-05 11:57 ` Shawn Guo
2015-07-28 14:43 ` [PATCH, v3 3/3] ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR Claudiu Manoil
2015-07-28 14:43 ` [PATCH,v3 " Claudiu Manoil
2015-07-28 14:43 ` Claudiu Manoil
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