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From: Will Deacon <will.deacon@arm.com>
To: Sricharan R <sricharan@codeaurora.org>
Cc: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"iommu@lists.linux-foundation.org"
	<iommu@lists.linux-foundation.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>,
	Robin Murphy <Robin.Murphy@arm.com>,
	"robdclark@gmail.com" <robdclark@gmail.com>,
	"joro@8bytes.org" <joro@8bytes.org>,
	"srinivas.kandagatla@linaro.org" <srinivas.kandagatla@linaro.org>,
	"laurent.pinchart@ideasonboard.com"
	<laurent.pinchart@ideasonboard.com>,
	"stepanm@codeaurora.org" <stepanm@codeaurora.org>,
	"treding@nvidia.com" <treding@nvidia.com>
Subject: Re: [PATCH 4/5] iommu/msm: Set cacheability attributes without tex remap
Date: Wed, 12 Aug 2015 15:53:46 +0100	[thread overview]
Message-ID: <20150812145346.GH23540@arm.com> (raw)
In-Reply-To: <1439390869-6347-5-git-send-email-sricharan@codeaurora.org>

On Wed, Aug 12, 2015 at 03:47:48PM +0100, Sricharan R wrote:
> The cacheablity attributes are set when IOMMU_CACHE property
> is true. So cachebility is set as either noncached (normal)
> or cached (normal WBWA) directly and avoid setting using
> tex remap.

Does this IOMMU support the ARMv7 short descriptor format? If so, would
it work with Yong's patch here:

  http://lists.infradead.org/pipermail/linux-arm-kernel/2015-August/361615.html

I've not gotten around to reviewing the latest version yet, but having
other IOMMUs consolidate on one set of page table code would be a good
thing.

Will

WARNING: multiple messages have this Message-ID (diff)
From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/5] iommu/msm: Set cacheability attributes without tex remap
Date: Wed, 12 Aug 2015 15:53:46 +0100	[thread overview]
Message-ID: <20150812145346.GH23540@arm.com> (raw)
In-Reply-To: <1439390869-6347-5-git-send-email-sricharan@codeaurora.org>

On Wed, Aug 12, 2015 at 03:47:48PM +0100, Sricharan R wrote:
> The cacheablity attributes are set when IOMMU_CACHE property
> is true. So cachebility is set as either noncached (normal)
> or cached (normal WBWA) directly and avoid setting using
> tex remap.

Does this IOMMU support the ARMv7 short descriptor format? If so, would
it work with Yong's patch here:

  http://lists.infradead.org/pipermail/linux-arm-kernel/2015-August/361615.html

I've not gotten around to reviewing the latest version yet, but having
other IOMMUs consolidate on one set of page table code would be a good
thing.

Will

  reply	other threads:[~2015-08-12 14:53 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-12 14:47 [PATCH 0/5] iommu/msm: Add DT adaptation and generic bindings support Sricharan R
2015-08-12 14:47 ` Sricharan R
2015-08-12 14:47 ` [PATCH 1/5] iommu/msm: Add DT adaptation Sricharan R
2015-08-12 14:47   ` Sricharan R
2015-08-12 14:47 ` [PATCH 2/5] iommu/msm: Move the contents from msm_iommu_dev.c to msm_iommu.c Sricharan R
2015-08-12 14:47   ` Sricharan R
     [not found] ` <1439390869-6347-1-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2015-08-12 14:47   ` [PATCH 3/5] iommu/msm: Add support for generic master bindings Sricharan R
2015-08-12 14:47     ` Sricharan R
2015-08-12 19:11     ` Stephen Boyd
2015-08-12 19:11       ` Stephen Boyd
     [not found]       ` <55CB9A7D.7080206-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2015-08-13  8:09         ` Sricharan
2015-08-13  8:09           ` Sricharan
2015-08-12 14:47   ` [PATCH 4/5] iommu/msm: Set cacheability attributes without tex remap Sricharan R
2015-08-12 14:47     ` Sricharan R
2015-08-12 14:53     ` Will Deacon [this message]
2015-08-12 14:53       ` Will Deacon
2015-08-13  6:37       ` Sricharan
2015-08-13  6:37         ` Sricharan
2015-08-12 14:47   ` [PATCH 5/5] iommu/msm: Remove driver BROKEN Sricharan R
2015-08-12 14:47     ` Sricharan R
2015-08-14  9:30 ` [PATCH 0/5] iommu/msm: Add DT adaptation and generic bindings support Srinivas Kandagatla
2015-08-14  9:30   ` Srinivas Kandagatla

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