From: Stephen Boyd <sboyd@codeaurora.org>
To: Sricharan R <sricharan@codeaurora.org>
Cc: linux-arm-kernel@lists.infradead.org,
iommu@lists.linux-foundation.org, devicetree@vger.kernel.org,
linux-arm-msm@vger.kernel.org, robin.murphy@arm.com,
robdclark@gmail.com, joro@8bytes.org,
srinivas.kandagatla@linaro.org,
laurent.pinchart@ideasonboard.com, Will.Deacon@arm.com,
stepanm@codeaurora.org, treding@nvidia.com
Subject: Re: [PATCH 3/5] iommu/msm: Add support for generic master bindings
Date: Wed, 12 Aug 2015 12:11:57 -0700 [thread overview]
Message-ID: <55CB9A7D.7080206@codeaurora.org> (raw)
In-Reply-To: <1439390869-6347-4-git-send-email-sricharan@codeaurora.org>
On 08/12/2015 07:47 AM, Sricharan R wrote:
> @@ -702,6 +703,44 @@ static void print_ctx_regs(void __iomem *base, int ctx)
> GET_PRRR(base, ctx), GET_NMRR(base, ctx));
> }
>
> +static void insert_iommu_master(struct device *dev,
> + struct msm_iommu_dev *iommu,
> + struct of_phandle_args *spec)
> +{
> + struct msm_iommu_ctx_dev *master;
> + int sid;
> +
> + master = kzalloc(sizeof(*master), GFP_KERNEL);
This is called with irqs disabled, but it's not GFP_ATOMIC. Please test
with DEBUG_ATOMIC_SLEEP=y.
> + master->of_node = dev->of_node;
> + list_add(&master->list, &iommu->ctx_list);
> +
> + for (sid = 0; sid < spec->args_count; sid++)
> + master->mids[sid] = spec->args[sid];
> +
> + master->num_mids = spec->args_count;
> +}
> +
> +static int qcom_iommu_of_xlate(struct device *dev,
> + struct of_phandle_args *spec)
> +{
> + struct msm_iommu_dev *iommu;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&msm_iommu_lock, flags);
> + list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
> + if (iommu->dev->of_node == spec->np)
> + break;
> + }
The braces are unnecessary here.
> +
> + if (!iommu || (iommu->dev->of_node != spec->np))
Please remove extraneous parentheses.
> + return -ENODEV;
> +
> + insert_iommu_master(dev, iommu, spec);
> + spin_unlock_irqrestore(&msm_iommu_lock, flags);
> +
> + return 0;
> +}
> +
> irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
> {
> struct msm_iommu_dev *iommu = dev_id;
> @@ -737,7 +776,7 @@ fail:
> return 0;
> }
>
> -static const struct iommu_ops msm_iommu_ops = {
> +static struct iommu_ops msm_iommu_ops = {
Is there a reason why we can't make of_iommu_set_ops() take a const ops
pointer?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/5] iommu/msm: Add support for generic master bindings
Date: Wed, 12 Aug 2015 12:11:57 -0700 [thread overview]
Message-ID: <55CB9A7D.7080206@codeaurora.org> (raw)
In-Reply-To: <1439390869-6347-4-git-send-email-sricharan@codeaurora.org>
On 08/12/2015 07:47 AM, Sricharan R wrote:
> @@ -702,6 +703,44 @@ static void print_ctx_regs(void __iomem *base, int ctx)
> GET_PRRR(base, ctx), GET_NMRR(base, ctx));
> }
>
> +static void insert_iommu_master(struct device *dev,
> + struct msm_iommu_dev *iommu,
> + struct of_phandle_args *spec)
> +{
> + struct msm_iommu_ctx_dev *master;
> + int sid;
> +
> + master = kzalloc(sizeof(*master), GFP_KERNEL);
This is called with irqs disabled, but it's not GFP_ATOMIC. Please test
with DEBUG_ATOMIC_SLEEP=y.
> + master->of_node = dev->of_node;
> + list_add(&master->list, &iommu->ctx_list);
> +
> + for (sid = 0; sid < spec->args_count; sid++)
> + master->mids[sid] = spec->args[sid];
> +
> + master->num_mids = spec->args_count;
> +}
> +
> +static int qcom_iommu_of_xlate(struct device *dev,
> + struct of_phandle_args *spec)
> +{
> + struct msm_iommu_dev *iommu;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&msm_iommu_lock, flags);
> + list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
> + if (iommu->dev->of_node == spec->np)
> + break;
> + }
The braces are unnecessary here.
> +
> + if (!iommu || (iommu->dev->of_node != spec->np))
Please remove extraneous parentheses.
> + return -ENODEV;
> +
> + insert_iommu_master(dev, iommu, spec);
> + spin_unlock_irqrestore(&msm_iommu_lock, flags);
> +
> + return 0;
> +}
> +
> irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
> {
> struct msm_iommu_dev *iommu = dev_id;
> @@ -737,7 +776,7 @@ fail:
> return 0;
> }
>
> -static const struct iommu_ops msm_iommu_ops = {
> +static struct iommu_ops msm_iommu_ops = {
Is there a reason why we can't make of_iommu_set_ops() take a const ops
pointer?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-08-12 19:12 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-12 14:47 [PATCH 0/5] iommu/msm: Add DT adaptation and generic bindings support Sricharan R
2015-08-12 14:47 ` Sricharan R
2015-08-12 14:47 ` [PATCH 1/5] iommu/msm: Add DT adaptation Sricharan R
2015-08-12 14:47 ` Sricharan R
2015-08-12 14:47 ` [PATCH 2/5] iommu/msm: Move the contents from msm_iommu_dev.c to msm_iommu.c Sricharan R
2015-08-12 14:47 ` Sricharan R
[not found] ` <1439390869-6347-1-git-send-email-sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2015-08-12 14:47 ` [PATCH 3/5] iommu/msm: Add support for generic master bindings Sricharan R
2015-08-12 14:47 ` Sricharan R
2015-08-12 19:11 ` Stephen Boyd [this message]
2015-08-12 19:11 ` Stephen Boyd
[not found] ` <55CB9A7D.7080206-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2015-08-13 8:09 ` Sricharan
2015-08-13 8:09 ` Sricharan
2015-08-12 14:47 ` [PATCH 4/5] iommu/msm: Set cacheability attributes without tex remap Sricharan R
2015-08-12 14:47 ` Sricharan R
2015-08-12 14:53 ` Will Deacon
2015-08-12 14:53 ` Will Deacon
2015-08-13 6:37 ` Sricharan
2015-08-13 6:37 ` Sricharan
2015-08-12 14:47 ` [PATCH 5/5] iommu/msm: Remove driver BROKEN Sricharan R
2015-08-12 14:47 ` Sricharan R
2015-08-14 9:30 ` [PATCH 0/5] iommu/msm: Add DT adaptation and generic bindings support Srinivas Kandagatla
2015-08-14 9:30 ` Srinivas Kandagatla
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