* [U-Boot] [PATCH 5/5] dra7xx: Add dra72_evm_defconfig using CONFIG_DM
2015-07-31 23:55 [U-Boot] [PATCH 1/5] am33xx: Update DT files, add am335x_gp_evm_config target Tom Rini
` (2 preceding siblings ...)
2015-07-31 23:55 ` [U-Boot] [PATCH 4/5] dra7xx: Move CONS_INDEX to Kconfig and enable CONFIG_SPL_STACK_ADDR Tom Rini
@ 2015-07-31 23:55 ` Tom Rini
2015-08-02 21:29 ` Simon Glass
2015-08-13 13:22 ` [U-Boot] [U-Boot, " Tom Rini
2015-08-13 13:22 ` [U-Boot] [U-Boot, 1/5] am33xx: Update DT files, add am335x_gp_evm_config target Tom Rini
4 siblings, 2 replies; 15+ messages in thread
From: Tom Rini @ 2015-07-31 23:55 UTC (permalink / raw)
To: u-boot
- Import various DT files for DRA7 / DR72x / dra72-evm from Linux Kernel
v4.1
- Add config file for this board, enable DM and DM_GPIO
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
For some reason I can't yet figure out, enabling CONFIG_DM_SERIAL seems
to be triggering the no console panic failure path, but I can't seem to
figure out why.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/dra7.dtsi | 1529 ++++++++++++++++++++++++
arch/arm/dts/dra72-evm.dts | 683 +++++++++++
arch/arm/dts/dra72x.dtsi | 47 +
arch/arm/dts/dra7xx-clocks.dtsi | 2149 ++++++++++++++++++++++++++++++++++
arch/arm/dts/omap4-cpu-thermal.dtsi | 41 +
arch/arm/dts/omap5-core-thermal.dtsi | 28 +
arch/arm/dts/omap5-gpu-thermal.dtsi | 28 +
configs/dra72_evm_defconfig | 17 +
drivers/serial/serial_omap.c | 1 +
include/dt-bindings/pinctrl/dra.h | 51 +
11 files changed, 4575 insertions(+)
create mode 100644 arch/arm/dts/dra7.dtsi
create mode 100644 arch/arm/dts/dra72-evm.dts
create mode 100644 arch/arm/dts/dra72x.dtsi
create mode 100644 arch/arm/dts/dra7xx-clocks.dtsi
create mode 100644 arch/arm/dts/omap4-cpu-thermal.dtsi
create mode 100644 arch/arm/dts/omap5-core-thermal.dtsi
create mode 100644 arch/arm/dts/omap5-gpu-thermal.dtsi
create mode 100644 configs/dra72_evm_defconfig
create mode 100644 include/dt-bindings/pinctrl/dra.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 43b1616..ca5e444 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -55,6 +55,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_socrates.dtb
+dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
new file mode 100644
index 0000000..8f1e25b
--- /dev/null
+++ b/arch/arm/dts/dra7.dtsi
@@ -0,0 +1,1529 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/dra.h>
+
+#include "skeleton.dtsi"
+
+#define MAX_SOURCES 400
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "ti,dra7xx";
+ interrupt-parent = <&crossbar_mpu>;
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ i2c4 = &i2c5;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ serial6 = &uart7;
+ serial7 = &uart8;
+ serial8 = &uart9;
+ serial9 = &uart10;
+ ethernet0 = &cpsw_emac0;
+ ethernet1 = &cpsw_emac1;
+ d_can0 = &dcan1;
+ d_can1 = &dcan2;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&gic>;
+ };
+
+ gic: interrupt-controller at 48211000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48211000 0x1000>,
+ <0x48212000 0x1000>,
+ <0x48214000 0x2000>,
+ <0x48216000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-parent = <&gic>;
+ };
+
+ wakeupgen: interrupt-controller at 48281000 {
+ compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48281000 0x1000>;
+ interrupt-parent = <&gic>;
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is used for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap5-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the SOC interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since it will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,dra7-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main_1", "l3_main_2";
+ reg = <0x44000000 0x1000000>,
+ <0x45000000 0x1000>;
+ interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ l4_cfg: l4 at 4a000000 {
+ compatible = "ti,dra7-l4-cfg", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4a000000 0x22c000>;
+
+ scm: scm at 2000 {
+ compatible = "ti,dra7-scm-core", "simple-bus";
+ reg = <0x2000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2000 0x2000>;
+
+ scm_conf: scm_conf at 0 {
+ compatible = "syscon";
+ reg = <0x0 0x1400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pbias_regulator: pbias_regulator {
+ compatible = "ti,pbias-omap";
+ reg = <0xe00 0x4>;
+ syscon = <&scm_conf>;
+ pbias_mmc_reg: pbias_mmc_omap5 {
+ regulator-name = "pbias_mmc_omap5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ };
+
+ scm_conf_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ dra7_pmx_core: pinmux at 1400 {
+ compatible = "ti,dra7-padconf",
+ "pinctrl-single";
+ reg = <0x1400 0x0464>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x3fffffff>;
+ };
+ };
+
+ cm_core_aon: cm_core_aon at 5000 {
+ compatible = "ti,dra7-cm-core-aon";
+ reg = <0x5000 0x2000>;
+
+ cm_core_aon_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_core_aon_clockdomains: clockdomains {
+ };
+ };
+
+ cm_core: cm_core at 8000 {
+ compatible = "ti,dra7-cm-core";
+ reg = <0x8000 0x3000>;
+
+ cm_core_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cm_core_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ l4_wkup: l4 at 4ae00000 {
+ compatible = "ti,dra7-l4-wkup", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4ae00000 0x3f000>;
+
+ counter32k: counter at 4000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x4000 0x40>;
+ ti,hwmods = "counter_32k";
+ };
+
+ prm: prm at 6000 {
+ compatible = "ti,dra7-prm";
+ reg = <0x6000 0x3000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+ prm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ axi at 0 {
+ compatible = "simple-bus";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges = <0x51000000 0x51000000 0x3000
+ 0x0 0x20000000 0x10000000>;
+ pcie at 51000000 {
+ compatible = "ti,dra7-pcie";
+ reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
+ reg-names = "rc_dbics", "ti_conf", "config";
+ interrupts = <0 232 0x4>, <0 233 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0 0x03000 0 0x00010000
+ 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ ti,hwmods = "pcie1";
+ phys = <&pcie1_phy>;
+ phy-names = "pcie-phy0";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 1>,
+ <0 0 0 2 &pcie1_intc 2>,
+ <0 0 0 3 &pcie1_intc 3>,
+ <0 0 0 4 &pcie1_intc 4>;
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ axi at 1 {
+ compatible = "simple-bus";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges = <0x51800000 0x51800000 0x3000
+ 0x0 0x30000000 0x10000000>;
+ status = "disabled";
+ pcie at 51000000 {
+ compatible = "ti,dra7-pcie";
+ reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
+ reg-names = "rc_dbics", "ti_conf", "config";
+ interrupts = <0 355 0x4>, <0 356 0x4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0 0x03000 0 0x00010000
+ 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
+ #interrupt-cells = <1>;
+ num-lanes = <1>;
+ ti,hwmods = "pcie2";
+ phys = <&pcie2_phy>;
+ phy-names = "pcie-phy0";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2_intc 1>,
+ <0 0 0 2 &pcie2_intc 2>,
+ <0 0 0 3 &pcie2_intc 3>,
+ <0 0 0 4 &pcie2_intc 4>;
+ pcie2_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ bandgap: bandgap at 4a0021e0 {
+ reg = <0x4a0021e0 0xc
+ 0x4a00232c 0xc
+ 0x4a002380 0x2c
+ 0x4a0023C0 0x3c
+ 0x4a002564 0x8
+ 0x4a002574 0x50>;
+ compatible = "ti,dra752-bandgap";
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ dra7_ctrl_core: ctrl_core at 4a002000 {
+ compatible = "syscon";
+ reg = <0x4a002000 0x6d0>;
+ };
+
+ dra7_ctrl_general: tisyscon at 4a002e00 {
+ compatible = "syscon";
+ reg = <0x4a002e00 0x7c>;
+ };
+
+ sdma: dma-controller at 4a056000 {
+ compatible = "ti,omap4430-sdma";
+ reg = <0x4a056000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <127>;
+ };
+
+ gpio1: gpio at 4ae10000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4ae10000 0x200>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 48055000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48055000 0x200>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio at 48057000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48057000 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio at 48059000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48059000 0x200>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio at 4805b000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805b000 0x200>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio5";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio at 4805d000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805d000 0x200>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio6";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio7: gpio at 48051000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48051000 0x200>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio7";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio8: gpio at 48053000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48053000 0x200>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "gpio8";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ uart1: serial at 4806a000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806a000 0x100>;
+ interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma 49>, <&sdma 50>;
+ dma-names = "tx", "rx";
+ };
+
+ uart2: serial at 4806c000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806c000 0x100>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma 51>, <&sdma 52>;
+ dma-names = "tx", "rx";
+ };
+
+ uart3: serial at 48020000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48020000 0x100>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma 53>, <&sdma 54>;
+ dma-names = "tx", "rx";
+ };
+
+ uart4: serial at 4806e000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806e000 0x100>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma 55>, <&sdma 56>;
+ dma-names = "tx", "rx";
+ };
+
+ uart5: serial at 48066000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48066000 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart5";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma 63>, <&sdma 64>;
+ dma-names = "tx", "rx";
+ };
+
+ uart6: serial at 48068000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48068000 0x100>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart6";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ dmas = <&sdma 79>, <&sdma 80>;
+ dma-names = "tx", "rx";
+ };
+
+ uart7: serial at 48420000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48420000 0x100>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart7";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart8: serial at 48422000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48422000 0x100>;
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart8";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart9: serial at 48424000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48424000 0x100>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart9";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ uart10: serial at 4ae2b000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4ae2b000 0x100>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "uart10";
+ clock-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ mailbox1: mailbox at 4a0f4000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4a0f4000 0x200>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox1";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <3>;
+ ti,mbox-num-fifos = <8>;
+ status = "disabled";
+ };
+
+ mailbox2: mailbox at 4883a000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4883a000 0x200>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox2";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox3: mailbox at 4883c000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4883c000 0x200>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox3";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox4: mailbox at 4883e000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4883e000 0x200>;
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox4";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox5: mailbox at 48840000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48840000 0x200>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox5";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox6: mailbox at 48842000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48842000 0x200>;
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox6";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox7: mailbox at 48844000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48844000 0x200>;
+ interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox7";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox8: mailbox at 48846000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48846000 0x200>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox8";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox9: mailbox at 4885e000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4885e000 0x200>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox9";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox10: mailbox at 48860000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48860000 0x200>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox10";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox11: mailbox at 48862000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48862000 0x200>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox11";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox12: mailbox at 48864000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48864000 0x200>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox12";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ mailbox13: mailbox at 48802000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x48802000 0x200>;
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mailbox13";
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <12>;
+ status = "disabled";
+ };
+
+ timer1: timer at 4ae18000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4ae18000 0x80>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer at 48032000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48032000 0x80>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer at 48034000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48034000 0x80>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer at 48036000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48036000 0x80>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer4";
+ };
+
+ timer5: timer at 48820000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48820000 0x80>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer5";
+ };
+
+ timer6: timer at 48822000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48822000 0x80>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer6";
+ };
+
+ timer7: timer at 48824000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48824000 0x80>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer7";
+ };
+
+ timer8: timer at 48826000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48826000 0x80>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer8";
+ };
+
+ timer9: timer at 4803e000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4803e000 0x80>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer9";
+ };
+
+ timer10: timer at 48086000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48086000 0x80>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer10";
+ };
+
+ timer11: timer at 48088000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48088000 0x80>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer11";
+ };
+
+ timer13: timer at 48828000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x48828000 0x80>;
+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer13";
+ status = "disabled";
+ };
+
+ timer14: timer at 4882a000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4882a000 0x80>;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer14";
+ status = "disabled";
+ };
+
+ timer15: timer at 4882c000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4882c000 0x80>;
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer15";
+ status = "disabled";
+ };
+
+ timer16: timer at 4882e000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x4882e000 0x80>;
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "timer16";
+ status = "disabled";
+ };
+
+ wdt2: wdt at 4ae14000 {
+ compatible = "ti,omap3-wdt";
+ reg = <0x4ae14000 0x80>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "wd_timer2";
+ };
+
+ hwspinlock: spinlock at 4a0f6000 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x4a0f6000 0x1000>;
+ ti,hwmods = "spinlock";
+ #hwlock-cells = <1>;
+ };
+
+ dmm at 4e000000 {
+ compatible = "ti,omap5-dmm";
+ reg = <0x4e000000 0x800>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "dmm";
+ };
+
+ i2c1: i2c at 48070000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48070000 0x100>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ status = "disabled";
+ };
+
+ i2c2: i2c at 48072000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48072000 0x100>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ status = "disabled";
+ };
+
+ i2c3: i2c at 48060000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48060000 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ status = "disabled";
+ };
+
+ i2c4: i2c at 4807a000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807a000 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c4";
+ status = "disabled";
+ };
+
+ i2c5: i2c at 4807c000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807c000 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c5";
+ status = "disabled";
+ };
+
+ mmc1: mmc at 4809c000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x4809c000 0x400>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ ti,needs-special-reset;
+ dmas = <&sdma 61>, <&sdma 62>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ pbias-supply = <&pbias_mmc_reg>;
+ };
+
+ mmc2: mmc at 480b4000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480b4000 0x400>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmc2";
+ ti,needs-special-reset;
+ dmas = <&sdma 47>, <&sdma 48>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ mmc3: mmc at 480ad000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480ad000 0x400>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmc3";
+ ti,needs-special-reset;
+ dmas = <&sdma 77>, <&sdma 78>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ mmc4: mmc at 480d1000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480d1000 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmc4";
+ ti,needs-special-reset;
+ dmas = <&sdma 57>, <&sdma 58>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ abb_mpu: regulator-abb-mpu {
+ compatible = "ti,abb-v3";
+ regulator-name = "abb_mpu";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin1>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
+ <0x4ae06014 0x4>, <0x4a003b20 0xc>,
+ <0x4ae0c158 0x4>;
+ reg-names = "setup-address", "control-address",
+ "int-address", "efuse-address",
+ "ldo-address";
+ ti,tranxdone-status-mask = <0x80>;
+ /* LDOVBBMPU_FBB_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBMPU_FBB_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1060000 0 0x0 0 0x02000000 0x01F00000
+ 1160000 0 0x4 0 0x02000000 0x01F00000
+ 1210000 0 0x8 0 0x02000000 0x01F00000
+ >;
+ };
+
+ abb_ivahd: regulator-abb-ivahd {
+ compatible = "ti,abb-v3";
+ regulator-name = "abb_ivahd";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin1>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
+ <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
+ <0x4a002470 0x4>;
+ reg-names = "setup-address", "control-address",
+ "int-address", "efuse-address",
+ "ldo-address";
+ ti,tranxdone-status-mask = <0x40000000>;
+ /* LDOVBBIVA_FBB_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBIVA_FBB_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1055000 0 0x0 0 0x02000000 0x01F00000
+ 1150000 0 0x4 0 0x02000000 0x01F00000
+ 1250000 0 0x8 0 0x02000000 0x01F00000
+ >;
+ };
+
+ abb_dspeve: regulator-abb-dspeve {
+ compatible = "ti,abb-v3";
+ regulator-name = "abb_dspeve";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin1>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
+ <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
+ <0x4a00246c 0x4>;
+ reg-names = "setup-address", "control-address",
+ "int-address", "efuse-address",
+ "ldo-address";
+ ti,tranxdone-status-mask = <0x20000000>;
+ /* LDOVBBDSPEVE_FBB_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBDSPEVE_FBB_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1055000 0 0x0 0 0x02000000 0x01F00000
+ 1150000 0 0x4 0 0x02000000 0x01F00000
+ 1250000 0 0x8 0 0x02000000 0x01F00000
+ >;
+ };
+
+ abb_gpu: regulator-abb-gpu {
+ compatible = "ti,abb-v3";
+ regulator-name = "abb_gpu";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ clocks = <&sys_clkin1>;
+ ti,settling-time = <50>;
+ ti,clock-cycles = <16>;
+
+ reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
+ <0x4ae06010 0x4>, <0x4a003b08 0xc>,
+ <0x4ae0c154 0x4>;
+ reg-names = "setup-address", "control-address",
+ "int-address", "efuse-address",
+ "ldo-address";
+ ti,tranxdone-status-mask = <0x10000000>;
+ /* LDOVBBGPU_FBB_MUX_CTRL */
+ ti,ldovbb-override-mask = <0x400>;
+ /* LDOVBBGPU_FBB_VSET_OUT */
+ ti,ldovbb-vset-mask = <0x1F>;
+
+ /*
+ * NOTE: only FBB mode used but actual vset will
+ * determine final biasing
+ */
+ ti,abb_info = <
+ /*uV ABB efuse rbb_m fbb_m vset_m*/
+ 1090000 0 0x0 0 0x02000000 0x01F00000
+ 1210000 0 0x4 0 0x02000000 0x01F00000
+ 1280000 0 0x8 0 0x02000000 0x01F00000
+ >;
+ };
+
+ mcspi1: spi at 48098000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x48098000 0x200>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi1";
+ ti,spi-num-cs = <4>;
+ dmas = <&sdma 35>,
+ <&sdma 36>,
+ <&sdma 37>,
+ <&sdma 38>,
+ <&sdma 39>,
+ <&sdma 40>,
+ <&sdma 41>,
+ <&sdma 42>;
+ dma-names = "tx0", "rx0", "tx1", "rx1",
+ "tx2", "rx2", "tx3", "rx3";
+ status = "disabled";
+ };
+
+ mcspi2: spi at 4809a000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x4809a000 0x200>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi2";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 43>,
+ <&sdma 44>,
+ <&sdma 45>,
+ <&sdma 46>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ status = "disabled";
+ };
+
+ mcspi3: spi at 480b8000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x480b8000 0x200>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi3";
+ ti,spi-num-cs = <2>;
+ dmas = <&sdma 15>, <&sdma 16>;
+ dma-names = "tx0", "rx0";
+ status = "disabled";
+ };
+
+ mcspi4: spi at 480ba000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x480ba000 0x200>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "mcspi4";
+ ti,spi-num-cs = <1>;
+ dmas = <&sdma 70>, <&sdma 71>;
+ dma-names = "tx0", "rx0";
+ status = "disabled";
+ };
+
+ qspi: qspi at 4b300000 {
+ compatible = "ti,dra7xxx-qspi";
+ reg = <0x4b300000 0x100>;
+ reg-names = "qspi_base";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "qspi";
+ clocks = <&qspi_gfclk_div>;
+ clock-names = "fck";
+ num-cs = <4>;
+ interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ omap_control_sata: control-phy at 4a002374 {
+ compatible = "ti,control-phy-pipe3";
+ reg = <0x4a002374 0x4>;
+ reg-names = "power";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ };
+
+ /* OCP2SCP3 */
+ ocp2scp at 4a090000 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0x4a090000 0x20>;
+ ti,hwmods = "ocp2scp3";
+ sata_phy: phy at 4A096000 {
+ compatible = "ti,phy-pipe3-sata";
+ reg = <0x4A096000 0x80>, /* phy_rx */
+ <0x4A096400 0x64>, /* phy_tx */
+ <0x4A096800 0x40>; /* pll_ctrl */
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ ctrl-module = <&omap_control_sata>;
+ clocks = <&sys_clkin1>, <&sata_ref_clk>;
+ clock-names = "sysclk", "refclk";
+ #phy-cells = <0>;
+ };
+
+ pcie1_phy: pciephy at 4a094000 {
+ compatible = "ti,phy-pipe3-pcie";
+ reg = <0x4a094000 0x80>, /* phy_rx */
+ <0x4a094400 0x64>; /* phy_tx */
+ reg-names = "phy_rx", "phy_tx";
+ ctrl-module = <&omap_control_pcie1phy>;
+ clocks = <&dpll_pcie_ref_ck>,
+ <&dpll_pcie_ref_m2ldo_ck>,
+ <&optfclk_pciephy1_32khz>,
+ <&optfclk_pciephy1_clk>,
+ <&optfclk_pciephy1_div_clk>,
+ <&optfclk_pciephy_div>;
+ clock-names = "dpll_ref", "dpll_ref_m2",
+ "wkupclk", "refclk",
+ "div-clk", "phy-div";
+ #phy-cells = <0>;
+ };
+
+ pcie2_phy: pciephy at 4a095000 {
+ compatible = "ti,phy-pipe3-pcie";
+ reg = <0x4a095000 0x80>, /* phy_rx */
+ <0x4a095400 0x64>; /* phy_tx */
+ reg-names = "phy_rx", "phy_tx";
+ ctrl-module = <&omap_control_pcie2phy>;
+ clocks = <&dpll_pcie_ref_ck>,
+ <&dpll_pcie_ref_m2ldo_ck>,
+ <&optfclk_pciephy2_32khz>,
+ <&optfclk_pciephy2_clk>,
+ <&optfclk_pciephy2_div_clk>,
+ <&optfclk_pciephy_div>;
+ clock-names = "dpll_ref", "dpll_ref_m2",
+ "wkupclk", "refclk",
+ "div-clk", "phy-div";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ sata: sata at 4a141100 {
+ compatible = "snps,dwc-ahci";
+ reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
+ clocks = <&sata_ref_clk>;
+ ti,hwmods = "sata";
+ };
+
+ omap_control_pcie1phy: control-phy at 0x4a003c40 {
+ compatible = "ti,control-phy-pcie";
+ reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
+ reg-names = "power", "control_sma", "pcie_pcs";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ };
+
+ omap_control_pcie2phy: control-pcie at 0x4a003c44 {
+ compatible = "ti,control-phy-pcie";
+ reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
+ reg-names = "power", "control_sma", "pcie_pcs";
+ clocks = <&sys_clkin1>;
+ clock-names = "sysclk";
+ status = "disabled";
+ };
+
+ rtc: rtc at 48838000 {
+ compatible = "ti,am3352-rtc";
+ reg = <0x48838000 0x100>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "rtcss";
+ clocks = <&sys_32k_ck>;
+ };
+
+ omap_control_usb2phy1: control-phy at 4a002300 {
+ compatible = "ti,control-phy-usb2";
+ reg = <0x4a002300 0x4>;
+ reg-names = "power";
+ };
+
+ omap_control_usb3phy1: control-phy at 4a002370 {
+ compatible = "ti,control-phy-pipe3";
+ reg = <0x4a002370 0x4>;
+ reg-names = "power";
+ };
+
+ omap_control_usb2phy2: control-phy at 0x4a002e74 {
+ compatible = "ti,control-phy-usb2-dra7";
+ reg = <0x4a002e74 0x4>;
+ reg-names = "power";
+ };
+
+ /* OCP2SCP1 */
+ ocp2scp at 4a080000 {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0x4a080000 0x20>;
+ ti,hwmods = "ocp2scp1";
+
+ usb2_phy1: phy at 4a084000 {
+ compatible = "ti,omap-usb2";
+ reg = <0x4a084000 0x400>;
+ ctrl-module = <&omap_control_usb2phy1>;
+ clocks = <&usb_phy1_always_on_clk32k>,
+ <&usb_otg_ss1_refclk960m>;
+ clock-names = "wkupclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+
+ usb2_phy2: phy at 4a085000 {
+ compatible = "ti,omap-usb2";
+ reg = <0x4a085000 0x400>;
+ ctrl-module = <&omap_control_usb2phy2>;
+ clocks = <&usb_phy2_always_on_clk32k>,
+ <&usb_otg_ss2_refclk960m>;
+ clock-names = "wkupclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+
+ usb3_phy1: phy at 4a084400 {
+ compatible = "ti,omap-usb3";
+ reg = <0x4a084400 0x80>,
+ <0x4a084800 0x64>,
+ <0x4a084c00 0x40>;
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ ctrl-module = <&omap_control_usb3phy1>;
+ clocks = <&usb_phy3_always_on_clk32k>,
+ <&sys_clkin1>,
+ <&usb_otg_ss1_refclk960m>;
+ clock-names = "wkupclk",
+ "sysclk",
+ "refclk";
+ #phy-cells = <0>;
+ };
+ };
+
+ omap_dwc3_1: omap_dwc3_1 at 48880000 {
+ compatible = "ti,dwc3";
+ ti,hwmods = "usb_otg_ss1";
+ reg = <0x48880000 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ usb1: usb at 48890000 {
+ compatible = "snps,dwc3";
+ reg = <0x48890000 0x17000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy1>, <&usb3_phy1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ snps,dis_u3_susphy_quirk;
+ snps,dis_u2_susphy_quirk;
+ };
+ };
+
+ omap_dwc3_2: omap_dwc3_2 at 488c0000 {
+ compatible = "ti,dwc3";
+ ti,hwmods = "usb_otg_ss2";
+ reg = <0x488c0000 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ usb2: usb at 488d0000 {
+ compatible = "snps,dwc3";
+ reg = <0x488d0000 0x17000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy2>;
+ phy-names = "usb2-phy";
+ tx-fifo-resize;
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ snps,dis_u3_susphy_quirk;
+ snps,dis_u2_susphy_quirk;
+ };
+ };
+
+ /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
+ omap_dwc3_3: omap_dwc3_3 at 48900000 {
+ compatible = "ti,dwc3";
+ ti,hwmods = "usb_otg_ss3";
+ reg = <0x48900000 0x10000>;
+ interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ status = "disabled";
+ usb3: usb at 48910000 {
+ compatible = "snps,dwc3";
+ reg = <0x48910000 0x17000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ tx-fifo-resize;
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ snps,dis_u3_susphy_quirk;
+ snps,dis_u2_susphy_quirk;
+ };
+ };
+
+ elm: elm at 48078000 {
+ compatible = "ti,am3352-elm";
+ reg = <0x48078000 0xfc0>; /* device IO registers */
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "elm";
+ status = "disabled";
+ };
+
+ gpmc: gpmc at 50000000 {
+ compatible = "ti,am3352-gpmc";
+ ti,hwmods = "gpmc";
+ reg = <0x50000000 0x37c>; /* device IO registers */
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ gpmc,num-cs = <8>;
+ gpmc,num-waitpins = <2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
+
+ atl: atl at 4843c000 {
+ compatible = "ti,dra7-atl";
+ reg = <0x4843c000 0x3ff>;
+ ti,hwmods = "atl";
+ ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
+ <&atl_clkin2_ck>, <&atl_clkin3_ck>;
+ clocks = <&atl_gfclk_mux>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ crossbar_mpu: crossbar at 4a002a48 {
+ compatible = "ti,irq-crossbar";
+ reg = <0x4a002a48 0x130>;
+ interrupt-controller;
+ interrupt-parent = <&wakeupgen>;
+ #interrupt-cells = <3>;
+ ti,max-irqs = <160>;
+ ti,max-crossbar-sources = <MAX_SOURCES>;
+ ti,reg-size = <2>;
+ ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
+ ti,irqs-skip = <10 133 139 140>;
+ ti,irqs-safe-map = <0>;
+ };
+
+ mac: ethernet at 4a100000 {
+ compatible = "ti,cpsw";
+ ti,hwmods = "gmac";
+ clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
+ clock-names = "fck", "cpts";
+ cpdma_channels = <8>;
+ ale_entries = <1024>;
+ bd_ram_size = <0x2000>;
+ no_bd_ram = <0>;
+ rx_descs = <64>;
+ mac_control = <0x20>;
+ slaves = <2>;
+ active_slave = <0>;
+ cpts_clock_mult = <0x80000000>;
+ cpts_clock_shift = <29>;
+ reg = <0x48484000 0x1000
+ 0x48485200 0x2E00>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * rx_thresh_pend
+ * rx_pend
+ * tx_pend
+ * misc_pend
+ */
+ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ status = "disabled";
+
+ davinci_mdio: mdio at 48485000 {
+ compatible = "ti,davinci_mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "davinci_mdio";
+ bus_freq = <1000000>;
+ reg = <0x48485000 0x100>;
+ };
+
+ cpsw_emac0: slave at 48480200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ cpsw_emac1: slave at 48480300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ phy_sel: cpsw-phy-sel at 4a002554 {
+ compatible = "ti,dra7xx-cpsw-phy-sel";
+ reg= <0x4a002554 0x4>;
+ reg-names = "gmii-sel";
+ };
+ };
+
+ dcan1: can at 481cc000 {
+ compatible = "ti,dra7-d_can";
+ ti,hwmods = "dcan1";
+ reg = <0x4ae3c000 0x2000>;
+ syscon-raminit = <&scm_conf 0x558 0>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dcan1_sys_clk_mux>;
+ status = "disabled";
+ };
+
+ dcan2: can at 481d0000 {
+ compatible = "ti,dra7-d_can";
+ ti,hwmods = "dcan2";
+ reg = <0x48480000 0x2000>;
+ syscon-raminit = <&scm_conf 0x558 1>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clkin1>;
+ status = "disabled";
+ };
+
+ dss: dss at 58000000 {
+ compatible = "ti,dra7-dss";
+ /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
+ /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
+ status = "disabled";
+ ti,hwmods = "dss_core";
+ /* CTRL_CORE_DSS_PLL_CONTROL */
+ syscon-pll-ctrl = <&scm_conf 0x538>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dispc at 58001000 {
+ compatible = "ti,dra7-dispc";
+ reg = <0x58001000 0x1000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "dss_dispc";
+ clocks = <&dss_dss_clk>;
+ clock-names = "fck";
+ /* CTRL_CORE_SMA_SW_1 */
+ syscon-pol = <&scm_conf 0x534>;
+ };
+
+ hdmi: encoder at 58060000 {
+ compatible = "ti,dra7-hdmi";
+ reg = <0x58040000 0x200>,
+ <0x58040200 0x80>,
+ <0x58040300 0x80>,
+ <0x58060000 0x19000>;
+ reg-names = "wp", "pll", "phy", "core";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ ti,hwmods = "dss_hdmi";
+ clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
+ clock-names = "fck", "sys_clk";
+ };
+ };
+ };
+
+ thermal_zones: thermal-zones {
+ #include "omap4-cpu-thermal.dtsi"
+ #include "omap5-gpu-thermal.dtsi"
+ #include "omap5-core-thermal.dtsi"
+ };
+
+};
+
+&cpu_thermal {
+ polling-delay = <500>; /* milliseconds */
+};
+
+/include/ "dra7xx-clocks.dtsi"
diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts
new file mode 100644
index 0000000..efb544c
--- /dev/null
+++ b/arch/arm/dts/dra72-evm.dts
@@ -0,0 +1,683 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dra72x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "TI DRA722";
+ compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>; /* 1024 MB */
+ };
+
+ aliases {
+ display0 = &hdmi0;
+ };
+
+ evm_3v3: fixedregulator-evm_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ extcon_usb2: extcon_usb2 {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ tpd12s015: encoder {
+ compatible = "ti,tpd12s015";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tpd12s015_pins>;
+
+ gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
+ <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+};
+
+&dra7_pmx_core {
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
+ 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
+ >;
+ };
+
+ i2c5_pins: pinmux_i2c5_pins {
+ pinctrl-single,pins = <
+ 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
+ 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
+ >;
+ };
+
+ nand_default: nand_default {
+ pinctrl-single,pins = <
+ 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
+ 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
+ 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
+ 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
+ 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
+ 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
+ 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
+ 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
+ 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
+ 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
+ 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
+ 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
+ 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
+ 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
+ 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
+ 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
+ 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
+ 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
+ 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
+ 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
+ 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
+ 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
+ >;
+ };
+
+ usb1_pins: pinmux_usb1_pins {
+ pinctrl-single,pins = <
+ 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+ >;
+ };
+
+ usb2_pins: pinmux_usb2_pins {
+ pinctrl-single,pins = <
+ 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
+ >;
+ };
+
+ tps65917_pins_default: tps65917_pins_default {
+ pinctrl-single,pins = <
+ 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
+ >;
+ };
+
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
+ 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ dcan1_pins_default: dcan1_pins_default {
+ pinctrl-single,pins = <
+ 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
+ 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
+ >;
+ };
+
+ dcan1_pins_sleep: dcan1_pins_sleep {
+ pinctrl-single,pins = <
+ 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
+ 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
+ >;
+ };
+
+ qspi1_pins: pinmux_qspi1_pins {
+ pinctrl-single,pins = <
+ 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
+ 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
+ 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
+ 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+ 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
+ 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
+ 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
+ >;
+ };
+
+ hdmi_pins: pinmux_hdmi_pins {
+ pinctrl-single,pins = <
+ 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
+ 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
+ >;
+ };
+
+ tpd12s015_pins: pinmux_tpd12s015_pins {
+ pinctrl-single,pins = <
+ 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
+ >;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+
+ tps65917: tps65917 at 58 {
+ compatible = "ti,tps65917";
+ reg = <0x58>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tps65917_pins_default>;
+
+ interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ti,system-power-controller;
+
+ tps65917_pmic {
+ compatible = "ti,tps65917-pmic";
+
+ regulators {
+ smps1_reg: smps1 {
+ /* VDD_MPU */
+ regulator-name = "smps1";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps2_reg: smps2 {
+ /* VDD_CORE */
+ regulator-name = "smps2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1060000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps3_reg: smps3 {
+ /* VDD_GPU IVA DSPEVE */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ smps4_reg: smps4 {
+ /* VDDS1V8 */
+ regulator-name = "smps4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps5_reg: smps5 {
+ /* VDD_DDR */
+ regulator-name = "smps5";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ /* LDO1_OUT --> SDIO */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+ ldo2_reg: ldo2 {
+ /* LDO2_OUT --> TP1017 (UNUSED) */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo3_reg: ldo3 {
+ /* VDDA_1V8_PHY */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ tps65917_power_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps65917>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <6>;
+ };
+ };
+
+ pcf_gpio_21: gpio at 21 {
+ compatible = "ti,pcf8575";
+ reg = <0x21>;
+ lines-initial-states = <0x1408>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ clock-frequency = <400000>;
+
+ pcf_hdmi: pcf8575 at 26 {
+ compatible = "nxp,pcf8575";
+ reg = <0x26>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * initial state is used here to keep the mdio interface
+ * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
+ * VIN2_S0 driven high otherwise Ethernet stops working
+ * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
+ */
+ lines-initial-states = <0x0f2b>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&elm {
+ status = "okay";
+};
+
+&gpmc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_default>;
+ ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
+ nand at 0,0 {
+ /* To use NAND, DIP switch SW5 must be set like so:
+ * SW5.1 (NAND_SELn) = ON (LOW)
+ * SW5.9 (GPMC_WPN) = OFF (HIGH)
+ */
+ reg = <0 0 4>; /* device IO registers */
+ ti,nand-ecc-opt = "bch8";
+ ti,elm-id = <&elm>;
+ nand-bus-width = <16>;
+ gpmc,device-width = <2>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <80>;
+ gpmc,cs-wr-off-ns = <80>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <60>;
+ gpmc,adv-wr-off-ns = <60>;
+ gpmc,we-on-ns = <10>;
+ gpmc,we-off-ns = <50>;
+ gpmc,oe-on-ns = <4>;
+ gpmc,oe-off-ns = <40>;
+ gpmc,access-ns = <40>;
+ gpmc,wr-access-ns = <80>;
+ gpmc,rd-cycle-ns = <80>;
+ gpmc,wr-cycle-ns = <80>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wait-monitoring-ns = <0>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+ * which can be independently programmable. For
+ * NAND flash this is equal to size of erase-block */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition at 0 {
+ label = "NAND.SPL";
+ reg = <0x00000000 0x000020000>;
+ };
+ partition at 1 {
+ label = "NAND.SPL.backup1";
+ reg = <0x00020000 0x00020000>;
+ };
+ partition at 2 {
+ label = "NAND.SPL.backup2";
+ reg = <0x00040000 0x00020000>;
+ };
+ partition at 3 {
+ label = "NAND.SPL.backup3";
+ reg = <0x00060000 0x00020000>;
+ };
+ partition at 4 {
+ label = "NAND.u-boot-spl-os";
+ reg = <0x00080000 0x00040000>;
+ };
+ partition at 5 {
+ label = "NAND.u-boot";
+ reg = <0x000c0000 0x00100000>;
+ };
+ partition at 6 {
+ label = "NAND.u-boot-env";
+ reg = <0x001c0000 0x00020000>;
+ };
+ partition at 7 {
+ label = "NAND.u-boot-env.backup1";
+ reg = <0x001e0000 0x00020000>;
+ };
+ partition at 8 {
+ label = "NAND.kernel";
+ reg = <0x00200000 0x00800000>;
+ };
+ partition at 9 {
+ label = "NAND.file-system";
+ reg = <0x00a00000 0x0f600000>;
+ };
+ };
+};
+
+&usb2_phy1 {
+ phy-supply = <&ldo4_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldo4_reg>;
+};
+
+&omap_dwc3_1 {
+ extcon = <&extcon_usb1>;
+};
+
+&omap_dwc3_2 {
+ extcon = <&extcon_usb2>;
+};
+
+&usb1 {
+ dr_mode = "peripheral";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins>;
+};
+
+&usb2 {
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_pins>;
+};
+
+&mmc1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+
+ vmmc-supply = <&ldo1_reg>;
+ bus-width = <4>;
+ /*
+ * SDCD signal is not being used here - using the fact that GPIO mode
+ * is a viable alternative
+ */
+ cd-gpios = <&gpio6 27 0>;
+};
+
+&mmc2 {
+ /* SW5-3 in ON position */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_default>;
+
+ vmmc-supply = <&evm_3v3>;
+ bus-width = <8>;
+ ti,non-removable;
+};
+
+&dra7_pmx_core {
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 2 */
+ 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
+ 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
+ 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
+ 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
+ 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
+ 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
+ 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
+ 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
+ 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
+ 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
+ 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
+ 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
+ >;
+
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 2 */
+ 0x198 (MUX_MODE15)
+ 0x19c (MUX_MODE15)
+ 0x1a0 (MUX_MODE15)
+ 0x1a4 (MUX_MODE15)
+ 0x1a8 (MUX_MODE15)
+ 0x1ac (MUX_MODE15)
+ 0x1b0 (MUX_MODE15)
+ 0x1b4 (MUX_MODE15)
+ 0x1b8 (MUX_MODE15)
+ 0x1bc (MUX_MODE15)
+ 0x1c0 (MUX_MODE15)
+ 0x1c4 (MUX_MODE15)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
+ 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ 0x23c (MUX_MODE15)
+ 0x240 (MUX_MODE15)
+ >;
+ };
+};
+
+&mac {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rgmii";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+ active_slave = <1>;
+};
+
+&dcan1 {
+ status = "ok";
+ pinctrl-names = "default", "sleep", "active";
+ pinctrl-0 = <&dcan1_pins_sleep>;
+ pinctrl-1 = <&dcan1_pins_sleep>;
+ pinctrl-2 = <&dcan1_pins_default>;
+};
+
+&qspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi1_pins>;
+
+ spi-max-frequency = <48000000>;
+ m25p80 at 0 {
+ compatible = "s25fl256s1";
+ spi-max-frequency = <48000000>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-cpol;
+ spi-cpha;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* MTD partition table.
+ * The ROM checks the first four physical blocks
+ * for a valid file to boot and the flash here is
+ * 64KiB block size.
+ */
+ partition at 0 {
+ label = "QSPI.SPL";
+ reg = <0x00000000 0x000010000>;
+ };
+ partition at 1 {
+ label = "QSPI.SPL.backup1";
+ reg = <0x00010000 0x00010000>;
+ };
+ partition at 2 {
+ label = "QSPI.SPL.backup2";
+ reg = <0x00020000 0x00010000>;
+ };
+ partition at 3 {
+ label = "QSPI.SPL.backup3";
+ reg = <0x00030000 0x00010000>;
+ };
+ partition at 4 {
+ label = "QSPI.u-boot";
+ reg = <0x00040000 0x00100000>;
+ };
+ partition at 5 {
+ label = "QSPI.u-boot-spl-os";
+ reg = <0x00140000 0x00080000>;
+ };
+ partition at 6 {
+ label = "QSPI.u-boot-env";
+ reg = <0x001c0000 0x00010000>;
+ };
+ partition at 7 {
+ label = "QSPI.u-boot-env.backup1";
+ reg = <0x001d0000 0x0010000>;
+ };
+ partition at 8 {
+ label = "QSPI.kernel";
+ reg = <0x001e0000 0x0800000>;
+ };
+ partition at 9 {
+ label = "QSPI.file-system";
+ reg = <0x009e0000 0x01620000>;
+ };
+ };
+};
+
+&dss {
+ status = "ok";
+
+ vdda_video-supply = <&ldo5_reg>;
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&ldo3_reg>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
diff --git a/arch/arm/dts/dra72x.dtsi b/arch/arm/dts/dra72x.dtsi
new file mode 100644
index 0000000..eaca143
--- /dev/null
+++ b/arch/arm/dts/dra72x.dtsi
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+#include "dra7.dtsi"
+
+/ {
+ compatible = "ti,dra722", "ti,dra72", "ti,dra7";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <2>;
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupt-parent = <&wakeupgen>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&dss {
+ reg = <0x58000000 0x80>,
+ <0x58004054 0x4>,
+ <0x58004300 0x20>;
+ reg-names = "dss", "pll1_clkctrl", "pll1";
+
+ clocks = <&dss_dss_clk>,
+ <&dss_video1_clk>;
+ clock-names = "fck", "video1_clk";
+};
diff --git a/arch/arm/dts/dra7xx-clocks.dtsi b/arch/arm/dts/dra7xx-clocks.dtsi
new file mode 100644
index 0000000..357bede
--- /dev/null
+++ b/arch/arm/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,2149 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_core_aon_clocks {
+ atl_clkin0_ck: atl_clkin0_ck {
+ #clock-cells = <0>;
+ compatible = "ti,dra7-atl-clock";
+ clocks = <&atl_gfclk_mux>;
+ };
+
+ atl_clkin1_ck: atl_clkin1_ck {
+ #clock-cells = <0>;
+ compatible = "ti,dra7-atl-clock";
+ clocks = <&atl_gfclk_mux>;
+ };
+
+ atl_clkin2_ck: atl_clkin2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,dra7-atl-clock";
+ clocks = <&atl_gfclk_mux>;
+ };
+
+ atl_clkin3_ck: atl_clkin3_ck {
+ #clock-cells = <0>;
+ compatible = "ti,dra7-atl-clock";
+ clocks = <&atl_gfclk_mux>;
+ };
+
+ hdmi_clkin_ck: hdmi_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ mlb_clkin_ck: mlb_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ mlbp_clkin_ck: mlbp_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ ref_clkin0_ck: ref_clkin0_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ref_clkin1_ck: ref_clkin1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ref_clkin2_ck: ref_clkin2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ref_clkin3_ck: ref_clkin3_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ rmii_clk_ck: rmii_clk_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ sdvenc_clkin_ck: sdvenc_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ virt_12000000_ck: virt_12000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ virt_13000000_ck: virt_13000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ };
+
+ virt_16800000_ck: virt_16800000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <16800000>;
+ };
+
+ virt_19200000_ck: virt_19200000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ };
+
+ virt_20000000_ck: virt_20000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+ };
+
+ virt_26000000_ck: virt_26000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ };
+
+ virt_27000000_ck: virt_27000000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+ };
+
+ virt_38400000_ck: virt_38400000_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ };
+
+ sys_clkin2: sys_clkin2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22579200>;
+ };
+
+ usb_otg_clkin_ck: usb_otg_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ video1_clkin_ck: video1_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ video1_m2_clkin_ck: video1_m2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ video2_clkin_ck: video2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ video2_m2_clkin_ck: video2_m2_clkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ dpll_abe_ck: dpll_abe_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-m4xen-clock";
+ clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+ reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+ };
+
+ dpll_abe_x2_ck: dpll_abe_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_abe_ck>;
+ };
+
+ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01f0>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ abe_clk: abe_clk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ ti,max-div = <4>;
+ reg = <0x0108>;
+ ti,index-power-of-two;
+ };
+
+ dpll_abe_m2_ck: dpll_abe_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01f0>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01f4>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_byp_mux: dpll_core_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x012c>;
+ };
+
+ dpll_core_ck: dpll_core_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-core-clock";
+ clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
+ reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+ };
+
+ dpll_core_x2_ck: dpll_core_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_core_ck>;
+ };
+
+ dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x013c>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_mpu_ck: dpll_mpu_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap5-mpu-dpll-clock";
+ clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
+ reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+ };
+
+ dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_mpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0170>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ mpu_dclk_div: mpu_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_mpu_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_dsp_byp_mux: dpll_dsp_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x0240>;
+ };
+
+ dpll_dsp_ck: dpll_dsp_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
+ reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
+ };
+
+ dpll_dsp_m2_ck: dpll_dsp_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0244>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_iva_byp_mux: dpll_iva_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x01ac>;
+ };
+
+ dpll_iva_ck: dpll_iva_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
+ reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+ };
+
+ dpll_iva_m2_ck: dpll_iva_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_iva_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x01b0>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ iva_dclk: iva_dclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_iva_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_gpu_byp_mux: dpll_gpu_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x02e4>;
+ };
+
+ dpll_gpu_ck: dpll_gpu_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
+ reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
+ };
+
+ dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gpu_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x02e8>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_m2_ck: dpll_core_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0130>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_ddr_byp_mux: dpll_ddr_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x021c>;
+ };
+
+ dpll_ddr_ck: dpll_ddr_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
+ reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
+ };
+
+ dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0220>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_gmac_byp_mux: dpll_gmac_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+ ti,bit-shift = <23>;
+ reg = <0x02b4>;
+ };
+
+ dpll_gmac_ck: dpll_gmac_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
+ reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
+ };
+
+ dpll_gmac_m2_ck: dpll_gmac_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x02b8>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ video2_dclk_div: video2_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_m2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ video1_dclk_div: video1_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_m2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ hdmi_dclk_div: hdmi_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_abe_m3x2_ck>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_core_h12x2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_eve_byp_mux: dpll_eve_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x0290>;
+ };
+
+ dpll_eve_ck: dpll_eve_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
+ reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
+ };
+
+ dpll_eve_m2_ck: dpll_eve_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_eve_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0294>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ eve_dclk_div: eve_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_eve_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0140>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0144>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0154>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0158>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x015c>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_ddr_ck>;
+ };
+
+ dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0228>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_dsp_ck>;
+ };
+
+ dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0248>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_gmac_ck>;
+ };
+
+ dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x02c0>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x02c4>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x02c8>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x02bc>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ gmii_m_clk_div: gmii_m_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_gmac_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ hdmi_clk2_div: hdmi_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ hdmi_div_clk: hdmi_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&hdmi_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ l3_iclk_div: l3_iclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ ti,max-div = <2>;
+ ti,bit-shift = <4>;
+ reg = <0x0100>;
+ clocks = <&dpll_core_h12x2_ck>;
+ ti,index-power-of-two;
+ };
+
+ l4_root_clk_div: l4_root_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&l3_iclk_div>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ video1_clk2_div: video1_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ video1_div_clk: video1_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video1_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ video2_clk2_div: video2_clk2_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ video2_div_clk: video2_div_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&video2_clkin_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ ipu1_gfclk_mux: ipu1_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x0520>;
+ };
+
+ mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <28>;
+ reg = <0x0550>;
+ };
+
+ mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x0550>;
+ };
+
+ mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x0550>;
+ };
+
+ timer5_gfclk_mux: timer5_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x0558>;
+ };
+
+ timer6_gfclk_mux: timer6_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x0560>;
+ };
+
+ timer7_gfclk_mux: timer7_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x0568>;
+ };
+
+ timer8_gfclk_mux: timer8_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x0570>;
+ };
+
+ uart6_gfclk_mux: uart6_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x0580>;
+ };
+
+ dummy_ck: dummy_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+&prm_clocks {
+ sys_clkin1: sys_clkin1 {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+ reg = <0x0110>;
+ ti,index-starts-at-one;
+ };
+
+ abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x0118>;
+ };
+
+ abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+ reg = <0x0114>;
+ };
+
+ abe_dpll_clk_mux: abe_dpll_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+ reg = <0x010c>;
+ };
+
+ abe_24m_fclk: abe_24m_fclk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x011c>;
+ ti,dividers = <8>, <16>;
+ };
+
+ aess_fclk: aess_fclk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&abe_clk>;
+ reg = <0x0178>;
+ ti,max-div = <2>;
+ };
+
+ abe_giclk_div: abe_giclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&aess_fclk>;
+ reg = <0x0174>;
+ ti,max-div = <2>;
+ };
+
+ abe_lp_clk_div: abe_lp_clk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2x2_ck>;
+ reg = <0x01d8>;
+ ti,dividers = <16>, <32>;
+ };
+
+ abe_sys_clk_div: abe_sys_clk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x0120>;
+ ti,max-div = <2>;
+ };
+
+ adc_gfclk_mux: adc_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
+ reg = <0x01dc>;
+ };
+
+ sys_clk1_dclk_div: sys_clk1_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ ti,max-div = <64>;
+ reg = <0x01c8>;
+ ti,index-power-of-two;
+ };
+
+ sys_clk2_dclk_div: sys_clk2_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin2>;
+ ti,max-div = <64>;
+ reg = <0x01cc>;
+ ti,index-power-of-two;
+ };
+
+ per_abe_x1_dclk_div: per_abe_x1_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x01bc>;
+ ti,index-power-of-two;
+ };
+
+ dsp_gclk_div: dsp_gclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_dsp_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x018c>;
+ ti,index-power-of-two;
+ };
+
+ gpu_dclk: gpu_dclk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gpu_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x01a0>;
+ ti,index-power-of-two;
+ };
+
+ emif_phy_dclk_div: emif_phy_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_ddr_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x0190>;
+ ti,index-power-of-two;
+ };
+
+ gmac_250m_dclk_div: gmac_250m_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x019c>;
+ ti,index-power-of-two;
+ };
+
+ l3init_480m_dclk_div: l3init_480m_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x01ac>;
+ ti,index-power-of-two;
+ };
+
+ usb_otg_dclk_div: usb_otg_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&usb_otg_clkin_ck>;
+ ti,max-div = <64>;
+ reg = <0x0184>;
+ ti,index-power-of-two;
+ };
+
+ sata_dclk_div: sata_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ ti,max-div = <64>;
+ reg = <0x01c0>;
+ ti,index-power-of-two;
+ };
+
+ pcie2_dclk_div: pcie2_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x01b8>;
+ ti,index-power-of-two;
+ };
+
+ pcie_dclk_div: pcie_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&apll_pcie_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x01b4>;
+ ti,index-power-of-two;
+ };
+
+ emu_dclk_div: emu_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ ti,max-div = <64>;
+ reg = <0x0194>;
+ ti,index-power-of-two;
+ };
+
+ secure_32k_dclk_div: secure_32k_dclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&secure_32k_clk_src_ck>;
+ ti,max-div = <64>;
+ reg = <0x01c4>;
+ ti,index-power-of-two;
+ };
+
+ clkoutmux0_clk_mux: clkoutmux0_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x0158>;
+ };
+
+ clkoutmux1_clk_mux: clkoutmux1_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x015c>;
+ };
+
+ clkoutmux2_clk_mux: clkoutmux2_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+ reg = <0x0160>;
+ };
+
+ custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin1>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ eve_clk: eve_clk {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
+ reg = <0x0180>;
+ };
+
+ hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x0164>;
+ };
+
+ mlb_clk: mlb_clk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mlb_clkin_ck>;
+ ti,max-div = <64>;
+ reg = <0x0134>;
+ ti,index-power-of-two;
+ };
+
+ mlbp_clk: mlbp_clk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mlbp_clkin_ck>;
+ ti,max-div = <64>;
+ reg = <0x0130>;
+ ti,index-power-of-two;
+ };
+
+ per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_abe_m2_ck>;
+ ti,max-div = <64>;
+ reg = <0x0138>;
+ ti,index-power-of-two;
+ };
+
+ timer_sys_clk_div: timer_sys_clk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&sys_clkin1>;
+ reg = <0x0144>;
+ ti,max-div = <2>;
+ };
+
+ video1_dpll_clk_mux: video1_dpll_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x0168>;
+ };
+
+ video2_dpll_clk_mux: video2_dpll_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ reg = <0x016c>;
+ };
+
+ wkupaon_iclk_mux: wkupaon_iclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
+ reg = <0x0108>;
+ };
+
+ gpio1_dbclk: gpio1_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1838>;
+ };
+
+ dcan1_sys_clk_mux: dcan1_sys_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin2>;
+ ti,bit-shift = <24>;
+ reg = <0x1888>;
+ };
+
+ timer1_gfclk_mux: timer1_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1840>;
+ };
+
+ uart10_gfclk_mux: uart10_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1880>;
+ };
+};
+&cm_core_clocks {
+ dpll_pcie_ref_ck: dpll_pcie_ref_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&sys_clkin1>;
+ reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+ };
+
+ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0210>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ apll_pcie_in_clk_mux: apll_pcie_in_clk_mux at 4ae06118 {
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
+ #clock-cells = <0>;
+ reg = <0x021c 0x4>;
+ ti,bit-shift = <7>;
+ };
+
+ apll_pcie_ck: apll_pcie_ck {
+ #clock-cells = <0>;
+ compatible = "ti,dra7-apll-clock";
+ clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+ reg = <0x021c>, <0x0220>;
+ };
+
+ optfclk_pciephy1_32khz: optfclk_pciephy1_32khz at 4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b0>;
+ ti,bit-shift = <8>;
+ };
+
+ optfclk_pciephy2_32khz: optfclk_pciephy2_32khz at 4a0093b8 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b8>;
+ ti,bit-shift = <8>;
+ };
+
+ optfclk_pciephy_div: optfclk_pciephy_div at 4a00821c {
+ compatible = "ti,divider-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x021c>;
+ ti,dividers = <2>, <1>;
+ ti,bit-shift = <8>;
+ ti,max-div = <2>;
+ };
+
+ optfclk_pciephy1_clk: optfclk_pciephy1_clk at 4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b0>;
+ ti,bit-shift = <9>;
+ };
+
+ optfclk_pciephy2_clk: optfclk_pciephy2_clk at 4a0093b8 {
+ compatible = "ti,gate-clock";
+ clocks = <&apll_pcie_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b8>;
+ ti,bit-shift = <9>;
+ };
+
+ optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk at 4a0093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&optfclk_pciephy_div>;
+ #clock-cells = <0>;
+ reg = <0x13b0>;
+ ti,bit-shift = <10>;
+ };
+
+ optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk at 4a0093b8 {
+ compatible = "ti,gate-clock";
+ clocks = <&optfclk_pciephy_div>;
+ #clock-cells = <0>;
+ reg = <0x13b8>;
+ ti,bit-shift = <10>;
+ };
+
+ apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll_pcie_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll_pcie_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ apll_pcie_m2_ck: apll_pcie_m2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&apll_pcie_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_per_byp_mux: dpll_per_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x014c>;
+ };
+
+ dpll_per_ck: dpll_per_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-clock";
+ clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
+ reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+ };
+
+ dpll_per_m2_ck: dpll_per_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ dpll_usb_byp_mux: dpll_usb_byp_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+ ti,bit-shift = <23>;
+ reg = <0x018c>;
+ };
+
+ dpll_usb_ck: dpll_usb_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-j-type-clock";
+ clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
+ reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+ };
+
+ dpll_usb_m2_ck: dpll_usb_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0190>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_pcie_ref_ck>;
+ ti,max-div = <127>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0210>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_x2_ck: dpll_per_x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-dpll-x2-clock";
+ clocks = <&dpll_per_ck>;
+ };
+
+ dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0158>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x015c>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_h13x2_ck: dpll_per_h13x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0160>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <63>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0164>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_per_x2_ck>;
+ ti,max-div = <31>;
+ ti,autoidle-shift = <8>;
+ reg = <0x0150>;
+ ti,index-starts-at-one;
+ ti,invert-autoidle-bit;
+ };
+
+ dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_usb_ck>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ };
+
+ func_128m_clk: func_128m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_h11x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ func_12m_fclk: func_12m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ func_24m_clk: func_24m_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ func_48m_fclk: func_48m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ func_96m_fclk: func_96m_fclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_per_m2x2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ l3init_60m_fclk: l3init_60m_fclk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_usb_m2_ck>;
+ reg = <0x0104>;
+ ti,dividers = <1>, <8>;
+ };
+
+ clkout2_clk: clkout2_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&clkoutmux2_clk_mux>;
+ ti,bit-shift = <8>;
+ reg = <0x06b0>;
+ };
+
+ l3init_960m_gfclk: l3init_960m_gfclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_usb_clkdcoldo>;
+ ti,bit-shift = <8>;
+ reg = <0x06c0>;
+ };
+
+ dss_32khz_clk: dss_32khz_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <11>;
+ reg = <0x1120>;
+ };
+
+ dss_48mhz_clk: dss_48mhz_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&func_48m_fclk>;
+ ti,bit-shift = <9>;
+ reg = <0x1120>;
+ };
+
+ dss_dss_clk: dss_dss_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_per_h12x2_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1120>;
+ ti,set-rate-parent;
+ };
+
+ dss_hdmi_clk: dss_hdmi_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&hdmi_dpll_clk_mux>;
+ ti,bit-shift = <10>;
+ reg = <0x1120>;
+ };
+
+ dss_video1_clk: dss_video1_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&video1_dpll_clk_mux>;
+ ti,bit-shift = <12>;
+ reg = <0x1120>;
+ };
+
+ dss_video2_clk: dss_video2_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&video2_dpll_clk_mux>;
+ ti,bit-shift = <13>;
+ reg = <0x1120>;
+ };
+
+ gpio2_dbclk: gpio2_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1760>;
+ };
+
+ gpio3_dbclk: gpio3_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1768>;
+ };
+
+ gpio4_dbclk: gpio4_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1770>;
+ };
+
+ gpio5_dbclk: gpio5_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1778>;
+ };
+
+ gpio6_dbclk: gpio6_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1780>;
+ };
+
+ gpio7_dbclk: gpio7_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1810>;
+ };
+
+ gpio8_dbclk: gpio8_dbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1818>;
+ };
+
+ mmc1_clk32k: mmc1_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1328>;
+ };
+
+ mmc2_clk32k: mmc2_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1330>;
+ };
+
+ mmc3_clk32k: mmc3_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1820>;
+ };
+
+ mmc4_clk32k: mmc4_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x1828>;
+ };
+
+ sata_ref_clk: sata_ref_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_clkin1>;
+ ti,bit-shift = <8>;
+ reg = <0x1388>;
+ };
+
+ usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_960m_gfclk>;
+ ti,bit-shift = <8>;
+ reg = <0x13f0>;
+ };
+
+ usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3init_960m_gfclk>;
+ ti,bit-shift = <8>;
+ reg = <0x1340>;
+ };
+
+ usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0640>;
+ };
+
+ usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0688>;
+ };
+
+ usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ ti,bit-shift = <8>;
+ reg = <0x0698>;
+ };
+
+ atl_dpll_clk_mux: atl_dpll_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x0c00>;
+ };
+
+ atl_gfclk_mux: atl_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
+ ti,bit-shift = <26>;
+ reg = <0x0c00>;
+ };
+
+ gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_m2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x13d0>;
+ ti,dividers = <2>;
+ };
+
+ gmac_rft_clk_mux: gmac_rft_clk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
+ ti,bit-shift = <25>;
+ reg = <0x13d0>;
+ };
+
+ gpu_core_gclk_mux: gpu_core_gclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1220>;
+ };
+
+ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+ ti,bit-shift = <26>;
+ reg = <0x1220>;
+ };
+
+ l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&wkupaon_iclk_mux>;
+ ti,bit-shift = <24>;
+ reg = <0x0e50>;
+ ti,dividers = <8>, <16>, <32>;
+ };
+
+ mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <28>;
+ reg = <0x1860>;
+ };
+
+ mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1860>;
+ };
+
+ mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x1860>;
+ };
+
+ mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1868>;
+ };
+
+ mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x1868>;
+ };
+
+ mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1898>;
+ };
+
+ mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x1898>;
+ };
+
+ mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1878>;
+ };
+
+ mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x1878>;
+ };
+
+ mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1904>;
+ };
+
+ mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x1904>;
+ };
+
+ mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1908>;
+ };
+
+ mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <22>;
+ reg = <0x1908>;
+ };
+
+ mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+ ti,bit-shift = <22>;
+ reg = <0x1890>;
+ };
+
+ mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+ ti,bit-shift = <24>;
+ reg = <0x1890>;
+ };
+
+ mmc1_fclk_mux: mmc1_fclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1328>;
+ };
+
+ mmc1_fclk_div: mmc1_fclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc1_fclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x1328>;
+ ti,index-power-of-two;
+ };
+
+ mmc2_fclk_mux: mmc2_fclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1330>;
+ };
+
+ mmc2_fclk_div: mmc2_fclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc2_fclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x1330>;
+ ti,index-power-of-two;
+ };
+
+ mmc3_gfclk_mux: mmc3_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1820>;
+ };
+
+ mmc3_gfclk_div: mmc3_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc3_gfclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x1820>;
+ ti,index-power-of-two;
+ };
+
+ mmc4_gfclk_mux: mmc4_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1828>;
+ };
+
+ mmc4_gfclk_div: mmc4_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&mmc4_gfclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x1828>;
+ ti,index-power-of-two;
+ };
+
+ qspi_gfclk_mux: qspi_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1838>;
+ };
+
+ qspi_gfclk_div: qspi_gfclk_div {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&qspi_gfclk_mux>;
+ ti,bit-shift = <25>;
+ ti,max-div = <4>;
+ reg = <0x1838>;
+ ti,index-power-of-two;
+ };
+
+ timer10_gfclk_mux: timer10_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1728>;
+ };
+
+ timer11_gfclk_mux: timer11_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1730>;
+ };
+
+ timer13_gfclk_mux: timer13_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x17c8>;
+ };
+
+ timer14_gfclk_mux: timer14_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x17d0>;
+ };
+
+ timer15_gfclk_mux: timer15_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x17d8>;
+ };
+
+ timer16_gfclk_mux: timer16_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1830>;
+ };
+
+ timer2_gfclk_mux: timer2_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1738>;
+ };
+
+ timer3_gfclk_mux: timer3_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1740>;
+ };
+
+ timer4_gfclk_mux: timer4_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1748>;
+ };
+
+ timer9_gfclk_mux: timer9_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+ ti,bit-shift = <24>;
+ reg = <0x1750>;
+ };
+
+ uart1_gfclk_mux: uart1_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1840>;
+ };
+
+ uart2_gfclk_mux: uart2_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1848>;
+ };
+
+ uart3_gfclk_mux: uart3_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1850>;
+ };
+
+ uart4_gfclk_mux: uart4_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1858>;
+ };
+
+ uart5_gfclk_mux: uart5_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1870>;
+ };
+
+ uart7_gfclk_mux: uart7_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x18d0>;
+ };
+
+ uart8_gfclk_mux: uart8_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x18e0>;
+ };
+
+ uart9_gfclk_mux: uart9_gfclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x18e8>;
+ };
+
+ vip1_gclk_mux: vip1_gclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1020>;
+ };
+
+ vip2_gclk_mux: vip2_gclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1028>;
+ };
+
+ vip3_gclk_mux: vip3_gclk_mux {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+ ti,bit-shift = <24>;
+ reg = <0x1030>;
+ };
+};
+
+&cm_core_clockdomains {
+ coreaon_clkdm: coreaon_clkdm {
+ compatible = "ti,clockdomain";
+ clocks = <&dpll_usb_ck>;
+ };
+};
+
+&scm_conf_clocks {
+ dss_deshdcp_clk: dss_deshdcp_clk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l3_iclk_div>;
+ ti,bit-shift = <0>;
+ reg = <0x558>;
+ };
+};
diff --git a/arch/arm/dts/omap4-cpu-thermal.dtsi b/arch/arm/dts/omap4-cpu-thermal.dtsi
new file mode 100644
index 0000000..ab7f87a
--- /dev/null
+++ b/arch/arm/dts/omap4-cpu-thermal.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Device Tree Source for OMAP4/5 SoC CPU thermal
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+cpu_thermal: cpu_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 0>;
+
+ cpu_trips: trips {
+ cpu_alert0: cpu_alert {
+ temperature = <100000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <125000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cpu_cooling_maps: cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
diff --git a/arch/arm/dts/omap5-core-thermal.dtsi b/arch/arm/dts/omap5-core-thermal.dtsi
new file mode 100644
index 0000000..de8a3d4
--- /dev/null
+++ b/arch/arm/dts/omap5-core-thermal.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Device Tree Source for OMAP543x SoC CORE thermal
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+core_thermal: core_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 2>;
+
+ trips {
+ core_crit: core_crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
diff --git a/arch/arm/dts/omap5-gpu-thermal.dtsi b/arch/arm/dts/omap5-gpu-thermal.dtsi
new file mode 100644
index 0000000..bc3090f
--- /dev/null
+++ b/arch/arm/dts/omap5-gpu-thermal.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Device Tree Source for OMAP543x SoC GPU thermal
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+gpu_thermal: gpu_thermal {
+ polling-delay-passive = <250>; /* milliseconds */
+ polling-delay = <500>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&bandgap 1>;
+
+ trips {
+ gpu_crit: gpu_crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+};
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
new file mode 100644
index 0000000..3205e72
--- /dev/null
+++ b/configs/dra72_evm_defconfig
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_OMAP54XX=y
+CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="dra72-evm"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_DM_GPIO=y
diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
index 265fe00..325fe42 100644
--- a/drivers/serial/serial_omap.c
+++ b/drivers/serial/serial_omap.c
@@ -15,6 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_OF_CONTROL
static const struct udevice_id omap_serial_ids[] = {
{ .compatible = "ti,omap3-uart" },
+ { .compatible = "ti,omap4-uart" },
{ }
};
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
new file mode 100644
index 0000000..7448edf
--- /dev/null
+++ b/include/dt-bindings/pinctrl/dra.h
@@ -0,0 +1,51 @@
+/*
+ * This header provides constants for DRA pinctrl bindings.
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_DRA_H
+#define _DT_BINDINGS_PINCTRL_DRA_H
+
+/* DRA7 mux mode options for each pin. See TRM for options */
+#define MUX_MODE0 0x0
+#define MUX_MODE1 0x1
+#define MUX_MODE2 0x2
+#define MUX_MODE3 0x3
+#define MUX_MODE4 0x4
+#define MUX_MODE5 0x5
+#define MUX_MODE6 0x6
+#define MUX_MODE7 0x7
+#define MUX_MODE8 0x8
+#define MUX_MODE9 0x9
+#define MUX_MODE10 0xa
+#define MUX_MODE11 0xb
+#define MUX_MODE12 0xc
+#define MUX_MODE13 0xd
+#define MUX_MODE14 0xe
+#define MUX_MODE15 0xf
+
+#define PULL_ENA (0 << 16)
+#define PULL_DIS (1 << 16)
+#define PULL_UP (1 << 17)
+#define INPUT_EN (1 << 18)
+#define SLEWCONTROL (1 << 19)
+#define WAKEUP_EN (1 << 24)
+#define WAKEUP_EVENT (1 << 25)
+
+/* Active pin states */
+#define PIN_OUTPUT (0 | PULL_DIS)
+#define PIN_OUTPUT_PULLUP (PULL_UP)
+#define PIN_OUTPUT_PULLDOWN (0)
+#define PIN_INPUT (INPUT_EN | PULL_DIS)
+#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL)
+#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
+
+#endif
+
--
1.7.9.5
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