[PULL] drm-intel-next

[Daniel Vetter <daniel.vetter@ffwll.ch>]

Hi Dave,

Another pull to make you open drm-next ;-)

drm-intel-next-2015-09-11:
- initialize backlight from VBT as fallback (Jani)
- hpd A support from Ville
- various atomic polish all over (mostly from Maarten)
- first parts of virtualize gpu guest support on bdw from
  Zhiyuan Lv
- GuC fixes from Alex
- polish for the chv clocks code (Ville)
- various things all over, as usual
drm-intel-next-2015-08-28:
- PML4 pagetable support for 48b from Michel Thierry
- more fixes for sink crc from Rodrigo
- DP link settings cleanup from Ville
- GuC-based command submission from Alex Dai and Dave Gordon
- dpll cleanups for chv from Ville
- max pixel clock checking from Mika Kahola
- cleanup hpd bits handling (Jani)
- more power well trickery for chv from Ville

Cheers, Daniel


The following changes since commit 6fa2d197936ba0b8936e813d0adecefac160062b:

  i915: Set ddi_pll_sel in DP MST path (2015-09-01 12:42:27 +0300)

are available in the git repository at:

  git://anongit.freedesktop.org/drm-intel tags/drm-intel-next-2015-09-11

for you to fetch changes up to fd1ee4cc9326c97b52154ee2ef8cdd23ac6aae1c:

  drm/i915: Update DRIVER_DATE to 20150911 (2015-09-11 21:57:24 +0200)

----------------------------------------------------------------
- initialize backlight from VBT as fallback (Jani)
- hpd A support from Ville
- various atomic polish all over (mostly from Maarten)
- first parts of virtualize gpu guest support on bdw from
  Zhiyuan Lv
- GuC fixes from Alex
- polish for the chv clocks code (Ville)
- various things all over, as usual

----------------------------------------------------------------
Alex Dai (7):
      drm/i915: GuC-specific firmware loader
      drm/i915: Debugfs interface to read GuC load status
      drm/i915: Prepare for GuC-based command submission
      drm/i915: Enable GuC firmware log
      drm/i915: Integrate GuC-based command submission
      drm/i915/guc: Support GuC version 4.3
      drm/i915: Notify GuC rc6 state

Arun Siluvery (1):
      drm/i915: Change SRM, LRM instructions to use correct length

Chris Wilson (3):
      drm/i915: Do not check or a stalled pageflip prior to it being queued
      drm/i915: Refactor common ringbuffer allocation code
      drm/i915: Fix cmdparser STORE/LOAD command descriptors

Daniel Vetter (4):
      drm/i915: Update DRIVER_DATE to 20150828
      Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queued
      drm/i915: Update comments around base bpp
      drm/i915: Update DRIVER_DATE to 20150911

Dave Gordon (5):
      drm/i915: Expose one LRC function for GuC submission mode
      drm/i915: Implementation of GuC submission client
      drm/i915: Interrupt routing for GuC submission
      drm/i915: Debugfs interface for GuC submission statistics
      drm/i915: fix driver's versions of WARN_ON & WARN_ON_ONCE

Francisco Jerez (1):
      drm/i915: Bump command parser version number.

Graham Whaley (1):
      doc: drm: Fix mis-spelling of i915_guc_submission includes

Imre Deak (4):
      drm/i915/bxt: work around HW coherency issue when accessing GPU seqno
      drm/i915/bxt: don't allow cached GEM mappings on A stepping
      drm/i915: access the PP_CONTROL reg only pre GEN5
      drm/i915: access the PP_ON_DELAYS/PP_OFF_DELAYS regs only pre GEN5

Jani Nikula (18):
      drm/i915: remove excessive scaler debugging messages
      drm/i915: move ibx_digital_port_connected to intel_dp.c
      drm/i915: make g4x_digital_port_connected return boolean status
      drm/i915: add MISSING_CASE annotation to ibx_digital_port_connected
      drm/i915: add common intel_digital_port_connected function
      drm/i915: split ibx_digital_port_connected to ibx and cpt variants
      drm/i915: split g4x_digital_port_connected to g4x and vlv variants
      drm/i915/bxt: Use correct live status register for BXT platform
      drm/dp: add drm_dp_tps3_supported helper
      drm/i915/dp: use the drm dp helper for determining sink tps3 support
      drm/i915: move intel_hrawclk() to intel_display.c
      drm/i915: add yesno utility function
      drm/i915/dp: move TPS3 logic to where it's used
      drm/i915: ignore link rate in TPS3 selection
      drm/i915: use the yesno helper for logging
      drm/i915: use pch backlight override on hsw too
      drm/i915: initialize backlight max from VBT
      drm/i915: don't hard code vlv backlight frequency if unset

Kumar, Mahesh (2):
      drm/i915/skl: Avoid using un-initialized bits_per_pixel
      drm/i915/skl+: Add YUV pixel format in Capability list

Maarten Lankhorst (11):
      Partially revert "drm/i915: Use full atomic modeset."
      drm/i915: Fix module initialisation, v2.
      drm/i915: Remove start frame argument to pipe_update_begin/end.
      drm/i915: Also record time difference if vblank evasion fails, v2.
      drm/i915: Use atomic plane state in the primary plane update.
      drm/i915: Use the plane state in intel_crtc_info.
      drm/i915: Use the atomic state in intel_update_primary_planes.
      drm/i915: Use atomic state when changing cursor visibility.
      drm/i915: Remove legacy plane updates for cursor and sprite planes.
      drm/i915: Do not handle a null plane state.
      drm/i915: Use crtc->state for duplication.

Michał Winiarski (1):
      drm/i915/gtt: Avoid calling kcalloc in a loop when allocating temp bitmaps

Michel Thierry (19):
      drm/i915: Remove unnecessary gen8_clamp_pd
      drm/i915/gen8: Make pdp allocation more dynamic
      drm/i915/gen8: Abstract PDP usage
      drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT
      drm/i915/gen8: Add dynamic page trace events
      drm/i915/gen8: Add PML4 structure
      drm/i915/gen8: implement alloc/free for 4lvl
      drm/i915/gen8: Add 4 level switching infrastructure and lrc support
      drm/i915/gen8: Pass sg_iter through pte inserts
      drm/i915/gen8: Add 4 level support in insert_entries and clear_range
      drm/i915/gen8: Initialize PDPs and PML4
      drm/i915: Expand error state's address width to 64b
      drm/i915/gen8: Add ppgtt info and debug_dump
      drm/i915: object size needs to be u64
      drm/i915: batch_obj vm offset must be u64
      drm/i915/userptr: Kill user_size limit check
      drm/i915/gtt: Allow >= 4GB offsets in X86_32
      drm/i915: Use complete virtual address range on 32-bit platforms
      drm/i915: Always pass dev pointer in pdp_init

Mika Kahola (4):
      drm/i915: Store max dotclock
      drm/i915: LVDS pixel clock check
      drm/i915: DSI pixel clock check
      drm/i915: DVO pixel clock check

Nick Hoath (1):
      drm/i915/bxt: Clean up bxt_init_clock_gating

Paulo Zanoni (1):
      drm/i915: gen 9 can check for unclaimed registers too

Rodrigo Vivi (7):
      drm/i915: Force sink crc stop before start.
      drm/i915: Save latest known sink CRC to compensate delayed counter reset.
      drm/i915: Dont -ETIMEDOUT on identical new and previous (count, crc).
      drm/i915: Also call frontbuffer flip when disabling planes.
      drm/i915: Future proof interrupt handler.
      drm/i915: Future proof uncore_init.
      drm/i915: Future proof panel fitter.

Shashank Sharma (1):
      drm/i915: add attached connector to hdmi container

Sonika Jindal (2):
      drm/i915/bxt: Add HPD support for DDIA
      drm/i915/bxt: WA for swapped HPD pins in A stepping

Tvrtko Ursulin (1):
      drm/i915: Remove one very outdated comment

Ville Syrjälä (48):
      drm/i915: clflush on pin_to_display after pwrite to UC bo in LLC
      drm/i915: Clean up DP/HDMI limited color range handling
      drm/i915: Don't use link_bw for PLL setup
      drm/i915: Don't pass clock to DDI PLL select functions
      drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP .get_config()
      drm/i915: Move intel_dp->lane_count into pipe_config
      drm/i915: Don't use link_bw to select between TP1 and TP3
      drm/i915: Kill intel_dp->{link_bw, rate_select}
      drm/i915: Put back lane_count into intel_dp and add link_rate too
      drm/i915: Always program m2 fractional value on CHV
      drm/i915: Always program unique transition scale for CHV
      drm/i915: Add encoder->post_pll_disable() hooks and move CHV clock buffer disables there
      drm/i915: Move DPIO port init earlier
      drm/i915: Add locking around chv_phy_control_init()
      drm/i915: Move VLV/CHV prepare_pll later
      drm/i915: Add vlv_dport_to_phy()
      drm/i915: Fix some gcc warnings
      drm/i915: Use ARRAY_SIZE() instead of hand rolling it
      drm/i915: Make some string arrays const
      drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable
      drm/i915: Implement PHY lane power gating for CHV
      drm/i915: Trick CL2 into life on CHV when using pipe B with port B
      drm/i915: Force common lane on for the PPS kick on CHV
      drm/i915: Enable DPIO SUS clock gating on CHV
      drm/i915: Force CL2 off in CHV x1 PHY
      drm/i915: Clean up CHV lane soft reset programming
      drm/i915: Add some CHV DPIO lane power state asserts
      drm/i915: Add CHV PHY LDO power sanity checks
      drm/i915: Fix clock readout when pipes are enabled w/o ports
      drm/i915: Factor out intel_crtc_has_encoders()
      drm/i915: Clean up various HPD defines
      drm/i915: Extract intel_hpd_enabled_irqs()
      drm/i915: Factor out ilk_update_display_irq()
      drm/i915: Add HAS_PCH_LPT_LP() macro
      drm/i915: Rename BXT PORTA HPD defines
      drm/i915: Move {pin, long}_mask initialization to caller from intel_get_hpd_pins()
      drm/i915: Introduce spt_irq_handler()
      drm/i915: Add port A HPD support for ILK/SNB
      drm/i915: Add port A HPD support for IVB/HSW
      drm/i915: LPT:LP needs port A HPD enabled in both north and south
      drm/i915: Add port A HPD support for BDW
      drm/i915: Add port A HPD support for SPT
      drm/i915: Reinitialize HPD after runtime D3
      drm/i915: Rewrite bxt_hpd_handler() to look like everyone else
      drm/i915: Refactor the hpd irq handling functions
      drm/i915: Rewrite BXT HPD code to conform to pre-existing style
      drm/i915: Don't call intel_get_hpd_pins() when there's no hotplug interrupt
      drm/i915: Dump pfit state as hex

Zhiyuan Lv (4):
      drm/i915: preallocate pdps for 32 bit vgpu
      drm/i915: Always enable execlists on BDW for vgpu
      drm/i915: Update PV INFO page definition for Intel GVT-g
      drm/i915: guest i915 notification for Intel GVT-g

 Documentation/DocBook/drm.tmpl             |  14 +
 drivers/gpu/drm/i915/Makefile              |   4 +
 drivers/gpu/drm/i915/i915_cmd_parser.c     |  13 +-
 drivers/gpu/drm/i915/i915_debugfs.c        | 196 +++++-
 drivers/gpu/drm/i915/i915_dma.c            |  35 +-
 drivers/gpu/drm/i915/i915_drv.c            |  31 +-
 drivers/gpu/drm/i915/i915_drv.h            |  52 +-
 drivers/gpu/drm/i915/i915_gem.c            |  61 +-
 drivers/gpu/drm/i915/i915_gem_context.c    |   7 +
 drivers/gpu/drm/i915/i915_gem_fence.c      |   4 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c        | 738 +++++++++++++++++++----
 drivers/gpu/drm/i915/i915_gem_gtt.h        |  66 ++-
 drivers/gpu/drm/i915/i915_gem_userptr.c    |   4 -
 drivers/gpu/drm/i915/i915_gpu_error.c      |  41 +-
 drivers/gpu/drm/i915/i915_guc_reg.h        |  17 +-
 drivers/gpu/drm/i915/i915_guc_submission.c | 916 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_irq.c            | 519 ++++++++++------
 drivers/gpu/drm/i915/i915_params.c         |   5 +
 drivers/gpu/drm/i915/i915_reg.h            | 152 +++--
 drivers/gpu/drm/i915/i915_trace.h          |  32 +-
 drivers/gpu/drm/i915/i915_vgpu.h           |  34 +-
 drivers/gpu/drm/i915/intel_atomic.c        |  13 +-
 drivers/gpu/drm/i915/intel_atomic_plane.c  |   6 +-
 drivers/gpu/drm/i915/intel_bios.c          |  18 -
 drivers/gpu/drm/i915/intel_bios.h          |   1 -
 drivers/gpu/drm/i915/intel_ddi.c           |  39 +-
 drivers/gpu/drm/i915/intel_display.c       | 309 +++++-----
 drivers/gpu/drm/i915/intel_dp.c            | 760 +++++++++++++++---------
 drivers/gpu/drm/i915/intel_dp_mst.c        |  21 +-
 drivers/gpu/drm/i915/intel_drv.h           |  58 +-
 drivers/gpu/drm/i915/intel_dsi.c           |   3 +
 drivers/gpu/drm/i915/intel_dvo.c           |   7 +
 drivers/gpu/drm/i915/intel_fbdev.c         |   2 +-
 drivers/gpu/drm/i915/intel_guc.h           | 122 ++++
 drivers/gpu/drm/i915/intel_guc_fwif.h      |  20 +-
 drivers/gpu/drm/i915/intel_guc_loader.c    | 606 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c          | 207 ++++---
 drivers/gpu/drm/i915/intel_lrc.c           | 247 +++++---
 drivers/gpu/drm/i915/intel_lrc.h           |   8 +
 drivers/gpu/drm/i915/intel_lvds.c          |  17 +-
 drivers/gpu/drm/i915/intel_panel.c         | 234 +++++++-
 drivers/gpu/drm/i915/intel_pm.c            |  27 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c    |  89 +--
 drivers/gpu/drm/i915/intel_ringbuffer.h    |  15 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c    | 379 ++++++++++--
 drivers/gpu/drm/i915/intel_sdvo.c          |   6 +-
 drivers/gpu/drm/i915/intel_sprite.c        |  22 +-
 drivers/gpu/drm/i915/intel_tv.c            |   2 +-
 drivers/gpu/drm/i915/intel_uncore.c        |  10 +-
 include/drm/drm_dp_helper.h                |   7 +
 50 files changed, 4888 insertions(+), 1308 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_guc_submission.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc.h
 create mode 100644 drivers/gpu/drm/i915/intel_guc_loader.c

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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