* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-21 12:22 ` Zhiqiang Hou
0 siblings, 0 replies; 75+ messages in thread
From: Zhiqiang Hou @ 2015-09-21 12:22 UTC (permalink / raw)
To: linux-arm-kernel
From: Mingkai Hu <Mingkai.Hu@freescale.com>
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks
similar to LS1021a which complies to Chassis 2.1 spec.
Following levels of DTSI/DTS files have been created for the
LS1043A SoC family:
- fsl-ls1043a.dtsi:
DTS-Include file for FSL LS1043A SoC.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 501 +++++++++++++++++++++++++
1 file changed, 501 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
new file mode 100644
index 0000000..eca094d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -0,0 +1,501 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+ compatible = "fsl,ls1043a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ clocks = <&clockgen 1 0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0x1>, /* Physical Secure PPI */
+ <1 14 0x1>, /* Physical Non-Secure PPI */
+ <1 11 0x1>, /* Virtual PPI */
+ <1 10 0x1>; /* Hypervisor PPI */
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 106 0x4>,
+ <0 107 0x4>,
+ <0 95 0x4>,
+ <0 97 0x4>;
+ };
+
+ gic: interrupt-controller at 1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+ <0x0 0x1402000 0 0x1000>, /* GICC */
+ <0x0 0x1404000 0 0x2000>, /* GICH */
+ <0x0 0x1406000 0 0x2000>; /* GICV */
+ interrupts = <1 9 0xf08>;
+ };
+
+ msi1: msi-controller1 at 1571000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1571000 0x0 0x4>,
+ <0x0 0x1571004 0x0 0x4>;
+ reg-names = "msiir", "msir";
+ msi-controller;
+ interrupts = <0 116 0x4>;
+ };
+
+ msi2: msi-controller2 at 1572000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1572000 0x0 0x4>,
+ <0x0 0x1572004 0x0 0x4>;
+ reg-names = "msiir", "msir";
+ msi-controller;
+ interrupts = <0 126 0x4>;
+ };
+
+ msi3: msi-controller3 at 1573000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1573000 0x0 0x4>,
+ <0x0 0x1573004 0x0 0x4>;
+ reg-names = "msiir", "msir";
+ msi-controller;
+ interrupts = <0 160 0x4>;
+ };
+
+ ifc: ifc at 1530000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x1530000 0x0 0x10000>;
+ interrupts = <0 43 0x4>;
+ };
+
+ esdhc: esdhc at 1560000 {
+ compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x1560000 0x0 0x10000>;
+ interrupts = <0 62 0x4>;
+ clock-frequency = <0>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ big-endian;
+ bus-width = <4>;
+ };
+
+ scfg: scfg at 1570000 {
+ compatible = "fsl,ls1043a-scfg", "syscon";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ big-endian;
+ };
+
+ dcfg: dcfg at 1ee0000 {
+ compatible = "fsl,ls1043a-dcfg", "syscon";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ };
+
+ clockgen: clocking at 1ee1000 {
+ compatible = "fsl,ls1043a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+ };
+
+ dspi0: dspi at 2100000 {
+ compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 64 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ dspi1: dspi at 2110000 {
+ compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <0 65 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ i2c0: i2c at 2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ dmas = <&edma0 1 39>,
+ <&edma0 1 38>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c1: i2c at 2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 21a0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21a0000 0x0 0x10000>;
+ interrupts = <0 58 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 21b0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21b0000 0x0 0x10000>;
+ interrupts = <0 59 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart0: serial at 21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart1: serial at 21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart2: serial at 21d0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0500 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart3: serial at 21d0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0600 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ gpio1: gpio at 2300000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 2310000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio at 2320000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 68 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio at 2330000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 134 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ lpuart0: serial at 2950000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2950000 0x0 0x1000>;
+ interrupts = <0 48 0x4>;
+ clocks = <&clockgen 0 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial at 2960000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2960000 0x0 0x1000>;
+ interrupts = <0 49 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial at 2970000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2970000 0x0 0x1000>;
+ interrupts = <0 50 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart3: serial at 2980000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2980000 0x0 0x1000>;
+ interrupts = <0 51 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial at 2990000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2990000 0x0 0x1000>;
+ interrupts = <0 52 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial at 29a0000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x29a0000 0x0 0x1000>;
+ interrupts = <0 53 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ wdog0: wdog at 2ad0000 {
+ compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+ interrupts = <0 83 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "wdog";
+ big-endian;
+ };
+
+ edma0: edma at 2c00000 {
+ #dma-cells = <2>;
+ compatible = "fsl,vf610-edma";
+ reg = <0x0 0x2c00000 0x0 0x10000>,
+ <0x0 0x2c10000 0x0 0x10000>,
+ <0x0 0x2c20000 0x0 0x10000>;
+ interrupts = <0 103 0x4>,
+ <0 103 0x4>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ big-endian;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clockgen 4 0>,
+ <&clockgen 4 0>;
+ };
+
+ usb0: usb3 at 2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <0 60 0x4>;
+ dr_mode = "host";
+ };
+
+ usb1: usb3 at 3000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <0 61 0x4>;
+ dr_mode = "host";
+ };
+ usb2: usb3 at 3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 63 0x4>;
+ dr_mode = "host";
+ };
+
+ pcie at 3400000 {
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 118 0x4>, /* controller interrupt */
+ <0 117 0x4>; /* PME interrupt */
+ interrupt-names = "intr", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
+ <0000 0 0 2 &gic 0 111 0x4>,
+ <0000 0 0 3 &gic 0 112 0x4>,
+ <0000 0 0 4 &gic 0 113 0x4>;
+ };
+
+ pcie at 3500000 {
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 128 0x4>,
+ <0 127 0x4>;
+ interrupt-names = "intr", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
+ <0000 0 0 2 &gic 0 121 0x4>,
+ <0000 0 0 3 &gic 0 122 0x4>,
+ <0000 0 0 4 &gic 0 123 0x4>;
+ };
+
+ pcie at 3600000 {
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 162 0x4>,
+ <0 161 0x4>;
+ interrupt-names = "intr", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi3>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
+ <0000 0 0 2 &gic 0 155 0x4>,
+ <0000 0 0 3 &gic 0 156 0x4>,
+ <0000 0 0 4 &gic 0 157 0x4>;
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>;
+ /* DRAM space 1 - 2 GB DRAM */
+ };
+
+};
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-21 12:22 ` Zhiqiang Hou
0 siblings, 0 replies; 75+ messages in thread
From: Zhiqiang Hou @ 2015-09-21 12:22 UTC (permalink / raw)
To: linux-arm-kernel, catalin.marinas, will.deacon, linux-i2c,
linux-watchdog, linux-doc, linux-clk
Cc: wsa, wim, corbet, mturquette, sboyd, Mingkai.Hu, Shaohui.Xie,
Wenbin.Song, scottwood, bhupesh.sharma, leoli, Hou Zhiqiang
From: Mingkai Hu <Mingkai.Hu@freescale.com>
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks
similar to LS1021a which complies to Chassis 2.1 spec.
Following levels of DTSI/DTS files have been created for the
LS1043A SoC family:
- fsl-ls1043a.dtsi:
DTS-Include file for FSL LS1043A SoC.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 501 +++++++++++++++++++++++++
1 file changed, 501 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
new file mode 100644
index 0000000..eca094d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -0,0 +1,501 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+ compatible = "fsl,ls1043a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ clocks = <&clockgen 1 0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0x1>, /* Physical Secure PPI */
+ <1 14 0x1>, /* Physical Non-Secure PPI */
+ <1 11 0x1>, /* Virtual PPI */
+ <1 10 0x1>; /* Hypervisor PPI */
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 106 0x4>,
+ <0 107 0x4>,
+ <0 95 0x4>,
+ <0 97 0x4>;
+ };
+
+ gic: interrupt-controller@1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+ <0x0 0x1402000 0 0x1000>, /* GICC */
+ <0x0 0x1404000 0 0x2000>, /* GICH */
+ <0x0 0x1406000 0 0x2000>; /* GICV */
+ interrupts = <1 9 0xf08>;
+ };
+
+ msi1: msi-controller1@1571000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1571000 0x0 0x4>,
+ <0x0 0x1571004 0x0 0x4>;
+ reg-names = "msiir", "msir";
+ msi-controller;
+ interrupts = <0 116 0x4>;
+ };
+
+ msi2: msi-controller2@1572000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1572000 0x0 0x4>,
+ <0x0 0x1572004 0x0 0x4>;
+ reg-names = "msiir", "msir";
+ msi-controller;
+ interrupts = <0 126 0x4>;
+ };
+
+ msi3: msi-controller3@1573000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1573000 0x0 0x4>,
+ <0x0 0x1573004 0x0 0x4>;
+ reg-names = "msiir", "msir";
+ msi-controller;
+ interrupts = <0 160 0x4>;
+ };
+
+ ifc: ifc@1530000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x1530000 0x0 0x10000>;
+ interrupts = <0 43 0x4>;
+ };
+
+ esdhc: esdhc@1560000 {
+ compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x1560000 0x0 0x10000>;
+ interrupts = <0 62 0x4>;
+ clock-frequency = <0>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ big-endian;
+ bus-width = <4>;
+ };
+
+ scfg: scfg@1570000 {
+ compatible = "fsl,ls1043a-scfg", "syscon";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ big-endian;
+ };
+
+ dcfg: dcfg@1ee0000 {
+ compatible = "fsl,ls1043a-dcfg", "syscon";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ };
+
+ clockgen: clocking@1ee1000 {
+ compatible = "fsl,ls1043a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+ };
+
+ dspi0: dspi@2100000 {
+ compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 64 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ dspi1: dspi@2110000 {
+ compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <0 65 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ dmas = <&edma0 1 39>,
+ <&edma0 1 38>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c1: i2c@2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@21a0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21a0000 0x0 0x10000>;
+ interrupts = <0 58 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@21b0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21b0000 0x0 0x10000>;
+ interrupts = <0 59 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart0: serial@21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart1: serial@21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart2: serial@21d0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0500 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart3: serial@21d0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0600 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ gpio1: gpio@2300000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2310000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2320000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 68 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@2330000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 134 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ lpuart0: serial@2950000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2950000 0x0 0x1000>;
+ interrupts = <0 48 0x4>;
+ clocks = <&clockgen 0 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial@2960000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2960000 0x0 0x1000>;
+ interrupts = <0 49 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial@2970000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2970000 0x0 0x1000>;
+ interrupts = <0 50 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart3: serial@2980000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2980000 0x0 0x1000>;
+ interrupts = <0 51 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial@2990000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2990000 0x0 0x1000>;
+ interrupts = <0 52 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial@29a0000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x29a0000 0x0 0x1000>;
+ interrupts = <0 53 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ wdog0: wdog@2ad0000 {
+ compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+ interrupts = <0 83 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "wdog";
+ big-endian;
+ };
+
+ edma0: edma@2c00000 {
+ #dma-cells = <2>;
+ compatible = "fsl,vf610-edma";
+ reg = <0x0 0x2c00000 0x0 0x10000>,
+ <0x0 0x2c10000 0x0 0x10000>,
+ <0x0 0x2c20000 0x0 0x10000>;
+ interrupts = <0 103 0x4>,
+ <0 103 0x4>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ big-endian;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clockgen 4 0>,
+ <&clockgen 4 0>;
+ };
+
+ usb0: usb3@2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <0 60 0x4>;
+ dr_mode = "host";
+ };
+
+ usb1: usb3@3000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <0 61 0x4>;
+ dr_mode = "host";
+ };
+ usb2: usb3@3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 63 0x4>;
+ dr_mode = "host";
+ };
+
+ pcie@3400000 {
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 118 0x4>, /* controller interrupt */
+ <0 117 0x4>; /* PME interrupt */
+ interrupt-names = "intr", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
+ <0000 0 0 2 &gic 0 111 0x4>,
+ <0000 0 0 3 &gic 0 112 0x4>,
+ <0000 0 0 4 &gic 0 113 0x4>;
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 128 0x4>,
+ <0 127 0x4>;
+ interrupt-names = "intr", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
+ <0000 0 0 2 &gic 0 121 0x4>,
+ <0000 0 0 3 &gic 0 122 0x4>,
+ <0000 0 0 4 &gic 0 123 0x4>;
+ };
+
+ pcie@3600000 {
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 162 0x4>,
+ <0 161 0x4>;
+ interrupt-names = "intr", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi3>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
+ <0000 0 0 2 &gic 0 155 0x4>,
+ <0000 0 0 3 &gic 0 156 0x4>,
+ <0000 0 0 4 &gic 0 157 0x4>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>;
+ /* DRAM space 1 - 2 GB DRAM */
+ };
+
+};
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-21 12:22 ` Zhiqiang Hou
0 siblings, 0 replies; 75+ messages in thread
From: Zhiqiang Hou @ 2015-09-21 12:22 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: wsa-z923LK4zBo2bacvFa/9K2g, wim-IQzOog9fTRqzQB+pC5nmwQ,
corbet-T1hC0tSOHrs, mturquette-rdvid1DuHRBWk0Htik3J/w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, Mingkai.Hu-KZfg59tc24xl57MIdRCFDg,
Shaohui.Xie-KZfg59tc24xl57MIdRCFDg,
Wenbin.Song-KZfg59tc24xl57MIdRCFDg,
scottwood-KZfg59tc24xl57MIdRCFDg,
bhupesh.sharma-KZfg59tc24xl57MIdRCFDg,
leoli-KZfg59tc24xl57MIdRCFDg, Hou Zhiqiang
From: Mingkai Hu <Mingkai.Hu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks
similar to LS1021a which complies to Chassis 2.1 spec.
Following levels of DTSI/DTS files have been created for the
LS1043A SoC family:
- fsl-ls1043a.dtsi:
DTS-Include file for FSL LS1043A SoC.
Signed-off-by: Li Yang <leoli-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Hou Zhiqiang <B48286-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Mingkai Hu <Mingkai.Hu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Signed-off-by: Wenbin Song <Wenbin.Song-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 501 +++++++++++++++++++++++++
1 file changed, 501 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
new file mode 100644
index 0000000..eca094d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -0,0 +1,501 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+ compatible = "fsl,ls1043a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ clocks = <&clockgen 1 0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0x1>, /* Physical Secure PPI */
+ <1 14 0x1>, /* Physical Non-Secure PPI */
+ <1 11 0x1>, /* Virtual PPI */
+ <1 10 0x1>; /* Hypervisor PPI */
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 106 0x4>,
+ <0 107 0x4>,
+ <0 95 0x4>,
+ <0 97 0x4>;
+ };
+
+ gic: interrupt-controller@1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+ <0x0 0x1402000 0 0x1000>, /* GICC */
+ <0x0 0x1404000 0 0x2000>, /* GICH */
+ <0x0 0x1406000 0 0x2000>; /* GICV */
+ interrupts = <1 9 0xf08>;
+ };
+
+ msi1: msi-controller1@1571000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1571000 0x0 0x4>,
+ <0x0 0x1571004 0x0 0x4>;
+ reg-names = "msiir", "msir";
+ msi-controller;
+ interrupts = <0 116 0x4>;
+ };
+
+ msi2: msi-controller2@1572000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1572000 0x0 0x4>,
+ <0x0 0x1572004 0x0 0x4>;
+ reg-names = "msiir", "msir";
+ msi-controller;
+ interrupts = <0 126 0x4>;
+ };
+
+ msi3: msi-controller3@1573000 {
+ compatible = "fsl,1s1043a-msi";
+ reg = <0x0 0x1573000 0x0 0x4>,
+ <0x0 0x1573004 0x0 0x4>;
+ reg-names = "msiir", "msir";
+ msi-controller;
+ interrupts = <0 160 0x4>;
+ };
+
+ ifc: ifc@1530000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x1530000 0x0 0x10000>;
+ interrupts = <0 43 0x4>;
+ };
+
+ esdhc: esdhc@1560000 {
+ compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x1560000 0x0 0x10000>;
+ interrupts = <0 62 0x4>;
+ clock-frequency = <0>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ big-endian;
+ bus-width = <4>;
+ };
+
+ scfg: scfg@1570000 {
+ compatible = "fsl,ls1043a-scfg", "syscon";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ big-endian;
+ };
+
+ dcfg: dcfg@1ee0000 {
+ compatible = "fsl,ls1043a-dcfg", "syscon";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ };
+
+ clockgen: clocking@1ee1000 {
+ compatible = "fsl,ls1043a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+ };
+
+ dspi0: dspi@2100000 {
+ compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 64 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ dspi1: dspi@2110000 {
+ compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <0 65 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ spi-num-chipselects = <5>;
+ big-endian;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ dmas = <&edma0 1 39>,
+ <&edma0 1 38>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c1: i2c@2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@21a0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21a0000 0x0 0x10000>;
+ interrupts = <0 58 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@21b0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21b0000 0x0 0x10000>;
+ interrupts = <0 59 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart0: serial@21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart1: serial@21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart2: serial@21d0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0500 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart3: serial@21d0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0600 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ gpio1: gpio@2300000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2310000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2320000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 68 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@2330000 {
+ compatible = "fsl,ls1043a-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 134 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ lpuart0: serial@2950000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2950000 0x0 0x1000>;
+ interrupts = <0 48 0x4>;
+ clocks = <&clockgen 0 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial@2960000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2960000 0x0 0x1000>;
+ interrupts = <0 49 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial@2970000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2970000 0x0 0x1000>;
+ interrupts = <0 50 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart3: serial@2980000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2980000 0x0 0x1000>;
+ interrupts = <0 51 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial@2990000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2990000 0x0 0x1000>;
+ interrupts = <0 52 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial@29a0000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x29a0000 0x0 0x1000>;
+ interrupts = <0 53 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ wdog0: wdog@2ad0000 {
+ compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
+ interrupts = <0 83 0x4>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "wdog";
+ big-endian;
+ };
+
+ edma0: edma@2c00000 {
+ #dma-cells = <2>;
+ compatible = "fsl,vf610-edma";
+ reg = <0x0 0x2c00000 0x0 0x10000>,
+ <0x0 0x2c10000 0x0 0x10000>,
+ <0x0 0x2c20000 0x0 0x10000>;
+ interrupts = <0 103 0x4>,
+ <0 103 0x4>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ big-endian;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clockgen 4 0>,
+ <&clockgen 4 0>;
+ };
+
+ usb0: usb3@2f00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x2f00000 0x0 0x10000>;
+ interrupts = <0 60 0x4>;
+ dr_mode = "host";
+ };
+
+ usb1: usb3@3000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3000000 0x0 0x10000>;
+ interrupts = <0 61 0x4>;
+ dr_mode = "host";
+ };
+ usb2: usb3@3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 63 0x4>;
+ dr_mode = "host";
+ };
+
+ pcie@3400000 {
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 118 0x4>, /* controller interrupt */
+ <0 117 0x4>; /* PME interrupt */
+ interrupt-names = "intr", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
+ <0000 0 0 2 &gic 0 111 0x4>,
+ <0000 0 0 3 &gic 0 112 0x4>,
+ <0000 0 0 4 &gic 0 113 0x4>;
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 128 0x4>,
+ <0 127 0x4>;
+ interrupt-names = "intr", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
+ <0000 0 0 2 &gic 0 121 0x4>,
+ <0000 0 0 3 &gic 0 122 0x4>,
+ <0000 0 0 4 &gic 0 123 0x4>;
+ };
+
+ pcie@3600000 {
+ compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 162 0x4>,
+ <0 161 0x4>;
+ interrupt-names = "intr", "pme";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&msi3>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
+ <0000 0 0 2 &gic 0 155 0x4>,
+ <0000 0 0 3 &gic 0 156 0x4>,
+ <0000 0 0 4 &gic 0 157 0x4>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>;
+ /* DRAM space 1 - 2 GB DRAM */
+ };
+
+};
--
2.1.0.27.g96db324
--
To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-21 12:22 ` Zhiqiang Hou
(?)
@ 2015-09-22 1:24 ` Mark Rutland, marc.zyngier
-1 siblings, 0 replies; 75+ messages in thread
From: Mark Rutland, marc.zyngier @ 2015-09-22 1:24 UTC (permalink / raw)
To: Zhiqiang Hou, marc.zyngier
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui.Xie@freescale.com,
corbet@lwn.net, bhupesh.sharma@freescale.com,
mturquette@baylibre.com, wsa@the-dreams.de, sboyd@codeaurora.org,
wim@iguana.be, Wenbin.Song@freescale.com, scottwood@freescale.com,
Mingkai.Hu@freescale.com, leoli@freescale.com
Hi,
> +/memreserve/ 0x80000000 0x00010000;
Why is this necessary?
If this is necessary, please add a comment stating what this is for.
> + cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x3>;
> + clocks = <&clockgen 1 0>;
> + };
Missing enable-method properties on all the secondary CPUs.
[...]
> + gic: interrupt-controller@1400000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
> + <0x0 0x1402000 0 0x1000>, /* GICC */
> + <0x0 0x1404000 0 0x2000>, /* GICH */
> + <0x0 0x1406000 0 0x2000>; /* GICV */
> + interrupts = <1 9 0xf08>;
> + };
These sizes don't look right.
To the best of my knowledge, GICC (and GICV) should be 0x2000 in size, while
GICD and GICH should be 0x1000.
[...]
> + ifc: ifc@1530000 {
> + compatible = "fsl,ifc", "simple-bus";
> + reg = <0x0 0x1530000 0x0 0x10000>;
> + interrupts = <0 43 0x4>;
> + };
Why simple-bus?
> + clockgen: clocking@1ee1000 {
> + compatible = "fsl,ls1043a-clockgen";
> + reg = <0x0 0x1ee1000 0x0 0x1000>;
> + #clock-cells = <2>;
> + clocks = <&sysclk>;
> + sysclk: sysclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-output-names = "sysclk";
> + };
> + };
Why does this fixed clock live under the clockgen? It should live directly
under the root node.
[...]
> + pcie@3400000 {
> + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
> + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 118 0x4>, /* controller interrupt */
> + <0 117 0x4>; /* PME interrupt */
> + interrupt-names = "intr", "pme";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <4>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&msi1>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
> + <0000 0 0 2 &gic 0 111 0x4>,
> + <0000 0 0 3 &gic 0 112 0x4>,
> + <0000 0 0 4 &gic 0 113 0x4>;
> + };
> +
> + pcie@3500000 {
> + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
> + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 128 0x4>,
> + <0 127 0x4>;
> + interrupt-names = "intr", "pme";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <2>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&msi2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
> + <0000 0 0 2 &gic 0 121 0x4>,
> + <0000 0 0 3 &gic 0 122 0x4>,
> + <0000 0 0 4 &gic 0 123 0x4>;
> + };
> +
> + pcie@3600000 {
> + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
> + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 162 0x4>,
> + <0 161 0x4>;
> + interrupt-names = "intr", "pme";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <2>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&msi3>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
> + <0000 0 0 2 &gic 0 155 0x4>,
> + <0000 0 0 3 &gic 0 156 0x4>,
> + <0000 0 0 4 &gic 0 157 0x4>;
> + };
You wait ages for a bus, then three show up at once...
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0 0x80000000>;
> + /* DRAM space 1 - 2 GB DRAM */
I don't understand the comment. This describes 2GB at 2GB.
Does the bootloader overwrite this?
Thanks,
Mark.
^ permalink raw reply [flat|nested] 75+ messages in thread* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 1:24 ` Mark Rutland, marc.zyngier
0 siblings, 0 replies; 75+ messages in thread
From: Mark Rutland @ 2015-09-22 1:24 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
> +/memreserve/ 0x80000000 0x00010000;
Why is this necessary?
If this is necessary, please add a comment stating what this is for.
> + cpu at 3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x3>;
> + clocks = <&clockgen 1 0>;
> + };
Missing enable-method properties on all the secondary CPUs.
[...]
> + gic: interrupt-controller at 1400000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
> + <0x0 0x1402000 0 0x1000>, /* GICC */
> + <0x0 0x1404000 0 0x2000>, /* GICH */
> + <0x0 0x1406000 0 0x2000>; /* GICV */
> + interrupts = <1 9 0xf08>;
> + };
These sizes don't look right.
To the best of my knowledge, GICC (and GICV) should be 0x2000 in size, while
GICD and GICH should be 0x1000.
[...]
> + ifc: ifc at 1530000 {
> + compatible = "fsl,ifc", "simple-bus";
> + reg = <0x0 0x1530000 0x0 0x10000>;
> + interrupts = <0 43 0x4>;
> + };
Why simple-bus?
> + clockgen: clocking at 1ee1000 {
> + compatible = "fsl,ls1043a-clockgen";
> + reg = <0x0 0x1ee1000 0x0 0x1000>;
> + #clock-cells = <2>;
> + clocks = <&sysclk>;
> + sysclk: sysclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-output-names = "sysclk";
> + };
> + };
Why does this fixed clock live under the clockgen? It should live directly
under the root node.
[...]
> + pcie at 3400000 {
> + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
> + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 118 0x4>, /* controller interrupt */
> + <0 117 0x4>; /* PME interrupt */
> + interrupt-names = "intr", "pme";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <4>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&msi1>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
> + <0000 0 0 2 &gic 0 111 0x4>,
> + <0000 0 0 3 &gic 0 112 0x4>,
> + <0000 0 0 4 &gic 0 113 0x4>;
> + };
> +
> + pcie at 3500000 {
> + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
> + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 128 0x4>,
> + <0 127 0x4>;
> + interrupt-names = "intr", "pme";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <2>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&msi2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
> + <0000 0 0 2 &gic 0 121 0x4>,
> + <0000 0 0 3 &gic 0 122 0x4>,
> + <0000 0 0 4 &gic 0 123 0x4>;
> + };
> +
> + pcie at 3600000 {
> + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
> + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 162 0x4>,
> + <0 161 0x4>;
> + interrupt-names = "intr", "pme";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <2>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&msi3>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
> + <0000 0 0 2 &gic 0 155 0x4>,
> + <0000 0 0 3 &gic 0 156 0x4>,
> + <0000 0 0 4 &gic 0 157 0x4>;
> + };
You wait ages for a bus, then three show up at once...
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0 0x80000000>;
> + /* DRAM space 1 - 2 GB DRAM */
I don't understand the comment. This describes 2GB at 2GB.
Does the bootloader overwrite this?
Thanks,
Mark.
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 1:24 ` Mark Rutland, marc.zyngier
0 siblings, 0 replies; 75+ messages in thread
From: Mark Rutland, marc.zyngier @ 2015-09-22 1:24 UTC (permalink / raw)
To: Zhiqiang Hou, marc.zyngier
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui.Xie@freescale.com,
corbet@lwn.net, bhupesh.sharma@freescale.com,
mturquette@baylibre.com, wsa@the-dreams.de, sboyd@codeaurora.org,
wim@iguana.be, Wenbin.Song@freescale.com, scottwood@freescale.com,
Mingkai.Hu@freescale.com
Hi,
> +/memreserve/ 0x80000000 0x00010000;
Why is this necessary?
If this is necessary, please add a comment stating what this is for.
> + cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x3>;
> + clocks = <&clockgen 1 0>;
> + };
Missing enable-method properties on all the secondary CPUs.
[...]
> + gic: interrupt-controller@1400000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
> + <0x0 0x1402000 0 0x1000>, /* GICC */
> + <0x0 0x1404000 0 0x2000>, /* GICH */
> + <0x0 0x1406000 0 0x2000>; /* GICV */
> + interrupts = <1 9 0xf08>;
> + };
These sizes don't look right.
To the best of my knowledge, GICC (and GICV) should be 0x2000 in size, while
GICD and GICH should be 0x1000.
[...]
> + ifc: ifc@1530000 {
> + compatible = "fsl,ifc", "simple-bus";
> + reg = <0x0 0x1530000 0x0 0x10000>;
> + interrupts = <0 43 0x4>;
> + };
Why simple-bus?
> + clockgen: clocking@1ee1000 {
> + compatible = "fsl,ls1043a-clockgen";
> + reg = <0x0 0x1ee1000 0x0 0x1000>;
> + #clock-cells = <2>;
> + clocks = <&sysclk>;
> + sysclk: sysclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-output-names = "sysclk";
> + };
> + };
Why does this fixed clock live under the clockgen? It should live directly
under the root node.
[...]
> + pcie@3400000 {
> + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
> + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 118 0x4>, /* controller interrupt */
> + <0 117 0x4>; /* PME interrupt */
> + interrupt-names = "intr", "pme";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <4>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&msi1>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
> + <0000 0 0 2 &gic 0 111 0x4>,
> + <0000 0 0 3 &gic 0 112 0x4>,
> + <0000 0 0 4 &gic 0 113 0x4>;
> + };
> +
> + pcie@3500000 {
> + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
> + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 128 0x4>,
> + <0 127 0x4>;
> + interrupt-names = "intr", "pme";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <2>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&msi2>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
> + <0000 0 0 2 &gic 0 121 0x4>,
> + <0000 0 0 3 &gic 0 122 0x4>,
> + <0000 0 0 4 &gic 0 123 0x4>;
> + };
> +
> + pcie@3600000 {
> + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
> + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
> + reg-names = "regs", "config";
> + interrupts = <0 162 0x4>,
> + <0 161 0x4>;
> + interrupt-names = "intr", "pme";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <2>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + msi-parent = <&msi3>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
> + <0000 0 0 2 &gic 0 155 0x4>,
> + <0000 0 0 3 &gic 0 156 0x4>,
> + <0000 0 0 4 &gic 0 157 0x4>;
> + };
You wait ages for a bus, then three show up at once...
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0 0x80000000>;
> + /* DRAM space 1 - 2 GB DRAM */
I don't understand the comment. This describes 2GB at 2GB.
Does the bootloader overwrite this?
Thanks,
Mark.
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 1:24 ` Mark Rutland, marc.zyngier
(?)
(?)
@ 2015-09-22 1:30 ` Scott Wood
-1 siblings, 0 replies; 75+ messages in thread
From: Scott Wood @ 2015-09-22 1:30 UTC (permalink / raw)
To: Mark Rutland, marc.zyngier
Cc: corbet@lwn.net, sboyd@codeaurora.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
bhupesh.sharma@freescale.com, Catalin Marinas,
mturquette@baylibre.com, Zhiqiang Hou, Will Deacon, wim@iguana.be,
linux-i2c@vger.kernel.org, wsa@the-dreams.de,
Mingkai.Hu@freescale.com, leoli@freescale.com,
Wenbin.Song@freescale.com, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Shaohui.Xie@freescale.com
On Tue, 2015-09-22 at 02:24 +0100, Mark Rutland wrote:
> > + clockgen: clocking@1ee1000{
> > + compatible = "fsl,ls1043a-clockgen";
> > + reg = <0x0 0x1ee1000 0x0 0x1000>;
> > + #clock-cells = <2>;
> > + clocks = <&sysclk>;
> > + sysclk: sysclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "sysclk";
> > + };
> > + };
>
> Why does this fixed clock live under the clockgen? It should live directly
> under the root node.
I think this is copy-and-paste from some legacy PPC stuff. There's no reason
anymore to put sysclk under clockgen.
-Scott
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 75+ messages in thread* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 1:30 ` Scott Wood
0 siblings, 0 replies; 75+ messages in thread
From: Scott Wood @ 2015-09-22 1:30 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 2015-09-22 at 02:24 +0100, Mark Rutland wrote:
> > + clockgen: clocking at 1ee1000{
> > + compatible = "fsl,ls1043a-clockgen";
> > + reg = <0x0 0x1ee1000 0x0 0x1000>;
> > + #clock-cells = <2>;
> > + clocks = <&sysclk>;
> > + sysclk: sysclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "sysclk";
> > + };
> > + };
>
> Why does this fixed clock live under the clockgen? It should live directly
> under the root node.
I think this is copy-and-paste from some legacy PPC stuff. There's no reason
anymore to put sysclk under clockgen.
-Scott
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 1:30 ` Scott Wood
0 siblings, 0 replies; 75+ messages in thread
From: Scott Wood @ 2015-09-22 1:30 UTC (permalink / raw)
To: Mark Rutland, marc.zyngier
Cc: Zhiqiang Hou, linux-arm-kernel@lists.infradead.org,
Catalin Marinas, Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui.Xie@freescale.com,
corbet@lwn.net, bhupesh.sharma@freescale.com,
mturquette@baylibre.com, wsa@the-dreams.de, sboyd@codeaurora.org,
wim@iguana.be, Wenbin.Song@freescale.com,
Mingkai.Hu@freescale.com, leoli@freescale.com
On Tue, 2015-09-22 at 02:24 +0100, Mark Rutland wrote:
> > + clockgen: clocking@1ee1000{
> > + compatible = "fsl,ls1043a-clockgen";
> > + reg = <0x0 0x1ee1000 0x0 0x1000>;
> > + #clock-cells = <2>;
> > + clocks = <&sysclk>;
> > + sysclk: sysclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "sysclk";
> > + };
> > + };
>
> Why does this fixed clock live under the clockgen? It should live directly
> under the root node.
I think this is copy-and-paste from some legacy PPC stuff. There's no reason
anymore to put sysclk under clockgen.
-Scott
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 1:30 ` Scott Wood
0 siblings, 0 replies; 75+ messages in thread
From: Scott Wood @ 2015-09-22 1:30 UTC (permalink / raw)
To: Mark Rutland, marc.zyngier
Cc: corbet@lwn.net, sboyd@codeaurora.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
bhupesh.sharma@freescale.com, Catalin Marinas,
mturquette@baylibre.com, Zhiqiang Hou, Will Deacon, wim@iguana.be,
linux-i2c@vger.kernel.org, wsa@the-dreams.de,
Mingkai.Hu@freescale.com, leoli@freescale.com,
Wenbin.Song@freescale.com, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Shaohui.Xie
On Tue, 2015-09-22 at 02:24 +0100, Mark Rutland wrote:
> > + clockgen: clocking@1ee1000{
> > + compatible = "fsl,ls1043a-clockgen";
> > + reg = <0x0 0x1ee1000 0x0 0x1000>;
> > + #clock-cells = <2>;
> > + clocks = <&sysclk>;
> > + sysclk: sysclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "sysclk";
> > + };
> > + };
>
> Why does this fixed clock live under the clockgen? It should live directly
> under the root node.
I think this is copy-and-paste from some legacy PPC stuff. There's no reason
anymore to put sysclk under clockgen.
-Scott
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 1:24 ` Mark Rutland, marc.zyngier
(?)
(?)
@ 2015-09-22 9:50 ` Hou Zhiqiang
-1 siblings, 0 replies; 75+ messages in thread
From: Hou Zhiqiang @ 2015-09-22 9:50 UTC (permalink / raw)
To: Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent, Li Leo
SGkgTWFyaywNCg0KPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBNYXJrIFJ1
dGxhbmQgW21haWx0bzptYXJrLnJ1dGxhbmRAYXJtLmNvbV0NCj4gU2VudDogMjAxNcTqOdTCMjLI
1SA5OjI0DQo+IFRvOiBIb3UgWmhpcWlhbmctQjQ4Mjg2OyBtYXJjLnp5bmdpZXJAYXJtLmNvbQ0K
PiBDYzogbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnOyBDYXRhbGluIE1hcmlu
YXM7IFdpbGwgRGVhY29uOw0KPiBsaW51eC1pMmNAdmdlci5rZXJuZWwub3JnOyBsaW51eC13YXRj
aGRvZ0B2Z2VyLmtlcm5lbC5vcmc7IGxpbnV4LQ0KPiBkb2NAdmdlci5rZXJuZWwub3JnOyBsaW51
eC1jbGtAdmdlci5rZXJuZWwub3JnOyBYaWUgU2hhb2h1aS1CMjE5ODk7DQo+IGNvcmJldEBsd24u
bmV0OyBTaGFybWEgQmh1cGVzaC1CNDUzNzA7IG10dXJxdWV0dGVAYmF5bGlicmUuY29tOyB3c2FA
dGhlLQ0KPiBkcmVhbXMuZGU7IHNib3lkQGNvZGVhdXJvcmEub3JnOyB3aW1AaWd1YW5hLmJlOyBT
b25nIFdlbmJpbi1CNTM3NDc7IFdvb2QNCj4gU2NvdHQtQjA3NDIxOyBIdSBNaW5na2FpLUIyMTI4
NDsgTGkgWWFuZy1MZW8tUjU4NDcyDQo+IFN1YmplY3Q6IFJlOiBbUEFUQ0ggNC82XSBhcm02NC9s
czEwNDNhOiBhZGQgRFRTIGZvciBGcmVlc2NhbGUgTFMxMDQzQSBTb0MNCj4gDQo+IEhpLA0KPiAN
Cj4gPiArL21lbXJlc2VydmUvIDB4ODAwMDAwMDAgMHgwMDAxMDAwMDsNCj4gDQo+IFdoeSBpcyB0
aGlzIG5lY2Vzc2FyeT8NCiANClRoaXMgbWVtb3J5IHJlZ2lvbiBpcyBwcmUtcmVzZXJ2ZWQgZm9y
IHRoZSBzcGluLXRhYmxlL3BzY2ksIGFsdGhvdWdoIGRpZG4ndCBhZGQNCkVuYWJsZSBtZXRob2Qg
b2Ygc2Vjb25kYXJ5IGNvcmVzLg0KDQo+IElmIHRoaXMgaXMgbmVjZXNzYXJ5LCBwbGVhc2UgYWRk
IGEgY29tbWVudCBzdGF0aW5nIHdoYXQgdGhpcyBpcyBmb3IuDQo+IA0KPiA+ICsgICAgICAgICAg
ICAgICBjcHVAMyB7DQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgZGV2aWNlX3R5cGUgPSAi
Y3B1IjsNCj4gPiArICAgICAgICAgICAgICAgICAgICAgICBjb21wYXRpYmxlID0gImFybSxjb3J0
ZXgtYTUzIjsNCj4gPiArICAgICAgICAgICAgICAgICAgICAgICByZWcgPSA8MHgwIDB4Mz47DQo+
ID4gKyAgICAgICAgICAgICAgICAgICAgICAgY2xvY2tzID0gPCZjbG9ja2dlbiAxIDA+Ow0KPiA+
ICsgICAgICAgICAgICAgICB9Ow0KPiANCj4gTWlzc2luZyBlbmFibGUtbWV0aG9kIHByb3BlcnRp
ZXMgb24gYWxsIHRoZSBzZWNvbmRhcnkgQ1BVcy4NCj4gDQoNClRoZXJlIGFyZSB0d28gbWV0aG9k
cyAoc3Bpbi10YWJsZSBhbmQgcHNjaSkgdG8gYnJpbmcgdXAgc2Vjb25kYXJ5IGNvcmVzLCB3aGlj
aCBvbmUNCmRvIHlvdSB0aGluayBpcyBiZXR0ZXI/DQoNCj4gWy4uLl0NCj4gDQo+ID4gKyAgICAg
ICBnaWM6IGludGVycnVwdC1jb250cm9sbGVyQDE0MDAwMDAgew0KPiA+ICsgICAgICAgICAgICAg
ICBjb21wYXRpYmxlID0gImFybSxnaWMtNDAwIjsNCj4gPiArICAgICAgICAgICAgICAgI2ludGVy
cnVwdC1jZWxscyA9IDwzPjsNCj4gPiArICAgICAgICAgICAgICAgaW50ZXJydXB0LWNvbnRyb2xs
ZXI7DQo+ID4gKyAgICAgICAgICAgICAgIHJlZyA9IDwweDAgMHgxNDAxMDAwIDAgMHgxMDAwPiwg
LyogR0lDRCAqLw0KPiA+ICsgICAgICAgICAgICAgICAgICAgICA8MHgwIDB4MTQwMjAwMCAwIDB4
MTAwMD4sIC8qIEdJQ0MgKi8NCj4gPiArICAgICAgICAgICAgICAgICAgICAgPDB4MCAweDE0MDQw
MDAgMCAweDIwMDA+LCAvKiBHSUNIICovDQo+ID4gKyAgICAgICAgICAgICAgICAgICAgIDwweDAg
MHgxNDA2MDAwIDAgMHgyMDAwPjsgLyogR0lDViAqLw0KPiA+ICsgICAgICAgICAgICAgICBpbnRl
cnJ1cHRzID0gPDEgOSAweGYwOD47DQo+ID4gKyAgICAgICB9Ow0KPiANCj4gVGhlc2Ugc2l6ZXMg
ZG9uJ3QgbG9vayByaWdodC4NCj4gDQo+IFRvIHRoZSBiZXN0IG9mIG15IGtub3dsZWRnZSwgR0lD
QyAoYW5kIEdJQ1YpIHNob3VsZCBiZSAweDIwMDAgaW4gc2l6ZSwNCj4gd2hpbGUgR0lDRCBhbmQg
R0lDSCBzaG91bGQgYmUgMHgxMDAwLg0KDQpUaGFua3MgZm9yIHlvdXIgY29ycmVjdGlvbi4NCg0K
PiANCj4gWy4uLl0NCj4gDQo+ID4gKyAgICAgICBpZmM6IGlmY0AxNTMwMDAwIHsNCj4gPiArICAg
ICAgICAgICAgICAgY29tcGF0aWJsZSA9ICJmc2wsaWZjIiwgInNpbXBsZS1idXMiOw0KPiA+ICsg
ICAgICAgICAgICAgICByZWcgPSA8MHgwIDB4MTUzMDAwMCAweDAgMHgxMDAwMD47DQo+ID4gKyAg
ICAgICAgICAgICAgIGludGVycnVwdHMgPSA8MCA0MyAweDQ+Ow0KPiA+ICsgICAgICAgfTsNCj4g
DQo+IFdoeSBzaW1wbGUtYnVzPw0KDQpUaGVyZSBhcmUgMyBjaGlsZCBub2RlIGxvY2F0ZWQgaW4g
ZHRzaSBmaWxlIHRoYXQgc2hvdWxkIGJlIGNyZWF0ZWQgYW5kIGFkZGVkDQp0byBwbGF0Zm9ybSBk
ZXZpY2UgbGlzdC4NCg0KPiANCj4gPiArICAgICAgIGNsb2NrZ2VuOiBjbG9ja2luZ0AxZWUxMDAw
IHsNCj4gPiArICAgICAgICAgICAgICAgY29tcGF0aWJsZSA9ICJmc2wsbHMxMDQzYS1jbG9ja2dl
biI7DQo+ID4gKyAgICAgICAgICAgICAgIHJlZyA9IDwweDAgMHgxZWUxMDAwIDB4MCAweDEwMDA+
Ow0KPiA+ICsgICAgICAgICAgICAgICAjY2xvY2stY2VsbHMgPSA8Mj47DQo+ID4gKyAgICAgICAg
ICAgICAgIGNsb2NrcyA9IDwmc3lzY2xrPjsNCj4gPiArICAgICAgICAgICAgICAgc3lzY2xrOiBz
eXNjbGsgew0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIGNvbXBhdGlibGUgPSAiZml4ZWQt
Y2xvY2siOw0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICNjbG9jay1jZWxscyA9IDwwPjsN
Cj4gPiArICAgICAgICAgICAgICAgICAgICAgICBjbG9jay1mcmVxdWVuY3kgPSA8MTAwMDAwMDAw
PjsNCj4gPiArICAgICAgICAgICAgICAgICAgICAgICBjbG9jay1vdXRwdXQtbmFtZXMgPSAic3lz
Y2xrIjsNCj4gPiArICAgICAgICAgICAgICAgfTsNCj4gPiArICAgICAgIH07DQo+IA0KPiBXaHkg
ZG9lcyB0aGlzIGZpeGVkIGNsb2NrIGxpdmUgdW5kZXIgdGhlIGNsb2NrZ2VuPyBJdCBzaG91bGQg
bGl2ZQ0KPiBkaXJlY3RseSB1bmRlciB0aGUgcm9vdCBub2RlLg0KPiANCg0KVGhhbmtzIGFuZCB3
aWxsIG1vdmUgaXQgb3V0IGluIHYyLg0KDQo+IFsuLi5dDQo+IA0KPiA+ICsgICAgICAgcGNpZUAz
NDAwMDAwIHsNCj4gPiArICAgICAgICAgICAgICAgY29tcGF0aWJsZSA9ICJmc2wsbHMxMDQzYS1w
Y2llIiwgInNucHMsZHctcGNpZSI7DQo+ID4gKyAgICAgICAgICAgICAgIHJlZyA9IDwweDAwIDB4
MDM0MDAwMDAgMHgwIDB4MDAxMDAwMDAgICAvKiBjb250cm9sbGVyDQo+IHJlZ2lzdGVycyAqLw0K
PiA+ICsgICAgICAgICAgICAgICAgICAgICAgMHg0MCAweDAwMDAwMDAwIDB4MCAweDAwMDAyMDAw
PjsgLyoNCj4gY29uZmlndXJhdGlvbiBzcGFjZSAqLw0KPiA+ICsgICAgICAgICAgICAgICByZWct
bmFtZXMgPSAicmVncyIsICJjb25maWciOw0KPiA+ICsgICAgICAgICAgICAgICBpbnRlcnJ1cHRz
ID0gPDAgMTE4IDB4ND4sIC8qIGNvbnRyb2xsZXIgaW50ZXJydXB0ICovDQo+ID4gKyAgICAgICAg
ICAgICAgICAgICAgICAgICAgICA8MCAxMTcgMHg0PjsgLyogUE1FIGludGVycnVwdCAqLw0KPiA+
ICsgICAgICAgICAgICAgICBpbnRlcnJ1cHQtbmFtZXMgPSAiaW50ciIsICJwbWUiOw0KPiA+ICsg
ICAgICAgICAgICAgICAjYWRkcmVzcy1jZWxscyA9IDwzPjsNCj4gPiArICAgICAgICAgICAgICAg
I3NpemUtY2VsbHMgPSA8Mj47DQo+ID4gKyAgICAgICAgICAgICAgIGRldmljZV90eXBlID0gInBj
aSI7DQo+ID4gKyAgICAgICAgICAgICAgIG51bS1sYW5lcyA9IDw0PjsNCj4gPiArICAgICAgICAg
ICAgICAgYnVzLXJhbmdlID0gPDB4MCAweGZmPjsNCj4gPiArICAgICAgICAgICAgICAgcmFuZ2Vz
ID0gPDB4ODEwMDAwMDAgMHgwIDB4MDAwMDAwMDAgMHg0MCAweDAwMDEwMDAwIDB4MA0KPiAweDAw
MDEwMDAwICAgLyogZG93bnN0cmVhbSBJL08gKi8NCj4gPiArICAgICAgICAgICAgICAgICAgICAg
ICAgIDB4ODIwMDAwMDAgMHgwIDB4NDAwMDAwMDAgMHg0MCAweDQwMDAwMDAwIDB4MA0KPiAweDQw
MDAwMDAwPjsgLyogbm9uLXByZWZldGNoYWJsZSBtZW1vcnkgKi8NCj4gPiArICAgICAgICAgICAg
ICAgbXNpLXBhcmVudCA9IDwmbXNpMT47DQo+ID4gKyAgICAgICAgICAgICAgICNpbnRlcnJ1cHQt
Y2VsbHMgPSA8MT47DQo+ID4gKyAgICAgICAgICAgICAgIGludGVycnVwdC1tYXAtbWFzayA9IDww
IDAgMCA3PjsNCj4gPiArICAgICAgICAgICAgICAgaW50ZXJydXB0LW1hcCA9IDwwMDAwIDAgMCAx
ICZnaWMgMCAxMTAgMHg0PiwNCj4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIDww
MDAwIDAgMCAyICZnaWMgMCAxMTEgMHg0PiwNCj4gPiArICAgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgIDwwMDAwIDAgMCAzICZnaWMgMCAxMTIgMHg0PiwNCj4gPiArICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgIDwwMDAwIDAgMCA0ICZnaWMgMCAxMTMgMHg0PjsNCj4gPiArICAgICAg
IH07DQo+ID4gKw0KPiA+ICsgICAgICAgcGNpZUAzNTAwMDAwIHsNCj4gPiArICAgICAgICAgICAg
ICAgY29tcGF0aWJsZSA9ICJmc2wsbHMxMDQzYS1wY2llIiwgInNucHMsZHctcGNpZSI7DQo+ID4g
KyAgICAgICAgICAgICAgIHJlZyA9IDwweDAwIDB4MDM1MDAwMDAgMHgwIDB4MDAxMDAwMDAgICAv
KiBjb250cm9sbGVyDQo+IHJlZ2lzdGVycyAqLw0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAg
MHg0OCAweDAwMDAwMDAwIDB4MCAweDAwMDAyMDAwPjsgLyoNCj4gY29uZmlndXJhdGlvbiBzcGFj
ZSAqLw0KPiA+ICsgICAgICAgICAgICAgICByZWctbmFtZXMgPSAicmVncyIsICJjb25maWciOw0K
PiA+ICsgICAgICAgICAgICAgICBpbnRlcnJ1cHRzID0gPDAgMTI4IDB4ND4sDQo+ID4gKyAgICAg
ICAgICAgICAgICAgICAgICAgICAgICA8MCAxMjcgMHg0PjsNCj4gPiArICAgICAgICAgICAgICAg
aW50ZXJydXB0LW5hbWVzID0gImludHIiLCAicG1lIjsNCj4gPiArICAgICAgICAgICAgICAgI2Fk
ZHJlc3MtY2VsbHMgPSA8Mz47DQo+ID4gKyAgICAgICAgICAgICAgICNzaXplLWNlbGxzID0gPDI+
Ow0KPiA+ICsgICAgICAgICAgICAgICBkZXZpY2VfdHlwZSA9ICJwY2kiOw0KPiA+ICsgICAgICAg
ICAgICAgICBudW0tbGFuZXMgPSA8Mj47DQo+ID4gKyAgICAgICAgICAgICAgIGJ1cy1yYW5nZSA9
IDwweDAgMHhmZj47DQo+ID4gKyAgICAgICAgICAgICAgIHJhbmdlcyA9IDwweDgxMDAwMDAwIDB4
MCAweDAwMDAwMDAwIDB4NDggMHgwMDAxMDAwMCAweDANCj4gMHgwMDAxMDAwMCAgIC8qIGRvd25z
dHJlYW0gSS9PICovDQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAweDgyMDAwMDAwIDB4
MCAweDQwMDAwMDAwIDB4NDggMHg0MDAwMDAwMCAweDANCj4gMHg0MDAwMDAwMD47IC8qIG5vbi1w
cmVmZXRjaGFibGUgbWVtb3J5ICovDQo+ID4gKyAgICAgICAgICAgICAgIG1zaS1wYXJlbnQgPSA8
Jm1zaTI+Ow0KPiA+ICsgICAgICAgICAgICAgICAjaW50ZXJydXB0LWNlbGxzID0gPDE+Ow0KPiA+
ICsgICAgICAgICAgICAgICBpbnRlcnJ1cHQtbWFwLW1hc2sgPSA8MCAwIDAgNz47DQo+ID4gKyAg
ICAgICAgICAgICAgIGludGVycnVwdC1tYXAgPSA8MDAwMCAwIDAgMSAmZ2ljIDAgMTIwICAweDQ+
LA0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgPDAwMDAgMCAwIDIgJmdpYyAw
IDEyMSAweDQ+LA0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgPDAwMDAgMCAw
IDMgJmdpYyAwIDEyMiAweDQ+LA0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg
PDAwMDAgMCAwIDQgJmdpYyAwIDEyMyAweDQ+Ow0KPiA+ICsgICAgICAgfTsNCj4gPiArDQo+ID4g
KyAgICAgICBwY2llQDM2MDAwMDAgew0KPiA+ICsgICAgICAgICAgICAgICBjb21wYXRpYmxlID0g
ImZzbCxsczEwNDNhLXBjaWUiLCAic25wcyxkdy1wY2llIjsNCj4gPiArICAgICAgICAgICAgICAg
cmVnID0gPDB4MDAgMHgwMzYwMDAwMCAweDAgMHgwMDEwMDAwMCAgIC8qIGNvbnRyb2xsZXINCj4g
cmVnaXN0ZXJzICovDQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAweDUwIDB4MDAwMDAwMDAg
MHgwIDB4MDAwMDIwMDA+OyAvKg0KPiBjb25maWd1cmF0aW9uIHNwYWNlICovDQo+ID4gKyAgICAg
ICAgICAgICAgIHJlZy1uYW1lcyA9ICJyZWdzIiwgImNvbmZpZyI7DQo+ID4gKyAgICAgICAgICAg
ICAgIGludGVycnVwdHMgPSA8MCAxNjIgMHg0PiwNCj4gPiArICAgICAgICAgICAgICAgICAgICAg
ICAgICAgIDwwIDE2MSAweDQ+Ow0KPiA+ICsgICAgICAgICAgICAgICBpbnRlcnJ1cHQtbmFtZXMg
PSAiaW50ciIsICJwbWUiOw0KPiA+ICsgICAgICAgICAgICAgICAjYWRkcmVzcy1jZWxscyA9IDwz
PjsNCj4gPiArICAgICAgICAgICAgICAgI3NpemUtY2VsbHMgPSA8Mj47DQo+ID4gKyAgICAgICAg
ICAgICAgIGRldmljZV90eXBlID0gInBjaSI7DQo+ID4gKyAgICAgICAgICAgICAgIG51bS1sYW5l
cyA9IDwyPjsNCj4gPiArICAgICAgICAgICAgICAgYnVzLXJhbmdlID0gPDB4MCAweGZmPjsNCj4g
PiArICAgICAgICAgICAgICAgcmFuZ2VzID0gPDB4ODEwMDAwMDAgMHgwIDB4MDAwMDAwMDAgMHg1
MCAweDAwMDEwMDAwIDB4MA0KPiAweDAwMDEwMDAwICAgLyogZG93bnN0cmVhbSBJL08gKi8NCj4g
PiArICAgICAgICAgICAgICAgICAgICAgICAgIDB4ODIwMDAwMDAgMHgwIDB4NDAwMDAwMDAgMHg1
MCAweDQwMDAwMDAwIDB4MA0KPiAweDQwMDAwMDAwPjsgLyogbm9uLXByZWZldGNoYWJsZSBtZW1v
cnkgKi8NCj4gPiArICAgICAgICAgICAgICAgbXNpLXBhcmVudCA9IDwmbXNpMz47DQo+ID4gKyAg
ICAgICAgICAgICAgICNpbnRlcnJ1cHQtY2VsbHMgPSA8MT47DQo+ID4gKyAgICAgICAgICAgICAg
IGludGVycnVwdC1tYXAtbWFzayA9IDwwIDAgMCA3PjsNCj4gPiArICAgICAgICAgICAgICAgaW50
ZXJydXB0LW1hcCA9IDwwMDAwIDAgMCAxICZnaWMgMCAxNTQgMHg0PiwNCj4gPiArICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgIDwwMDAwIDAgMCAyICZnaWMgMCAxNTUgMHg0PiwNCj4gPiAr
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIDwwMDAwIDAgMCAzICZnaWMgMCAxNTYgMHg0
PiwNCj4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIDwwMDAwIDAgMCA0ICZnaWMg
MCAxNTcgMHg0PjsNCj4gPiArICAgICAgIH07DQo+IA0KPiBZb3Ugd2FpdCBhZ2VzIGZvciBhIGJ1
cywgdGhlbiB0aHJlZSBzaG93IHVwIGF0IG9uY2UuLi4NCj4gDQo+ID4gKw0KPiA+ICsgICAgICAg
bWVtb3J5QDgwMDAwMDAwIHsNCj4gPiArICAgICAgICAgICAgICAgZGV2aWNlX3R5cGUgPSAibWVt
b3J5IjsNCj4gPiArICAgICAgICAgICAgICAgcmVnID0gPDB4MCAweDgwMDAwMDAwIDAgMHg4MDAw
MDAwMD47DQo+ID4gKyAgICAgICAgICAgICAgICAgICAgIC8qIERSQU0gc3BhY2UgMSAtIDIgR0Ig
RFJBTSAqLw0KPiANCj4gSSBkb24ndCB1bmRlcnN0YW5kIHRoZSBjb21tZW50LiBUaGlzIGRlc2Ny
aWJlcyAyR0IgYXQgMkdCLg0KPiANCg0KWWVzLCB0aGVyZSBpcyBhIDJHQiBzcGFjZSBmb3IgRFJB
TSBmcm9tIGFkZHJlc3MgMkcuDQpUaGUgRFJBTSBhZGRyZXNzIDB4MCB3aWxsIGJlIHJlbWFwcGVk
IHRvIFNvQyBhZGRyZXNzIDJHLCB0aGlzIHJlbWFwIGlzIGRvbmUgYnkgaGFyZHdhcmUuDQoNCj4g
RG9lcyB0aGUgYm9vdGxvYWRlciBvdmVyd3JpdGUgdGhpcz8NCg0KTm8uDQogDQpUaGFua3MsDQpa
aGlxaWFuZw0K
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 9:50 ` Hou Zhiqiang
0 siblings, 0 replies; 75+ messages in thread
From: Hou Zhiqiang @ 2015-09-22 9:50 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mark,
> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland at arm.com]
> Sent: 2015?9?22? 9:24
> To: Hou Zhiqiang-B48286; marc.zyngier at arm.com
> Cc: linux-arm-kernel at lists.infradead.org; Catalin Marinas; Will Deacon;
> linux-i2c at vger.kernel.org; linux-watchdog at vger.kernel.org; linux-
> doc at vger.kernel.org; linux-clk at vger.kernel.org; Xie Shaohui-B21989;
> corbet at lwn.net; Sharma Bhupesh-B45370; mturquette at baylibre.com; wsa at the-
> dreams.de; sboyd at codeaurora.org; wim at iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284; Li Yang-Leo-R58472
> Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> Hi,
>
> > +/memreserve/ 0x80000000 0x00010000;
>
> Why is this necessary?
This memory region is pre-reserved for the spin-table/psci, although didn't add
Enable method of secondary cores.
> If this is necessary, please add a comment stating what this is for.
>
> > + cpu at 3 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x0 0x3>;
> > + clocks = <&clockgen 1 0>;
> > + };
>
> Missing enable-method properties on all the secondary CPUs.
>
There are two methods (spin-table and psci) to bring up secondary cores, which one
do you think is better?
> [...]
>
> > + gic: interrupt-controller at 1400000 {
> > + compatible = "arm,gic-400";
> > + #interrupt-cells = <3>;
> > + interrupt-controller;
> > + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
> > + <0x0 0x1402000 0 0x1000>, /* GICC */
> > + <0x0 0x1404000 0 0x2000>, /* GICH */
> > + <0x0 0x1406000 0 0x2000>; /* GICV */
> > + interrupts = <1 9 0xf08>;
> > + };
>
> These sizes don't look right.
>
> To the best of my knowledge, GICC (and GICV) should be 0x2000 in size,
> while GICD and GICH should be 0x1000.
Thanks for your correction.
>
> [...]
>
> > + ifc: ifc at 1530000 {
> > + compatible = "fsl,ifc", "simple-bus";
> > + reg = <0x0 0x1530000 0x0 0x10000>;
> > + interrupts = <0 43 0x4>;
> > + };
>
> Why simple-bus?
There are 3 child node located in dtsi file that should be created and added
to platform device list.
>
> > + clockgen: clocking at 1ee1000 {
> > + compatible = "fsl,ls1043a-clockgen";
> > + reg = <0x0 0x1ee1000 0x0 0x1000>;
> > + #clock-cells = <2>;
> > + clocks = <&sysclk>;
> > + sysclk: sysclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "sysclk";
> > + };
> > + };
>
> Why does this fixed clock live under the clockgen? It should live
> directly under the root node.
>
Thanks and will move it out in v2.
> [...]
>
> > + pcie at 3400000 {
> > + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> > + reg = <0x00 0x03400000 0x0 0x00100000 /* controller
> registers */
> > + 0x40 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 118 0x4>, /* controller interrupt */
> > + <0 117 0x4>; /* PME interrupt */
> > + interrupt-names = "intr", "pme";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + num-lanes = <4>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&msi1>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
> > + <0000 0 0 2 &gic 0 111 0x4>,
> > + <0000 0 0 3 &gic 0 112 0x4>,
> > + <0000 0 0 4 &gic 0 113 0x4>;
> > + };
> > +
> > + pcie at 3500000 {
> > + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> > + reg = <0x00 0x03500000 0x0 0x00100000 /* controller
> registers */
> > + 0x48 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 128 0x4>,
> > + <0 127 0x4>;
> > + interrupt-names = "intr", "pme";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + num-lanes = <2>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&msi2>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
> > + <0000 0 0 2 &gic 0 121 0x4>,
> > + <0000 0 0 3 &gic 0 122 0x4>,
> > + <0000 0 0 4 &gic 0 123 0x4>;
> > + };
> > +
> > + pcie at 3600000 {
> > + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> > + reg = <0x00 0x03600000 0x0 0x00100000 /* controller
> registers */
> > + 0x50 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 162 0x4>,
> > + <0 161 0x4>;
> > + interrupt-names = "intr", "pme";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + num-lanes = <2>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&msi3>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
> > + <0000 0 0 2 &gic 0 155 0x4>,
> > + <0000 0 0 3 &gic 0 156 0x4>,
> > + <0000 0 0 4 &gic 0 157 0x4>;
> > + };
>
> You wait ages for a bus, then three show up at once...
>
> > +
> > + memory at 80000000 {
> > + device_type = "memory";
> > + reg = <0x0 0x80000000 0 0x80000000>;
> > + /* DRAM space 1 - 2 GB DRAM */
>
> I don't understand the comment. This describes 2GB at 2GB.
>
Yes, there is a 2GB space for DRAM from address 2G.
The DRAM address 0x0 will be remapped to SoC address 2G, this remap is done by hardware.
> Does the bootloader overwrite this?
No.
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 9:50 ` Hou Zhiqiang
0 siblings, 0 replies; 75+ messages in thread
From: Hou Zhiqiang @ 2015-09-22 9:50 UTC (permalink / raw)
To: Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent, Li Leo
Hi Mark,
> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland@arm.com]
> Sent: 2015年9月22日 9:24
> To: Hou Zhiqiang-B48286; marc.zyngier@arm.com
> Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will Deacon;
> linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284; Li Yang-Leo-R58472
> Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> Hi,
>
> > +/memreserve/ 0x80000000 0x00010000;
>
> Why is this necessary?
This memory region is pre-reserved for the spin-table/psci, although didn't add
Enable method of secondary cores.
> If this is necessary, please add a comment stating what this is for.
>
> > + cpu@3 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x0 0x3>;
> > + clocks = <&clockgen 1 0>;
> > + };
>
> Missing enable-method properties on all the secondary CPUs.
>
There are two methods (spin-table and psci) to bring up secondary cores, which one
do you think is better?
> [...]
>
> > + gic: interrupt-controller@1400000 {
> > + compatible = "arm,gic-400";
> > + #interrupt-cells = <3>;
> > + interrupt-controller;
> > + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
> > + <0x0 0x1402000 0 0x1000>, /* GICC */
> > + <0x0 0x1404000 0 0x2000>, /* GICH */
> > + <0x0 0x1406000 0 0x2000>; /* GICV */
> > + interrupts = <1 9 0xf08>;
> > + };
>
> These sizes don't look right.
>
> To the best of my knowledge, GICC (and GICV) should be 0x2000 in size,
> while GICD and GICH should be 0x1000.
Thanks for your correction.
>
> [...]
>
> > + ifc: ifc@1530000 {
> > + compatible = "fsl,ifc", "simple-bus";
> > + reg = <0x0 0x1530000 0x0 0x10000>;
> > + interrupts = <0 43 0x4>;
> > + };
>
> Why simple-bus?
There are 3 child node located in dtsi file that should be created and added
to platform device list.
>
> > + clockgen: clocking@1ee1000 {
> > + compatible = "fsl,ls1043a-clockgen";
> > + reg = <0x0 0x1ee1000 0x0 0x1000>;
> > + #clock-cells = <2>;
> > + clocks = <&sysclk>;
> > + sysclk: sysclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "sysclk";
> > + };
> > + };
>
> Why does this fixed clock live under the clockgen? It should live
> directly under the root node.
>
Thanks and will move it out in v2.
> [...]
>
> > + pcie@3400000 {
> > + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> > + reg = <0x00 0x03400000 0x0 0x00100000 /* controller
> registers */
> > + 0x40 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 118 0x4>, /* controller interrupt */
> > + <0 117 0x4>; /* PME interrupt */
> > + interrupt-names = "intr", "pme";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + num-lanes = <4>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&msi1>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
> > + <0000 0 0 2 &gic 0 111 0x4>,
> > + <0000 0 0 3 &gic 0 112 0x4>,
> > + <0000 0 0 4 &gic 0 113 0x4>;
> > + };
> > +
> > + pcie@3500000 {
> > + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> > + reg = <0x00 0x03500000 0x0 0x00100000 /* controller
> registers */
> > + 0x48 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 128 0x4>,
> > + <0 127 0x4>;
> > + interrupt-names = "intr", "pme";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + num-lanes = <2>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&msi2>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
> > + <0000 0 0 2 &gic 0 121 0x4>,
> > + <0000 0 0 3 &gic 0 122 0x4>,
> > + <0000 0 0 4 &gic 0 123 0x4>;
> > + };
> > +
> > + pcie@3600000 {
> > + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> > + reg = <0x00 0x03600000 0x0 0x00100000 /* controller
> registers */
> > + 0x50 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 162 0x4>,
> > + <0 161 0x4>;
> > + interrupt-names = "intr", "pme";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + num-lanes = <2>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&msi3>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
> > + <0000 0 0 2 &gic 0 155 0x4>,
> > + <0000 0 0 3 &gic 0 156 0x4>,
> > + <0000 0 0 4 &gic 0 157 0x4>;
> > + };
>
> You wait ages for a bus, then three show up at once...
>
> > +
> > + memory@80000000 {
> > + device_type = "memory";
> > + reg = <0x0 0x80000000 0 0x80000000>;
> > + /* DRAM space 1 - 2 GB DRAM */
>
> I don't understand the comment. This describes 2GB at 2GB.
>
Yes, there is a 2GB space for DRAM from address 2G.
The DRAM address 0x0 will be remapped to SoC address 2G, this remap is done by hardware.
> Does the bootloader overwrite this?
No.
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 9:50 ` Hou Zhiqiang
0 siblings, 0 replies; 75+ messages in thread
From: Hou Zhiqiang @ 2015-09-22 9:50 UTC (permalink / raw)
To: Mark Rutland, marc.zyngier-5wv7dgnIgG8@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Catalin Marinas, Will Deacon,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Shaohui Xie,
corbet-T1hC0tSOHrs@public.gmane.org, Sharma Bhupesh,
mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
wim-IQzOog9fTRqzQB+pC5nmwQ@public.gmane.org, Wenbin Song,
Scott Wood, Hu Vincent, Li Leo
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="gb2312", Size: 7954 bytes --]
Hi Mark,
> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland@arm.com]
> Sent: 2015Äê9ÔÂ22ÈÕ 9:24
> To: Hou Zhiqiang-B48286; marc.zyngier@arm.com
> Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will Deacon;
> linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284; Li Yang-Leo-R58472
> Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> Hi,
>
> > +/memreserve/ 0x80000000 0x00010000;
>
> Why is this necessary?
This memory region is pre-reserved for the spin-table/psci, although didn't add
Enable method of secondary cores.
> If this is necessary, please add a comment stating what this is for.
>
> > + cpu@3 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x0 0x3>;
> > + clocks = <&clockgen 1 0>;
> > + };
>
> Missing enable-method properties on all the secondary CPUs.
>
There are two methods (spin-table and psci) to bring up secondary cores, which one
do you think is better?
> [...]
>
> > + gic: interrupt-controller@1400000 {
> > + compatible = "arm,gic-400";
> > + #interrupt-cells = <3>;
> > + interrupt-controller;
> > + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
> > + <0x0 0x1402000 0 0x1000>, /* GICC */
> > + <0x0 0x1404000 0 0x2000>, /* GICH */
> > + <0x0 0x1406000 0 0x2000>; /* GICV */
> > + interrupts = <1 9 0xf08>;
> > + };
>
> These sizes don't look right.
>
> To the best of my knowledge, GICC (and GICV) should be 0x2000 in size,
> while GICD and GICH should be 0x1000.
Thanks for your correction.
>
> [...]
>
> > + ifc: ifc@1530000 {
> > + compatible = "fsl,ifc", "simple-bus";
> > + reg = <0x0 0x1530000 0x0 0x10000>;
> > + interrupts = <0 43 0x4>;
> > + };
>
> Why simple-bus?
There are 3 child node located in dtsi file that should be created and added
to platform device list.
>
> > + clockgen: clocking@1ee1000 {
> > + compatible = "fsl,ls1043a-clockgen";
> > + reg = <0x0 0x1ee1000 0x0 0x1000>;
> > + #clock-cells = <2>;
> > + clocks = <&sysclk>;
> > + sysclk: sysclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "sysclk";
> > + };
> > + };
>
> Why does this fixed clock live under the clockgen? It should live
> directly under the root node.
>
Thanks and will move it out in v2.
> [...]
>
> > + pcie@3400000 {
> > + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> > + reg = <0x00 0x03400000 0x0 0x00100000 /* controller
> registers */
> > + 0x40 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 118 0x4>, /* controller interrupt */
> > + <0 117 0x4>; /* PME interrupt */
> > + interrupt-names = "intr", "pme";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + num-lanes = <4>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&msi1>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
> > + <0000 0 0 2 &gic 0 111 0x4>,
> > + <0000 0 0 3 &gic 0 112 0x4>,
> > + <0000 0 0 4 &gic 0 113 0x4>;
> > + };
> > +
> > + pcie@3500000 {
> > + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> > + reg = <0x00 0x03500000 0x0 0x00100000 /* controller
> registers */
> > + 0x48 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 128 0x4>,
> > + <0 127 0x4>;
> > + interrupt-names = "intr", "pme";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + num-lanes = <2>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&msi2>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
> > + <0000 0 0 2 &gic 0 121 0x4>,
> > + <0000 0 0 3 &gic 0 122 0x4>,
> > + <0000 0 0 4 &gic 0 123 0x4>;
> > + };
> > +
> > + pcie@3600000 {
> > + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
> > + reg = <0x00 0x03600000 0x0 0x00100000 /* controller
> registers */
> > + 0x50 0x00000000 0x0 0x00002000>; /*
> configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <0 162 0x4>,
> > + <0 161 0x4>;
> > + interrupt-names = "intr", "pme";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + num-lanes = <2>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > + msi-parent = <&msi3>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
> > + <0000 0 0 2 &gic 0 155 0x4>,
> > + <0000 0 0 3 &gic 0 156 0x4>,
> > + <0000 0 0 4 &gic 0 157 0x4>;
> > + };
>
> You wait ages for a bus, then three show up at once...
>
> > +
> > + memory@80000000 {
> > + device_type = "memory";
> > + reg = <0x0 0x80000000 0 0x80000000>;
> > + /* DRAM space 1 - 2 GB DRAM */
>
> I don't understand the comment. This describes 2GB at 2GB.
>
Yes, there is a 2GB space for DRAM from address 2G.
The DRAM address 0x0 will be remapped to SoC address 2G, this remap is done by hardware.
> Does the bootloader overwrite this?
No.
Thanks,
Zhiqiang
N‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·¥Š{±Á«\…Ú Š{ayº\x1dʇڙë,j\a¢f£¢·hš‹»öì\x17/oSc¾™Ú³9˜uÀ¦æå‰È&jw¨®\x03(階ŠÝ¢j"ú\x1a¶^[m§ÿïêäz¹Þ–Šàþf£¢·hšˆ§~ˆmš
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 17:23 ` Li Leo
0 siblings, 0 replies; 75+ messages in thread
From: Li Leo @ 2015-09-22 17:23 UTC (permalink / raw)
To: Hou Zhiqiang, Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent
> >
> > Hi,
> >
> > > +/memreserve/ 0x80000000 0x00010000;
> >
> > Why is this necessary?
>=20
> This memory region is pre-reserved for the spin-table/psci, although didn=
't add
> Enable method of secondary cores.
Can this be reserved by bootloader?
>=20
> > If this is necessary, please add a comment stating what this is for.
> >
> > > + cpu@3 {
> > > + device_type =3D "cpu";
> > > + compatible =3D "arm,cortex-a53";
> > > + reg =3D <0x0 0x3>;
> > > + clocks =3D <&clockgen 1 0>;
> > > + };
> >
> > Missing enable-method properties on all the secondary CPUs.
> >
>=20
> There are two methods (spin-table and psci) to bring up secondary cores, =
which
> one do you think is better?
Do we have the PSCI support ready in both UEFI and u-boot? If not, we shou=
ld use spin-table for now.
Regards,
Leo
^ permalink raw reply [flat|nested] 75+ messages in thread* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 17:23 ` Li Leo
0 siblings, 0 replies; 75+ messages in thread
From: Li Leo @ 2015-09-22 17:23 UTC (permalink / raw)
To: linux-arm-kernel
> >
> > Hi,
> >
> > > +/memreserve/ 0x80000000 0x00010000;
> >
> > Why is this necessary?
>
> This memory region is pre-reserved for the spin-table/psci, although didn't add
> Enable method of secondary cores.
Can this be reserved by bootloader?
>
> > If this is necessary, please add a comment stating what this is for.
> >
> > > + cpu at 3 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a53";
> > > + reg = <0x0 0x3>;
> > > + clocks = <&clockgen 1 0>;
> > > + };
> >
> > Missing enable-method properties on all the secondary CPUs.
> >
>
> There are two methods (spin-table and psci) to bring up secondary cores, which
> one do you think is better?
Do we have the PSCI support ready in both UEFI and u-boot? If not, we should use spin-table for now.
Regards,
Leo
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 17:23 ` Li Leo
0 siblings, 0 replies; 75+ messages in thread
From: Li Leo @ 2015-09-22 17:23 UTC (permalink / raw)
To: Hou Zhiqiang, Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent
> >
> > Hi,
> >
> > > +/memreserve/ 0x80000000 0x00010000;
> >
> > Why is this necessary?
>
> This memory region is pre-reserved for the spin-table/psci, although didn't add
> Enable method of secondary cores.
Can this be reserved by bootloader?
>
> > If this is necessary, please add a comment stating what this is for.
> >
> > > + cpu@3 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a53";
> > > + reg = <0x0 0x3>;
> > > + clocks = <&clockgen 1 0>;
> > > + };
> >
> > Missing enable-method properties on all the secondary CPUs.
> >
>
> There are two methods (spin-table and psci) to bring up secondary cores, which
> one do you think is better?
Do we have the PSCI support ready in both UEFI and u-boot? If not, we should use spin-table for now.
Regards,
Leo
--
To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 17:23 ` Li Leo
0 siblings, 0 replies; 75+ messages in thread
From: Li Leo @ 2015-09-22 17:23 UTC (permalink / raw)
To: Hou Zhiqiang, Mark Rutland,
marc.zyngier-5wv7dgnIgG8@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Catalin Marinas, Will Deacon,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Shaohui Xie,
corbet-T1hC0tSOHrs@public.gmane.org, Sharma Bhupesh,
mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
wim-IQzOog9fTRqzQB+pC5nmwQ@public.gmane.org, Wenbin Song,
Scott Wood, Hu Vincent
> >
> > Hi,
> >
> > > +/memreserve/ 0x80000000 0x00010000;
> >
> > Why is this necessary?
>
> This memory region is pre-reserved for the spin-table/psci, although didn't add
> Enable method of secondary cores.
Can this be reserved by bootloader?
>
> > If this is necessary, please add a comment stating what this is for.
> >
> > > + cpu@3 {
> > > + device_type = "cpu";
> > > + compatible = "arm,cortex-a53";
> > > + reg = <0x0 0x3>;
> > > + clocks = <&clockgen 1 0>;
> > > + };
> >
> > Missing enable-method properties on all the secondary CPUs.
> >
>
> There are two methods (spin-table and psci) to bring up secondary cores, which
> one do you think is better?
Do we have the PSCI support ready in both UEFI and u-boot? If not, we should use spin-table for now.
Regards,
Leo
--
To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 17:23 ` Li Leo
(?)
@ 2015-09-22 19:04 ` Sharma Bhupesh
-1 siblings, 0 replies; 75+ messages in thread
From: Sharma Bhupesh @ 2015-09-22 19:04 UTC (permalink / raw)
To: Li Leo, Hou Zhiqiang, Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
mturquette@baylibre.com, wsa@the-dreams.de, sboyd@codeaurora.org,
wim@iguana.be, Wenbin Song, Scott Wood, Hu Vincent
> -----Original Message-----
> From: Li Yang-Leo-R58472
> Sent: Tuesday, September 22, 2015 10:53 PM
> To: Hou Zhiqiang-B48286; Mark Rutland; marc.zyngier@arm.com
> Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will Deacon;
> linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284
> Subject: RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>=20
> > >
> > > Hi,
> > >
> > > > +/memreserve/ 0x80000000 0x00010000;
> > >
> > > Why is this necessary?
> >
> > This memory region is pre-reserved for the spin-table/psci, although
> > didn't add Enable method of secondary cores.
>=20
> Can this be reserved by bootloader?
No need to reserve this for PSCI based secondary bootup.
> >
> > > If this is necessary, please add a comment stating what this is for.
> > >
> > > > + cpu@3 {
> > > > + device_type =3D "cpu";
> > > > + compatible =3D "arm,cortex-a53";
> > > > + reg =3D <0x0 0x3>;
> > > > + clocks =3D <&clockgen 1 0>;
> > > > + };
> > >
> > > Missing enable-method properties on all the secondary CPUs.
> > >
> >
> > There are two methods (spin-table and psci) to bring up secondary
> > cores, which one do you think is better?
>=20
> Do we have the PSCI support ready in both UEFI and u-boot? If not, we
> should use spin-table for now.
UEFI has been using PSCI with Arm Trusted Firmware (ATF) since some time. U=
-boot can also work with ATF seamlessly.
Spin-table method is deprecated and newer patches should support PSCI. If n=
ot, all intelligence should be left to the
Bootloader and the Linux DTS should not mention the 'enable-method' and the=
'memreserve' regions.=20
For details please see the LS2085A Freescale DTS already present in mainlin=
e kernel.
Regards,
Bhupesh
^ permalink raw reply [flat|nested] 75+ messages in thread* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 19:04 ` Sharma Bhupesh
0 siblings, 0 replies; 75+ messages in thread
From: Sharma Bhupesh @ 2015-09-22 19:04 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Li Yang-Leo-R58472
> Sent: Tuesday, September 22, 2015 10:53 PM
> To: Hou Zhiqiang-B48286; Mark Rutland; marc.zyngier at arm.com
> Cc: linux-arm-kernel at lists.infradead.org; Catalin Marinas; Will Deacon;
> linux-i2c at vger.kernel.org; linux-watchdog at vger.kernel.org; linux-
> doc at vger.kernel.org; linux-clk at vger.kernel.org; Xie Shaohui-B21989;
> corbet at lwn.net; Sharma Bhupesh-B45370; mturquette at baylibre.com; wsa at the-
> dreams.de; sboyd at codeaurora.org; wim at iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284
> Subject: RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> > >
> > > Hi,
> > >
> > > > +/memreserve/ 0x80000000 0x00010000;
> > >
> > > Why is this necessary?
> >
> > This memory region is pre-reserved for the spin-table/psci, although
> > didn't add Enable method of secondary cores.
>
> Can this be reserved by bootloader?
No need to reserve this for PSCI based secondary bootup.
> >
> > > If this is necessary, please add a comment stating what this is for.
> > >
> > > > + cpu at 3 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x0 0x3>;
> > > > + clocks = <&clockgen 1 0>;
> > > > + };
> > >
> > > Missing enable-method properties on all the secondary CPUs.
> > >
> >
> > There are two methods (spin-table and psci) to bring up secondary
> > cores, which one do you think is better?
>
> Do we have the PSCI support ready in both UEFI and u-boot? If not, we
> should use spin-table for now.
UEFI has been using PSCI with Arm Trusted Firmware (ATF) since some time. U-boot can also work with ATF seamlessly.
Spin-table method is deprecated and newer patches should support PSCI. If not, all intelligence should be left to the
Bootloader and the Linux DTS should not mention the 'enable-method' and the 'memreserve' regions.
For details please see the LS2085A Freescale DTS already present in mainline kernel.
Regards,
Bhupesh
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 19:04 ` Sharma Bhupesh
0 siblings, 0 replies; 75+ messages in thread
From: Sharma Bhupesh @ 2015-09-22 19:04 UTC (permalink / raw)
To: Li Leo, Hou Zhiqiang, Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
mturquette@baylibre.com, wsa@the-dreams.de, sboyd@codeaurora.org,
wim@iguana.be, Wenbin Song, Scott Wood, Hu Vincent
> -----Original Message-----
> From: Li Yang-Leo-R58472
> Sent: Tuesday, September 22, 2015 10:53 PM
> To: Hou Zhiqiang-B48286; Mark Rutland; marc.zyngier@arm.com
> Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will Deacon;
> linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284
> Subject: RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> > >
> > > Hi,
> > >
> > > > +/memreserve/ 0x80000000 0x00010000;
> > >
> > > Why is this necessary?
> >
> > This memory region is pre-reserved for the spin-table/psci, although
> > didn't add Enable method of secondary cores.
>
> Can this be reserved by bootloader?
No need to reserve this for PSCI based secondary bootup.
> >
> > > If this is necessary, please add a comment stating what this is for.
> > >
> > > > + cpu@3 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x0 0x3>;
> > > > + clocks = <&clockgen 1 0>;
> > > > + };
> > >
> > > Missing enable-method properties on all the secondary CPUs.
> > >
> >
> > There are two methods (spin-table and psci) to bring up secondary
> > cores, which one do you think is better?
>
> Do we have the PSCI support ready in both UEFI and u-boot? If not, we
> should use spin-table for now.
UEFI has been using PSCI with Arm Trusted Firmware (ATF) since some time. U-boot can also work with ATF seamlessly.
Spin-table method is deprecated and newer patches should support PSCI. If not, all intelligence should be left to the
Bootloader and the Linux DTS should not mention the 'enable-method' and the 'memreserve' regions.
For details please see the LS2085A Freescale DTS already present in mainline kernel.
Regards,
Bhupesh
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-23 3:05 ` Hou Zhiqiang
0 siblings, 0 replies; 75+ messages in thread
From: Hou Zhiqiang @ 2015-09-23 3:05 UTC (permalink / raw)
To: Li Leo, Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent
DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogTGkgWWFuZy1MZW8tUjU4
NDcyDQo+IFNlbnQ6IDIwMTXE6jnUwjIzyNUgMToyMw0KPiBUbzogSG91IFpoaXFpYW5nLUI0ODI4
NjsgTWFyayBSdXRsYW5kOyBtYXJjLnp5bmdpZXJAYXJtLmNvbQ0KPiBDYzogbGludXgtYXJtLWtl
cm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnOyBDYXRhbGluIE1hcmluYXM7IFdpbGwgRGVhY29uOw0K
PiBsaW51eC1pMmNAdmdlci5rZXJuZWwub3JnOyBsaW51eC13YXRjaGRvZ0B2Z2VyLmtlcm5lbC5v
cmc7IGxpbnV4LQ0KPiBkb2NAdmdlci5rZXJuZWwub3JnOyBsaW51eC1jbGtAdmdlci5rZXJuZWwu
b3JnOyBYaWUgU2hhb2h1aS1CMjE5ODk7DQo+IGNvcmJldEBsd24ubmV0OyBTaGFybWEgQmh1cGVz
aC1CNDUzNzA7IG10dXJxdWV0dGVAYmF5bGlicmUuY29tOyB3c2FAdGhlLQ0KPiBkcmVhbXMuZGU7
IHNib3lkQGNvZGVhdXJvcmEub3JnOyB3aW1AaWd1YW5hLmJlOyBTb25nIFdlbmJpbi1CNTM3NDc7
IFdvb2QNCj4gU2NvdHQtQjA3NDIxOyBIdSBNaW5na2FpLUIyMTI4NA0KPiBTdWJqZWN0OiBSRTog
W1BBVENIIDQvNl0gYXJtNjQvbHMxMDQzYTogYWRkIERUUyBmb3IgRnJlZXNjYWxlIExTMTA0M0Eg
U29DDQo+IA0KPiA+ID4NCj4gPiA+IEhpLA0KPiA+ID4NCj4gPiA+ID4gKy9tZW1yZXNlcnZlLyAw
eDgwMDAwMDAwIDB4MDAwMTAwMDA7DQo+ID4gPg0KPiA+ID4gV2h5IGlzIHRoaXMgbmVjZXNzYXJ5
Pw0KPiA+DQo+ID4gVGhpcyBtZW1vcnkgcmVnaW9uIGlzIHByZS1yZXNlcnZlZCBmb3IgdGhlIHNw
aW4tdGFibGUvcHNjaSwgYWx0aG91Z2gNCj4gPiBkaWRuJ3QgYWRkIEVuYWJsZSBtZXRob2Qgb2Yg
c2Vjb25kYXJ5IGNvcmVzLg0KPiANCj4gQ2FuIHRoaXMgYmUgcmVzZXJ2ZWQgYnkgYm9vdGxvYWRl
cj8NCg0KWWVzLCB0aGUgbWVtb3J5IGZvciBwc2NpIHdhcyByZXNlcnZlZCBieSB1LWJvb3QgY29k
ZS4gQnV0IGR1ZSB0byBzcGluLXRhYmxlDQpuZWVkIHRoZSByZWxlYXNlIGFkZHJlc3MsIGlzIGl0
IGJldHRlciBhZGRpbmcgdGhlIC9tZW1yZXNlcnZlLyBpbiBkdHMgZmlsZT8NCk9yIGFkZCBpdCBi
eSBib290bG9hZGVyIGFuZCBmaXggdGhlIHJlbGVhc2UgYWRkcmVzcyBhY2NvcmRpbmdseT8NCg0K
PiANCj4gPg0KPiA+ID4gSWYgdGhpcyBpcyBuZWNlc3NhcnksIHBsZWFzZSBhZGQgYSBjb21tZW50
IHN0YXRpbmcgd2hhdCB0aGlzIGlzIGZvci4NCj4gPiA+DQo+ID4gPiA+ICsgICAgICAgICAgICAg
ICBjcHVAMyB7DQo+ID4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIGRldmljZV90eXBlID0g
ImNwdSI7DQo+ID4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIGNvbXBhdGlibGUgPSAiYXJt
LGNvcnRleC1hNTMiOw0KPiA+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICByZWcgPSA8MHgw
IDB4Mz47DQo+ID4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIGNsb2NrcyA9IDwmY2xvY2tn
ZW4gMSAwPjsNCj4gPiA+ID4gKyAgICAgICAgICAgICAgIH07DQo+ID4gPg0KPiA+ID4gTWlzc2lu
ZyBlbmFibGUtbWV0aG9kIHByb3BlcnRpZXMgb24gYWxsIHRoZSBzZWNvbmRhcnkgQ1BVcy4NCj4g
PiA+DQo+ID4NCj4gPiBUaGVyZSBhcmUgdHdvIG1ldGhvZHMgKHNwaW4tdGFibGUgYW5kIHBzY2kp
IHRvIGJyaW5nIHVwIHNlY29uZGFyeQ0KPiA+IGNvcmVzLCB3aGljaCBvbmUgZG8geW91IHRoaW5r
IGlzIGJldHRlcj8NCj4gDQo+IERvIHdlIGhhdmUgdGhlIFBTQ0kgc3VwcG9ydCByZWFkeSBpbiBi
b3RoIFVFRkkgYW5kIHUtYm9vdD8gIElmIG5vdCwgd2UNCj4gc2hvdWxkIHVzZSBzcGluLXRhYmxl
IGZvciBub3cuDQo+DQoNCm91ciBpbnRlcm5hbCB1LWJvb3Qgc3VwcG9ydHMgUFNDSSBidXQgb3Bl
bnNvdXJjZSBkb2Vzbid0IHN1cHBvcnQgaXQgZm9yIEFSTXY4Lg0KDQpUaGFua3MsDQpaaGlxaWFu
Zw0K
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-23 3:05 ` Hou Zhiqiang
0 siblings, 0 replies; 75+ messages in thread
From: Hou Zhiqiang @ 2015-09-23 3:05 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Li Yang-Leo-R58472
> Sent: 2015?9?23? 1:23
> To: Hou Zhiqiang-B48286; Mark Rutland; marc.zyngier at arm.com
> Cc: linux-arm-kernel at lists.infradead.org; Catalin Marinas; Will Deacon;
> linux-i2c at vger.kernel.org; linux-watchdog at vger.kernel.org; linux-
> doc at vger.kernel.org; linux-clk at vger.kernel.org; Xie Shaohui-B21989;
> corbet at lwn.net; Sharma Bhupesh-B45370; mturquette at baylibre.com; wsa at the-
> dreams.de; sboyd at codeaurora.org; wim at iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284
> Subject: RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> > >
> > > Hi,
> > >
> > > > +/memreserve/ 0x80000000 0x00010000;
> > >
> > > Why is this necessary?
> >
> > This memory region is pre-reserved for the spin-table/psci, although
> > didn't add Enable method of secondary cores.
>
> Can this be reserved by bootloader?
Yes, the memory for psci was reserved by u-boot code. But due to spin-table
need the release address, is it better adding the /memreserve/ in dts file?
Or add it by bootloader and fix the release address accordingly?
>
> >
> > > If this is necessary, please add a comment stating what this is for.
> > >
> > > > + cpu at 3 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x0 0x3>;
> > > > + clocks = <&clockgen 1 0>;
> > > > + };
> > >
> > > Missing enable-method properties on all the secondary CPUs.
> > >
> >
> > There are two methods (spin-table and psci) to bring up secondary
> > cores, which one do you think is better?
>
> Do we have the PSCI support ready in both UEFI and u-boot? If not, we
> should use spin-table for now.
>
our internal u-boot supports PSCI but opensource doesn't support it for ARMv8.
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-23 3:05 ` Hou Zhiqiang
0 siblings, 0 replies; 75+ messages in thread
From: Hou Zhiqiang @ 2015-09-23 3:05 UTC (permalink / raw)
To: Li Leo, Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent
> -----Original Message-----
> From: Li Yang-Leo-R58472
> Sent: 2015年9月23日 1:23
> To: Hou Zhiqiang-B48286; Mark Rutland; marc.zyngier@arm.com
> Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will Deacon;
> linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284
> Subject: RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> > >
> > > Hi,
> > >
> > > > +/memreserve/ 0x80000000 0x00010000;
> > >
> > > Why is this necessary?
> >
> > This memory region is pre-reserved for the spin-table/psci, although
> > didn't add Enable method of secondary cores.
>
> Can this be reserved by bootloader?
Yes, the memory for psci was reserved by u-boot code. But due to spin-table
need the release address, is it better adding the /memreserve/ in dts file?
Or add it by bootloader and fix the release address accordingly?
>
> >
> > > If this is necessary, please add a comment stating what this is for.
> > >
> > > > + cpu@3 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x0 0x3>;
> > > > + clocks = <&clockgen 1 0>;
> > > > + };
> > >
> > > Missing enable-method properties on all the secondary CPUs.
> > >
> >
> > There are two methods (spin-table and psci) to bring up secondary
> > cores, which one do you think is better?
>
> Do we have the PSCI support ready in both UEFI and u-boot? If not, we
> should use spin-table for now.
>
our internal u-boot supports PSCI but opensource doesn't support it for ARMv8.
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-23 3:05 ` Hou Zhiqiang
0 siblings, 0 replies; 75+ messages in thread
From: Hou Zhiqiang @ 2015-09-23 3:05 UTC (permalink / raw)
To: Li Leo, Mark Rutland, marc.zyngier-5wv7dgnIgG8@public.gmane.org
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Catalin Marinas, Will Deacon,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Shaohui Xie,
corbet-T1hC0tSOHrs@public.gmane.org, Sharma Bhupesh,
mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
wim-IQzOog9fTRqzQB+pC5nmwQ@public.gmane.org, Wenbin Song,
Scott Wood, Hu Vincent
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="gb2312", Size: 2077 bytes --]
> -----Original Message-----
> From: Li Yang-Leo-R58472
> Sent: 2015Äê9ÔÂ23ÈÕ 1:23
> To: Hou Zhiqiang-B48286; Mark Rutland; marc.zyngier@arm.com
> Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will Deacon;
> linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284
> Subject: RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> > >
> > > Hi,
> > >
> > > > +/memreserve/ 0x80000000 0x00010000;
> > >
> > > Why is this necessary?
> >
> > This memory region is pre-reserved for the spin-table/psci, although
> > didn't add Enable method of secondary cores.
>
> Can this be reserved by bootloader?
Yes, the memory for psci was reserved by u-boot code. But due to spin-table
need the release address, is it better adding the /memreserve/ in dts file?
Or add it by bootloader and fix the release address accordingly?
>
> >
> > > If this is necessary, please add a comment stating what this is for.
> > >
> > > > + cpu@3 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x0 0x3>;
> > > > + clocks = <&clockgen 1 0>;
> > > > + };
> > >
> > > Missing enable-method properties on all the secondary CPUs.
> > >
> >
> > There are two methods (spin-table and psci) to bring up secondary
> > cores, which one do you think is better?
>
> Do we have the PSCI support ready in both UEFI and u-boot? If not, we
> should use spin-table for now.
>
our internal u-boot supports PSCI but opensource doesn't support it for ARMv8.
Thanks,
Zhiqiang
N‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·¥Š{±Á«\…Ú Š{ayº\x1dʇڙë,j\a¢f£¢·hš‹»öì\x17/oSc¾™Ú³9˜uÀ¦æå‰È&jw¨®\x03(階ŠÝ¢j"ú\x1a¶^[m§ÿïêäz¹Þ–Šàþf£¢·hšˆ§~ˆmš
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-23 3:05 ` Hou Zhiqiang
(?)
@ 2015-09-23 4:16 ` Li Leo
-1 siblings, 0 replies; 75+ messages in thread
From: Li Leo @ 2015-09-23 4:16 UTC (permalink / raw)
To: Hou Zhiqiang, Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent
> > > >
> > > > Hi,
> > > >
> > > > > +/memreserve/ 0x80000000 0x00010000;
> > > >
> > > > Why is this necessary?
> > >
> > > This memory region is pre-reserved for the spin-table/psci, although
> > > didn't add Enable method of secondary cores.
> >
> > Can this be reserved by bootloader?
>=20
> Yes, the memory for psci was reserved by u-boot code. But due to spin-tab=
le
> need the release address, is it better adding the /memreserve/ in dts fil=
e?
> Or add it by bootloader and fix the release address accordingly?
Both the reserved memory region and cpu-release-addr should be updated by b=
ootloader.
Regards,
Leo
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-23 4:16 ` Li Leo
0 siblings, 0 replies; 75+ messages in thread
From: Li Leo @ 2015-09-23 4:16 UTC (permalink / raw)
To: linux-arm-kernel
> > > >
> > > > Hi,
> > > >
> > > > > +/memreserve/ 0x80000000 0x00010000;
> > > >
> > > > Why is this necessary?
> > >
> > > This memory region is pre-reserved for the spin-table/psci, although
> > > didn't add Enable method of secondary cores.
> >
> > Can this be reserved by bootloader?
>
> Yes, the memory for psci was reserved by u-boot code. But due to spin-table
> need the release address, is it better adding the /memreserve/ in dts file?
> Or add it by bootloader and fix the release address accordingly?
Both the reserved memory region and cpu-release-addr should be updated by bootloader.
Regards,
Leo
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-23 4:16 ` Li Leo
0 siblings, 0 replies; 75+ messages in thread
From: Li Leo @ 2015-09-23 4:16 UTC (permalink / raw)
To: Hou Zhiqiang, Mark Rutland, marc.zyngier@arm.com
Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas,
Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent
> > > >
> > > > Hi,
> > > >
> > > > > +/memreserve/ 0x80000000 0x00010000;
> > > >
> > > > Why is this necessary?
> > >
> > > This memory region is pre-reserved for the spin-table/psci, although
> > > didn't add Enable method of secondary cores.
> >
> > Can this be reserved by bootloader?
>
> Yes, the memory for psci was reserved by u-boot code. But due to spin-table
> need the release address, is it better adding the /memreserve/ in dts file?
> Or add it by bootloader and fix the release address accordingly?
Both the reserved memory region and cpu-release-addr should be updated by bootloader.
Regards,
Leo
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 22:15 ` Mark Rutland
0 siblings, 0 replies; 75+ messages in thread
From: Mark Rutland @ 2015-09-22 22:15 UTC (permalink / raw)
To: Hou Zhiqiang
Cc: Marc Zyngier, linux-arm-kernel@lists.infradead.org,
Catalin Marinas, Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent, Li Leo
On Tue, Sep 22, 2015 at 10:50:21AM +0100, Hou Zhiqiang wrote:
> Hi Mark,
>
> > -----Original Message-----
> > From: Mark Rutland [mailto:mark.rutland@arm.com]
> > Sent: 2015年9月22日 9:24
> > To: Hou Zhiqiang-B48286; marc.zyngier@arm.com
> > Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will Deacon;
> > linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> > doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> > corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> > dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> > Scott-B07421; Hu Mingkai-B21284; Li Yang-Leo-R58472
> > Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
> >
> > Hi,
> >
> > > +/memreserve/ 0x80000000 0x00010000;
> >
> > Why is this necessary?
>
> This memory region is pre-reserved for the spin-table/psci, although didn't add
> Enable method of secondary cores.
Your PSCI implementation isn't in secure memory?
> > > + ifc: ifc@1530000 {
> > > + compatible = "fsl,ifc", "simple-bus";
> > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > + interrupts = <0 43 0x4>;
> > > + };
> >
> > Why simple-bus?
>
> There are 3 child node located in dtsi file that should be created and added
> to platform device list.
Are they usable even if the kernel knew nothing about the IFC node? If not, the
IFC driver should probe them, and simple-bus should go.
> > > + memory@80000000 {
> > > + device_type = "memory";
> > > + reg = <0x0 0x80000000 0 0x80000000>;
> > > + /* DRAM space 1 - 2 GB DRAM */
> >
> > I don't understand the comment. This describes 2GB at 2GB.
> >
>
> Yes, there is a 2GB space for DRAM from address 2G.
> The DRAM address 0x0 will be remapped to SoC address 2G, this remap is done by hardware.
I just realised my mistake -- I read this as "1 to 2 GB", when this is actually
"DRAM space 1". Sorry for the noise.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 75+ messages in thread* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 22:15 ` Mark Rutland
0 siblings, 0 replies; 75+ messages in thread
From: Mark Rutland @ 2015-09-22 22:15 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Sep 22, 2015 at 10:50:21AM +0100, Hou Zhiqiang wrote:
> Hi Mark,
>
> > -----Original Message-----
> > From: Mark Rutland [mailto:mark.rutland at arm.com]
> > Sent: 2015?9?22? 9:24
> > To: Hou Zhiqiang-B48286; marc.zyngier at arm.com
> > Cc: linux-arm-kernel at lists.infradead.org; Catalin Marinas; Will Deacon;
> > linux-i2c at vger.kernel.org; linux-watchdog at vger.kernel.org; linux-
> > doc at vger.kernel.org; linux-clk at vger.kernel.org; Xie Shaohui-B21989;
> > corbet at lwn.net; Sharma Bhupesh-B45370; mturquette at baylibre.com; wsa at the-
> > dreams.de; sboyd at codeaurora.org; wim at iguana.be; Song Wenbin-B53747; Wood
> > Scott-B07421; Hu Mingkai-B21284; Li Yang-Leo-R58472
> > Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
> >
> > Hi,
> >
> > > +/memreserve/ 0x80000000 0x00010000;
> >
> > Why is this necessary?
>
> This memory region is pre-reserved for the spin-table/psci, although didn't add
> Enable method of secondary cores.
Your PSCI implementation isn't in secure memory?
> > > + ifc: ifc at 1530000 {
> > > + compatible = "fsl,ifc", "simple-bus";
> > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > + interrupts = <0 43 0x4>;
> > > + };
> >
> > Why simple-bus?
>
> There are 3 child node located in dtsi file that should be created and added
> to platform device list.
Are they usable even if the kernel knew nothing about the IFC node? If not, the
IFC driver should probe them, and simple-bus should go.
> > > + memory at 80000000 {
> > > + device_type = "memory";
> > > + reg = <0x0 0x80000000 0 0x80000000>;
> > > + /* DRAM space 1 - 2 GB DRAM */
> >
> > I don't understand the comment. This describes 2GB at 2GB.
> >
>
> Yes, there is a 2GB space for DRAM from address 2G.
> The DRAM address 0x0 will be remapped to SoC address 2G, this remap is done by hardware.
I just realised my mistake -- I read this as "1 to 2 GB", when this is actually
"DRAM space 1". Sorry for the noise.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 22:15 ` Mark Rutland
0 siblings, 0 replies; 75+ messages in thread
From: Mark Rutland @ 2015-09-22 22:15 UTC (permalink / raw)
To: Hou Zhiqiang
Cc: Marc Zyngier,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Catalin Marinas, Will Deacon,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Shaohui Xie,
corbet-T1hC0tSOHrs@public.gmane.org, Sharma Bhupesh,
mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
wim-IQzOog9fTRqzQB+pC5nmwQ@public.gmane.org, Wenbin Song,
Scott Wood, Hu Vincent, Li Leo
On Tue, Sep 22, 2015 at 10:50:21AM +0100, Hou Zhiqiang wrote:
> Hi Mark,
>
> > -----Original Message-----
> > From: Mark Rutland [mailto:mark.rutland-5wv7dgnIgG8@public.gmane.org]
> > Sent: 2015年9月22日 9:24
> > To: Hou Zhiqiang-B48286; marc.zyngier-5wv7dgnIgG8@public.gmane.org
> > Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; Catalin Marinas; Will Deacon;
> > linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-
> > doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Xie Shaohui-B21989;
> > corbet-T1hC0tSOHrs@public.gmane.org; Sharma Bhupesh-B45370; mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org; wsa@the-
> > dreams.de; sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org; wim-IQzOog9fTRqzQB+pC5nmwQ@public.gmane.org; Song Wenbin-B53747; Wood
> > Scott-B07421; Hu Mingkai-B21284; Li Yang-Leo-R58472
> > Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
> >
> > Hi,
> >
> > > +/memreserve/ 0x80000000 0x00010000;
> >
> > Why is this necessary?
>
> This memory region is pre-reserved for the spin-table/psci, although didn't add
> Enable method of secondary cores.
Your PSCI implementation isn't in secure memory?
> > > + ifc: ifc@1530000 {
> > > + compatible = "fsl,ifc", "simple-bus";
> > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > + interrupts = <0 43 0x4>;
> > > + };
> >
> > Why simple-bus?
>
> There are 3 child node located in dtsi file that should be created and added
> to platform device list.
Are they usable even if the kernel knew nothing about the IFC node? If not, the
IFC driver should probe them, and simple-bus should go.
> > > + memory@80000000 {
> > > + device_type = "memory";
> > > + reg = <0x0 0x80000000 0 0x80000000>;
> > > + /* DRAM space 1 - 2 GB DRAM */
> >
> > I don't understand the comment. This describes 2GB at 2GB.
> >
>
> Yes, there is a 2GB space for DRAM from address 2G.
> The DRAM address 0x0 will be remapped to SoC address 2G, this remap is done by hardware.
I just realised my mistake -- I read this as "1 to 2 GB", when this is actually
"DRAM space 1". Sorry for the noise.
Thanks,
Mark.
--
To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 22:15 ` Mark Rutland
(?)
(?)
@ 2015-09-22 22:39 ` Li Leo
-1 siblings, 0 replies; 75+ messages in thread
From: Li Leo @ 2015-09-22 22:39 UTC (permalink / raw)
To: Mark Rutland, Hou Zhiqiang, Kushwaha Prabhakar
Cc: Marc Zyngier, linux-arm-kernel@lists.infradead.org,
Catalin Marinas, Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent
DQo+ID4gPiA+ICsgICAgICAgaWZjOiBpZmNAMTUzMDAwMCB7DQo+ID4gPiA+ICsgICAgICAgICAg
ICAgICBjb21wYXRpYmxlID0gImZzbCxpZmMiLCAic2ltcGxlLWJ1cyI7DQo+ID4gPiA+ICsgICAg
ICAgICAgICAgICByZWcgPSA8MHgwIDB4MTUzMDAwMCAweDAgMHgxMDAwMD47DQo+ID4gPiA+ICsg
ICAgICAgICAgICAgICBpbnRlcnJ1cHRzID0gPDAgNDMgMHg0PjsNCj4gPiA+ID4gKyAgICAgICB9
Ow0KPiA+ID4NCj4gPiA+IFdoeSBzaW1wbGUtYnVzPw0KPiA+DQo+ID4gVGhlcmUgYXJlIDMgY2hp
bGQgbm9kZSBsb2NhdGVkIGluIGR0c2kgZmlsZSB0aGF0IHNob3VsZCBiZSBjcmVhdGVkIGFuZA0K
PiA+IGFkZGVkIHRvIHBsYXRmb3JtIGRldmljZSBsaXN0Lg0KPiANCj4gQXJlIHRoZXkgdXNhYmxl
IGV2ZW4gaWYgdGhlIGtlcm5lbCBrbmV3IG5vdGhpbmcgYWJvdXQgdGhlIElGQyBub2RlPyBJZiBu
b3QsIHRoZQ0KPiBJRkMgZHJpdmVyIHNob3VsZCBwcm9iZSB0aGVtLCBhbmQgc2ltcGxlLWJ1cyBz
aG91bGQgZ28uDQoNCkFkZGluZyB0aGUgSUZDIGRyaXZlciBvd25lciB0byB0aGUgbG9vcC4NCg0K
UmVnYXJkcywNCkxlbw0K
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 22:39 ` Li Leo
0 siblings, 0 replies; 75+ messages in thread
From: Li Leo @ 2015-09-22 22:39 UTC (permalink / raw)
To: linux-arm-kernel
> > > > + ifc: ifc at 1530000 {
> > > > + compatible = "fsl,ifc", "simple-bus";
> > > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > > + interrupts = <0 43 0x4>;
> > > > + };
> > >
> > > Why simple-bus?
> >
> > There are 3 child node located in dtsi file that should be created and
> > added to platform device list.
>
> Are they usable even if the kernel knew nothing about the IFC node? If not, the
> IFC driver should probe them, and simple-bus should go.
Adding the IFC driver owner to the loop.
Regards,
Leo
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 22:39 ` Li Leo
0 siblings, 0 replies; 75+ messages in thread
From: Li Leo @ 2015-09-22 22:39 UTC (permalink / raw)
To: Mark Rutland, Hou Zhiqiang, Kushwaha Prabhakar
Cc: Marc Zyngier, linux-arm-kernel@lists.infradead.org,
Catalin Marinas, Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent
> > > > + ifc: ifc@1530000 {
> > > > + compatible = "fsl,ifc", "simple-bus";
> > > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > > + interrupts = <0 43 0x4>;
> > > > + };
> > >
> > > Why simple-bus?
> >
> > There are 3 child node located in dtsi file that should be created and
> > added to platform device list.
>
> Are they usable even if the kernel knew nothing about the IFC node? If not, the
> IFC driver should probe them, and simple-bus should go.
Adding the IFC driver owner to the loop.
Regards,
Leo
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 22:39 ` Li Leo
0 siblings, 0 replies; 75+ messages in thread
From: Li Leo @ 2015-09-22 22:39 UTC (permalink / raw)
To: Mark Rutland, Hou Zhiqiang, Kushwaha Prabhakar
Cc: Marc Zyngier,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Catalin Marinas, Will Deacon,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Shaohui Xie,
corbet-T1hC0tSOHrs@public.gmane.org, Sharma Bhupesh,
mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
wim-IQzOog9fTRqzQB+pC5nmwQ@public.gmane.org, Wenbin Song,
Scott Wood, Hu Vincent
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 721 bytes --]
> > > > + ifc: ifc@1530000 {
> > > > + compatible = "fsl,ifc", "simple-bus";
> > > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > > + interrupts = <0 43 0x4>;
> > > > + };
> > >
> > > Why simple-bus?
> >
> > There are 3 child node located in dtsi file that should be created and
> > added to platform device list.
>
> Are they usable even if the kernel knew nothing about the IFC node? If not, the
> IFC driver should probe them, and simple-bus should go.
Adding the IFC driver owner to the loop.
Regards,
Leo
N‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·¥Š{±Á«\…Ú Š{ayº\x1dʇڙë,j\a¢f£¢·hš‹»öì\x17/oSc¾™Ú³9˜uÀ¦æå‰È&jw¨®\x03(階ŠÝ¢j"ú\x1a¶^[m§ÿïêäz¹Þ–Šàþf£¢·hšˆ§~ˆmš
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 22:15 ` Mark Rutland
(?)
@ 2015-09-22 22:43 ` Scott Wood
-1 siblings, 0 replies; 75+ messages in thread
From: Scott Wood @ 2015-09-22 22:43 UTC (permalink / raw)
To: Mark Rutland
Cc: Hou Zhiqiang, Marc Zyngier, linux-arm-kernel@lists.infradead.org,
Catalin Marinas, Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Hu Vincent,
Li Leo, Kushwaha Prabhakar-B32579
On Tue, 2015-09-22 at 23:15 +0100, Mark Rutland wrote:
> On Tue, Sep 22, 2015 at 10:50:21AM +0100, Hou Zhiqiang wrote:
> > > > + ifc: ifc@1530000{
> > > > + compatible = "fsl,ifc", "simple-bus";
> > > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > > + interrupts = <0 43 0x4>;
> > > > + };
> > >
> > > Why simple-bus?
> >
> > There are 3 child node located in dtsi file that should be created and
> > added
> > to platform device list.
>
> Are they usable even if the kernel knew nothing about the IFC node?
Yes, except for NAND.
> If not, the IFC driver should probe them, and simple-bus should go.
IFC is not a new binding. IFC nodes are expected to have simple-bus.
-Scott
^ permalink raw reply [flat|nested] 75+ messages in thread* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 22:43 ` Scott Wood
0 siblings, 0 replies; 75+ messages in thread
From: Scott Wood @ 2015-09-22 22:43 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 2015-09-22 at 23:15 +0100, Mark Rutland wrote:
> On Tue, Sep 22, 2015 at 10:50:21AM +0100, Hou Zhiqiang wrote:
> > > > + ifc: ifc at 1530000{
> > > > + compatible = "fsl,ifc", "simple-bus";
> > > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > > + interrupts = <0 43 0x4>;
> > > > + };
> > >
> > > Why simple-bus?
> >
> > There are 3 child node located in dtsi file that should be created and
> > added
> > to platform device list.
>
> Are they usable even if the kernel knew nothing about the IFC node?
Yes, except for NAND.
> If not, the IFC driver should probe them, and simple-bus should go.
IFC is not a new binding. IFC nodes are expected to have simple-bus.
-Scott
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-22 22:43 ` Scott Wood
0 siblings, 0 replies; 75+ messages in thread
From: Scott Wood @ 2015-09-22 22:43 UTC (permalink / raw)
To: Mark Rutland
Cc: Hou Zhiqiang, Marc Zyngier,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Catalin Marinas, Will Deacon,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-watchdog-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Shaohui Xie,
corbet-T1hC0tSOHrs@public.gmane.org, Sharma Bhupesh,
mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
wim-IQzOog9fTRqzQB+pC5nmwQ@public.gmane.org, Wenbin Song,
Hu Vincent, Li Leo
On Tue, 2015-09-22 at 23:15 +0100, Mark Rutland wrote:
> On Tue, Sep 22, 2015 at 10:50:21AM +0100, Hou Zhiqiang wrote:
> > > > + ifc: ifc@1530000{
> > > > + compatible = "fsl,ifc", "simple-bus";
> > > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > > + interrupts = <0 43 0x4>;
> > > > + };
> > >
> > > Why simple-bus?
> >
> > There are 3 child node located in dtsi file that should be created and
> > added
> > to platform device list.
>
> Are they usable even if the kernel knew nothing about the IFC node?
Yes, except for NAND.
> If not, the IFC driver should probe them, and simple-bus should go.
IFC is not a new binding. IFC nodes are expected to have simple-bus.
-Scott
--
To unsubscribe from this list: send the line "unsubscribe linux-watchdog" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
2015-09-22 22:15 ` Mark Rutland
(?)
@ 2015-09-23 3:57 ` Hou Zhiqiang
-1 siblings, 0 replies; 75+ messages in thread
From: Hou Zhiqiang @ 2015-09-23 3:57 UTC (permalink / raw)
To: Mark Rutland
Cc: Marc Zyngier, linux-arm-kernel@lists.infradead.org,
Catalin Marinas, Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent, Li Leo
DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogTWFyayBSdXRsYW5kIFtt
YWlsdG86bWFyay5ydXRsYW5kQGFybS5jb21dDQo+IFNlbnQ6IDIwMTXlubQ55pyIMjPml6UgNjox
NQ0KPiBUbzogSG91IFpoaXFpYW5nLUI0ODI4Ng0KPiBDYzogTWFyYyBaeW5naWVyOyBsaW51eC1h
cm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmc7IENhdGFsaW4gTWFyaW5hczsNCj4gV2lsbCBE
ZWFjb247IGxpbnV4LWkyY0B2Z2VyLmtlcm5lbC5vcmc7IGxpbnV4LXdhdGNoZG9nQHZnZXIua2Vy
bmVsLm9yZzsNCj4gbGludXgtZG9jQHZnZXIua2VybmVsLm9yZzsgbGludXgtY2xrQHZnZXIua2Vy
bmVsLm9yZzsgWGllIFNoYW9odWktQjIxOTg5Ow0KPiBjb3JiZXRAbHduLm5ldDsgU2hhcm1hIEJo
dXBlc2gtQjQ1MzcwOyBtdHVycXVldHRlQGJheWxpYnJlLmNvbTsgd3NhQHRoZS0NCj4gZHJlYW1z
LmRlOyBzYm95ZEBjb2RlYXVyb3JhLm9yZzsgd2ltQGlndWFuYS5iZTsgU29uZyBXZW5iaW4tQjUz
NzQ3OyBXb29kDQo+IFNjb3R0LUIwNzQyMTsgSHUgTWluZ2thaS1CMjEyODQ7IExpIFlhbmctTGVv
LVI1ODQ3Mg0KPiBTdWJqZWN0OiBSZTogW1BBVENIIDQvNl0gYXJtNjQvbHMxMDQzYTogYWRkIERU
UyBmb3IgRnJlZXNjYWxlIExTMTA0M0EgU29DDQo+IA0KPiBPbiBUdWUsIFNlcCAyMiwgMjAxNSBh
dCAxMDo1MDoyMUFNICswMTAwLCBIb3UgWmhpcWlhbmcgd3JvdGU6DQo+ID4gSGkgTWFyaywNCj4g
Pg0KPiA+ID4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gPiA+IEZyb206IE1hcmsgUnV0
bGFuZCBbbWFpbHRvOm1hcmsucnV0bGFuZEBhcm0uY29tXQ0KPiA+ID4gU2VudDogMjAxNeW5tDnm
nIgyMuaXpSA5OjI0DQo+ID4gPiBUbzogSG91IFpoaXFpYW5nLUI0ODI4NjsgbWFyYy56eW5naWVy
QGFybS5jb20NCj4gPiA+IENjOiBsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmc7
IENhdGFsaW4gTWFyaW5hczsgV2lsbA0KPiA+ID4gRGVhY29uOyBsaW51eC1pMmNAdmdlci5rZXJu
ZWwub3JnOyBsaW51eC13YXRjaGRvZ0B2Z2VyLmtlcm5lbC5vcmc7DQo+ID4gPiBsaW51eC0gZG9j
QHZnZXIua2VybmVsLm9yZzsgbGludXgtY2xrQHZnZXIua2VybmVsLm9yZzsgWGllDQo+ID4gPiBT
aGFvaHVpLUIyMTk4OTsgY29yYmV0QGx3bi5uZXQ7IFNoYXJtYSBCaHVwZXNoLUI0NTM3MDsNCj4g
PiA+IG10dXJxdWV0dGVAYmF5bGlicmUuY29tOyB3c2FAdGhlLSBkcmVhbXMuZGU7IHNib3lkQGNv
ZGVhdXJvcmEub3JnOw0KPiA+ID4gd2ltQGlndWFuYS5iZTsgU29uZyBXZW5iaW4tQjUzNzQ3OyBX
b29kIFNjb3R0LUIwNzQyMTsgSHUNCj4gPiA+IE1pbmdrYWktQjIxMjg0OyBMaSBZYW5nLUxlby1S
NTg0NzINCj4gPiA+IFN1YmplY3Q6IFJlOiBbUEFUQ0ggNC82XSBhcm02NC9sczEwNDNhOiBhZGQg
RFRTIGZvciBGcmVlc2NhbGUNCj4gPiA+IExTMTA0M0EgU29DDQo+ID4gPg0KPiA+ID4gSGksDQo+
ID4gPg0KPiA+ID4gPiArL21lbXJlc2VydmUvIDB4ODAwMDAwMDAgMHgwMDAxMDAwMDsNCj4gPiA+
DQo+ID4gPiBXaHkgaXMgdGhpcyBuZWNlc3Nhcnk/DQo+ID4NCj4gPiBUaGlzIG1lbW9yeSByZWdp
b24gaXMgcHJlLXJlc2VydmVkIGZvciB0aGUgc3Bpbi10YWJsZS9wc2NpLCBhbHRob3VnaA0KPiA+
IGRpZG4ndCBhZGQgRW5hYmxlIG1ldGhvZCBvZiBzZWNvbmRhcnkgY29yZXMuDQo+IA0KPiBZb3Vy
IFBTQ0kgaW1wbGVtZW50YXRpb24gaXNuJ3QgaW4gc2VjdXJlIG1lbW9yeT8NCj4gDQoNClNvcnJ5
LCB0aGlzIGlzIGZvciBzcGluLXRhYmxlLCBwc2NpIHdpbGwgZml4IGl0IGluIHUtYm9vdC4NCg0K
PiA+ID4gPiArICAgICAgIGlmYzogaWZjQDE1MzAwMDAgew0KPiA+ID4gPiArICAgICAgICAgICAg
ICAgY29tcGF0aWJsZSA9ICJmc2wsaWZjIiwgInNpbXBsZS1idXMiOw0KPiA+ID4gPiArICAgICAg
ICAgICAgICAgcmVnID0gPDB4MCAweDE1MzAwMDAgMHgwIDB4MTAwMDA+Ow0KPiA+ID4gPiArICAg
ICAgICAgICAgICAgaW50ZXJydXB0cyA9IDwwIDQzIDB4ND47DQo+ID4gPiA+ICsgICAgICAgfTsN
Cj4gPiA+DQo+ID4gPiBXaHkgc2ltcGxlLWJ1cz8NCj4gPg0KPiA+IFRoZXJlIGFyZSAzIGNoaWxk
IG5vZGUgbG9jYXRlZCBpbiBkdHNpIGZpbGUgdGhhdCBzaG91bGQgYmUgY3JlYXRlZCBhbmQNCj4g
PiBhZGRlZCB0byBwbGF0Zm9ybSBkZXZpY2UgbGlzdC4NCj4gDQo+IEFyZSB0aGV5IHVzYWJsZSBl
dmVuIGlmIHRoZSBrZXJuZWwga25ldyBub3RoaW5nIGFib3V0IHRoZSBJRkMgbm9kZT8gSWYNCj4g
bm90LCB0aGUgSUZDIGRyaXZlciBzaG91bGQgcHJvYmUgdGhlbSwgYW5kIHNpbXBsZS1idXMgc2hv
dWxkIGdvLg0KPiANCj4gPiA+ID4gKyAgICAgICBtZW1vcnlAODAwMDAwMDAgew0KPiA+ID4gPiAr
ICAgICAgICAgICAgICAgZGV2aWNlX3R5cGUgPSAibWVtb3J5IjsNCj4gPiA+ID4gKyAgICAgICAg
ICAgICAgIHJlZyA9IDwweDAgMHg4MDAwMDAwMCAwIDB4ODAwMDAwMDA+Ow0KPiA+ID4gPiArICAg
ICAgICAgICAgICAgICAgICAgLyogRFJBTSBzcGFjZSAxIC0gMiBHQiBEUkFNICovDQo+ID4gPg0K
PiA+ID4gSSBkb24ndCB1bmRlcnN0YW5kIHRoZSBjb21tZW50LiBUaGlzIGRlc2NyaWJlcyAyR0Ig
YXQgMkdCLg0KPiA+ID4NCj4gPg0KPiA+IFllcywgdGhlcmUgaXMgYSAyR0Igc3BhY2UgZm9yIERS
QU0gZnJvbSBhZGRyZXNzIDJHLg0KPiA+IFRoZSBEUkFNIGFkZHJlc3MgMHgwIHdpbGwgYmUgcmVt
YXBwZWQgdG8gU29DIGFkZHJlc3MgMkcsIHRoaXMgcmVtYXAgaXMNCj4gZG9uZSBieSBoYXJkd2Fy
ZS4NCj4gDQo+IEkganVzdCByZWFsaXNlZCBteSBtaXN0YWtlIC0tIEkgcmVhZCB0aGlzIGFzICIx
IHRvIDIgR0IiLCB3aGVuIHRoaXMgaXMNCj4gYWN0dWFsbHkgIkRSQU0gc3BhY2UgMSIuIFNvcnJ5
IGZvciB0aGUgbm9pc2UuDQo+IA0KDQpUaGFua3MsDQpaaGlxaWFuZw0K
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-23 3:57 ` Hou Zhiqiang
0 siblings, 0 replies; 75+ messages in thread
From: Hou Zhiqiang @ 2015-09-23 3:57 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland at arm.com]
> Sent: 2015?9?23? 6:15
> To: Hou Zhiqiang-B48286
> Cc: Marc Zyngier; linux-arm-kernel at lists.infradead.org; Catalin Marinas;
> Will Deacon; linux-i2c at vger.kernel.org; linux-watchdog at vger.kernel.org;
> linux-doc at vger.kernel.org; linux-clk at vger.kernel.org; Xie Shaohui-B21989;
> corbet at lwn.net; Sharma Bhupesh-B45370; mturquette at baylibre.com; wsa at the-
> dreams.de; sboyd at codeaurora.org; wim at iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284; Li Yang-Leo-R58472
> Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> On Tue, Sep 22, 2015 at 10:50:21AM +0100, Hou Zhiqiang wrote:
> > Hi Mark,
> >
> > > -----Original Message-----
> > > From: Mark Rutland [mailto:mark.rutland at arm.com]
> > > Sent: 2015?9?22? 9:24
> > > To: Hou Zhiqiang-B48286; marc.zyngier at arm.com
> > > Cc: linux-arm-kernel at lists.infradead.org; Catalin Marinas; Will
> > > Deacon; linux-i2c at vger.kernel.org; linux-watchdog at vger.kernel.org;
> > > linux- doc at vger.kernel.org; linux-clk at vger.kernel.org; Xie
> > > Shaohui-B21989; corbet at lwn.net; Sharma Bhupesh-B45370;
> > > mturquette at baylibre.com; wsa at the- dreams.de; sboyd at codeaurora.org;
> > > wim at iguana.be; Song Wenbin-B53747; Wood Scott-B07421; Hu
> > > Mingkai-B21284; Li Yang-Leo-R58472
> > > Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale
> > > LS1043A SoC
> > >
> > > Hi,
> > >
> > > > +/memreserve/ 0x80000000 0x00010000;
> > >
> > > Why is this necessary?
> >
> > This memory region is pre-reserved for the spin-table/psci, although
> > didn't add Enable method of secondary cores.
>
> Your PSCI implementation isn't in secure memory?
>
Sorry, this is for spin-table, psci will fix it in u-boot.
> > > > + ifc: ifc at 1530000 {
> > > > + compatible = "fsl,ifc", "simple-bus";
> > > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > > + interrupts = <0 43 0x4>;
> > > > + };
> > >
> > > Why simple-bus?
> >
> > There are 3 child node located in dtsi file that should be created and
> > added to platform device list.
>
> Are they usable even if the kernel knew nothing about the IFC node? If
> not, the IFC driver should probe them, and simple-bus should go.
>
> > > > + memory at 80000000 {
> > > > + device_type = "memory";
> > > > + reg = <0x0 0x80000000 0 0x80000000>;
> > > > + /* DRAM space 1 - 2 GB DRAM */
> > >
> > > I don't understand the comment. This describes 2GB at 2GB.
> > >
> >
> > Yes, there is a 2GB space for DRAM from address 2G.
> > The DRAM address 0x0 will be remapped to SoC address 2G, this remap is
> done by hardware.
>
> I just realised my mistake -- I read this as "1 to 2 GB", when this is
> actually "DRAM space 1". Sorry for the noise.
>
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 75+ messages in thread* RE: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
@ 2015-09-23 3:57 ` Hou Zhiqiang
0 siblings, 0 replies; 75+ messages in thread
From: Hou Zhiqiang @ 2015-09-23 3:57 UTC (permalink / raw)
To: Mark Rutland
Cc: Marc Zyngier, linux-arm-kernel@lists.infradead.org,
Catalin Marinas, Will Deacon, linux-i2c@vger.kernel.org,
linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Shaohui Xie, corbet@lwn.net,
Sharma Bhupesh, mturquette@baylibre.com, wsa@the-dreams.de,
sboyd@codeaurora.org, wim@iguana.be, Wenbin Song, Scott Wood,
Hu Vincent, Li Leo
> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland@arm.com]
> Sent: 2015年9月23日 6:15
> To: Hou Zhiqiang-B48286
> Cc: Marc Zyngier; linux-arm-kernel@lists.infradead.org; Catalin Marinas;
> Will Deacon; linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org;
> linux-doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie Shaohui-B21989;
> corbet@lwn.net; Sharma Bhupesh-B45370; mturquette@baylibre.com; wsa@the-
> dreams.de; sboyd@codeaurora.org; wim@iguana.be; Song Wenbin-B53747; Wood
> Scott-B07421; Hu Mingkai-B21284; Li Yang-Leo-R58472
> Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale LS1043A SoC
>
> On Tue, Sep 22, 2015 at 10:50:21AM +0100, Hou Zhiqiang wrote:
> > Hi Mark,
> >
> > > -----Original Message-----
> > > From: Mark Rutland [mailto:mark.rutland@arm.com]
> > > Sent: 2015年9月22日 9:24
> > > To: Hou Zhiqiang-B48286; marc.zyngier@arm.com
> > > Cc: linux-arm-kernel@lists.infradead.org; Catalin Marinas; Will
> > > Deacon; linux-i2c@vger.kernel.org; linux-watchdog@vger.kernel.org;
> > > linux- doc@vger.kernel.org; linux-clk@vger.kernel.org; Xie
> > > Shaohui-B21989; corbet@lwn.net; Sharma Bhupesh-B45370;
> > > mturquette@baylibre.com; wsa@the- dreams.de; sboyd@codeaurora.org;
> > > wim@iguana.be; Song Wenbin-B53747; Wood Scott-B07421; Hu
> > > Mingkai-B21284; Li Yang-Leo-R58472
> > > Subject: Re: [PATCH 4/6] arm64/ls1043a: add DTS for Freescale
> > > LS1043A SoC
> > >
> > > Hi,
> > >
> > > > +/memreserve/ 0x80000000 0x00010000;
> > >
> > > Why is this necessary?
> >
> > This memory region is pre-reserved for the spin-table/psci, although
> > didn't add Enable method of secondary cores.
>
> Your PSCI implementation isn't in secure memory?
>
Sorry, this is for spin-table, psci will fix it in u-boot.
> > > > + ifc: ifc@1530000 {
> > > > + compatible = "fsl,ifc", "simple-bus";
> > > > + reg = <0x0 0x1530000 0x0 0x10000>;
> > > > + interrupts = <0 43 0x4>;
> > > > + };
> > >
> > > Why simple-bus?
> >
> > There are 3 child node located in dtsi file that should be created and
> > added to platform device list.
>
> Are they usable even if the kernel knew nothing about the IFC node? If
> not, the IFC driver should probe them, and simple-bus should go.
>
> > > > + memory@80000000 {
> > > > + device_type = "memory";
> > > > + reg = <0x0 0x80000000 0 0x80000000>;
> > > > + /* DRAM space 1 - 2 GB DRAM */
> > >
> > > I don't understand the comment. This describes 2GB at 2GB.
> > >
> >
> > Yes, there is a 2GB space for DRAM from address 2G.
> > The DRAM address 0x0 will be remapped to SoC address 2G, this remap is
> done by hardware.
>
> I just realised my mistake -- I read this as "1 to 2 GB", when this is
> actually "DRAM space 1". Sorry for the noise.
>
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 75+ messages in thread