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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org, Nick Bowler <nbowler@draconx.ca>,
	stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4
Date: Thu, 8 Oct 2015 11:18:44 +0300	[thread overview]
Message-ID: <20151008081844.GS26517@intel.com> (raw)
In-Reply-To: <20151008081730.GZ3383@phenom.ffwll.local>

On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote:
> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > We accidentally lost the initial DPLL register write in
> > 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M
> > 
> > The "three times for luck" hack probably saved us from a total
> > disaster. But anyway, bring the initial write back so that the
> > code actually makes some sense.
> > 
> > Cc: stable@vger.kernel.org
> > Cc: Nick Bowler <nbowler@draconx.ca>
> Reported-and-tested-by: Nick Bowler <nbowler@draconx.ca>
> References: http://lists.freedesktop.org/archives/intel-gfx/2015-October/077463.html
> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 147e700..f4fdff9 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
> >  			   I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
> 
> Don't we also need a POSTING_READ here to make sure the two-step 2x mode
> sequence is still followed?

We don't do write combining on registers, and there are no shadow
register type of things to consider in this case either.

> 
> With that addressed Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >  	}
> >  
> > +	I915_WRITE(reg, dpll);
> > +
> >  	/* Wait for the clocks to stabilize. */
> >  	POSTING_READ(reg);
> >  	udelay(150);
> > -- 
> > 2.4.9
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC

WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org, Nick Bowler <nbowler@draconx.ca>,
	stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4
Date: Thu, 8 Oct 2015 11:18:44 +0300	[thread overview]
Message-ID: <20151008081844.GS26517@intel.com> (raw)
In-Reply-To: <20151008081730.GZ3383@phenom.ffwll.local>

On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote:
> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> > 
> > We accidentally lost the initial DPLL register write in
> > 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M
> > 
> > The "three times for luck" hack probably saved us from a total
> > disaster. But anyway, bring the initial write back so that the
> > code actually makes some sense.
> > 
> > Cc: stable@vger.kernel.org
> > Cc: Nick Bowler <nbowler@draconx.ca>
> Reported-and-tested-by: Nick Bowler <nbowler@draconx.ca>
> References: http://lists.freedesktop.org/archives/intel-gfx/2015-October/077463.html
> 
> > Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 147e700..f4fdff9 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
> >  			   I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
> 
> Don't we also need a POSTING_READ here to make sure the two-step 2x mode
> sequence is still followed?

We don't do write combining on registers, and there are no shadow
register type of things to consider in this case either.

> 
> With that addressed Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >  	}
> >  
> > +	I915_WRITE(reg, dpll);
> > +
> >  	/* Wait for the clocks to stabilize. */
> >  	POSTING_READ(reg);
> >  	udelay(150);
> > -- 
> > 2.4.9
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrj�l�
Intel OTC

  reply	other threads:[~2015-10-08  8:18 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-07 19:08 [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4 ville.syrjala
2015-10-07 19:08 ` [PATCH 2/2] drm/i915: Enable DPLL VGA mode before P1/P2 divider write ville.syrjala
2015-10-08  8:19   ` Daniel Vetter
2015-10-08  8:47     ` Chris Wilson
2015-10-08  8:17 ` [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4 Daniel Vetter
2015-10-08  8:17   ` Daniel Vetter
2015-10-08  8:18   ` Ville Syrjälä [this message]
2015-10-08  8:18     ` Ville Syrjälä
2015-10-13 13:10     ` Jani Nikula
2015-10-13 13:10       ` [Intel-gfx] " Jani Nikula
2015-10-13 13:56       ` Daniel Vetter
2015-10-13 13:56         ` [Intel-gfx] " Daniel Vetter
2015-10-13 14:07         ` Jani Nikula
2015-10-13 14:07           ` [Intel-gfx] " Jani Nikula

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