Re: [Qemu-devel] [PATCH v3 5/6] tcg/mips: Support r6 multiply/divide encodings

[Aurelien Jarno <aurelien@aurel32.net>]

On 2015-10-02 13:24, James Hogan wrote:
> MIPSr6 adds several new integer multiply, divide, and modulo
> instructions, and removes several pre-r6 encodings, along with the HI/LO
> registers which were the implicit operands of some of those
> instructions. Update TCG to use the new instructions when built for r6.
> 
> The new instructions actually map much more directly to the TCG ops, as
> they only provide a single 32-bit half of the result and in a normal
> general purpose register instead of HI or LO.
> 
> The mulu2_i32 and muls2_i32 operations are no longer appropriate for r6,
> so they are removed from the TCG opcode table. This is because they
> would need to emit two separate host instructions anyway (for the high
> and low half of the result), which TCG can arrange automatically for us
> in the absense of mulu2_i32/muls2_i32 by splitting it into mul_i32 and
> mul*h_i32 TCG ops.
> 
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Reviewed-by: Richard Henderson <rth@twiddle.net>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> ---
> Changes in v2:
> - Use a common OPC_MUL definition. use_mips32_instructions will always
>   be 1 for MIPS r6 builds (Richard)
> ---
>  tcg/mips/tcg-target.c | 42 +++++++++++++++++++++++++++++++++++++++++-
>  tcg/mips/tcg-target.h |  4 ++--
>  2 files changed, 43 insertions(+), 3 deletions(-)

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net