Re: [Qemu-devel] [PATCH v3 6/6] tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ

[Aurelien Jarno <aurelien@aurel32.net>]

On 2015-10-02 13:24, James Hogan wrote:
> Extend MIPS movcond implementation to support the SELNEZ/SELEQZ
> instructions introduced in MIPS r6 (where MOVN/MOVZ have been removed).
> 
> Whereas the "MOVN/MOVZ rd, rs, rt" instructions have the following
> semantics:
>  rd = [!]rt ? rs : rd
> 
> The "SELNEZ/SELEQZ rd, rs, rt" instructions are slightly different:
>  rd = [!]rt ? rs : 0
> 
> First we ensure that if one of the movcond input values is zero that it
> comes last (we can swap the input arguments if we invert the condition).
> This is so that it can exactly match one of the SELNEZ/SELEQZ
> instructions and avoid the need to emit the other one.
> 
> Otherwise we emit the opposite instruction first into a temporary
> register, and OR that into the result:
>  SELNEZ/SELEQZ  TMP1, v2, c1
>  SELEQZ/SELNEZ  ret, v1, c1
>  OR             ret, ret, TMP1
> 
> Which does the following:
>  ret = cond ? v1 : v2
> 
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Cc: Richard Henderson <rth@twiddle.net>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> ---
> Changes in v3:
> - Switch to using bool eqz to indicate whether to use SELEQZ / MOVZ
>   instead of SELNEZ / MOVN (Richard).
> - Add tcg_debug_assert(v2 == ret) for pre-r6 case with comment to remind
>   reader that it should be guaranteed via constraints (Richard).
> 
> Changes in v2:
> - Combine with patch 6 from v1, and drop functional changes to movcond
>   implementation pre-r6. We now provide different constraints for
>   movcond depending on presence of r6. (thanks Richard for feedback).
> ---
>  tcg/mips/tcg-target.c | 43 +++++++++++++++++++++++++++++++++++++------
>  1 file changed, 37 insertions(+), 6 deletions(-)

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net