[PATCH 1/3] mtd: nand: fsmc: Small whitespace cleanup

[PATCH 1/3] mtd: nand: fsmc: Small whitespace cleanup

[Stefan Roese]

Remove tab in empty line.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Brian Norris <computersforpeace@gmail.com>
---
 drivers/mtd/nand/fsmc_nand.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 793872f..dc94882 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -960,7 +960,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	host->data_va = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(host->data_va))
 		return PTR_ERR(host->data_va);
-	
+
 	host->data_pa = (dma_addr_t)res->start;
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
-- 
2.5.3

[PATCH 2/3] mtd: nand: fsmc: Remove BUG macros

[Stefan Roese]

Remove the BUG macros and return with error (if possible) instead.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Brian Norris <computersforpeace@gmail.com>
---
 drivers/mtd/nand/fsmc_nand.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index dc94882..45948e8 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -348,7 +348,7 @@ static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
 		break;
 
 	default:
-		BUG();
+		dev_err(host->dev, "unsupported chip-select %d\n", chipnr);
 	}
 }
 
@@ -1111,7 +1111,8 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 		default:
 			dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
 				 mtd->oobsize);
-			BUG();
+			ret = -EINVAL;
+			goto err_probe;
 		}
 	} else {
 		switch (host->mtd.oobsize) {
@@ -1127,7 +1128,8 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 		default:
 			dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
 				 mtd->oobsize);
-			BUG();
+			ret = -EINVAL;
+			goto err_probe;
 		}
 	}
 
-- 
2.5.3

Re: [PATCH 2/3] mtd: nand: fsmc: Remove BUG macros

[Linus Walleij]

On Fri, Oct 2, 2015 at 12:40 PM, Stefan Roese <sr@denx.de> wrote:

> Remove the BUG macros and return with error (if possible) instead.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> Cc: Brian Norris <computersforpeace@gmail.com>

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

[PATCH 3/3 v2] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600

[Stefan Roese]

This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC
strength. The SPEAr600 HW ECC only supports 1-bit ECC strength.

To enable SW BCH4, you need to specify this in your nand controller
DT node:

	nand-ecc-mode = "soft_bch";
	nand-ecc-strength = <4>;
	nand-ecc-step-size = <512>;

Tested on a custom SPEAr600 board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Brian Norris <computersforpeace@gmail.com>
---
v2:
- Used nand_dt_init() to parse the ECC properties
- Added optional ECC bindings documentation
- Removed whitespace change from this patch, moved to a separate patch
- Removed setting of nand_bch_calculate_ecc / nand_bch_correct_data as its
  already done in nand_scan_tail()
- Moved ECC checking after nand_scan_ident()
- Removed addition of ecc_mode to platform_data as its not needed anymore

 .../devicetree/bindings/mtd/fsmc-nand.txt          |  3 ++
 drivers/mtd/nand/fsmc_nand.c                       | 57 ++++++++++++++++------
 2 files changed, 44 insertions(+), 16 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
index 5235cbc..f861178 100644
--- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
@@ -30,6 +30,9 @@ Optional properties:
                  command is asserted. Zero means one cycle, 255 means 256
                  cycles.
 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
+- nand-ecc-mode      : see nand.txt
+- nand-ecc-strength  : see nand.txt
+- nand-ecc-step-size : see nand.txt
 
 Example:
 
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 45948e8..b2928b4 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -1023,12 +1023,17 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	nand->cmd_ctrl = fsmc_cmd_ctrl;
 	nand->chip_delay = 30;
 
+	/*
+	 * Setup default ECC mode. nand_dt_init() called from nand_scan_init()
+	 * can overwrite this value if the DT provides a different value.
+	 */
 	nand->ecc.mode = NAND_ECC_HW;
 	nand->ecc.hwctl = fsmc_enable_hwecc;
 	nand->ecc.size = 512;
 	nand->options = pdata->options;
 	nand->select_chip = fsmc_select_chip;
 	nand->badblockbits = 7;
+	nand->dn = np;
 
 	if (pdata->width == FSMC_NAND_BW16)
 		nand->options |= NAND_BUSWIDTH_16;
@@ -1070,11 +1075,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 		nand->ecc.correct = fsmc_bch8_correct_data;
 		nand->ecc.bytes = 13;
 		nand->ecc.strength = 8;
-	} else {
-		nand->ecc.calculate = fsmc_read_hwecc_ecc1;
-		nand->ecc.correct = nand_correct_data;
-		nand->ecc.bytes = 3;
-		nand->ecc.strength = 1;
 	}
 
 	/*
@@ -1115,22 +1115,47 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 			goto err_probe;
 		}
 	} else {
-		switch (host->mtd.oobsize) {
-		case 16:
-			nand->ecc.layout = &fsmc_ecc1_16_layout;
+		switch (nand->ecc.mode) {
+		case NAND_ECC_HW:
+			dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
+			nand->ecc.calculate = fsmc_read_hwecc_ecc1;
+			nand->ecc.correct = nand_correct_data;
+			nand->ecc.bytes = 3;
+			nand->ecc.strength = 1;
 			break;
-		case 64:
-			nand->ecc.layout = &fsmc_ecc1_64_layout;
-			break;
-		case 128:
-			nand->ecc.layout = &fsmc_ecc1_128_layout;
+
+		case NAND_ECC_SOFT_BCH:
+			dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
 			break;
+
 		default:
-			dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
-				 mtd->oobsize);
-			ret = -EINVAL;
+			dev_err(&pdev->dev, "Unsupported ECC mode!\n");
 			goto err_probe;
 		}
+
+		/*
+		 * Don't set layout for BCH4 SW ECC. This will be
+		 * generated later in nand_bch_init() later.
+		 */
+		if (nand->ecc.mode != NAND_ECC_SOFT_BCH) {
+			switch (host->mtd.oobsize) {
+			case 16:
+				nand->ecc.layout = &fsmc_ecc1_16_layout;
+				break;
+			case 64:
+				nand->ecc.layout = &fsmc_ecc1_64_layout;
+				break;
+			case 128:
+				nand->ecc.layout = &fsmc_ecc1_128_layout;
+				break;
+			default:
+				dev_warn(&pdev->dev,
+					 "No oob scheme defined for oobsize %d\n",
+					 mtd->oobsize);
+				ret = -EINVAL;
+				goto err_probe;
+			}
+		}
 	}
 
 	/* Second stage of scan to fill MTD data-structures */
-- 
2.5.3

Re: [PATCH 3/3 v2] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600

[Brian Norris]

Please base your series on linux-next.git or l2-mtd.git. See:

http://linux-mtd.infradead.org/source.html

or the MAINTAINERS file.

On Fri, Oct 02, 2015 at 12:40:22PM +0200, Stefan Roese wrote:
> --- a/drivers/mtd/nand/fsmc_nand.c
> +++ b/drivers/mtd/nand/fsmc_nand.c
> @@ -1023,12 +1023,17 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
>  	nand->cmd_ctrl = fsmc_cmd_ctrl;
>  	nand->chip_delay = 30;
>  
> +	/*
> +	 * Setup default ECC mode. nand_dt_init() called from nand_scan_init()
> +	 * can overwrite this value if the DT provides a different value.
> +	 */
>  	nand->ecc.mode = NAND_ECC_HW;
>  	nand->ecc.hwctl = fsmc_enable_hwecc;
>  	nand->ecc.size = 512;
>  	nand->options = pdata->options;
>  	nand->select_chip = fsmc_select_chip;
>  	nand->badblockbits = 7;
> +	nand->dn = np;

drivers/mtd/nand/fsmc_nand.c: In function ‘fsmc_nand_probe’:
drivers/mtd/nand/fsmc_nand.c:1036:6: error: ‘struct nand_chip’ has no member named ‘dn’

This field was renamed for clarity, to flash_node.

>  
>  	if (pdata->width == FSMC_NAND_BW16)
>  		nand->options |= NAND_BUSWIDTH_16;

[...]

Brian

[PATCH 3/3 v3] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600

[Stefan Roese]

This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC
strength. The SPEAr600 HW ECC only supports 1-bit ECC strength.

To enable SW BCH4, you need to specify this in your nand controller
DT node:

	nand-ecc-mode = "soft_bch";
	nand-ecc-strength = <4>;
	nand-ecc-step-size = <512>;

Tested on a custom SPEAr600 board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Brian Norris <computersforpeace@gmail.com>
---
v3:
- Rebased on top of l2-mtd.git
- Changed "dn" to "flash_node"

v2:
- Used nand_dt_init() to parse the ECC properties
- Added optional ECC bindings documentation
- Removed whitespace change from this patch, moved to a separate patch
- Removed setting of nand_bch_calculate_ecc / nand_bch_correct_data as its
  already done in nand_scan_tail()
- Moved ECC checking after nand_scan_ident()
- Removed addition of ecc_mode to platform_data as its not needed anymore

 .../devicetree/bindings/mtd/fsmc-nand.txt          |  3 ++
 drivers/mtd/nand/fsmc_nand.c                       | 57 ++++++++++++++++------
 2 files changed, 44 insertions(+), 16 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
index 5235cbc..f861178 100644
--- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
@@ -30,6 +30,9 @@ Optional properties:
                  command is asserted. Zero means one cycle, 255 means 256
                  cycles.
 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
+- nand-ecc-mode      : see nand.txt
+- nand-ecc-strength  : see nand.txt
+- nand-ecc-step-size : see nand.txt
 
 Example:
 
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index 9e4fd0f..b50be0d 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -1023,12 +1023,17 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	nand->cmd_ctrl = fsmc_cmd_ctrl;
 	nand->chip_delay = 30;
 
+	/*
+	 * Setup default ECC mode. nand_dt_init() called from nand_scan_init()
+	 * can overwrite this value if the DT provides a different value.
+	 */
 	nand->ecc.mode = NAND_ECC_HW;
 	nand->ecc.hwctl = fsmc_enable_hwecc;
 	nand->ecc.size = 512;
 	nand->options = pdata->options;
 	nand->select_chip = fsmc_select_chip;
 	nand->badblockbits = 7;
+	nand->flash_node = np;
 
 	if (pdata->width == FSMC_NAND_BW16)
 		nand->options |= NAND_BUSWIDTH_16;
@@ -1070,11 +1075,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 		nand->ecc.correct = fsmc_bch8_correct_data;
 		nand->ecc.bytes = 13;
 		nand->ecc.strength = 8;
-	} else {
-		nand->ecc.calculate = fsmc_read_hwecc_ecc1;
-		nand->ecc.correct = nand_correct_data;
-		nand->ecc.bytes = 3;
-		nand->ecc.strength = 1;
 	}
 
 	/*
@@ -1115,22 +1115,47 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 			goto err_probe;
 		}
 	} else {
-		switch (host->mtd.oobsize) {
-		case 16:
-			nand->ecc.layout = &fsmc_ecc1_16_layout;
+		switch (nand->ecc.mode) {
+		case NAND_ECC_HW:
+			dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
+			nand->ecc.calculate = fsmc_read_hwecc_ecc1;
+			nand->ecc.correct = nand_correct_data;
+			nand->ecc.bytes = 3;
+			nand->ecc.strength = 1;
 			break;
-		case 64:
-			nand->ecc.layout = &fsmc_ecc1_64_layout;
-			break;
-		case 128:
-			nand->ecc.layout = &fsmc_ecc1_128_layout;
+
+		case NAND_ECC_SOFT_BCH:
+			dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
 			break;
+
 		default:
-			dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
-				 mtd->oobsize);
-			ret = -EINVAL;
+			dev_err(&pdev->dev, "Unsupported ECC mode!\n");
 			goto err_probe;
 		}
+
+		/*
+		 * Don't set layout for BCH4 SW ECC. This will be
+		 * generated later in nand_bch_init() later.
+		 */
+		if (nand->ecc.mode != NAND_ECC_SOFT_BCH) {
+			switch (host->mtd.oobsize) {
+			case 16:
+				nand->ecc.layout = &fsmc_ecc1_16_layout;
+				break;
+			case 64:
+				nand->ecc.layout = &fsmc_ecc1_64_layout;
+				break;
+			case 128:
+				nand->ecc.layout = &fsmc_ecc1_128_layout;
+				break;
+			default:
+				dev_warn(&pdev->dev,
+					 "No oob scheme defined for oobsize %d\n",
+					 mtd->oobsize);
+				ret = -EINVAL;
+				goto err_probe;
+			}
+		}
 	}
 
 	/* Second stage of scan to fill MTD data-structures */
-- 
2.6.2

Re: [PATCH 3/3 v3] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600

[Brian Norris]

Hi Stefan,

On Mon, Oct 19, 2015 at 08:40:13AM +0200, Stefan Roese wrote:
> This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
> be used by boards equipped with a NAND chip that requires 4-bit ECC
> strength. The SPEAr600 HW ECC only supports 1-bit ECC strength.
> 
> To enable SW BCH4, you need to specify this in your nand controller
> DT node:
> 
> 	nand-ecc-mode = "soft_bch";
> 	nand-ecc-strength = <4>;
> 	nand-ecc-step-size = <512>;
> 
> Tested on a custom SPEAr600 board.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> Cc: Brian Norris <computersforpeace@gmail.com>
> ---

Looks good. Applied to l2-mtd.git with a small addition.

> v3:
> - Rebased on top of l2-mtd.git
> - Changed "dn" to "flash_node"
> 
> v2:
> - Used nand_dt_init() to parse the ECC properties
> - Added optional ECC bindings documentation
> - Removed whitespace change from this patch, moved to a separate patch
> - Removed setting of nand_bch_calculate_ecc / nand_bch_correct_data as its
>   already done in nand_scan_tail()
> - Moved ECC checking after nand_scan_ident()
> - Removed addition of ecc_mode to platform_data as its not needed anymore
> 
>  .../devicetree/bindings/mtd/fsmc-nand.txt          |  3 ++
>  drivers/mtd/nand/fsmc_nand.c                       | 57 ++++++++++++++++------
>  2 files changed, 44 insertions(+), 16 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
> index 5235cbc..f861178 100644
> --- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
> @@ -30,6 +30,9 @@ Optional properties:
>                   command is asserted. Zero means one cycle, 255 means 256
>                   cycles.
>  - bank: default NAND bank to use (0-3 are valid, 0 is the default).
> +- nand-ecc-mode      : see nand.txt
> +- nand-ecc-strength  : see nand.txt
> +- nand-ecc-step-size : see nand.txt

nand.txt provides more latitude than some controllers/drivers do. It's
nice to specify which sort of modes are supported. I added a note aboute
HW and soft BCH support here.

>  
>  Example:
>  
> diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
> index 9e4fd0f..b50be0d 100644
> --- a/drivers/mtd/nand/fsmc_nand.c
> +++ b/drivers/mtd/nand/fsmc_nand.c
> @@ -1023,12 +1023,17 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
>  	nand->cmd_ctrl = fsmc_cmd_ctrl;
>  	nand->chip_delay = 30;
>  
> +	/*
> +	 * Setup default ECC mode. nand_dt_init() called from nand_scan_init()

s/nand_scan_init/nand_scan_ident/

> +	 * can overwrite this value if the DT provides a different value.
> +	 */
>  	nand->ecc.mode = NAND_ECC_HW;
>  	nand->ecc.hwctl = fsmc_enable_hwecc;
>  	nand->ecc.size = 512;
>  	nand->options = pdata->options;
>  	nand->select_chip = fsmc_select_chip;
>  	nand->badblockbits = 7;
> +	nand->flash_node = np;
>  
>  	if (pdata->width == FSMC_NAND_BW16)
>  		nand->options |= NAND_BUSWIDTH_16;
[snip]

I squashed in the following change.

diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
index f861178fe69f..32636eb77304 100644
--- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
@@ -34,6 +34,9 @@ Optional properties:
 - nand-ecc-strength  : see nand.txt
 - nand-ecc-step-size : see nand.txt
 
+Can support 1-bit HW ECC (default) or if stronger correction is required,
+software-based BCH.
+
 Example:
 
 	fsmc: flash@d1800000 {
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index b50be0ddeadc..07af3dc7a4d2 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -1024,7 +1024,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
 	nand->chip_delay = 30;
 
 	/*
-	 * Setup default ECC mode. nand_dt_init() called from nand_scan_init()
+	 * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
 	 * can overwrite this value if the DT provides a different value.
 	 */
 	nand->ecc.mode = NAND_ECC_HW;

Re: [PATCH 3/3 v3] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600

[Stefan Roese]

Hi Brian,

On 26.10.2015 21:20, Brian Norris wrote:
> Hi Stefan,
>
> On Mon, Oct 19, 2015 at 08:40:13AM +0200, Stefan Roese wrote:
>> This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
>> be used by boards equipped with a NAND chip that requires 4-bit ECC
>> strength. The SPEAr600 HW ECC only supports 1-bit ECC strength.
>>
>> To enable SW BCH4, you need to specify this in your nand controller
>> DT node:
>>
>> 	nand-ecc-mode = "soft_bch";
>> 	nand-ecc-strength = <4>;
>> 	nand-ecc-step-size = <512>;
>>
>> Tested on a custom SPEAr600 board.
>>
>> Signed-off-by: Stefan Roese <sr@denx.de>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> Cc: Viresh Kumar <viresh.kumar@linaro.org>
>> Cc: Brian Norris <computersforpeace@gmail.com>
>> ---
>
> Looks good. Applied to l2-mtd.git with a small addition.

Thanks Brian. Really appreciated.

Thanks,
Stefan

Re: [PATCH 1/3] mtd: nand: fsmc: Small whitespace cleanup

[Brian Norris]

On Fri, Oct 02, 2015 at 12:40:20PM +0200, Stefan Roese wrote:
> Remove tab in empty line.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> Cc: Brian Norris <computersforpeace@gmail.com>

Pushed patch 1 and 2 to l2-mtd.git. If you resend, you can just resend
patch 3 based on the appropriate repo.

Thanks,
Brian