From: Daniel Vetter <daniel@ffwll.ch>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 03/14] drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB
Date: Fri, 30 Oct 2015 16:42:26 +0100 [thread overview]
Message-ID: <20151030154226.GD16848@phenom.ffwll.local> (raw)
In-Reply-To: <20151029212128.GY4437@intel.com>
On Thu, Oct 29, 2015 at 11:21:28PM +0200, Ville Syrjälä wrote:
> On Thu, Oct 29, 2015 at 05:57:57PM -0200, Paulo Zanoni wrote:
> > 2015-10-29 17:25 GMT-02:00 <ville.syrjala@linux.intel.com>:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > We get spurious PCH FIFO underruns if we enable the reporting too soon
> > > after enabling the crtc. Move it to be the last step, after the encoder
> > > enable. Additionally we need an extra vblank wait, otherwise we still
> > > get the underruns. Presumably the pipe/fdi isn't yet fully up and running
> > > otherwise.
> > >
> > > For symmetry, disable the PCH underrun reporting as the first thing,
> > > just before encoder disable, when shutting down the crtc.
> >
> > Is there any place that describes where/when a FIFO underrun is
> > expected and where/when one is an actual problem that needs to be
> > solved? How do we know the underruns avoided by these patch are not a
> > signal of real bugs?
>
> Can't be 100% sure since its not documented anywhere. But we've been
> getting these since forever now and stuff still works (more or less at
> least), so I'm inclined to say we don't have to care about them. Also
> in these case we only get PCH FIFO underruns and no CPU pipe
> underruns, so I'm tempted to say it's not that serious.
>
> IIRC I once tracked some of these down to having the FDI PLL enabled
> with FDI RX/TX disabled. Or something like that, but don't quote me
> on that since my memory might be failing here. Obviously that can't
> explain it all since I still need the vblank wait to eliminate them.
> Anyway, this time I didn't try to narrow it down too much. Instead
> my aim was more to reliably eliminate them without permamently disabling
> the underrun detection.
>
> In any case, we can't get the bat stuff really working until we get
> the results to be stable, and these underruns are one big obstacle
> to that.
Agreed with Ville here, these are old platforms and we want stable BAT
results first. On gen9+ we should try a bit harder, or at least make a
note in JIRA that we need to look into this.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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next prev parent reply other threads:[~2015-10-30 15:42 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-29 19:25 [PATCH 00/14] drm/i915: FIFO underrun elimination for PCH platforms ville.syrjala
2015-10-29 19:25 ` [PATCH 01/14] drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config around ville.syrjala
2015-10-29 19:34 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 02/14] drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL ville.syrjala
2015-10-29 19:33 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 03/14] drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB ville.syrjala
2015-10-29 19:34 ` Jesse Barnes
2015-10-29 19:57 ` Paulo Zanoni
2015-10-29 21:21 ` Ville Syrjälä
2015-10-30 15:42 ` Daniel Vetter [this message]
2015-10-30 10:06 ` Jani Nikula
2015-10-30 12:08 ` Ville Syrjälä
2015-10-30 12:31 ` Jani Nikula
2015-10-30 15:41 ` Daniel Vetter
2015-10-30 17:20 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 04/14] drm/i915: Enable PCH FIFO underruns later on HSW+ ville.syrjala
2015-10-29 19:34 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 05/14] drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabled ville.syrjala
2015-10-29 19:36 ` Jesse Barnes
2015-10-29 21:39 ` Ville Syrjälä
2015-10-30 17:21 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 06/14] drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPT ville.syrjala
2015-10-30 15:45 ` Daniel Vetter
2015-10-30 17:22 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 07/14] drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder() ville.syrjala
2015-10-29 19:37 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 08/14] drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaround ville.syrjala
2015-10-29 19:38 ` Jesse Barnes
2015-10-30 10:11 ` Jani Nikula
2015-10-30 12:15 ` Ville Syrjälä
2015-10-30 17:23 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 09/14] drm/i915: Hide underruns from eDP PLL and port enable on ILK ville.syrjala
2015-10-29 19:39 ` Jesse Barnes
2015-10-29 21:33 ` Ville Syrjälä
2015-10-29 19:25 ` [PATCH 10/14] drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/ ville.syrjala
2015-10-30 15:49 ` Daniel Vetter
2015-10-29 19:26 ` [PATCH 11/14] drm/i915: Remove ILK-A eDP PLL workaround notes ville.syrjala
2015-10-29 19:40 ` Jesse Barnes
2015-10-29 19:26 ` [PATCH 12/14] drm/i915: Clean up eDP PLL state asserts ville.syrjala
2015-10-30 15:53 ` Daniel Vetter
2015-10-29 19:26 ` [PATCH 13/14] drm/i915: Use intel_dp->DP in eDP PLL setup ville.syrjala
2015-10-30 16:00 ` Daniel Vetter
2015-10-30 16:36 ` Ville Syrjälä
2015-11-10 14:37 ` Jani Nikula
2015-11-10 14:16 ` [PATCH v2 " ville.syrjala
2015-11-10 14:43 ` Jani Nikula
2015-10-29 19:26 ` [PATCH 14/14] drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on() ville.syrjala
2015-10-30 16:01 ` Daniel Vetter
2015-10-30 13:30 ` [PATCH 00/14] drm/i915: FIFO underrun elimination for PCH platforms Jani Nikula
2015-11-10 15:04 ` Ville Syrjälä
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