From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 00/14] drm/i915: FIFO underrun elimination for PCH platforms
Date: Tue, 10 Nov 2015 17:04:44 +0200 [thread overview]
Message-ID: <20151110150444.GG4437@intel.com> (raw)
In-Reply-To: <1446146763-31821-1-git-send-email-ville.syrjala@linux.intel.com>
On Thu, Oct 29, 2015 at 09:25:49PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> This series eliminates all spurious PCH FIFO underrun reports on my
> machines during a BAT run ('-t basic -x reload -x suspend' actually).
> It also eliminates the non-spurious but expected underrun reports
> on ILK.
>
> I also embarked on a small scale cleanup of the CPU eDP PLL code while
> I was trying to get to the bottom of the underruns on ILK. So I figured
> I'd include that work here as well.
>
> I've tested this on ILK, SNB, two IVBs, and one HSW, with as many
> displays plugged in as possible. What I could actually test is HSW/BDW
> CRT output since I have no machine for that.
>
> The series is available here:
> git://github.com/vsyrjala/linux.git pch_fifo_underrun_fix_4
>
> Ville Syrjälä (14):
> drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe
> config around
> drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL
> drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB
> drm/i915: Enable PCH FIFO underruns later on HSW+
> drm/i915: Re-enable PCH FIO underrun reporting after pipe has been
> disabled
> drm/i915: Check for FIFO underruns after modeset on IVB/HSW and
> CPT/PPT
> drm/i915: Check for CPT and not !IBX in
> ironlake_disable_pch_transcoder()
> drm/i915: Disable FIFO underrun reporting around IBX transcoder B
> workaround
> drm/i915: Hide underruns from eDP PLL and port enable on ILK
> drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/
> drm/i915: Remove ILK-A eDP PLL workaround notes
> drm/i915: Clean up eDP PLL state asserts
> drm/i915: Use intel_dp->DP in eDP PLL setup
> drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on()
Entire series applied. Thanks for the reviews.
>
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 64 +++++++----
> drivers/gpu/drm/i915/intel_dp.c | 179 ++++++++++++++++++-----------
> drivers/gpu/drm/i915/intel_drv.h | 12 +-
> drivers/gpu/drm/i915/intel_fifo_underrun.c | 121 +++++++++++++++----
> drivers/gpu/drm/i915/intel_hdmi.c | 11 ++
> drivers/gpu/drm/i915/intel_sdvo.c | 11 ++
> 7 files changed, 285 insertions(+), 115 deletions(-)
>
> --
> 2.4.10
--
Ville Syrjälä
Intel OTC
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prev parent reply other threads:[~2015-11-10 15:05 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-29 19:25 [PATCH 00/14] drm/i915: FIFO underrun elimination for PCH platforms ville.syrjala
2015-10-29 19:25 ` [PATCH 01/14] drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config around ville.syrjala
2015-10-29 19:34 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 02/14] drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL ville.syrjala
2015-10-29 19:33 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 03/14] drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB ville.syrjala
2015-10-29 19:34 ` Jesse Barnes
2015-10-29 19:57 ` Paulo Zanoni
2015-10-29 21:21 ` Ville Syrjälä
2015-10-30 15:42 ` Daniel Vetter
2015-10-30 10:06 ` Jani Nikula
2015-10-30 12:08 ` Ville Syrjälä
2015-10-30 12:31 ` Jani Nikula
2015-10-30 15:41 ` Daniel Vetter
2015-10-30 17:20 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 04/14] drm/i915: Enable PCH FIFO underruns later on HSW+ ville.syrjala
2015-10-29 19:34 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 05/14] drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabled ville.syrjala
2015-10-29 19:36 ` Jesse Barnes
2015-10-29 21:39 ` Ville Syrjälä
2015-10-30 17:21 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 06/14] drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPT ville.syrjala
2015-10-30 15:45 ` Daniel Vetter
2015-10-30 17:22 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 07/14] drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder() ville.syrjala
2015-10-29 19:37 ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 08/14] drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaround ville.syrjala
2015-10-29 19:38 ` Jesse Barnes
2015-10-30 10:11 ` Jani Nikula
2015-10-30 12:15 ` Ville Syrjälä
2015-10-30 17:23 ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 09/14] drm/i915: Hide underruns from eDP PLL and port enable on ILK ville.syrjala
2015-10-29 19:39 ` Jesse Barnes
2015-10-29 21:33 ` Ville Syrjälä
2015-10-29 19:25 ` [PATCH 10/14] drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/ ville.syrjala
2015-10-30 15:49 ` Daniel Vetter
2015-10-29 19:26 ` [PATCH 11/14] drm/i915: Remove ILK-A eDP PLL workaround notes ville.syrjala
2015-10-29 19:40 ` Jesse Barnes
2015-10-29 19:26 ` [PATCH 12/14] drm/i915: Clean up eDP PLL state asserts ville.syrjala
2015-10-30 15:53 ` Daniel Vetter
2015-10-29 19:26 ` [PATCH 13/14] drm/i915: Use intel_dp->DP in eDP PLL setup ville.syrjala
2015-10-30 16:00 ` Daniel Vetter
2015-10-30 16:36 ` Ville Syrjälä
2015-11-10 14:37 ` Jani Nikula
2015-11-10 14:16 ` [PATCH v2 " ville.syrjala
2015-11-10 14:43 ` Jani Nikula
2015-10-29 19:26 ` [PATCH 14/14] drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on() ville.syrjala
2015-10-30 16:01 ` Daniel Vetter
2015-10-30 13:30 ` [PATCH 00/14] drm/i915: FIFO underrun elimination for PCH platforms Jani Nikula
2015-11-10 15:04 ` Ville Syrjälä [this message]
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