* [PATCH v5 0/7] ARM: dts: Add Advantech board support
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ, Akshay Bhat
This series aims to add Advantech BA-16 module (iMX6 based) and GE board support.
This series has been tested against linux-next tag next-20151202.
Modifications:
v4->v5:
- BA16: Move SPI FLASH partitions to a "partitions" subnode
- B450v3, B650v3 and B850v3: Fix model names
History:
--------
[v1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/381872.html
[v2]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/383276.html
[v3]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/384202.html
[v4]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390373.html
Akshay Bhat (5):
of: Add vendor prefix for Advantech Corporation
of: Add vendor prefix for General Electric Company
ARM: dts: imx: Add support for Advantech/GE B450v3
ARM: dts: imx: Add support for Advantech/GE B650v3
ARM: dts: imx: Add support for Advantech/GE B850v3
Justin Waters (2):
ARM: dts: imx: Add Advantech BA-16 Qseven module
ARM: dts: imx: Add support for Advantech/GE Bx50v3
.../devicetree/bindings/vendor-prefixes.txt | 2 +
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/imx6q-b450v3.dts | 84 +++
arch/arm/boot/dts/imx6q-b650v3.dts | 84 +++
arch/arm/boot/dts/imx6q-b850v3.dts | 127 +++++
arch/arm/boot/dts/imx6q-ba16.dtsi | 589 +++++++++++++++++++++
arch/arm/boot/dts/imx6q-bx50v3.dtsi | 207 ++++++++
7 files changed, 1096 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b450v3.dts
create mode 100644 arch/arm/boot/dts/imx6q-b650v3.dts
create mode 100644 arch/arm/boot/dts/imx6q-b850v3.dts
create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
create mode 100644 arch/arm/boot/dts/imx6q-bx50v3.dtsi
--
2.6.3
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v5 1/7] of: Add vendor prefix for Advantech Corporation
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds vendor prefix for Advantech Corporation.
Website: http://www.advantech.com/
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 62ff22f..c51bf7c 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -10,6 +10,7 @@ ad Avionic Design GmbH
adapteva Adapteva, Inc.
adh AD Holdings Plc.
adi Analog Devices, Inc.
+advantech Advantech Corporation
aeroflexgaisler Aeroflex Gaisler AB
al Annapurna Labs
allwinner Allwinner Technology Co., Ltd.
--
2.6.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v5 1/7] of: Add vendor prefix for Advantech Corporation
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ, Akshay Bhat
This patch adds vendor prefix for Advantech Corporation.
Website: http://www.advantech.com/
Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 62ff22f..c51bf7c 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -10,6 +10,7 @@ ad Avionic Design GmbH
adapteva Adapteva, Inc.
adh AD Holdings Plc.
adi Analog Devices, Inc.
+advantech Advantech Corporation
aeroflexgaisler Aeroflex Gaisler AB
al Annapurna Labs
allwinner Allwinner Technology Co., Ltd.
--
2.6.3
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v5 2/7] of: Add vendor prefix for General Electric Company
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds vendor prefix for General Electric Company
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index c51bf7c..f1cc839 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -88,6 +88,7 @@ fcs Fairchild Semiconductor
firefly Firefly
focaltech FocalTech Systems Co.,Ltd
fsl Freescale Semiconductor
+ge General Electric Company
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
geniatech Geniatech, Inc.
--
2.6.3
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v5 2/7] of: Add vendor prefix for General Electric Company
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ, Akshay Bhat
This patch adds vendor prefix for General Electric Company
Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index c51bf7c..f1cc839 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -88,6 +88,7 @@ fcs Fairchild Semiconductor
firefly Firefly
focaltech FocalTech Systems Co.,Ltd
fsl Freescale Semiconductor
+ge General Electric Company
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
geniatech Geniatech, Inc.
--
2.6.3
--
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v5 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: linux-arm-kernel
From: Justin Waters <justin.waters@timesys.com>
Add support for Advantech BA-16 module based on iMX6D processor
http://www2.advantech.com/products/medical_computing_system/dms-ba16/mod_64aa1566-169c-483d-97c8-c2c22c163fc3.aspx
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/imx6q-ba16.dtsi | 589 ++++++++++++++++++++++++++++++++++++++
1 file changed, 589 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
new file mode 100644
index 0000000..9510713
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -0,0 +1,589 @@
+/*
+ * Support for imx6 based Advantech DMS-BA16 Qseven module
+ *
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ memory {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ clocks {
+ clk24m: clk24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+ backlight_lvds: backlight {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_display>;
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100 101 102 103 104 105 106 107 108 109
+ 110 111 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127 128 129
+ 130 131 132 133 134 135 136 137 138 139
+ 140 141 142 143 144 145 146 147 148 149
+ 150 151 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167 168 169
+ 170 171 172 173 174 175 176 177 178 179
+ 180 181 182 183 184 185 186 187 188 189
+ 190 191 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207 208 209
+ 210 211 212 213 214 215 216 217 218 219
+ 220 221 222 223 224 225 226 227 228 229
+ 230 231 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247 248 249
+ 250 251 252 253 254 255>;
+ default-brightness-level = <255>;
+ enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_1p8v: regulator at 1 {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator at 2 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_lvds: regulator at 3 {
+ compatible = "regulator-fixed";
+ regulator-name = "lvds_ppen";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg_vbus: regulator at 4 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_h1_vbus: regulator at 5 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash: n25q032 at 0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ partitions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "U-Boot";
+ reg = <0x0 0xC0000>;
+ };
+ partition at C0000 {
+ label = "env";
+ reg = <0xC0000 0x10000>;
+ };
+ partition at D0000 {
+ label = "spare";
+ reg = <0xD0000 0x130000>;
+ };
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ pmic at 58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ vdd_bcore1: bcore1 {
+ regulator-min-microvolt = <1420000>;
+ regulator-max-microvolt = <1420000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bcore2: bcore2 {
+ regulator-min-microvolt = <1420000>;
+ regulator-max-microvolt = <1420000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bpro: bpro {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bmem: bmem {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bio: bio {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bperi: bperi {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_ldo1: ldo1 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1860000>;
+ };
+
+ vdd_ldo2: ldo2 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1860000>;
+ };
+
+ vdd_ldo3: ldo3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3440000>;
+ };
+
+ vdd_ldo4: ldo4 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3440000>;
+ };
+
+ vdd_ldo5: ldo5 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo6: ldo6 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo7: ldo7 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo8: ldo8 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo9: ldo9 {
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo10: ldo10 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo11: ldo11 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ rtc at 32 {
+ compatible = "epson,rx8010";
+ reg = <0x32>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx6q-ba16 {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
+ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM CLK */
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 /* SUS_S3_OUT */
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
+ >;
+ };
+
+ pinctrl_usbhub: usbhubgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIe Reset */
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* PCIe Wake */
+ >;
+ };
+
+ pinctrl_display: dispgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* BLEN_OUT */
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
+ >;
+ };
+
+ pinctrl_ecspi5: ecspi5rp-1 {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
+ MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
+ MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_reset: usdhc3grp-reset {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
+ >;
+ };
+
+ pinctrl_audmux: audmux {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
+ MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
+ MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
+ >;
+ };
+
+ pinctrl_enet: pinctrl_enet {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
+ >;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&ssi1 {
+ fsl,mode = "i2s-master";
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbhub>;
+ vbus-supply = <®_usb_h1_vbus>;
+ reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
+ bus-width = <8>;
+ vmmc-supply = <&vdd_bperi>;
+ vqmmc-supply = <&vdd_bio>;
+ non-removable;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ, Akshay Bhat
From: Justin Waters <justin.waters-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
Add support for Advantech BA-16 module based on iMX6D processor
http://www2.advantech.com/products/medical_computing_system/dms-ba16/mod_64aa1566-169c-483d-97c8-c2c22c163fc3.aspx
Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
---
arch/arm/boot/dts/imx6q-ba16.dtsi | 589 ++++++++++++++++++++++++++++++++++++++
1 file changed, 589 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
new file mode 100644
index 0000000..9510713
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -0,0 +1,589 @@
+/*
+ * Support for imx6 based Advantech DMS-BA16 Qseven module
+ *
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ memory {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ clocks {
+ clk24m: clk24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+ backlight_lvds: backlight {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_display>;
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100 101 102 103 104 105 106 107 108 109
+ 110 111 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127 128 129
+ 130 131 132 133 134 135 136 137 138 139
+ 140 141 142 143 144 145 146 147 148 149
+ 150 151 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167 168 169
+ 170 171 172 173 174 175 176 177 178 179
+ 180 181 182 183 184 185 186 187 188 189
+ 190 191 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207 208 209
+ 210 211 212 213 214 215 216 217 218 219
+ 220 221 222 223 224 225 226 227 228 229
+ 230 231 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247 248 249
+ 250 251 252 253 254 255>;
+ default-brightness-level = <255>;
+ enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_1p8v: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_lvds: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "lvds_ppen";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg_vbus: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_h1_vbus: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash: n25q032@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ partitions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0xC0000>;
+ };
+ partition@C0000 {
+ label = "env";
+ reg = <0xC0000 0x10000>;
+ };
+ partition@D0000 {
+ label = "spare";
+ reg = <0xD0000 0x130000>;
+ };
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ vdd_bcore1: bcore1 {
+ regulator-min-microvolt = <1420000>;
+ regulator-max-microvolt = <1420000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bcore2: bcore2 {
+ regulator-min-microvolt = <1420000>;
+ regulator-max-microvolt = <1420000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bpro: bpro {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bmem: bmem {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bio: bio {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_bperi: bperi {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_ldo1: ldo1 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1860000>;
+ };
+
+ vdd_ldo2: ldo2 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1860000>;
+ };
+
+ vdd_ldo3: ldo3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3440000>;
+ };
+
+ vdd_ldo4: ldo4 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3440000>;
+ };
+
+ vdd_ldo5: ldo5 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo6: ldo6 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo7: ldo7 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo8: ldo8 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo9: ldo9 {
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo10: ldo10 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ vdd_ldo11: ldo11 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ rtc@32 {
+ compatible = "epson,rx8010";
+ reg = <0x32>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx6q-ba16 {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
+ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM CLK */
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 /* SUS_S3_OUT */
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
+ >;
+ };
+
+ pinctrl_usbhub: usbhubgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIe Reset */
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* PCIe Wake */
+ >;
+ };
+
+ pinctrl_display: dispgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* BLEN_OUT */
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
+ >;
+ };
+
+ pinctrl_ecspi5: ecspi5rp-1 {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
+ MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
+ MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_reset: usdhc3grp-reset {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
+ >;
+ };
+
+ pinctrl_audmux: audmux {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
+ MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
+ MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
+ >;
+ };
+
+ pinctrl_enet: pinctrl_enet {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
+ >;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&ssi1 {
+ fsl,mode = "i2s-master";
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbhub>;
+ vbus-supply = <®_usb_h1_vbus>;
+ reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
+ bus-width = <8>;
+ vmmc-supply = <&vdd_bperi>;
+ vqmmc-supply = <&vdd_bio>;
+ non-removable;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+};
--
2.6.3
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^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
2015-12-03 21:10 ` Akshay Bhat
@ 2015-12-22 11:40 ` Shawn Guo
-1 siblings, 0 replies; 28+ messages in thread
From: Shawn Guo @ 2015-12-22 11:40 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Dec 03, 2015 at 04:10:32PM -0500, Akshay Bhat wrote:
> From: Justin Waters <justin.waters@timesys.com>
>
> Add support for Advantech BA-16 module based on iMX6D processor
>
> http://www2.advantech.com/products/medical_computing_system/dms-ba16/mod_64aa1566-169c-483d-97c8-c2c22c163fc3.aspx
> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
> ---
> arch/arm/boot/dts/imx6q-ba16.dtsi | 589 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 589 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
> new file mode 100644
> index 0000000..9510713
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
> @@ -0,0 +1,589 @@
> +/*
> + * Support for imx6 based Advantech DMS-BA16 Qseven module
> + *
> + * Copyright 2015 Timesys Corporation.
> + * Copyright 2015 General Electric Company
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
GPL/X11 dual licences are generally suggested for new dts files to
consider non-Linux users. You can grep "X11" in arch/arm/boot/dts to
find a plenty of examples.
> +
> +#include "imx6q.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + memory {
> + reg = <0x10000000 0x40000000>;
> + };
> +
> + clocks {
> + clk24m: clk24m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> + };
> +
> + backlight_lvds: backlight {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_display>;
> + compatible = "pwm-backlight";
> + pwms = <&pwm1 0 5000000>;
> + brightness-levels = < 0 1 2 3 4 5 6 7 8 9
> + 10 11 12 13 14 15 16 17 18 19
> + 20 21 22 23 24 25 26 27 28 29
> + 30 31 32 33 34 35 36 37 38 39
> + 40 41 42 43 44 45 46 47 48 49
> + 50 51 52 53 54 55 56 57 58 59
> + 60 61 62 63 64 65 66 67 68 69
> + 70 71 72 73 74 75 76 77 78 79
> + 80 81 82 83 84 85 86 87 88 89
> + 90 91 92 93 94 95 96 97 98 99
> + 100 101 102 103 104 105 106 107 108 109
> + 110 111 112 113 114 115 116 117 118 119
> + 120 121 122 123 124 125 126 127 128 129
> + 130 131 132 133 134 135 136 137 138 139
> + 140 141 142 143 144 145 146 147 148 149
> + 150 151 152 153 154 155 156 157 158 159
> + 160 161 162 163 164 165 166 167 168 169
> + 170 171 172 173 174 175 176 177 178 179
> + 180 181 182 183 184 185 186 187 188 189
> + 190 191 192 193 194 195 196 197 198 199
> + 200 201 202 203 204 205 206 207 208 209
> + 210 211 212 213 214 215 216 217 218 219
> + 220 221 222 223 224 225 226 227 228 229
> + 230 231 232 233 234 235 236 237 238 239
> + 240 241 242 243 244 245 246 247 248 249
> + 250 251 252 253 254 255>;
> + default-brightness-level = <255>;
> + enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
> + };
> +
> + reg_1p8v: regulator at 1 {
@unit-address should only present for nodes which have 'reg' property.
As we choose to put these regulators directly under root node, we would
probably want to name them like:
reg_xxx: regulator-xxx {
...
}
> + compatible = "regulator-fixed";
> + regulator-name = "1P8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + reg_3p3v: regulator at 2 {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + reg_lvds: regulator at 3 {
> + compatible = "regulator-fixed";
> + regulator-name = "lvds_ppen";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_usb_otg_vbus: regulator at 4 {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_otg_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + reg_usb_h1_vbus: regulator at 5 {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_h1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +};
> +
> +&audmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_audmux>;
> + status = "okay";
> +};
> +
> +&ecspi1 {
> + fsl,spi-num-chipselects = <1>;
> + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + status = "okay";
> +
> + flash: n25q032 at 0 {
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <20000000>;
> + reg = <0>;
Have a new line between properties and sub-nodes.
> + partitions {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition at 0 {
> + label = "U-Boot";
> + reg = <0x0 0xC0000>;
Please consistently use lowercase for hex values.
> + };
> + partition at C0000 {
> + label = "env";
> + reg = <0xC0000 0x10000>;
> + };
Have a new line between nodes.
> + partition at D0000 {
> + label = "spare";
> + reg = <0xD0000 0x130000>;
> + };
> + };
> + };
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-mode = "rgmii";
> + status = "okay";
> +};
> +
> +&hdmi {
> + ddc-i2c-bus = <&i2c2>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +};
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + status = "okay";
> +
> + pmic at 58 {
> + compatible = "dlg,da9063";
> + reg = <0x58>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> + interrupt-parent = <&gpio7>;
> + interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
> +
> + regulators {
> + vdd_bcore1: bcore1 {
> + regulator-min-microvolt = <1420000>;
> + regulator-max-microvolt = <1420000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bcore2: bcore2 {
> + regulator-min-microvolt = <1420000>;
> + regulator-max-microvolt = <1420000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bpro: bpro {
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bmem: bmem {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bio: bio {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bperi: bperi {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_ldo1: ldo1 {
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1860000>;
> + };
> +
> + vdd_ldo2: ldo2 {
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1860000>;
> + };
> +
> + vdd_ldo3: ldo3 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3440000>;
> + };
> +
> + vdd_ldo4: ldo4 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3440000>;
> + };
> +
> + vdd_ldo5: ldo5 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo6: ldo6 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo7: ldo7 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo8: ldo8 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo9: ldo9 {
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo10: ldo10 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo11: ldo11 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> + };
> + };
> +
> + rtc at 32 {
> + compatible = "epson,rx8010";
Is this compatible string documented somewhere?
> + reg = <0x32>;
> + interrupt-parent = <&gpio4>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +};
> +
> +&iomuxc {
Suggest to put the iomuxc node at the bottom of the dts to make the read
of this file a bit easier.
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog>;
> +
> + imx6q-ba16 {
With commit 5fcdf6a7ed95 (pinctrl: imx: Allow parsing DT without function
nodes) in place, we can get rid of this container node to save one level
of indentation.
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
> + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM CLK */
> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 /* SUS_S3_OUT */
> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
> + >;
The hog group should be used for very limited pins which do not have
clear owner device. In the most case, the pins should go to owner
device's pin group. Also, instead of using 0x80000000, a proper
pad configuration value should be used.
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
> + >;
> + };
> +
> + pinctrl_pmic: pmicgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
> + >;
> + };
Please try to sort these pinctrl nodes alphabetically, so that
searching and adding pinctrl entries can be easier.
Shawn
> +
> + pinctrl_usbhub: usbhubgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
> + >;
> + };
> +
> + pinctrl_pcie: pciegrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIe Reset */
> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* PCIe Wake */
> + >;
> + };
> +
> + pinctrl_display: dispgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* BLEN_OUT */
> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
> + >;
> + };
> +
> + pinctrl_usdhc4: usdhc4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
> + >;
> + };
> +
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
> + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
> + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
> + >;
> + };
> +
> + pinctrl_ecspi5: ecspi5rp-1 {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
> + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
> + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
> + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_pwm2: pwm2grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbotg: usbotggrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
> + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc3_reset: usdhc3grp-reset {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
> + >;
> + };
> +
> + pinctrl_audmux: audmux {
> + fsl,pins = <
> + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
> + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
> + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
> + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
> + >;
> + };
> +
> + pinctrl_enet: pinctrl_enet {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
> + >;
> + };
> + };
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "okay";
> +};
> +
> +&pwm2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm2>;
> + status = "okay";
> +};
> +
> +&sata {
> + status = "okay";
> +};
> +
> +&ssi1 {
> + fsl,mode = "i2s-master";
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + fsl,uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>;
> + status = "okay";
> +};
> +
> +&usbh1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbhub>;
> + vbus-supply = <®_usb_h1_vbus>;
> + reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +&usbotg {
> + vbus-supply = <®_usb_otg_vbus>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg>;
> + disable-over-current;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + keep-power-in-suspend;
> + enable-sdio-wakeup;
> + status = "okay";
> +};
> +
> +&usdhc3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
> + bus-width = <8>;
> + vmmc-supply = <&vdd_bperi>;
> + vqmmc-supply = <&vdd_bio>;
> + non-removable;
> + keep-power-in-suspend;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> +};
> --
> 2.6.3
>
>
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v5 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-12-22 11:40 ` Shawn Guo
0 siblings, 0 replies; 28+ messages in thread
From: Shawn Guo @ 2015-12-22 11:40 UTC (permalink / raw)
To: Akshay Bhat
Cc: mark.rutland, devicetree, linux, ijc+devicetree, robh+dt, kernel,
galak, justin.waters, linux-arm-kernel, l.stach
On Thu, Dec 03, 2015 at 04:10:32PM -0500, Akshay Bhat wrote:
> From: Justin Waters <justin.waters@timesys.com>
>
> Add support for Advantech BA-16 module based on iMX6D processor
>
> http://www2.advantech.com/products/medical_computing_system/dms-ba16/mod_64aa1566-169c-483d-97c8-c2c22c163fc3.aspx
> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
> ---
> arch/arm/boot/dts/imx6q-ba16.dtsi | 589 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 589 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
> new file mode 100644
> index 0000000..9510713
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
> @@ -0,0 +1,589 @@
> +/*
> + * Support for imx6 based Advantech DMS-BA16 Qseven module
> + *
> + * Copyright 2015 Timesys Corporation.
> + * Copyright 2015 General Electric Company
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
GPL/X11 dual licences are generally suggested for new dts files to
consider non-Linux users. You can grep "X11" in arch/arm/boot/dts to
find a plenty of examples.
> +
> +#include "imx6q.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + memory {
> + reg = <0x10000000 0x40000000>;
> + };
> +
> + clocks {
> + clk24m: clk24m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> + };
> +
> + backlight_lvds: backlight {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_display>;
> + compatible = "pwm-backlight";
> + pwms = <&pwm1 0 5000000>;
> + brightness-levels = < 0 1 2 3 4 5 6 7 8 9
> + 10 11 12 13 14 15 16 17 18 19
> + 20 21 22 23 24 25 26 27 28 29
> + 30 31 32 33 34 35 36 37 38 39
> + 40 41 42 43 44 45 46 47 48 49
> + 50 51 52 53 54 55 56 57 58 59
> + 60 61 62 63 64 65 66 67 68 69
> + 70 71 72 73 74 75 76 77 78 79
> + 80 81 82 83 84 85 86 87 88 89
> + 90 91 92 93 94 95 96 97 98 99
> + 100 101 102 103 104 105 106 107 108 109
> + 110 111 112 113 114 115 116 117 118 119
> + 120 121 122 123 124 125 126 127 128 129
> + 130 131 132 133 134 135 136 137 138 139
> + 140 141 142 143 144 145 146 147 148 149
> + 150 151 152 153 154 155 156 157 158 159
> + 160 161 162 163 164 165 166 167 168 169
> + 170 171 172 173 174 175 176 177 178 179
> + 180 181 182 183 184 185 186 187 188 189
> + 190 191 192 193 194 195 196 197 198 199
> + 200 201 202 203 204 205 206 207 208 209
> + 210 211 212 213 214 215 216 217 218 219
> + 220 221 222 223 224 225 226 227 228 229
> + 230 231 232 233 234 235 236 237 238 239
> + 240 241 242 243 244 245 246 247 248 249
> + 250 251 252 253 254 255>;
> + default-brightness-level = <255>;
> + enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
> + };
> +
> + reg_1p8v: regulator@1 {
@unit-address should only present for nodes which have 'reg' property.
As we choose to put these regulators directly under root node, we would
probably want to name them like:
reg_xxx: regulator-xxx {
...
}
> + compatible = "regulator-fixed";
> + regulator-name = "1P8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + reg_3p3v: regulator@2 {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + reg_lvds: regulator@3 {
> + compatible = "regulator-fixed";
> + regulator-name = "lvds_ppen";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_usb_otg_vbus: regulator@4 {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_otg_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + reg_usb_h1_vbus: regulator@5 {
> + compatible = "regulator-fixed";
> + regulator-name = "usb_h1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +};
> +
> +&audmux {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_audmux>;
> + status = "okay";
> +};
> +
> +&ecspi1 {
> + fsl,spi-num-chipselects = <1>;
> + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + status = "okay";
> +
> + flash: n25q032@0 {
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <20000000>;
> + reg = <0>;
Have a new line between properties and sub-nodes.
> + partitions {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "U-Boot";
> + reg = <0x0 0xC0000>;
Please consistently use lowercase for hex values.
> + };
> + partition@C0000 {
> + label = "env";
> + reg = <0xC0000 0x10000>;
> + };
Have a new line between nodes.
> + partition@D0000 {
> + label = "spare";
> + reg = <0xD0000 0x130000>;
> + };
> + };
> + };
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-mode = "rgmii";
> + status = "okay";
> +};
> +
> +&hdmi {
> + ddc-i2c-bus = <&i2c2>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +};
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + status = "okay";
> +
> + pmic@58 {
> + compatible = "dlg,da9063";
> + reg = <0x58>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> + interrupt-parent = <&gpio7>;
> + interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
> +
> + regulators {
> + vdd_bcore1: bcore1 {
> + regulator-min-microvolt = <1420000>;
> + regulator-max-microvolt = <1420000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bcore2: bcore2 {
> + regulator-min-microvolt = <1420000>;
> + regulator-max-microvolt = <1420000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bpro: bpro {
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bmem: bmem {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bio: bio {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_bperi: bperi {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_ldo1: ldo1 {
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1860000>;
> + };
> +
> + vdd_ldo2: ldo2 {
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1860000>;
> + };
> +
> + vdd_ldo3: ldo3 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3440000>;
> + };
> +
> + vdd_ldo4: ldo4 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3440000>;
> + };
> +
> + vdd_ldo5: ldo5 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo6: ldo6 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo7: ldo7 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo8: ldo8 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo9: ldo9 {
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo10: ldo10 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + };
> +
> + vdd_ldo11: ldo11 {
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <3600000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> + };
> + };
> +
> + rtc@32 {
> + compatible = "epson,rx8010";
Is this compatible string documented somewhere?
> + reg = <0x32>;
> + interrupt-parent = <&gpio4>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +};
> +
> +&iomuxc {
Suggest to put the iomuxc node at the bottom of the dts to make the read
of this file a bit easier.
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog>;
> +
> + imx6q-ba16 {
With commit 5fcdf6a7ed95 (pinctrl: imx: Allow parsing DT without function
nodes) in place, we can get rid of this container node to save one level
of indentation.
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
> + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM CLK */
> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 /* SUS_S3_OUT */
> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
> + >;
The hog group should be used for very limited pins which do not have
clear owner device. In the most case, the pins should go to owner
device's pin group. Also, instead of using 0x80000000, a proper
pad configuration value should be used.
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
> + >;
> + };
> +
> + pinctrl_pmic: pmicgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
> + >;
> + };
Please try to sort these pinctrl nodes alphabetically, so that
searching and adding pinctrl entries can be easier.
Shawn
> +
> + pinctrl_usbhub: usbhubgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
> + >;
> + };
> +
> + pinctrl_pcie: pciegrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIe Reset */
> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* PCIe Wake */
> + >;
> + };
> +
> + pinctrl_display: dispgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* BLEN_OUT */
> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
> + >;
> + };
> +
> + pinctrl_usdhc4: usdhc4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
> + >;
> + };
> +
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
> + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
> + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
> + >;
> + };
> +
> + pinctrl_ecspi5: ecspi5rp-1 {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
> + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
> + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
> + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_pwm2: pwm2grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbotg: usbotggrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
> + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc3_reset: usdhc3grp-reset {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
> + >;
> + };
> +
> + pinctrl_audmux: audmux {
> + fsl,pins = <
> + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
> + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
> + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
> + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
> + >;
> + };
> +
> + pinctrl_enet: pinctrl_enet {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
> + >;
> + };
> + };
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "okay";
> +};
> +
> +&pwm2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm2>;
> + status = "okay";
> +};
> +
> +&sata {
> + status = "okay";
> +};
> +
> +&ssi1 {
> + fsl,mode = "i2s-master";
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + fsl,uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>;
> + status = "okay";
> +};
> +
> +&usbh1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbhub>;
> + vbus-supply = <®_usb_h1_vbus>;
> + reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +&usbotg {
> + vbus-supply = <®_usb_otg_vbus>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg>;
> + disable-over-current;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + keep-power-in-suspend;
> + enable-sdio-wakeup;
> + status = "okay";
> +};
> +
> +&usdhc3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
> + bus-width = <8>;
> + vmmc-supply = <&vdd_bperi>;
> + vqmmc-supply = <&vdd_bio>;
> + non-removable;
> + keep-power-in-suspend;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> +};
> --
> 2.6.3
>
>
^ permalink raw reply [flat|nested] 28+ messages in thread* [PATCH v5 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
2015-12-22 11:40 ` Shawn Guo
@ 2015-12-22 22:42 ` Akshay Bhat
-1 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-22 22:42 UTC (permalink / raw)
To: linux-arm-kernel
Shawn, thanks for the feedback. I have addressed all the comments with
the exception of removing imx6q-ba16 container node in iomux. I get
errors if I do so, details in-line.
On 12/22/2015 06:40 AM, Shawn Guo wrote:
> On Thu, Dec 03, 2015 at 04:10:32PM -0500, Akshay Bhat wrote:
>> From: Justin Waters <justin.waters@timesys.com>
>>
>> Add support for Advantech BA-16 module based on iMX6D processor
>>
>> http://www2.advantech.com/products/medical_computing_system/dms-ba16/mod_64aa1566-169c-483d-97c8-c2c22c163fc3.aspx
>> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
>> ---
>> arch/arm/boot/dts/imx6q-ba16.dtsi | 589 ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 589 insertions(+)
>> create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
>>
>> diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
>> new file mode 100644
>> index 0000000..9510713
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
>> @@ -0,0 +1,589 @@
>> +/*
>> + * Support for imx6 based Advantech DMS-BA16 Qseven module
>> + *
>> + * Copyright 2015 Timesys Corporation.
>> + * Copyright 2015 General Electric Company
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>
> GPL/X11 dual licences are generally suggested for new dts files to
> consider non-Linux users. You can grep "X11" in arch/arm/boot/dts to
> find a plenty of examples.
>
Will fix it.
>> +
>> +#include "imx6q.dtsi"
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + memory {
>> + reg = <0x10000000 0x40000000>;
>> + };
>> +
>> + clocks {
>> + clk24m: clk24m {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <24000000>;
>> + };
>> + };
>> +
>> + backlight_lvds: backlight {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_display>;
>> + compatible = "pwm-backlight";
>> + pwms = <&pwm1 0 5000000>;
>> + brightness-levels = < 0 1 2 3 4 5 6 7 8 9
>> + 10 11 12 13 14 15 16 17 18 19
>> + 20 21 22 23 24 25 26 27 28 29
>> + 30 31 32 33 34 35 36 37 38 39
>> + 40 41 42 43 44 45 46 47 48 49
>> + 50 51 52 53 54 55 56 57 58 59
>> + 60 61 62 63 64 65 66 67 68 69
>> + 70 71 72 73 74 75 76 77 78 79
>> + 80 81 82 83 84 85 86 87 88 89
>> + 90 91 92 93 94 95 96 97 98 99
>> + 100 101 102 103 104 105 106 107 108 109
>> + 110 111 112 113 114 115 116 117 118 119
>> + 120 121 122 123 124 125 126 127 128 129
>> + 130 131 132 133 134 135 136 137 138 139
>> + 140 141 142 143 144 145 146 147 148 149
>> + 150 151 152 153 154 155 156 157 158 159
>> + 160 161 162 163 164 165 166 167 168 169
>> + 170 171 172 173 174 175 176 177 178 179
>> + 180 181 182 183 184 185 186 187 188 189
>> + 190 191 192 193 194 195 196 197 198 199
>> + 200 201 202 203 204 205 206 207 208 209
>> + 210 211 212 213 214 215 216 217 218 219
>> + 220 221 222 223 224 225 226 227 228 229
>> + 230 231 232 233 234 235 236 237 238 239
>> + 240 241 242 243 244 245 246 247 248 249
>> + 250 251 252 253 254 255>;
>> + default-brightness-level = <255>;
>> + enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
>> + };
>> +
>> + reg_1p8v: regulator at 1 {
>
> @unit-address should only present for nodes which have 'reg' property.
> As we choose to put these regulators directly under root node, we would
> probably want to name them like:
>
> reg_xxx: regulator-xxx {
> ...
> }
>
Will fix it
>
>> + compatible = "regulator-fixed";
>> + regulator-name = "1P8V";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + };
>> +
>> + reg_3p3v: regulator at 2 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "3P3V";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + };
>> +
>> + reg_lvds: regulator at 3 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "lvds_ppen";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-boot-on;
>> + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + };
>> +
>> + reg_usb_otg_vbus: regulator at 4 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "usb_otg_vbus";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + };
>> +
>> + reg_usb_h1_vbus: regulator at 5 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "usb_h1_vbus";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + };
>> +};
>> +
>> +&audmux {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_audmux>;
>> + status = "okay";
>> +};
>> +
>> +&ecspi1 {
>> + fsl,spi-num-chipselects = <1>;
>> + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_ecspi1>;
>> + status = "okay";
>> +
>> + flash: n25q032 at 0 {
>> + compatible = "jedec,spi-nor";
>> + spi-max-frequency = <20000000>;
>> + reg = <0>;
>
> Have a new line between properties and sub-nodes.
>
Will fix it
>> + partitions {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + partition at 0 {
>> + label = "U-Boot";
>> + reg = <0x0 0xC0000>;
>
> Please consistently use lowercase for hex values.
>
Will fix it
>> + };
>> + partition at C0000 {
>> + label = "env";
>> + reg = <0xC0000 0x10000>;
>> + };
>
> Have a new line between nodes.
>
Will fix it
>> + partition at D0000 {
>> + label = "spare";
>> + reg = <0xD0000 0x130000>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&fec {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_enet>;
>> + phy-mode = "rgmii";
>> + status = "okay";
>> +};
>> +
>> +&hdmi {
>> + ddc-i2c-bus = <&i2c2>;
>> + status = "okay";
>> +};
>> +
>> +&i2c1 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c1>;
>> + status = "okay";
>> +};
>> +
>> +&i2c2 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c2>;
>> + status = "okay";
>> +};
>> +
>> +&i2c3 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c3>;
>> + status = "okay";
>> +
>> + pmic at 58 {
>> + compatible = "dlg,da9063";
>> + reg = <0x58>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pmic>;
>> + interrupt-parent = <&gpio7>;
>> + interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
>> +
>> + regulators {
>> + vdd_bcore1: bcore1 {
>> + regulator-min-microvolt = <1420000>;
>> + regulator-max-microvolt = <1420000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bcore2: bcore2 {
>> + regulator-min-microvolt = <1420000>;
>> + regulator-max-microvolt = <1420000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bpro: bpro {
>> + regulator-min-microvolt = <1500000>;
>> + regulator-max-microvolt = <1500000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bmem: bmem {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bio: bio {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bperi: bperi {
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_ldo1: ldo1 {
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <1860000>;
>> + };
>> +
>> + vdd_ldo2: ldo2 {
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <1860000>;
>> + };
>> +
>> + vdd_ldo3: ldo3 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3440000>;
>> + };
>> +
>> + vdd_ldo4: ldo4 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3440000>;
>> + };
>> +
>> + vdd_ldo5: ldo5 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo6: ldo6 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo7: ldo7 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo8: ldo8 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo9: ldo9 {
>> + regulator-min-microvolt = <950000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo10: ldo10 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo11: ldo11 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> + };
>> + };
>> +
>> + rtc at 32 {
>> + compatible = "epson,rx8010";
>
> Is this compatible string documented somewhere?
>
Will submit a separate patch to update
devicetree/bindings/i2c/trivial-devices.txt
>> + reg = <0x32>;
>> + interrupt-parent = <&gpio4>;
>> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +};
>> +
>> +&iomuxc {
>
> Suggest to put the iomuxc node at the bottom of the dts to make the read
> of this file a bit easier.
>
Will fix it
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_hog>;
>> +
>> + imx6q-ba16 {
>
> With commit 5fcdf6a7ed95 (pinctrl: imx: Allow parsing DT without function
> nodes) in place, we can get rid of this container node to save one level
> of indentation.
>
If i remove the imx6q-ba16 container node, then I get multiple errors
during boot.
[ 2.043594] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node ecspi1grp
.....
[ 2.467403] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usbotggrp
[ 2.482394] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usbhubgrp
.....
[ 2.640509] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usdhc2grp
[ 2.640889] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usdhc2grp
[ 2.640986] sdhci-esdhc-imx: probe of 2194000.usdhc failed with error -22
[ 2.641048] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usdhc3grp
[ 2.641301] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usdhc3grp
[ 2.641385] sdhci-esdhc-imx: probe of 2198000.usdhc failed with error -22
[ 2.641446] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usdhc4grp
[ 2.641688] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usdhc4grp
[ 2.641770] sdhci-esdhc-imx: probe of 219c000.usdhc failed with error -22
The change I did was:
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_audmux: audmux {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
>;
};
pinctrl_display: dispgrp {
fsl,pins = <
/* BLEN_OUT */
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
/* LVDS_PPEN_OUT */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
/* SPI1 CS */
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
>;
};
............
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
>;
};
};
>> + pinctrl_hog: hoggrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
>> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
>> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
>> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
>> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
>> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
>> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
>> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
>> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
>> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
>> + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM CLK */
>> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 /* SUS_S3_OUT */
>> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
>> + >;
>
> The hog group should be used for very limited pins which do not have
> clear owner device. In the most case, the pins should go to owner
> device's pin group. Also, instead of using 0x80000000, a proper
> pad configuration value should be used.
>
I will remove the CAM_PWDN/RST/CLK since it is not yet supported. I will
move RTC_INT into its own group. However the GPIO's are generic and does
not have any owner. Same goes for SUS_S3_OUT since it is connected to a
FPGA.
>> + };
>> +
>> + pinctrl_wdog: wdoggrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
>> + >;
>> + };
>> +
>> + pinctrl_pmic: pmicgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
>> + >;
>> + };
>
> Please try to sort these pinctrl nodes alphabetically, so that
> searching and adding pinctrl entries can be easier.
>
> Shawn
>
Will fix it
>> +
>> + pinctrl_usbhub: usbhubgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
>> + >;
>> + };
>> +
>> + pinctrl_pcie: pciegrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIe Reset */
>> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* PCIe Wake */
>> + >;
>> + };
>> +
>> + pinctrl_display: dispgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* BLEN_OUT */
>> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
>> + >;
>> + };
>> +
>> + pinctrl_usdhc4: usdhc4grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
>> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
>> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
>> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
>> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
>> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
>> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
>> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
>> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
>> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
>> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
>> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
>> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
>> + >;
>> + };
>> +
>> + pinctrl_ecspi1: ecspi1grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
>> + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
>> + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
>> + >;
>> + };
>> +
>> + pinctrl_ecspi5: ecspi5rp-1 {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
>> + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
>> + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
>> + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
>> + >;
>> + };
>> +
>> + pinctrl_pwm1: pwm1grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_pwm2: pwm2grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usbotg: usbotggrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_i2c1: i2c1grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
>> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>> + >;
>> + };
>> +
>> + pinctrl_i2c2: i2c2grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
>> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>> + >;
>> + };
>> +
>> + pinctrl_i2c3: i2c3grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
>> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>> + >;
>> + };
>> +
>> + pinctrl_uart3: uart3grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
>> + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
>> + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_uart4: uart4grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
>> + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
>> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
>> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
>> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
>> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
>> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3: usdhc3grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
>> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
>> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
>> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
>> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
>> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
>> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
>> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
>> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3_reset: usdhc3grp-reset {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
>> + >;
>> + };
>> +
>> + pinctrl_audmux: audmux {
>> + fsl,pins = <
>> + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
>> + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
>> + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
>> + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
>> + >;
>> + };
>> +
>> + pinctrl_enet: pinctrl_enet {
>> + fsl,pins = <
>> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
>> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
>> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
>> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
>> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
>> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
>> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
>> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
>> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
>> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
>> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
>> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
>> + >;
>> + };
>> + };
>> +};
>> +
>> +&pcie {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pcie>;
>> + reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
>> + status = "okay";
>> +};
>> +
>> +
>> +&pwm1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pwm1>;
>> + status = "okay";
>> +};
>> +
>> +&pwm2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pwm2>;
>> + status = "okay";
>> +};
>> +
>> +&sata {
>> + status = "okay";
>> +};
>> +
>> +&ssi1 {
>> + fsl,mode = "i2s-master";
>> + status = "okay";
>> +};
>> +
>> +&uart3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart3>;
>> + fsl,uart-has-rtscts;
>> + status = "okay";
>> +};
>> +
>> +&uart4 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart4>;
>> + status = "okay";
>> +};
>> +
>> +&usbh1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usbhub>;
>> + vbus-supply = <®_usb_h1_vbus>;
>> + reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
>> + status = "okay";
>> +};
>> +
>> +&usbotg {
>> + vbus-supply = <®_usb_otg_vbus>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usbotg>;
>> + disable-over-current;
>> + status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc2>;
>> + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
>> + no-1-8-v;
>> + keep-power-in-suspend;
>> + enable-sdio-wakeup;
>> + status = "okay";
>> +};
>> +
>> +&usdhc3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
>> + bus-width = <8>;
>> + vmmc-supply = <&vdd_bperi>;
>> + vqmmc-supply = <&vdd_bio>;
>> + non-removable;
>> + keep-power-in-suspend;
>> + status = "okay";
>> +};
>> +
>> +&wdog1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_wdog>;
>> +};
>> --
>> 2.6.3
>>
>>
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v5 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-12-22 22:42 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-22 22:42 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ
Shawn, thanks for the feedback. I have addressed all the comments with
the exception of removing imx6q-ba16 container node in iomux. I get
errors if I do so, details in-line.
On 12/22/2015 06:40 AM, Shawn Guo wrote:
> On Thu, Dec 03, 2015 at 04:10:32PM -0500, Akshay Bhat wrote:
>> From: Justin Waters <justin.waters-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
>>
>> Add support for Advantech BA-16 module based on iMX6D processor
>>
>> http://www2.advantech.com/products/medical_computing_system/dms-ba16/mod_64aa1566-169c-483d-97c8-c2c22c163fc3.aspx
>> Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
>> ---
>> arch/arm/boot/dts/imx6q-ba16.dtsi | 589 ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 589 insertions(+)
>> create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
>>
>> diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
>> new file mode 100644
>> index 0000000..9510713
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
>> @@ -0,0 +1,589 @@
>> +/*
>> + * Support for imx6 based Advantech DMS-BA16 Qseven module
>> + *
>> + * Copyright 2015 Timesys Corporation.
>> + * Copyright 2015 General Electric Company
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>
> GPL/X11 dual licences are generally suggested for new dts files to
> consider non-Linux users. You can grep "X11" in arch/arm/boot/dts to
> find a plenty of examples.
>
Will fix it.
>> +
>> +#include "imx6q.dtsi"
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + memory {
>> + reg = <0x10000000 0x40000000>;
>> + };
>> +
>> + clocks {
>> + clk24m: clk24m {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <24000000>;
>> + };
>> + };
>> +
>> + backlight_lvds: backlight {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_display>;
>> + compatible = "pwm-backlight";
>> + pwms = <&pwm1 0 5000000>;
>> + brightness-levels = < 0 1 2 3 4 5 6 7 8 9
>> + 10 11 12 13 14 15 16 17 18 19
>> + 20 21 22 23 24 25 26 27 28 29
>> + 30 31 32 33 34 35 36 37 38 39
>> + 40 41 42 43 44 45 46 47 48 49
>> + 50 51 52 53 54 55 56 57 58 59
>> + 60 61 62 63 64 65 66 67 68 69
>> + 70 71 72 73 74 75 76 77 78 79
>> + 80 81 82 83 84 85 86 87 88 89
>> + 90 91 92 93 94 95 96 97 98 99
>> + 100 101 102 103 104 105 106 107 108 109
>> + 110 111 112 113 114 115 116 117 118 119
>> + 120 121 122 123 124 125 126 127 128 129
>> + 130 131 132 133 134 135 136 137 138 139
>> + 140 141 142 143 144 145 146 147 148 149
>> + 150 151 152 153 154 155 156 157 158 159
>> + 160 161 162 163 164 165 166 167 168 169
>> + 170 171 172 173 174 175 176 177 178 179
>> + 180 181 182 183 184 185 186 187 188 189
>> + 190 191 192 193 194 195 196 197 198 199
>> + 200 201 202 203 204 205 206 207 208 209
>> + 210 211 212 213 214 215 216 217 218 219
>> + 220 221 222 223 224 225 226 227 228 229
>> + 230 231 232 233 234 235 236 237 238 239
>> + 240 241 242 243 244 245 246 247 248 249
>> + 250 251 252 253 254 255>;
>> + default-brightness-level = <255>;
>> + enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
>> + };
>> +
>> + reg_1p8v: regulator@1 {
>
> @unit-address should only present for nodes which have 'reg' property.
> As we choose to put these regulators directly under root node, we would
> probably want to name them like:
>
> reg_xxx: regulator-xxx {
> ...
> }
>
Will fix it
>
>> + compatible = "regulator-fixed";
>> + regulator-name = "1P8V";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + };
>> +
>> + reg_3p3v: regulator@2 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "3P3V";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + };
>> +
>> + reg_lvds: regulator@3 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "lvds_ppen";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-boot-on;
>> + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + };
>> +
>> + reg_usb_otg_vbus: regulator@4 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "usb_otg_vbus";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + };
>> +
>> + reg_usb_h1_vbus: regulator@5 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "usb_h1_vbus";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + };
>> +};
>> +
>> +&audmux {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_audmux>;
>> + status = "okay";
>> +};
>> +
>> +&ecspi1 {
>> + fsl,spi-num-chipselects = <1>;
>> + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_ecspi1>;
>> + status = "okay";
>> +
>> + flash: n25q032@0 {
>> + compatible = "jedec,spi-nor";
>> + spi-max-frequency = <20000000>;
>> + reg = <0>;
>
> Have a new line between properties and sub-nodes.
>
Will fix it
>> + partitions {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + partition@0 {
>> + label = "U-Boot";
>> + reg = <0x0 0xC0000>;
>
> Please consistently use lowercase for hex values.
>
Will fix it
>> + };
>> + partition@C0000 {
>> + label = "env";
>> + reg = <0xC0000 0x10000>;
>> + };
>
> Have a new line between nodes.
>
Will fix it
>> + partition@D0000 {
>> + label = "spare";
>> + reg = <0xD0000 0x130000>;
>> + };
>> + };
>> + };
>> +};
>> +
>> +&fec {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_enet>;
>> + phy-mode = "rgmii";
>> + status = "okay";
>> +};
>> +
>> +&hdmi {
>> + ddc-i2c-bus = <&i2c2>;
>> + status = "okay";
>> +};
>> +
>> +&i2c1 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c1>;
>> + status = "okay";
>> +};
>> +
>> +&i2c2 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c2>;
>> + status = "okay";
>> +};
>> +
>> +&i2c3 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c3>;
>> + status = "okay";
>> +
>> + pmic@58 {
>> + compatible = "dlg,da9063";
>> + reg = <0x58>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pmic>;
>> + interrupt-parent = <&gpio7>;
>> + interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
>> +
>> + regulators {
>> + vdd_bcore1: bcore1 {
>> + regulator-min-microvolt = <1420000>;
>> + regulator-max-microvolt = <1420000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bcore2: bcore2 {
>> + regulator-min-microvolt = <1420000>;
>> + regulator-max-microvolt = <1420000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bpro: bpro {
>> + regulator-min-microvolt = <1500000>;
>> + regulator-max-microvolt = <1500000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bmem: bmem {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bio: bio {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_bperi: bperi {
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_ldo1: ldo1 {
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <1860000>;
>> + };
>> +
>> + vdd_ldo2: ldo2 {
>> + regulator-min-microvolt = <600000>;
>> + regulator-max-microvolt = <1860000>;
>> + };
>> +
>> + vdd_ldo3: ldo3 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3440000>;
>> + };
>> +
>> + vdd_ldo4: ldo4 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3440000>;
>> + };
>> +
>> + vdd_ldo5: ldo5 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo6: ldo6 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo7: ldo7 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo8: ldo8 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo9: ldo9 {
>> + regulator-min-microvolt = <950000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo10: ldo10 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + };
>> +
>> + vdd_ldo11: ldo11 {
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <3600000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> + };
>> + };
>> +
>> + rtc@32 {
>> + compatible = "epson,rx8010";
>
> Is this compatible string documented somewhere?
>
Will submit a separate patch to update
devicetree/bindings/i2c/trivial-devices.txt
>> + reg = <0x32>;
>> + interrupt-parent = <&gpio4>;
>> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +};
>> +
>> +&iomuxc {
>
> Suggest to put the iomuxc node at the bottom of the dts to make the read
> of this file a bit easier.
>
Will fix it
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_hog>;
>> +
>> + imx6q-ba16 {
>
> With commit 5fcdf6a7ed95 (pinctrl: imx: Allow parsing DT without function
> nodes) in place, we can get rid of this container node to save one level
> of indentation.
>
If i remove the imx6q-ba16 container node, then I get multiple errors
during boot.
[ 2.043594] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node ecspi1grp
.....
[ 2.467403] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usbotggrp
[ 2.482394] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usbhubgrp
.....
[ 2.640509] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usdhc2grp
[ 2.640889] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usdhc2grp
[ 2.640986] sdhci-esdhc-imx: probe of 2194000.usdhc failed with error -22
[ 2.641048] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usdhc3grp
[ 2.641301] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usdhc3grp
[ 2.641385] sdhci-esdhc-imx: probe of 2198000.usdhc failed with error -22
[ 2.641446] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usdhc4grp
[ 2.641688] imx6q-pinctrl 20e0000.iomuxc: unable to find group for
node usdhc4grp
[ 2.641770] sdhci-esdhc-imx: probe of 219c000.usdhc failed with error -22
The change I did was:
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_audmux: audmux {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
>;
};
pinctrl_display: dispgrp {
fsl,pins = <
/* BLEN_OUT */
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
/* LVDS_PPEN_OUT */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
/* SPI1 CS */
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
>;
};
............
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
>;
};
};
>> + pinctrl_hog: hoggrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */
>> + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */
>> + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */
>> + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */
>> + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */
>> + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */
>> + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */
>> + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */
>> + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */
>> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */
>> + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM CLK */
>> + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000 /* SUS_S3_OUT */
>> + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */
>> + >;
>
> The hog group should be used for very limited pins which do not have
> clear owner device. In the most case, the pins should go to owner
> device's pin group. Also, instead of using 0x80000000, a proper
> pad configuration value should be used.
>
I will remove the CAM_PWDN/RST/CLK since it is not yet supported. I will
move RTC_INT into its own group. However the GPIO's are generic and does
not have any owner. Same goes for SUS_S3_OUT since it is connected to a
FPGA.
>> + };
>> +
>> + pinctrl_wdog: wdoggrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */
>> + >;
>> + };
>> +
>> + pinctrl_pmic: pmicgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */
>> + >;
>> + };
>
> Please try to sort these pinctrl nodes alphabetically, so that
> searching and adding pinctrl entries can be easier.
>
> Shawn
>
Will fix it
>> +
>> + pinctrl_usbhub: usbhubgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */
>> + >;
>> + };
>> +
>> + pinctrl_pcie: pciegrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIe Reset */
>> + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* PCIe Wake */
>> + >;
>> + };
>> +
>> + pinctrl_display: dispgrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* BLEN_OUT */
>> + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */
>> + >;
>> + };
>> +
>> + pinctrl_usdhc4: usdhc4grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
>> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
>> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
>> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
>> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
>> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
>> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
>> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
>> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
>> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>> + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */
>> + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */
>> + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */
>> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */
>> + >;
>> + };
>> +
>> + pinctrl_ecspi1: ecspi1grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
>> + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
>> + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>> + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */
>> + >;
>> + };
>> +
>> + pinctrl_ecspi5: ecspi5rp-1 {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
>> + MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x80000000
>> + MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x80000000
>> + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
>> + >;
>> + };
>> +
>> + pinctrl_pwm1: pwm1grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_pwm2: pwm2grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usbotg: usbotggrp {
>> + fsl,pins = <
>> + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_i2c1: i2c1grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
>> + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>> + >;
>> + };
>> +
>> + pinctrl_i2c2: i2c2grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
>> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>> + >;
>> + };
>> +
>> + pinctrl_i2c3: i2c3grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
>> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>> + >;
>> + };
>> +
>> + pinctrl_uart3: uart3grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
>> + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
>> + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_uart4: uart4grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
>> + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
>> + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
>> + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
>> + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
>> + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
>> + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3: usdhc3grp {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
>> + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
>> + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
>> + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
>> + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
>> + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>> + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
>> + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
>> + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
>> + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3_reset: usdhc3grp-reset {
>> + fsl,pins = <
>> + MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9
>> + >;
>> + };
>> +
>> + pinctrl_audmux: audmux {
>> + fsl,pins = <
>> + MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
>> + MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
>> + MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
>> + MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
>> + >;
>> + };
>> +
>> + pinctrl_enet: pinctrl_enet {
>> + fsl,pins = <
>> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
>> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
>> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
>> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
>> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
>> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
>> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
>> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
>> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
>> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
>> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
>> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>> + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */
>> + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */
>> + >;
>> + };
>> + };
>> +};
>> +
>> +&pcie {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pcie>;
>> + reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
>> + status = "okay";
>> +};
>> +
>> +
>> +&pwm1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pwm1>;
>> + status = "okay";
>> +};
>> +
>> +&pwm2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pwm2>;
>> + status = "okay";
>> +};
>> +
>> +&sata {
>> + status = "okay";
>> +};
>> +
>> +&ssi1 {
>> + fsl,mode = "i2s-master";
>> + status = "okay";
>> +};
>> +
>> +&uart3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart3>;
>> + fsl,uart-has-rtscts;
>> + status = "okay";
>> +};
>> +
>> +&uart4 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart4>;
>> + status = "okay";
>> +};
>> +
>> +&usbh1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usbhub>;
>> + vbus-supply = <®_usb_h1_vbus>;
>> + reset-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
>> + status = "okay";
>> +};
>> +
>> +&usbotg {
>> + vbus-supply = <®_usb_otg_vbus>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usbotg>;
>> + disable-over-current;
>> + status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc2>;
>> + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
>> + no-1-8-v;
>> + keep-power-in-suspend;
>> + enable-sdio-wakeup;
>> + status = "okay";
>> +};
>> +
>> +&usdhc3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>;
>> + bus-width = <8>;
>> + vmmc-supply = <&vdd_bperi>;
>> + vqmmc-supply = <&vdd_bio>;
>> + non-removable;
>> + keep-power-in-suspend;
>> + status = "okay";
>> +};
>> +
>> +&wdog1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_wdog>;
>> +};
>> --
>> 2.6.3
>>
>>
--
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^ permalink raw reply [flat|nested] 28+ messages in thread* [PATCH v5 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-12-23 2:31 ` Shawn Guo
0 siblings, 0 replies; 28+ messages in thread
From: Shawn Guo @ 2015-12-23 2:31 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Dec 22, 2015 at 05:42:01PM -0500, Akshay Bhat wrote:
> >>+&iomuxc {
> >
> >Suggest to put the iomuxc node at the bottom of the dts to make the read
> >of this file a bit easier.
> >
> Will fix it
>
> >>+ pinctrl-names = "default";
> >>+ pinctrl-0 = <&pinctrl_hog>;
> >>+
> >>+ imx6q-ba16 {
> >
> >With commit 5fcdf6a7ed95 (pinctrl: imx: Allow parsing DT without function
> >nodes) in place, we can get rid of this container node to save one level
> >of indentation.
> >
>
> If i remove the imx6q-ba16 container node, then I get multiple
> errors during boot.
>
> [ 2.043594] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node ecspi1grp
> .....
> [ 2.467403] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usbotggrp
> [ 2.482394] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usbhubgrp
> .....
> [ 2.640509] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usdhc2grp
> [ 2.640889] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usdhc2grp
> [ 2.640986] sdhci-esdhc-imx: probe of 2194000.usdhc failed with error -22
> [ 2.641048] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usdhc3grp
> [ 2.641301] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usdhc3grp
> [ 2.641385] sdhci-esdhc-imx: probe of 2198000.usdhc failed with error -22
> [ 2.641446] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usdhc4grp
> [ 2.641688] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usdhc4grp
> [ 2.641770] sdhci-esdhc-imx: probe of 219c000.usdhc failed with error -22
Sorry. I just found that to get this work on imx6q board we need to
clean up the ipu2/ipu2grp-1 group from imx6q.dtsi. I just send a patch
doing that with you on copy. Let me know if it works for you with that
change.
Shawn
>
>
> The change I did was:
>
> &iomuxc {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_hog>;
>
> pinctrl_audmux: audmux {
> fsl,pins = <
> MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
> MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
> MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
> MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
> >;
> };
>
> pinctrl_display: dispgrp {
> fsl,pins = <
> /* BLEN_OUT */
> MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
> /* LVDS_PPEN_OUT */
> MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
> >;
> };
>
> pinctrl_ecspi1: ecspi1grp {
> fsl,pins = <
> MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
> MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
> MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
> /* SPI1 CS */
> MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
> >;
> };
>
> ............
>
> pinctrl_wdog: wdoggrp {
> fsl,pins = <
> MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
> >;
> };
> };
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v5 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-12-23 2:31 ` Shawn Guo
0 siblings, 0 replies; 28+ messages in thread
From: Shawn Guo @ 2015-12-23 2:31 UTC (permalink / raw)
To: Akshay Bhat
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ
On Tue, Dec 22, 2015 at 05:42:01PM -0500, Akshay Bhat wrote:
> >>+&iomuxc {
> >
> >Suggest to put the iomuxc node at the bottom of the dts to make the read
> >of this file a bit easier.
> >
> Will fix it
>
> >>+ pinctrl-names = "default";
> >>+ pinctrl-0 = <&pinctrl_hog>;
> >>+
> >>+ imx6q-ba16 {
> >
> >With commit 5fcdf6a7ed95 (pinctrl: imx: Allow parsing DT without function
> >nodes) in place, we can get rid of this container node to save one level
> >of indentation.
> >
>
> If i remove the imx6q-ba16 container node, then I get multiple
> errors during boot.
>
> [ 2.043594] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node ecspi1grp
> .....
> [ 2.467403] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usbotggrp
> [ 2.482394] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usbhubgrp
> .....
> [ 2.640509] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usdhc2grp
> [ 2.640889] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usdhc2grp
> [ 2.640986] sdhci-esdhc-imx: probe of 2194000.usdhc failed with error -22
> [ 2.641048] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usdhc3grp
> [ 2.641301] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usdhc3grp
> [ 2.641385] sdhci-esdhc-imx: probe of 2198000.usdhc failed with error -22
> [ 2.641446] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usdhc4grp
> [ 2.641688] imx6q-pinctrl 20e0000.iomuxc: unable to find group
> for node usdhc4grp
> [ 2.641770] sdhci-esdhc-imx: probe of 219c000.usdhc failed with error -22
Sorry. I just found that to get this work on imx6q board we need to
clean up the ipu2/ipu2grp-1 group from imx6q.dtsi. I just send a patch
doing that with you on copy. Let me know if it works for you with that
change.
Shawn
>
>
> The change I did was:
>
> &iomuxc {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_hog>;
>
> pinctrl_audmux: audmux {
> fsl,pins = <
> MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
> MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
> MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
> MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
> >;
> };
>
> pinctrl_display: dispgrp {
> fsl,pins = <
> /* BLEN_OUT */
> MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
> /* LVDS_PPEN_OUT */
> MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
> >;
> };
>
> pinctrl_ecspi1: ecspi1grp {
> fsl,pins = <
> MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
> MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
> MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
> /* SPI1 CS */
> MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
> >;
> };
>
> ............
>
> pinctrl_wdog: wdoggrp {
> fsl,pins = <
> MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
> >;
> };
> };
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 28+ messages in thread* [PATCH v5 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
2015-12-23 2:31 ` Shawn Guo
@ 2015-12-23 22:12 ` Akshay Bhat
-1 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-23 22:12 UTC (permalink / raw)
To: linux-arm-kernel
On 12/22/2015 09:31 PM, Shawn Guo wrote:
> On Tue, Dec 22, 2015 at 05:42:01PM -0500, Akshay Bhat wrote:
>>>> +&iomuxc {
>>>
>>> Suggest to put the iomuxc node at the bottom of the dts to make the read
>>> of this file a bit easier.
>>>
>> Will fix it
>>
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&pinctrl_hog>;
>>>> +
>>>> + imx6q-ba16 {
>>>
>>> With commit 5fcdf6a7ed95 (pinctrl: imx: Allow parsing DT without function
>>> nodes) in place, we can get rid of this container node to save one level
>>> of indentation.
>>>
>>
>> If i remove the imx6q-ba16 container node, then I get multiple
>> errors during boot.
>>
>> [ 2.043594] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node ecspi1grp
>> .....
>> [ 2.467403] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usbotggrp
>> [ 2.482394] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usbhubgrp
>> .....
>> [ 2.640509] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usdhc2grp
>> [ 2.640889] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usdhc2grp
>> [ 2.640986] sdhci-esdhc-imx: probe of 2194000.usdhc failed with error -22
>> [ 2.641048] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usdhc3grp
>> [ 2.641301] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usdhc3grp
>> [ 2.641385] sdhci-esdhc-imx: probe of 2198000.usdhc failed with error -22
>> [ 2.641446] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usdhc4grp
>> [ 2.641688] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usdhc4grp
>> [ 2.641770] sdhci-esdhc-imx: probe of 219c000.usdhc failed with error -22
>
> Sorry. I just found that to get this work on imx6q board we need to
> clean up the ipu2/ipu2grp-1 group from imx6q.dtsi. I just send a patch
> doing that with you on copy. Let me know if it works for you with that
> change.
>
> Shawn
>
Thanks Shawn, I applied the patch you sent and it fixed the above issue.
Also I have addressed all the comments and re-submitted the patches.
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/396131.html
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v5 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-12-23 22:12 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-23 22:12 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ
On 12/22/2015 09:31 PM, Shawn Guo wrote:
> On Tue, Dec 22, 2015 at 05:42:01PM -0500, Akshay Bhat wrote:
>>>> +&iomuxc {
>>>
>>> Suggest to put the iomuxc node at the bottom of the dts to make the read
>>> of this file a bit easier.
>>>
>> Will fix it
>>
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&pinctrl_hog>;
>>>> +
>>>> + imx6q-ba16 {
>>>
>>> With commit 5fcdf6a7ed95 (pinctrl: imx: Allow parsing DT without function
>>> nodes) in place, we can get rid of this container node to save one level
>>> of indentation.
>>>
>>
>> If i remove the imx6q-ba16 container node, then I get multiple
>> errors during boot.
>>
>> [ 2.043594] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node ecspi1grp
>> .....
>> [ 2.467403] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usbotggrp
>> [ 2.482394] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usbhubgrp
>> .....
>> [ 2.640509] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usdhc2grp
>> [ 2.640889] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usdhc2grp
>> [ 2.640986] sdhci-esdhc-imx: probe of 2194000.usdhc failed with error -22
>> [ 2.641048] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usdhc3grp
>> [ 2.641301] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usdhc3grp
>> [ 2.641385] sdhci-esdhc-imx: probe of 2198000.usdhc failed with error -22
>> [ 2.641446] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usdhc4grp
>> [ 2.641688] imx6q-pinctrl 20e0000.iomuxc: unable to find group
>> for node usdhc4grp
>> [ 2.641770] sdhci-esdhc-imx: probe of 219c000.usdhc failed with error -22
>
> Sorry. I just found that to get this work on imx6q board we need to
> clean up the ipu2/ipu2grp-1 group from imx6q.dtsi. I just send a patch
> doing that with you on copy. Let me know if it works for you with that
> change.
>
> Shawn
>
Thanks Shawn, I applied the patch you sent and it fixed the above issue.
Also I have addressed all the comments and re-submitted the patches.
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/396131.html
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v5 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
2015-12-22 11:40 ` Shawn Guo
@ 2015-12-23 22:22 ` Akshay Bhat
-1 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-23 22:22 UTC (permalink / raw)
To: linux-arm-kernel
On 12/22/2015 06:40 AM, Shawn Guo wrote:
> On Thu, Dec 03, 2015 at 04:10:32PM -0500, Akshay Bhat wrote:
>> +
>> + rtc at 32 {
>> + compatible = "epson,rx8010";
>
> Is this compatible string documented somewhere?
>
Patches have been submitted to update the documentation for the above
string along with a couple others that were missing/incorrect:
http://marc.info/?l=linux-i2c&m=145089597514804&w=2
http://marc.info/?l=linux-i2c&m=145089715915019&w=2
http://marc.info/?l=linux-i2c&m=145089835615289&w=2
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v5 3/7] ARM: dts: imx: Add Advantech BA-16 Qseven module
@ 2015-12-23 22:22 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-23 22:22 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ
On 12/22/2015 06:40 AM, Shawn Guo wrote:
> On Thu, Dec 03, 2015 at 04:10:32PM -0500, Akshay Bhat wrote:
>> +
>> + rtc@32 {
>> + compatible = "epson,rx8010";
>
> Is this compatible string documented somewhere?
>
Patches have been submitted to update the documentation for the above
string along with a couple others that were missing/incorrect:
http://marc.info/?l=linux-i2c&m=145089597514804&w=2
http://marc.info/?l=linux-i2c&m=145089715915019&w=2
http://marc.info/?l=linux-i2c&m=145089835615289&w=2
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v5 4/7] ARM: dts: imx: Add support for Advantech/GE Bx50v3
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: linux-arm-kernel
From: Justin Waters <justin.waters@timesys.com>
Advantech has 3 carrier boards (B450v3, B650v3, B850v3) which use
the Advantech BA-16 module (based on iMX6D). This file has the
devicetree entries that are common to all 3 boards.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/imx6q-bx50v3.dtsi | 207 ++++++++++++++++++++++++++++++++++++
1 file changed, 207 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-bx50v3.dtsi
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
new file mode 100644
index 0000000..61bb9aa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q-ba16.dtsi"
+
+/ {
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mclk: clock at 0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <22000000>;
+ };
+ };
+
+ reg_wl18xx_vmmc: regulator at 6 {
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1807";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ reg_wlan: regulator at 7 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V_wlan";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ sound {
+ compatible = "fsl,imx6q-ba16-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx6q-ba16-sgtl5000";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <4>;
+ };
+};
+
+&ecspi5 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi5>;
+ status = "okay";
+
+ m25_eeprom: m25p80 at 0 {
+ compatible = "atmel,at25";
+ spi-max-frequency = <20000000>;
+ size = <0x8000>;
+ pagesize = <64>;
+ reg = <0>;
+ address-width = <16>;
+ };
+};
+
+&i2c1 {
+ pca9547: mux at 70 {
+ compatible = "nxp,pca9547";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mux_i2c3: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ ads7830: ads7830 at 48 {
+ compatible = "ti,ads7830";
+ reg = <0x48>;
+ };
+
+ mma8453: mma8453 at 1c {
+ compatible = "fsl,mma8453";
+ reg = <0x1c>;
+ };
+ };
+
+ mux_i2c4: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+
+ eeprom: eeprom at 50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ };
+
+ mpl3115: mpl3115 at 60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+ };
+ };
+
+ mux_i2c5: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ };
+
+ mux_i2c6: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ codec: sgtl5000 at 0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&mclk>;
+ VDDA-supply = <®_1p8v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+ };
+
+ mux_i2c7: i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ pca9539: pca9539 at 74 {
+ compatible = "nxp,pca9539";
+ reg = <0x74>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio2>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ mux_i2c8: i2c at 5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x5>;
+
+ igb at 49 {
+ compatible = "intel,igb";
+ reg = <0x49>;
+ };
+
+ igb at 61 {
+ compatible = "intel,igb";
+ reg = <0x61>;
+ };
+ };
+
+ mux_i2c9: i2c at 6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6>;
+ };
+
+ mux_i2c10: i2c at 7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7>;
+ };
+ };
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <4>;
+ vmmc-supply = <®_wl18xx_vmmc>;
+ no-1-8-v;
+ non-removable;
+ enable-sdio-wakeup;
+ keep-power-in-suspend;
+ cap-power-off-card;
+ max-frequency = <25000000>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore at 0 {
+ compatible = "ti,wl1837";
+ reg = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 4/7] ARM: dts: imx: Add support for Advantech/GE Bx50v3
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ, Akshay Bhat
From: Justin Waters <justin.waters-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
Advantech has 3 carrier boards (B450v3, B650v3, B850v3) which use
the Advantech BA-16 module (based on iMX6D). This file has the
devicetree entries that are common to all 3 boards.
Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
---
arch/arm/boot/dts/imx6q-bx50v3.dtsi | 207 ++++++++++++++++++++++++++++++++++++
1 file changed, 207 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-bx50v3.dtsi
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
new file mode 100644
index 0000000..61bb9aa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q-ba16.dtsi"
+
+/ {
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mclk: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <22000000>;
+ };
+ };
+
+ reg_wl18xx_vmmc: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1807";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pca9539 3 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ reg_wlan: regulator@7 {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V_wlan";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio6 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ sound {
+ compatible = "fsl,imx6q-ba16-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx6q-ba16-sgtl5000";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <4>;
+ };
+};
+
+&ecspi5 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi5>;
+ status = "okay";
+
+ m25_eeprom: m25p80@0 {
+ compatible = "atmel,at25";
+ spi-max-frequency = <20000000>;
+ size = <0x8000>;
+ pagesize = <64>;
+ reg = <0>;
+ address-width = <16>;
+ };
+};
+
+&i2c1 {
+ pca9547: mux@70 {
+ compatible = "nxp,pca9547";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mux_i2c3: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ ads7830: ads7830@48 {
+ compatible = "ti,ads7830";
+ reg = <0x48>;
+ };
+
+ mma8453: mma8453@1c {
+ compatible = "fsl,mma8453";
+ reg = <0x1c>;
+ };
+ };
+
+ mux_i2c4: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ };
+
+ mpl3115: mpl3115@60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+ };
+ };
+
+ mux_i2c5: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ };
+
+ mux_i2c6: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&mclk>;
+ VDDA-supply = <®_1p8v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+ };
+
+ mux_i2c7: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ pca9539: pca9539@74 {
+ compatible = "nxp,pca9539";
+ reg = <0x74>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio2>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ mux_i2c8: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x5>;
+
+ igb@49 {
+ compatible = "intel,igb";
+ reg = <0x49>;
+ };
+
+ igb@61 {
+ compatible = "intel,igb";
+ reg = <0x61>;
+ };
+ };
+
+ mux_i2c9: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6>;
+ };
+
+ mux_i2c10: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7>;
+ };
+ };
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <4>;
+ vmmc-supply = <®_wl18xx_vmmc>;
+ no-1-8-v;
+ non-removable;
+ enable-sdio-wakeup;
+ keep-power-in-suspend;
+ cap-power-off-card;
+ max-frequency = <25000000>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@0 {
+ compatible = "ti,wl1837";
+ reg = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
--
2.6.3
--
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v5 5/7] ARM: dts: imx: Add support for Advantech/GE B450v3
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: linux-arm-kernel
Add support for Advantech/GE B450v3 board.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-b450v3.dts | 84 ++++++++++++++++++++++++++++++++++++++
2 files changed, 85 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b450v3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 760a737..219830f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -310,6 +310,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-wandboard-revb1.dtb \
imx6q-apf6dev.dtb \
imx6q-arm2.dtb \
+ imx6q-b450v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
new file mode 100644
index 0000000..6c76d05
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-b450v3.dts
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+ model = "General Electric B450v3";
+ compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ panel_lvds0 {
+ compatible = "innolux,g121x1-l03";
+ backlight = <&backlight_lvds>;
+ power-supply = <®_lvds>;
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ panel_lvds1 {
+ compatible = "innolux,g121x1-l03";
+ backlight = <&backlight_lvds>;
+ power-supply = <®_lvds>;
+
+ port {
+ panel_in_lvds1: endpoint {
+ remote-endpoint = <&lvds1_out>;
+ };
+ };
+ };
+};
+
+&ldb {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ status = "okay";
+
+ lvds0: lvds-channel at 0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port at 4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+ };
+
+ lvds1: lvds-channel at 1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port at 4 {
+ reg = <4>;
+
+ lvds1_out: endpoint {
+ remote-endpoint = <&panel_in_lvds1>;
+ };
+ };
+ };
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 5/7] ARM: dts: imx: Add support for Advantech/GE B450v3
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ, Akshay Bhat
Add support for Advantech/GE B450v3 board.
Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-b450v3.dts | 84 ++++++++++++++++++++++++++++++++++++++
2 files changed, 85 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b450v3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 760a737..219830f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -310,6 +310,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-wandboard-revb1.dtb \
imx6q-apf6dev.dtb \
imx6q-arm2.dtb \
+ imx6q-b450v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
new file mode 100644
index 0000000..6c76d05
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-b450v3.dts
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+ model = "General Electric B450v3";
+ compatible = "ge,imx6q-b450v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ panel_lvds0 {
+ compatible = "innolux,g121x1-l03";
+ backlight = <&backlight_lvds>;
+ power-supply = <®_lvds>;
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ panel_lvds1 {
+ compatible = "innolux,g121x1-l03";
+ backlight = <&backlight_lvds>;
+ power-supply = <®_lvds>;
+
+ port {
+ panel_in_lvds1: endpoint {
+ remote-endpoint = <&lvds1_out>;
+ };
+ };
+ };
+};
+
+&ldb {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+ };
+
+ lvds1: lvds-channel@1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds1_out: endpoint {
+ remote-endpoint = <&panel_in_lvds1>;
+ };
+ };
+ };
+};
--
2.6.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v5 6/7] ARM: dts: imx: Add support for Advantech/GE B650v3
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: linux-arm-kernel
Add support for Advantech/GE B650v3 board.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-b650v3.dts | 84 ++++++++++++++++++++++++++++++++++++++
2 files changed, 85 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b650v3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 219830f..9cdff66 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -311,6 +311,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-apf6dev.dtb \
imx6q-arm2.dtb \
imx6q-b450v3.dtb \
+ imx6q-b650v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts
new file mode 100644
index 0000000..52f3038
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-b650v3.dts
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+ model = "General Electric B650v3";
+ compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ panel_lvds0 {
+ compatible = "innolux,g121x1-l03";
+ backlight = <&backlight_lvds>;
+ power-supply = <®_lvds>;
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ panel_lvds1 {
+ compatible = "innolux,g121x1-l03";
+ backlight = <&backlight_lvds>;
+ power-supply = <®_lvds>;
+
+ port {
+ panel_in_lvds1: endpoint {
+ remote-endpoint = <&lvds1_out>;
+ };
+ };
+ };
+};
+
+&ldb {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ status = "okay";
+
+ lvds0: lvds-channel at 0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port at 4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+ };
+
+ lvds1: lvds-channel at 1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port at 4 {
+ reg = <4>;
+
+ lvds1_out: endpoint {
+ remote-endpoint = <&panel_in_lvds1>;
+ };
+ };
+ };
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 6/7] ARM: dts: imx: Add support for Advantech/GE B650v3
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ, Akshay Bhat
Add support for Advantech/GE B650v3 board.
Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-b650v3.dts | 84 ++++++++++++++++++++++++++++++++++++++
2 files changed, 85 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b650v3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 219830f..9cdff66 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -311,6 +311,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-apf6dev.dtb \
imx6q-arm2.dtb \
imx6q-b450v3.dtb \
+ imx6q-b650v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts
new file mode 100644
index 0000000..52f3038
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-b650v3.dts
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+ model = "General Electric B650v3";
+ compatible = "ge,imx6q-b650v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ panel_lvds0 {
+ compatible = "innolux,g121x1-l03";
+ backlight = <&backlight_lvds>;
+ power-supply = <®_lvds>;
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ panel_lvds1 {
+ compatible = "innolux,g121x1-l03";
+ backlight = <&backlight_lvds>;
+ power-supply = <®_lvds>;
+
+ port {
+ panel_in_lvds1: endpoint {
+ remote-endpoint = <&lvds1_out>;
+ };
+ };
+ };
+};
+
+&ldb {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+ };
+
+ lvds1: lvds-channel@1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds1_out: endpoint {
+ remote-endpoint = <&panel_in_lvds1>;
+ };
+ };
+ };
+};
--
2.6.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v5 7/7] ARM: dts: imx: Add support for Advantech/GE B850v3
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: linux-arm-kernel
Add support for Advantech/GE B850v3 board.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-b850v3.dts | 127 +++++++++++++++++++++++++++++++++++++
2 files changed, 128 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b850v3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9cdff66..37d5b09 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -312,6 +312,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-arm2.dtb \
imx6q-b450v3.dtb \
imx6q-b650v3.dtb \
+ imx6q-b850v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
new file mode 100644
index 0000000..652f237
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+ model = "General Electric B850v3";
+ compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ panel_lvds0 {
+ compatible = "auo,b133htn01";
+ backlight = <&backlight_lvds>;
+ ddc-i2c-bus = <&mux_i2c12>;
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+};
+
+&ldb {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ fsl,dual-channel;
+ status = "okay";
+
+ lvds0: lvds-channel at 0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port at 4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ pca9547_ddc: mux at 70 {
+ compatible = "nxp,pca9547";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mux_i2c11: i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ };
+
+ mux_i2c12: i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ };
+
+ mux_i2c13: i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ };
+
+ mux_i2c14: i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+ };
+
+ mux_i2c15: i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+ };
+
+ mux_i2c16: i2c at 5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x5>;
+ };
+
+ mux_i2c17: i2c at 6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6>;
+ };
+
+ mux_i2c18: i2c at 7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7>;
+ };
+ };
+};
+
+&hdmi {
+ ddc-i2c-bus = <&mux_i2c11>;
+};
+
+&mux_i2c3 {
+ ads7830_2: ads7830 at 4a {
+ compatible = "ti,ads7830";
+ reg = <0x4a>;
+ };
+};
--
2.6.3
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v5 7/7] ARM: dts: imx: Add support for Advantech/GE B850v3
@ 2015-12-03 21:10 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-03 21:10 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
justin.waters-jEh4hwF5bVhBDgjK7y7TUQ,
l.stach-bIcnvbaLZ9MEGnE8C9+IrQ, Akshay Bhat
Add support for Advantech/GE B850v3 board.
Signed-off-by: Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6q-b850v3.dts | 127 +++++++++++++++++++++++++++++++++++++
2 files changed, 128 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6q-b850v3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9cdff66..37d5b09 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -312,6 +312,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-arm2.dtb \
imx6q-b450v3.dtb \
imx6q-b650v3.dtb \
+ imx6q-b850v3.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-dfi-fs700-m60.dtb \
diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
new file mode 100644
index 0000000..652f237
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2015 Timesys Corporation.
+ * Copyright 2015 General Electric Company
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q-bx50v3.dtsi"
+
+/ {
+ model = "General Electric B850v3";
+ compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ panel_lvds0 {
+ compatible = "auo,b133htn01";
+ backlight = <&backlight_lvds>;
+ ddc-i2c-bus = <&mux_i2c12>;
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+};
+
+&ldb {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ fsl,dual-channel;
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ pca9547_ddc: mux@70 {
+ compatible = "nxp,pca9547";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mux_i2c11: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ };
+
+ mux_i2c12: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ };
+
+ mux_i2c13: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ };
+
+ mux_i2c14: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+ };
+
+ mux_i2c15: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+ };
+
+ mux_i2c16: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x5>;
+ };
+
+ mux_i2c17: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6>;
+ };
+
+ mux_i2c18: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7>;
+ };
+ };
+};
+
+&hdmi {
+ ddc-i2c-bus = <&mux_i2c11>;
+};
+
+&mux_i2c3 {
+ ads7830_2: ads7830@4a {
+ compatible = "ti,ads7830";
+ reg = <0x4a>;
+ };
+};
--
2.6.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v5 0/7] ARM: dts: Add Advantech board support
@ 2015-12-21 22:53 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-21 22:53 UTC (permalink / raw)
To: linux-arm-kernel
Lucas, Shawn,
Any further review comments on the patches. If not can this be applied?
Thanks,
Akshay
On Thu, Dec 3, 2015 at 4:10 PM, Akshay Bhat <akshay.bhat@timesys.com> wrote:
> This series aims to add Advantech BA-16 module (iMX6 based) and GE board support.
>
> This series has been tested against linux-next tag next-20151202.
>
> Modifications:
> v4->v5:
> - BA16: Move SPI FLASH partitions to a "partitions" subnode
> - B450v3, B650v3 and B850v3: Fix model names
>
> History:
> --------
> [v1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/381872.html
> [v2]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/383276.html
> [v3]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/384202.html
> [v4]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390373.html
>
> Akshay Bhat (5):
> of: Add vendor prefix for Advantech Corporation
> of: Add vendor prefix for General Electric Company
> ARM: dts: imx: Add support for Advantech/GE B450v3
> ARM: dts: imx: Add support for Advantech/GE B650v3
> ARM: dts: imx: Add support for Advantech/GE B850v3
>
> Justin Waters (2):
> ARM: dts: imx: Add Advantech BA-16 Qseven module
> ARM: dts: imx: Add support for Advantech/GE Bx50v3
>
> .../devicetree/bindings/vendor-prefixes.txt | 2 +
> arch/arm/boot/dts/Makefile | 3 +
> arch/arm/boot/dts/imx6q-b450v3.dts | 84 +++
> arch/arm/boot/dts/imx6q-b650v3.dts | 84 +++
> arch/arm/boot/dts/imx6q-b850v3.dts | 127 +++++
> arch/arm/boot/dts/imx6q-ba16.dtsi | 589 +++++++++++++++++++++
> arch/arm/boot/dts/imx6q-bx50v3.dtsi | 207 ++++++++
> 7 files changed, 1096 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6q-b450v3.dts
> create mode 100644 arch/arm/boot/dts/imx6q-b650v3.dts
> create mode 100644 arch/arm/boot/dts/imx6q-b850v3.dts
> create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
> create mode 100644 arch/arm/boot/dts/imx6q-bx50v3.dtsi
>
> --
> 2.6.3
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v5 0/7] ARM: dts: Add Advantech board support
@ 2015-12-21 22:53 ` Akshay Bhat
0 siblings, 0 replies; 28+ messages in thread
From: Akshay Bhat @ 2015-12-21 22:53 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Shawn Guo, Sascha Hauer, Rob Herring, Russell King - ARM Linux,
Kumar Gala, Mark Rutland, Ian Campbell,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Justin Waters,
Lucas Stach, Akshay Bhat
Lucas, Shawn,
Any further review comments on the patches. If not can this be applied?
Thanks,
Akshay
On Thu, Dec 3, 2015 at 4:10 PM, Akshay Bhat <akshay.bhat-jEh4hwF5bVhBDgjK7y7TUQ@public.gmane.org> wrote:
> This series aims to add Advantech BA-16 module (iMX6 based) and GE board support.
>
> This series has been tested against linux-next tag next-20151202.
>
> Modifications:
> v4->v5:
> - BA16: Move SPI FLASH partitions to a "partitions" subnode
> - B450v3, B650v3 and B850v3: Fix model names
>
> History:
> --------
> [v1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/381872.html
> [v2]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/383276.html
> [v3]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/384202.html
> [v4]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390373.html
>
> Akshay Bhat (5):
> of: Add vendor prefix for Advantech Corporation
> of: Add vendor prefix for General Electric Company
> ARM: dts: imx: Add support for Advantech/GE B450v3
> ARM: dts: imx: Add support for Advantech/GE B650v3
> ARM: dts: imx: Add support for Advantech/GE B850v3
>
> Justin Waters (2):
> ARM: dts: imx: Add Advantech BA-16 Qseven module
> ARM: dts: imx: Add support for Advantech/GE Bx50v3
>
> .../devicetree/bindings/vendor-prefixes.txt | 2 +
> arch/arm/boot/dts/Makefile | 3 +
> arch/arm/boot/dts/imx6q-b450v3.dts | 84 +++
> arch/arm/boot/dts/imx6q-b650v3.dts | 84 +++
> arch/arm/boot/dts/imx6q-b850v3.dts | 127 +++++
> arch/arm/boot/dts/imx6q-ba16.dtsi | 589 +++++++++++++++++++++
> arch/arm/boot/dts/imx6q-bx50v3.dtsi | 207 ++++++++
> 7 files changed, 1096 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6q-b450v3.dts
> create mode 100644 arch/arm/boot/dts/imx6q-b650v3.dts
> create mode 100644 arch/arm/boot/dts/imx6q-b850v3.dts
> create mode 100644 arch/arm/boot/dts/imx6q-ba16.dtsi
> create mode 100644 arch/arm/boot/dts/imx6q-bx50v3.dtsi
>
> --
> 2.6.3
>
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