* [PATCH v2 1/2] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs @ 2016-05-16 17:51 Felix Fietkau 2016-05-16 17:51 ` [PATCH v2 2/2] MIPS: ath79: fix regression in PCI window initialization Felix Fietkau 2016-05-20 12:49 ` [PATCH v2 1/2] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs Alban 0 siblings, 2 replies; 4+ messages in thread From: Felix Fietkau @ 2016-05-16 17:51 UTC (permalink / raw) To: linux-mips; +Cc: albeu, sergei.shtylyov AR913x, AR724x and AR933x are the only SoCs where the ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c Invert the logic to make the code compatible with AR95xx Signed-off-by: Felix Fietkau <nbd@nbd.name> --- arch/mips/ath79/common.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c index 3cedd1f..84d4502 100644 --- a/arch/mips/ath79/common.c +++ b/arch/mips/ath79/common.c @@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void) { ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE); - if (soc_is_ar71xx() || soc_is_ar934x()) { - ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c; - ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; - } else { + if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) { ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c; ath79_ddr_pci_win_base = 0; + } else { + ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c; + ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; } } EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init); -- 2.2.2 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 2/2] MIPS: ath79: fix regression in PCI window initialization 2016-05-16 17:51 [PATCH v2 1/2] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs Felix Fietkau @ 2016-05-16 17:51 ` Felix Fietkau 2016-05-20 13:10 ` Alban 2016-05-20 12:49 ` [PATCH v2 1/2] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs Alban 1 sibling, 1 reply; 4+ messages in thread From: Felix Fietkau @ 2016-05-16 17:51 UTC (permalink / raw) To: linux-mips; +Cc: albeu, sergei.shtylyov ath79_ddr_pci_win_base has the type void __iomem *, so register offsets need to be a multiple of 4. Cc: Alban Bedel <albeu@free.fr> Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface") Signed-off-by: Felix Fietkau <nbd@nbd.name> --- arch/mips/ath79/common.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c index 84d4502..d071a3a 100644 --- a/arch/mips/ath79/common.c +++ b/arch/mips/ath79/common.c @@ -76,14 +76,14 @@ void ath79_ddr_set_pci_windows(void) { BUG_ON(!ath79_ddr_pci_win_base); - __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0); - __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 1); - __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 2); - __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 3); - __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 4); - __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 5); - __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 6); - __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 7); + __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0); + __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4); + __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8); + __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc); + __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10); + __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14); + __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18); + __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c); } EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows); -- 2.2.2 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2 2/2] MIPS: ath79: fix regression in PCI window initialization 2016-05-16 17:51 ` [PATCH v2 2/2] MIPS: ath79: fix regression in PCI window initialization Felix Fietkau @ 2016-05-20 13:10 ` Alban 0 siblings, 0 replies; 4+ messages in thread From: Alban @ 2016-05-20 13:10 UTC (permalink / raw) To: Felix Fietkau; +Cc: Aban Bedel, linux-mips, sergei.shtylyov [-- Attachment #1: Type: text/plain, Size: 393 bytes --] On Mon, 16 May 2016 19:51:55 +0200 Felix Fietkau <nbd@nbd.name> wrote: > ath79_ddr_pci_win_base has the type void __iomem *, so register offsets > need to be a multiple of 4. > > Cc: Alban Bedel <albeu@free.fr> > Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface") > Signed-off-by: Felix Fietkau <nbd@nbd.name> Acked-by: Aban Bedel <albeu@free.fr> Alban [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 1/2] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs 2016-05-16 17:51 [PATCH v2 1/2] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs Felix Fietkau 2016-05-16 17:51 ` [PATCH v2 2/2] MIPS: ath79: fix regression in PCI window initialization Felix Fietkau @ 2016-05-20 12:49 ` Alban 1 sibling, 0 replies; 4+ messages in thread From: Alban @ 2016-05-20 12:49 UTC (permalink / raw) To: Felix Fietkau; +Cc: Aban Bedel, linux-mips, sergei.shtylyov [-- Attachment #1: Type: text/plain, Size: 359 bytes --] On Mon, 16 May 2016 19:51:54 +0200 Felix Fietkau <nbd@nbd.name> wrote: > AR913x, AR724x and AR933x are the only SoCs where the > ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c > Invert the logic to make the code compatible with AR95xx > > Signed-off-by: Felix Fietkau <nbd@nbd.name> Acked-by: Aban Bedel <albeu@free.fr> Alban [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 819 bytes --] ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-05-20 13:10 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-05-16 17:51 [PATCH v2 1/2] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs Felix Fietkau 2016-05-16 17:51 ` [PATCH v2 2/2] MIPS: ath79: fix regression in PCI window initialization Felix Fietkau 2016-05-20 13:10 ` Alban 2016-05-20 12:49 ` [PATCH v2 1/2] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs Alban
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