From: vincent.siles@provenrun.com (Vincent Siles)
To: linux-arm-kernel@lists.infradead.org
Subject: lsl / lsr possible confusion in v7_flush_dcache_all
Date: Thu, 8 Sep 2016 11:15:20 +0200 [thread overview]
Message-ID: <20160908091520.GE14909@vsiles-Desktop> (raw)
Hi !
While reading the v7_flush_dcache_all (arch/arm/mm/cache-v7.S), I
stumbled upon this line:
# r10 is the current cache level
127: add r2, r10, r10, lsr #1 @ work out 3x current cache level
If we want r2 to be 3 * r10, we should compute r10 + (r10 << 1), which
is lsl, not lsr.
I check for a recent kernel, the issue seems to still be here:
repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
revision: d71f058617564750261b673ea9b3352382b9cde4
Best regards,
Vincent Siles
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From: Vincent Siles <vincent.siles@provenrun.com>
To: Russell King <linux@armlinux.org.uk>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: lsl / lsr possible confusion in v7_flush_dcache_all
Date: Thu, 8 Sep 2016 11:15:20 +0200 [thread overview]
Message-ID: <20160908091520.GE14909@vsiles-Desktop> (raw)
[-- Attachment #1: Type: text/plain, Size: 513 bytes --]
Hi !
While reading the v7_flush_dcache_all (arch/arm/mm/cache-v7.S), I
stumbled upon this line:
# r10 is the current cache level
127: add r2, r10, r10, lsr #1 @ work out 3x current cache level
If we want r2 to be 3 * r10, we should compute r10 + (r10 << 1), which
is lsl, not lsr.
I check for a recent kernel, the issue seems to still be here:
repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
revision: d71f058617564750261b673ea9b3352382b9cde4
Best regards,
Vincent Siles
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next reply other threads:[~2016-09-08 9:15 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-08 9:15 Vincent Siles [this message]
2016-09-08 9:15 ` lsl / lsr possible confusion in v7_flush_dcache_all Vincent Siles
2016-09-08 9:38 ` Will Deacon
2016-09-08 9:38 ` Will Deacon
2016-09-08 9:50 ` Vincent Siles
2016-09-08 9:50 ` Vincent Siles
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