* lsl / lsr possible confusion in v7_flush_dcache_all
@ 2016-09-08 9:15 ` Vincent Siles
0 siblings, 0 replies; 6+ messages in thread
From: Vincent Siles @ 2016-09-08 9:15 UTC (permalink / raw)
To: linux-arm-kernel
Hi !
While reading the v7_flush_dcache_all (arch/arm/mm/cache-v7.S), I
stumbled upon this line:
# r10 is the current cache level
127: add r2, r10, r10, lsr #1 @ work out 3x current cache level
If we want r2 to be 3 * r10, we should compute r10 + (r10 << 1), which
is lsl, not lsr.
I check for a recent kernel, the issue seems to still be here:
repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
revision: d71f058617564750261b673ea9b3352382b9cde4
Best regards,
Vincent Siles
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^ permalink raw reply [flat|nested] 6+ messages in thread
* lsl / lsr possible confusion in v7_flush_dcache_all
@ 2016-09-08 9:15 ` Vincent Siles
0 siblings, 0 replies; 6+ messages in thread
From: Vincent Siles @ 2016-09-08 9:15 UTC (permalink / raw)
To: Russell King, linux-arm-kernel, linux-kernel
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Hi !
While reading the v7_flush_dcache_all (arch/arm/mm/cache-v7.S), I
stumbled upon this line:
# r10 is the current cache level
127: add r2, r10, r10, lsr #1 @ work out 3x current cache level
If we want r2 to be 3 * r10, we should compute r10 + (r10 << 1), which
is lsl, not lsr.
I check for a recent kernel, the issue seems to still be here:
repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
revision: d71f058617564750261b673ea9b3352382b9cde4
Best regards,
Vincent Siles
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^ permalink raw reply [flat|nested] 6+ messages in thread
* lsl / lsr possible confusion in v7_flush_dcache_all
2016-09-08 9:15 ` Vincent Siles
@ 2016-09-08 9:38 ` Will Deacon
-1 siblings, 0 replies; 6+ messages in thread
From: Will Deacon @ 2016-09-08 9:38 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Sep 08, 2016 at 11:15:20AM +0200, Vincent Siles wrote:
> While reading the v7_flush_dcache_all (arch/arm/mm/cache-v7.S), I
> stumbled upon this line:
>
> # r10 is the current cache level
> 127: add r2, r10, r10, lsr #1 @ work out 3x current cache level
>
> If we want r2 to be 3 * r10, we should compute r10 + (r10 << 1), which
> is lsl, not lsr.
>
> I check for a recent kernel, the issue seems to still be here:
> repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> revision: d71f058617564750261b673ea9b3352382b9cde4
This code is take pretty much verbatim from the ARM ARM and, despite
being fairly obfuscated, does what it says on the tin. r10 is incremented
by 2 each time round the loop, so this is basically doing 2i + (2i / 2).
Will
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: lsl / lsr possible confusion in v7_flush_dcache_all
@ 2016-09-08 9:38 ` Will Deacon
0 siblings, 0 replies; 6+ messages in thread
From: Will Deacon @ 2016-09-08 9:38 UTC (permalink / raw)
To: Vincent Siles; +Cc: Russell King, linux-arm-kernel, linux-kernel
On Thu, Sep 08, 2016 at 11:15:20AM +0200, Vincent Siles wrote:
> While reading the v7_flush_dcache_all (arch/arm/mm/cache-v7.S), I
> stumbled upon this line:
>
> # r10 is the current cache level
> 127: add r2, r10, r10, lsr #1 @ work out 3x current cache level
>
> If we want r2 to be 3 * r10, we should compute r10 + (r10 << 1), which
> is lsl, not lsr.
>
> I check for a recent kernel, the issue seems to still be here:
> repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> revision: d71f058617564750261b673ea9b3352382b9cde4
This code is take pretty much verbatim from the ARM ARM and, despite
being fairly obfuscated, does what it says on the tin. r10 is incremented
by 2 each time round the loop, so this is basically doing 2i + (2i / 2).
Will
^ permalink raw reply [flat|nested] 6+ messages in thread
* lsl / lsr possible confusion in v7_flush_dcache_all
2016-09-08 9:38 ` Will Deacon
@ 2016-09-08 9:50 ` Vincent Siles
-1 siblings, 0 replies; 6+ messages in thread
From: Vincent Siles @ 2016-09-08 9:50 UTC (permalink / raw)
To: linux-arm-kernel
Oh, right. I missed that !
Thank you for the help.
Best,
Vincent
On 08-09-16 10:38:01, Will Deacon wrote:
> On Thu, Sep 08, 2016 at 11:15:20AM +0200, Vincent Siles wrote:
> > While reading the v7_flush_dcache_all (arch/arm/mm/cache-v7.S), I
> > stumbled upon this line:
> >
> > # r10 is the current cache level
> > 127: add r2, r10, r10, lsr #1 @ work out 3x current cache level
> >
> > If we want r2 to be 3 * r10, we should compute r10 + (r10 << 1), which
> > is lsl, not lsr.
> >
> > I check for a recent kernel, the issue seems to still be here:
> > repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> > revision: d71f058617564750261b673ea9b3352382b9cde4
>
> This code is take pretty much verbatim from the ARM ARM and, despite
> being fairly obfuscated, does what it says on the tin. r10 is incremented
> by 2 each time round the loop, so this is basically doing 2i + (2i / 2).
>
> Will
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* Re: lsl / lsr possible confusion in v7_flush_dcache_all
@ 2016-09-08 9:50 ` Vincent Siles
0 siblings, 0 replies; 6+ messages in thread
From: Vincent Siles @ 2016-09-08 9:50 UTC (permalink / raw)
To: Will Deacon; +Cc: Russell King, linux-arm-kernel, linux-kernel
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Oh, right. I missed that !
Thank you for the help.
Best,
Vincent
On 08-09-16 10:38:01, Will Deacon wrote:
> On Thu, Sep 08, 2016 at 11:15:20AM +0200, Vincent Siles wrote:
> > While reading the v7_flush_dcache_all (arch/arm/mm/cache-v7.S), I
> > stumbled upon this line:
> >
> > # r10 is the current cache level
> > 127: add r2, r10, r10, lsr #1 @ work out 3x current cache level
> >
> > If we want r2 to be 3 * r10, we should compute r10 + (r10 << 1), which
> > is lsl, not lsr.
> >
> > I check for a recent kernel, the issue seems to still be here:
> > repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> > revision: d71f058617564750261b673ea9b3352382b9cde4
>
> This code is take pretty much verbatim from the ARM ARM and, despite
> being fairly obfuscated, does what it says on the tin. r10 is incremented
> by 2 each time round the loop, so this is basically doing 2i + (2i / 2).
>
> Will
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2016-09-08 9:15 lsl / lsr possible confusion in v7_flush_dcache_all Vincent Siles
2016-09-08 9:15 ` Vincent Siles
2016-09-08 9:38 ` Will Deacon
2016-09-08 9:38 ` Will Deacon
2016-09-08 9:50 ` Vincent Siles
2016-09-08 9:50 ` Vincent Siles
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