Re: [PATCH 3/9] MIPS: traps: Ensure full EBase is written

[Ralf Baechle <ralf@linux-mips.org>]

On Thu, Sep 01, 2016 at 05:30:09PM +0100, James Hogan wrote:

> On CPUs which support the EBase WG (write gate) flag, the most
> significant bits of the exception base can be changed. Firmware running
> on a VP(E) using MIPS rproc may change EBase to point into the user
> segment where the firmware is located such that it can service
> interrupts. When control is transferred back to the kernel the EBase
> must be switched back into the kernel segment, such that the kernel's
> exception vectors are used.
> 
> Similarly when vectored interrupts (vint) or vectored external interrupt
> controllers (veic) are enabled an exception vector is allocated from
> bootmem, and written to the EBase register. Due to the WG flag being
> clear, only bits 29:12 will be written. Asside from the rproc case above
> this is normally fine (as it will usually be a low allocation within the
> KSeg0 range, however when Enhanced Virtual Addressing (EVA) is enabled
> the allocation may be outside of the traditional KSeg0/KSeg1 address
> range, resulting in the wrong EBase being written.
> 
> Correct both cases (configure_exception_vector() for the boot CPU, and
> per_cpu_trap_init() for secondary CPUs) to write EBase with the WG flag
> first if supported.
> 
> On the Malta EVA configuration, KSeg0 is mapped to physical address 0,
> and memory is allocated from the KUSeg segment which is mapped to
> physical address 0x80000000, which physically aliases the RAM at 0. This
> only worked due to the exception base address aliasing the same
> underlying RAM that was written to & cache flushed, and due to
> flush_icache_range() going beyond the call of duty and flushing from the
> L2 cache too (due to the differing physical addresses).

See comments on 1/9.

I think I can apply the remaining patches already before we finished
sorting out 1/9 and 3/9, so I will do so.

  Ralf