Re: [PATCH 1/9] MIPS: traps: 64bit kernels should read CP0_EBase 64bit

[James Hogan <james.hogan@imgtec.com>]

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Hi Maciej,

On Sun, Oct 02, 2016 at 11:30:13AM +0100, Maciej W. Rozycki wrote:
> On Wed, 21 Sep 2016, Matt Redfearn wrote:
> 
> > > > When reading the CP0_EBase register containing the WG (write gate) bit,
> > > > the ebase variable should be set to the full value of the register, i.e.
> > > > on a 64-bit kernel the full 64-bit width of the register via
> > > > read_cp0_ebase_64(), and on a 32-bit kernel the full 32-bit width
> > > > including bits 31:30 which may be writeable.
> > > How about changing the definition of read/write_c0_ebase to
> > >
> > > #define read_c0_ebase()         __read_ulong_c0_register($15, 1)
> > > #define write_c0_ebase(val)     __write_ulong_c0_register($15, 1, val)
> > 
> > James added the {read,write}_c0_ebase_64 functions in
> > 37fb60f8e3f011c25c120081a73886ad8dbc42fd, because performing a 64bit access to
> > 32bit cp0 registers (like ebase on 32bit cpus) was an undefined operation
> > pre-r6, so we can't always access them as longs.
> 
>  Well, `long' is 32-bit with 32-bit processors, however in older (as in: 
> before 3.50) architecture revisions EBase was 32-bit even with 64-bit 
> processors,
> so I take it you meant "like ebase on 64bit cpus", right?
> 
> > > or using a new variant like
> > >
> > > #define read_c0_ebase_ulong()         __read_ulong_c0_register($15, 1)
> > > #define write_c0_ebase_ulong(val)     __write_ulong_c0_register($15, 1, val)
> > >
> > > to avoid the ifdefery?  This could also make this bit
> > >
> > >                  ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
> > > : (s32)read_c0_ebase();
> > 
> > This relies on being able to determine a 64bit value for ebase, either by
> > reading it in its entirety on a 64bit cpu (including on a 32bit kernel) or sign
> > extending it from a 32bit read.
> 
>  This does look wrong to me, as I noted above EBase is 64-bit with MIPS64 
> processors as from architecture revision 3.50.  Also I don't think we want 

MIPS64 PRA (I'm looking at r5 and r6) seems to allow for write-gate not
to be implemented, in which case the register is only 32-bits.

Cheers
James

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