From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
To: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>, <linux-mips@linux-mips.org>
Subject: Re: [PATCH 7/9] MIPS: uprobes: Flush icache via kernel address
Date: Thu, 22 Sep 2016 15:27:41 -0700 [thread overview]
Message-ID: <57E45ADD.6000202@imgtec.com> (raw)
In-Reply-To: <7C466D41-C786-48E0-9BFB-1024D6F9AFFC@imgtec.com>
On 09/22/2016 03:13 PM, James Hogan wrote:
> well it'll do a protected dcache flush (i.e. using CACHEE with EVA). Would kmap/kunmap or variants (fixed to work with aliasing dcache) be able to take care of colouring / further flushing?
We should flush kernel D-cache and user I-cache in any cache aliasing
system. I was wrong - a fixed HIGHMEM doesn't do any difference
actually, because page may be located in directly addressed memory (all
HIGHMEM stuff is irrelevant in this case, kmap returns a lowmem address).
>
> In any case, simply changing to the user_ one is a no-op compared to leaving as is where patch 9 would probably break it on EVA by making it operate only on kernel addresses.
EVA or not has no difference here - kernel address can still be a
different color to user address.
And keeping kernel I-cache flush does break it really, not EVA.
- Leonid.
WARNING: multiple messages have this Message-ID (diff)
From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
To: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
Subject: Re: [PATCH 7/9] MIPS: uprobes: Flush icache via kernel address
Date: Thu, 22 Sep 2016 15:27:41 -0700 [thread overview]
Message-ID: <57E45ADD.6000202@imgtec.com> (raw)
Message-ID: <20160922222741.NZc9MSWFZ1QvYwLyP0EyebAvBfir6IhGmV6GKY-NieA@z> (raw)
In-Reply-To: <7C466D41-C786-48E0-9BFB-1024D6F9AFFC@imgtec.com>
On 09/22/2016 03:13 PM, James Hogan wrote:
> well it'll do a protected dcache flush (i.e. using CACHEE with EVA). Would kmap/kunmap or variants (fixed to work with aliasing dcache) be able to take care of colouring / further flushing?
We should flush kernel D-cache and user I-cache in any cache aliasing
system. I was wrong - a fixed HIGHMEM doesn't do any difference
actually, because page may be located in directly addressed memory (all
HIGHMEM stuff is irrelevant in this case, kmap returns a lowmem address).
>
> In any case, simply changing to the user_ one is a no-op compared to leaving as is where patch 9 would probably break it on EVA by making it operate only on kernel addresses.
EVA or not has no difference here - kernel address can still be a
different color to user address.
And keeping kernel I-cache flush does break it really, not EVA.
- Leonid.
next prev parent reply other threads:[~2016-09-22 22:27 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-01 16:30 [PATCH 0/9] MIPS: General EVA fixes & cleanups James Hogan
2016-09-01 16:30 ` [PATCH 1/9] MIPS: traps: 64bit kernels should read CP0_EBase 64bit James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-21 13:08 ` Ralf Baechle
2016-09-21 15:01 ` Matt Redfearn
2016-09-21 15:01 ` Matt Redfearn
2016-10-02 10:30 ` Maciej W. Rozycki
2016-10-05 15:56 ` James Hogan
2016-10-05 15:56 ` James Hogan
2016-10-06 16:18 ` Maciej W. Rozycki
2016-10-06 18:05 ` James Hogan
2016-10-06 18:05 ` James Hogan
2016-10-06 19:56 ` Maciej W. Rozycki
2016-10-06 20:19 ` James Hogan
2016-10-06 20:19 ` James Hogan
2016-10-06 22:41 ` Maciej W. Rozycki
2016-10-06 22:50 ` James Hogan
2016-10-06 22:50 ` James Hogan
2016-10-06 23:07 ` Maciej W. Rozycki
2016-10-07 15:35 ` David Daney
2016-10-07 15:41 ` David Daney
2016-10-07 17:39 ` Maciej W. Rozycki
2016-09-01 16:30 ` [PATCH 2/9] MIPS: traps: Convert ebase to KSeg0 James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-01 16:30 ` [PATCH 3/9] MIPS: traps: Ensure full EBase is written James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-21 13:19 ` Ralf Baechle
2016-09-01 16:30 ` [PATCH 4/9] MIPS: c-r4k: Drop bc_wback_inv() from icache flush James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-01 16:30 ` [PATCH 5/9] MIPS: c-r4k: Split user/kernel flush_icache_range() James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-01 16:30 ` [PATCH 6/9] MIPS: cacheflush: Use __flush_icache_user_range() James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-01 16:30 ` [PATCH 7/9] MIPS: uprobes: Flush icache via kernel address James Hogan
2016-09-01 16:30 ` James Hogan
2016-09-21 13:26 ` Ralf Baechle
2016-09-21 18:15 ` Leonid Yegoshin
2016-09-21 18:15 ` Leonid Yegoshin
2016-09-22 21:15 ` James Hogan
2016-09-22 21:15 ` James Hogan
2016-09-22 21:38 ` Leonid Yegoshin
2016-09-22 21:38 ` Leonid Yegoshin
2016-09-22 21:42 ` Leonid Yegoshin
2016-09-22 21:42 ` Leonid Yegoshin
2016-09-22 22:13 ` James Hogan
2016-09-22 22:27 ` Leonid Yegoshin [this message]
2016-09-22 22:27 ` Leonid Yegoshin
2016-09-23 7:10 ` James Hogan
2016-09-01 16:30 ` [PATCH 8/9] MIPS: KVM: Use __local_flush_icache_user_range() James Hogan
2016-09-01 16:30 ` [PATCH 9/9] MIPS: c-r4k: Fix flush_icache_range() for EVA James Hogan
2016-09-01 16:30 ` James Hogan
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