From: David Gibson <david@gibson.dropbear.id.au>
To: Richard Henderson <rth@twiddle.net>
Cc: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>,
Vasant Hegde <hegdevasant@linux.vnet.ibm.com>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 1/6] target-ppc: add vmul10[u, eu, cu, ecu]q instructions
Date: Thu, 29 Sep 2016 14:24:48 +1000 [thread overview]
Message-ID: <20160929042448.GP8390@umbus.fritz.box> (raw)
In-Reply-To: <6c666347-fa50-a824-b8bb-8a6f31f454e5@twiddle.net>
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On Wed, Sep 28, 2016 at 09:00:51PM -0700, Richard Henderson wrote:
> On 09/28/2016 07:07 PM, David Gibson wrote:
> > > + tcg_gen_mulu2_i64(t0, t1, cpu_avrl[rA(ctx->opcode)], val); \
> >
> > Do you really want to be using an actual mul op, rather than (in << 3)
> > + (in << 1)? Obviously working out al the carries correctly will be a
> > bit fiddly.
>
> I think it's fine. Modern hardware will do the double-word multiply in 3-5
> cycles, which is probably equal to what we could do by hand with
> shifts.
Fair enough. And it will make for less dicking around with the carry
in and carry out.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2016-09-29 5:36 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-28 5:45 [Qemu-devel] [PATCH 0/6] POWER9 TCG enablement - part5 Rajalakshmi Srinivasaraghavan
2016-09-28 5:45 ` [Qemu-devel] [PATCH 1/6] target-ppc: add vmul10[u, eu, cu, ecu]q instructions Rajalakshmi Srinivasaraghavan
2016-09-28 16:42 ` Richard Henderson
2016-10-05 5:23 ` Rajalakshmi Srinivasaraghavan
2016-09-29 2:07 ` David Gibson
2016-09-29 4:00 ` Richard Henderson
2016-09-29 4:24 ` David Gibson [this message]
2016-09-28 5:45 ` [Qemu-devel] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions Rajalakshmi Srinivasaraghavan
2016-09-28 16:54 ` Richard Henderson
2016-10-05 5:21 ` Rajalakshmi Srinivasaraghavan
2016-10-25 4:31 ` Rajalakshmi Srinivasaraghavan
2016-09-28 5:45 ` [Qemu-devel] [PATCH 3/6] target-ppc: add vextu[bhw]rx instructions Rajalakshmi Srinivasaraghavan
2016-10-25 4:32 ` Rajalakshmi Srinivasaraghavan
2016-09-28 5:45 ` [Qemu-devel] [PATCH 4/6] target-ppc: fix invalid mask - cmpl, bctar Rajalakshmi Srinivasaraghavan
2016-09-29 2:22 ` David Gibson
2016-09-28 5:45 ` [Qemu-devel] [PATCH 5/6] target-ppc: add vector compare not equal instructions Rajalakshmi Srinivasaraghavan
2016-09-28 17:01 ` Richard Henderson
2016-09-29 2:22 ` David Gibson
2016-09-28 5:45 ` [Qemu-devel] [PATCH 6/6] target-ppc: add vclzlsbb/vctzlsbb instructions Rajalakshmi Srinivasaraghavan
2016-09-28 17:08 ` Richard Henderson
2016-09-29 2:23 ` David Gibson
2016-09-29 2:25 ` David Gibson
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