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From: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
To: Richard Henderson <rth@twiddle.net>,
	qemu-ppc@nongnu.org, david@gibson.dropbear.id.au
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
	benh@kernel.crashing.org,
	Avinesh Kumar <avinesku@linux.vnet.ibm.com>
Subject: Re: [Qemu-devel] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions
Date: Wed, 5 Oct 2016 10:51:33 +0530	[thread overview]
Message-ID: <897d84d4-9b85-4d03-a117-555da740b48c@linux.vnet.ibm.com> (raw)
In-Reply-To: <443643e4-26c4-d049-c521-fc8a15da663f@twiddle.net>



On 09/28/2016 10:24 PM, Richard Henderson wrote:
> On 09/27/2016 10:45 PM, Rajalakshmi Srinivasaraghavan wrote:
>> +#if defined(HOST_WORDS_BIGENDIAN)
>> +#define VEXTULX_DO(name, elem)                                  \
>> +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
>> +{                                                               \
>> +    target_ulong r = 0;                                         \
>> +    int i;                                                      \
>> +    int index = a & 0xf;                                        \
>> +    for (i = 0; i < elem; i++) {                                \
>> +        r = r << 8;                                             \
>> +        if (index + i <= 15) {                                  \
>> +            r = r | b->u8[index + i];                           \
>> +        }                                                       \
>> +    }                                                           \
>> +    return r;                                                   \
>> +}
>> +#else
>> +#define VEXTULX_DO(name, elem)                                  \
>> +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b)  \
>> +{                                                               \
>> +    target_ulong r = 0;                                         \
>> +    int i;                                                      \
>> +    int index = 15 - (a & 0xf);                                 \
>> +    for (i = 0; i < elem; i++) {                                \
>> +        r = r << 8;                                             \
>> +        if (index - i >= 0) {                                   \
>> +            r = r | b->u8[index - i];                           \
>> +        }                                                       \
>> +    }                                                           \
>> +    return r;                                                   \
>> +}
>> +#endif
>> +
>> +VEXTULX_DO(vextublx, 1)
>> +VEXTULX_DO(vextuhlx, 2)
>> +VEXTULX_DO(vextuwlx, 4)
>> +#undef VEXTULX_DO
> Ew.
>
> This should be one 128-bit shift and one and.
>
> Since the shift amount is a multiple of 8, the 128-bit shift for vextub[lr]x
> does not need to cross a double-word boundary, and so can be decomposed into
> one 64-bit shift of (count & 64 ? hi : lo).
>
> For vextu[hw]lr]x, you'd need to do the whole left-shift, right-shift, or thing.
>
> But still, fantastically better than a loop.
Ack. Will send an updated patch.
>
>
> r~
>
>

-- 
Thanks
Rajalakshmi S

  reply	other threads:[~2016-10-05  5:21 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-28  5:45 [Qemu-devel] [PATCH 0/6] POWER9 TCG enablement - part5 Rajalakshmi Srinivasaraghavan
2016-09-28  5:45 ` [Qemu-devel] [PATCH 1/6] target-ppc: add vmul10[u, eu, cu, ecu]q instructions Rajalakshmi Srinivasaraghavan
2016-09-28 16:42   ` Richard Henderson
2016-10-05  5:23     ` Rajalakshmi Srinivasaraghavan
2016-09-29  2:07   ` David Gibson
2016-09-29  4:00     ` Richard Henderson
2016-09-29  4:24       ` [Qemu-devel] [Qemu-ppc] " David Gibson
2016-09-28  5:45 ` [Qemu-devel] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions Rajalakshmi Srinivasaraghavan
2016-09-28 16:54   ` Richard Henderson
2016-10-05  5:21     ` Rajalakshmi Srinivasaraghavan [this message]
2016-10-25  4:31       ` Rajalakshmi Srinivasaraghavan
2016-09-28  5:45 ` [Qemu-devel] [PATCH 3/6] target-ppc: add vextu[bhw]rx instructions Rajalakshmi Srinivasaraghavan
2016-10-25  4:32   ` Rajalakshmi Srinivasaraghavan
2016-09-28  5:45 ` [Qemu-devel] [PATCH 4/6] target-ppc: fix invalid mask - cmpl, bctar Rajalakshmi Srinivasaraghavan
2016-09-29  2:22   ` David Gibson
2016-09-28  5:45 ` [Qemu-devel] [PATCH 5/6] target-ppc: add vector compare not equal instructions Rajalakshmi Srinivasaraghavan
2016-09-28 17:01   ` Richard Henderson
2016-09-29  2:22   ` David Gibson
2016-09-28  5:45 ` [Qemu-devel] [PATCH 6/6] target-ppc: add vclzlsbb/vctzlsbb instructions Rajalakshmi Srinivasaraghavan
2016-09-28 17:08   ` Richard Henderson
2016-09-29  2:23     ` David Gibson
2016-09-29  2:25   ` David Gibson

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