From: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
To: Richard Henderson <rth@twiddle.net>,
qemu-ppc@nongnu.org, david@gibson.dropbear.id.au
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
Avinesh Kumar <avinesku@linux.vnet.ibm.com>
Subject: Re: [Qemu-devel] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions
Date: Tue, 25 Oct 2016 10:01:21 +0530 [thread overview]
Message-ID: <e205d4b4-b287-d86d-62b0-c1c82e1241c3@linux.vnet.ibm.com> (raw)
In-Reply-To: <897d84d4-9b85-4d03-a117-555da740b48c@linux.vnet.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 2725 bytes --]
On 10/05/2016 10:51 AM, Rajalakshmi Srinivasaraghavan wrote:
>
>
> On 09/28/2016 10:24 PM, Richard Henderson wrote:
>> On 09/27/2016 10:45 PM, Rajalakshmi Srinivasaraghavan wrote:
>>> +#if defined(HOST_WORDS_BIGENDIAN)
>>> +#define VEXTULX_DO(name, elem) \
>>> +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
>>> +{ \
>>> + target_ulong r = 0; \
>>> + int i; \
>>> + int index = a & 0xf; \
>>> + for (i = 0; i < elem; i++) { \
>>> + r = r << 8; \
>>> + if (index + i <= 15) { \
>>> + r = r | b->u8[index + i]; \
>>> + } \
>>> + } \
>>> + return r; \
>>> +}
>>> +#else
>>> +#define VEXTULX_DO(name, elem) \
>>> +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
>>> +{ \
>>> + target_ulong r = 0; \
>>> + int i; \
>>> + int index = 15 - (a & 0xf); \
>>> + for (i = 0; i < elem; i++) { \
>>> + r = r << 8; \
>>> + if (index - i >= 0) { \
>>> + r = r | b->u8[index - i]; \
>>> + } \
>>> + } \
>>> + return r; \
>>> +}
>>> +#endif
>>> +
>>> +VEXTULX_DO(vextublx, 1)
>>> +VEXTULX_DO(vextuhlx, 2)
>>> +VEXTULX_DO(vextuwlx, 4)
>>> +#undef VEXTULX_DO
>> Ew.
>>
>> This should be one 128-bit shift and one and.
>>
>> Since the shift amount is a multiple of 8, the 128-bit shift for
>> vextub[lr]x
>> does not need to cross a double-word boundary, and so can be
>> decomposed into
>> one 64-bit shift of (count & 64 ? hi : lo).
>>
>> For vextu[hw]lr]x, you'd need to do the whole left-shift,
>> right-shift, or thing.
>>
>> But still, fantastically better than a loop.
> Ack. Will send an updated patch.
Attached updated patch.
>>
>>
>> r~
>>
>>
>
--
Thanks
Rajalakshmi S
[-- Attachment #2: 0001-target-ppc-add-vextu-bhw-lx-instructions.patch --]
[-- Type: text/x-patch, Size: 7387 bytes --]
>From 59b96e11dd4c649ba9dbf0435439f717b931530f Mon Sep 17 00:00:00 2001
From: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Date: Mon, 24 Oct 2016 11:36:33 +0530
Subject: [PATCH 1/2] target-ppc: add vextu[bhw]lx instructions
vextublx: Vector Extract Unsigned Byte Left
vextuhlx: Vector Extract Unsigned Halfword Left
vextuwlx: Vector Extract Unsigned Word Left
Signed-off-by: Avinesh Kumar <avinesku@linux.vnet.ibm.com>
Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
---
target-ppc/helper.h | 3 ++
target-ppc/int_helper.c | 63 +++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 18 ++++++++++
target-ppc/translate/vmx-ops.inc.c | 4 ++-
4 files changed, 87 insertions(+), 1 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 04c6421..8551568 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -357,6 +357,9 @@ DEF_HELPER_3(vpmsumb, void, avr, avr, avr)
DEF_HELPER_3(vpmsumh, void, avr, avr, avr)
DEF_HELPER_3(vpmsumw, void, avr, avr, avr)
DEF_HELPER_3(vpmsumd, void, avr, avr, avr)
+DEF_HELPER_2(vextublx, tl, tl, avr)
+DEF_HELPER_2(vextuhlx, tl, tl, avr)
+DEF_HELPER_2(vextuwlx, tl, tl, avr)
DEF_HELPER_2(vsbox, void, avr, avr)
DEF_HELPER_3(vcipher, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 5aee0a8..2b28848 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1742,6 +1742,69 @@ void helper_vlogefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
}
}
+#define EXTRACT128(value, start, length) \
+ ((value >> start) & (~(__uint128_t)0 >> (128 - length)))
+
+#if defined(HOST_WORDS_BIGENDIAN)
+# if defined (CONFIG_INT128) \
+# define VEXTULX_DO(name, elem) \
+target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
+{ \
+ target_ulong r = 0; \
+ int index = (a & 0xf) * 8; \
+ r = EXTRACT128(b->u128, index, elem * 8); \
+ return r; \
+}
+# else
+# define VEXTULX_DO(name, elem) \
+target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
+{ \
+ target_ulong r = 0; \
+ int i; \
+ int index = a & 0xf; \
+ for (i = 0; i < elem; i++) { \
+ r = r << 8; \
+ if (index + i <= 15) { \
+ r = r | b->u8[index + i]; \
+ } \
+ } \
+ return r; \
+}
+# endif
+#else
+# if defined (CONFIG_INT128)
+# define VEXTULX_DO(name, elem) \
+target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
+{ \
+ target_ulong r = 0; \
+ int size = elem * 8; \
+ int index = (15 - (a & 0xf) + 1) * 8; \
+ r = EXTRACT128(b->u128, (index - size), size); \
+ return r; \
+}
+# else
+# define VEXTULX_DO(name, elem) \
+target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
+{ \
+ target_ulong r = 0; \
+ int i; \
+ int index = 15 - (a & 0xf); \
+ for (i = 0; i < elem; i++) { \
+ r = r << 8; \
+ if (index - i >= 0) { \
+ r = r | b->u8[index - i]; \
+ } \
+ } \
+ return r; \
+}
+# endif
+#endif
+
+VEXTULX_DO(vextublx, 1)
+VEXTULX_DO(vextuhlx, 2)
+VEXTULX_DO(vextuwlx, 4)
+#undef VEXTULX_DO
+
/* The specification says that the results are undefined if all of the
* shift counts are not identical. We check to make sure that they are
* to conform to what real hardware appears to do. */
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index c8998f3..0a9d609 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -276,6 +276,19 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
} \
}
+#define GEN_VXFORM_HETRO(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv_ptr rb; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
+ tcg_temp_free_ptr(rb); \
+}
+
GEN_VXFORM(vaddubm, 0, 0);
GEN_VXFORM(vadduhm, 0, 1);
GEN_VXFORM(vadduwm, 0, 2);
@@ -441,6 +454,11 @@ GEN_VXFORM_ENV(vaddfp, 5, 0);
GEN_VXFORM_ENV(vsubfp, 5, 1);
GEN_VXFORM_ENV(vmaxfp, 5, 16);
GEN_VXFORM_ENV(vminfp, 5, 17);
+GEN_VXFORM_HETRO(vextublx, 6, 24)
+GEN_VXFORM_HETRO(vextuhlx, 6, 25)
+GEN_VXFORM_HETRO(vextuwlx, 6, 26)
+GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
+ vextuwlx, PPC_NONE, PPC2_ISA300)
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c
index 68cba3e..70dc250 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -91,8 +91,10 @@ GEN_VXFORM(vmrghw, 6, 2),
GEN_VXFORM(vmrglb, 6, 4),
GEN_VXFORM(vmrglh, 6, 5),
GEN_VXFORM(vmrglw, 6, 6),
+GEN_VXFORM_300(vextublx, 6, 24),
+GEN_VXFORM_300(vextuhlx, 6, 25),
+GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_207(vmrgew, 6, 30),
-GEN_VXFORM_207(vmrgow, 6, 26),
GEN_VXFORM(vmuloub, 4, 0),
GEN_VXFORM(vmulouh, 4, 1),
GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
--
1.7.1
next prev parent reply other threads:[~2016-10-25 4:31 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-28 5:45 [Qemu-devel] [PATCH 0/6] POWER9 TCG enablement - part5 Rajalakshmi Srinivasaraghavan
2016-09-28 5:45 ` [Qemu-devel] [PATCH 1/6] target-ppc: add vmul10[u, eu, cu, ecu]q instructions Rajalakshmi Srinivasaraghavan
2016-09-28 16:42 ` Richard Henderson
2016-10-05 5:23 ` Rajalakshmi Srinivasaraghavan
2016-09-29 2:07 ` David Gibson
2016-09-29 4:00 ` Richard Henderson
2016-09-29 4:24 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2016-09-28 5:45 ` [Qemu-devel] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions Rajalakshmi Srinivasaraghavan
2016-09-28 16:54 ` Richard Henderson
2016-10-05 5:21 ` Rajalakshmi Srinivasaraghavan
2016-10-25 4:31 ` Rajalakshmi Srinivasaraghavan [this message]
2016-09-28 5:45 ` [Qemu-devel] [PATCH 3/6] target-ppc: add vextu[bhw]rx instructions Rajalakshmi Srinivasaraghavan
2016-10-25 4:32 ` Rajalakshmi Srinivasaraghavan
2016-09-28 5:45 ` [Qemu-devel] [PATCH 4/6] target-ppc: fix invalid mask - cmpl, bctar Rajalakshmi Srinivasaraghavan
2016-09-29 2:22 ` David Gibson
2016-09-28 5:45 ` [Qemu-devel] [PATCH 5/6] target-ppc: add vector compare not equal instructions Rajalakshmi Srinivasaraghavan
2016-09-28 17:01 ` Richard Henderson
2016-09-29 2:22 ` David Gibson
2016-09-28 5:45 ` [Qemu-devel] [PATCH 6/6] target-ppc: add vclzlsbb/vctzlsbb instructions Rajalakshmi Srinivasaraghavan
2016-09-28 17:08 ` Richard Henderson
2016-09-29 2:23 ` David Gibson
2016-09-29 2:25 ` David Gibson
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