From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-arm] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1
Date: Thu, 6 Oct 2016 18:55:09 +0200 [thread overview]
Message-ID: <20161006165509.GA28109@toto> (raw)
In-Reply-To: <1475760067-25756-2-git-send-email-peter.maydell@linaro.org>
On Thu, Oct 06, 2016 at 02:21:05PM +0100, Peter Maydell wrote:
> MDCCINT_EL1 is part of the DCC debugger communication
> channel between the CPU and an attached external debugger.
> QEMU doesn't implement this, but since Linux may try
> to access this register we need to provide at least
> a dummy implementation.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target-arm/helper.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 25f612d..23792ab 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -4060,6 +4060,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
> .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
> .access = PL1_RW, .accessfn = access_tda,
> .type = ARM_CP_NOP },
> + /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
> + * Channel but Linux may try to access this register. The 32-bit
> + * alias is DBGDCCINT.
> + */
> + { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
> + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
> + .access = PL1_RW, .accessfn = access_tda,
> + .type = ARM_CP_NOP },
> REGINFO_SENTINEL
> };
>
> --
> 2.7.4
>
WARNING: multiple messages have this Message-ID (diff)
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1
Date: Thu, 6 Oct 2016 18:55:09 +0200 [thread overview]
Message-ID: <20161006165509.GA28109@toto> (raw)
In-Reply-To: <1475760067-25756-2-git-send-email-peter.maydell@linaro.org>
On Thu, Oct 06, 2016 at 02:21:05PM +0100, Peter Maydell wrote:
> MDCCINT_EL1 is part of the DCC debugger communication
> channel between the CPU and an attached external debugger.
> QEMU doesn't implement this, but since Linux may try
> to access this register we need to provide at least
> a dummy implementation.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target-arm/helper.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 25f612d..23792ab 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -4060,6 +4060,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
> .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
> .access = PL1_RW, .accessfn = access_tda,
> .type = ARM_CP_NOP },
> + /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
> + * Channel but Linux may try to access this register. The 32-bit
> + * alias is DBGDCCINT.
> + */
> + { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
> + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
> + .access = PL1_RW, .accessfn = access_tda,
> + .type = ARM_CP_NOP },
> REGINFO_SENTINEL
> };
>
> --
> 2.7.4
>
next prev parent reply other threads:[~2016-10-06 16:56 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-06 13:21 [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Peter Maydell
2016-10-06 13:21 ` Peter Maydell
2016-10-06 13:21 ` [Qemu-arm] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1 Peter Maydell
2016-10-06 13:21 ` [Qemu-devel] " Peter Maydell
2016-10-06 16:55 ` Edgar E. Iglesias [this message]
2016-10-06 16:55 ` Edgar E. Iglesias
2016-10-06 13:21 ` [Qemu-devel] [PATCH 2/3] target-arm: Add trace events for the generic timers Peter Maydell
2016-10-06 13:21 ` Peter Maydell
2016-10-06 16:55 ` Edgar E. Iglesias
2016-10-06 13:21 ` [Qemu-arm] [PATCH 3/3] hw/intc/arm_gicv3: Fix ICC register tracepoints Peter Maydell
2016-10-06 13:21 ` [Qemu-devel] " Peter Maydell
2016-10-06 16:59 ` [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support Edgar E. Iglesias
2016-10-06 17:48 ` [Qemu-arm] " Peter Maydell
2016-10-06 17:48 ` [Qemu-devel] " Peter Maydell
2016-10-06 17:59 ` [Qemu-arm] " Peter Maydell
2016-10-06 17:59 ` [Qemu-devel] " Peter Maydell
2016-10-11 9:15 ` no-reply
2016-10-11 9:15 ` no-reply
2016-10-11 9:19 ` [Qemu-arm] " Peter Maydell
2016-10-11 9:19 ` Peter Maydell
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