From: jan.glauber@caviumnetworks.com (Jan Glauber)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 0/5] Cavium ThunderX uncore PMU support
Date: Fri, 28 Oct 2016 17:36:46 +0200 [thread overview]
Message-ID: <20161028153646.GA11371@hardcore> (raw)
In-Reply-To: <20161028151749.GG14402@arm.com>
On Fri, Oct 28, 2016 at 04:17:49PM +0100, Will Deacon wrote:
> On Thu, Oct 20, 2016 at 01:23:51PM +0200, Jan Glauber wrote:
> > On Thu, Oct 20, 2016 at 12:37:07PM +0200, Peter Zijlstra wrote:
> > > On Thu, Oct 20, 2016 at 11:30:36AM +0200, Jan Glauber wrote:
> > > > Note:
> > > > I'm using perf_sw_context in difference to perf_invalid_context
> > > > (see WARN_ON in perf_pmu_register). Reason is that with perf_invalid_context
> > > > add() is never called and the counter results are shown as "unsupported" by
> > > > perf. With perf_sw_context everything works as expected.
> > >
> > > What?! All the uncore PMUs use perf_invalid_context. What doesn't work
> > > for you?
> >
> > OK, so using perf_invalid_context and "-a" seems to work.
> >
> > But I must say that I hate that from a user perspective. The user needs to know about
> > the type of PMU behind the event and then provide "-a" or get a "<not supported"
> > as counter value?
>
> Sure, but in the interest of getting *something* merged, can we start
> off using perf_invalid_context and then have the discussion about whether
> or not this can be extended later on, please? If your PMU is a shared
> resource amongst CPUs, it maybe that all you want is a better error
> message from the perf tool (but again, this can come later!).
If that is the only obstacle I can repost with perf_sw_context (or do a
follow-up patch). After all it works, it is just "clueless" people like
me that are not aware of the required switches.
--Jan
> Will
WARNING: multiple messages have this Message-ID (diff)
From: Jan Glauber <jan.glauber@caviumnetworks.com>
To: Will Deacon <will.deacon@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Mark Rutland <mark.rutland@arm.com>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 0/5] Cavium ThunderX uncore PMU support
Date: Fri, 28 Oct 2016 17:36:46 +0200 [thread overview]
Message-ID: <20161028153646.GA11371@hardcore> (raw)
In-Reply-To: <20161028151749.GG14402@arm.com>
On Fri, Oct 28, 2016 at 04:17:49PM +0100, Will Deacon wrote:
> On Thu, Oct 20, 2016 at 01:23:51PM +0200, Jan Glauber wrote:
> > On Thu, Oct 20, 2016 at 12:37:07PM +0200, Peter Zijlstra wrote:
> > > On Thu, Oct 20, 2016 at 11:30:36AM +0200, Jan Glauber wrote:
> > > > Note:
> > > > I'm using perf_sw_context in difference to perf_invalid_context
> > > > (see WARN_ON in perf_pmu_register). Reason is that with perf_invalid_context
> > > > add() is never called and the counter results are shown as "unsupported" by
> > > > perf. With perf_sw_context everything works as expected.
> > >
> > > What?! All the uncore PMUs use perf_invalid_context. What doesn't work
> > > for you?
> >
> > OK, so using perf_invalid_context and "-a" seems to work.
> >
> > But I must say that I hate that from a user perspective. The user needs to know about
> > the type of PMU behind the event and then provide "-a" or get a "<not supported"
> > as counter value?
>
> Sure, but in the interest of getting *something* merged, can we start
> off using perf_invalid_context and then have the discussion about whether
> or not this can be extended later on, please? If your PMU is a shared
> resource amongst CPUs, it maybe that all you want is a better error
> message from the perf tool (but again, this can come later!).
If that is the only obstacle I can repost with perf_sw_context (or do a
follow-up patch). After all it works, it is just "clueless" people like
me that are not aware of the required switches.
--Jan
> Will
next prev parent reply other threads:[~2016-10-28 15:36 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-20 9:30 [PATCH v3 0/5] Cavium ThunderX uncore PMU support Jan Glauber
2016-10-20 9:30 ` Jan Glauber
2016-10-20 9:30 ` [PATCH v3 1/5] arm64: perf: Basic uncore counter support for Cavium ThunderX SOC Jan Glauber
2016-10-20 9:30 ` Jan Glauber
2016-10-20 9:30 ` [PATCH v3 2/5] arm64: perf: Cavium ThunderX L2C TAD uncore support Jan Glauber
2016-10-20 9:30 ` Jan Glauber
2016-10-20 9:30 ` [PATCH v3 3/5] arm64: perf: Cavium ThunderX L2C CBC " Jan Glauber
2016-10-20 9:30 ` Jan Glauber
2016-10-20 9:30 ` [PATCH v3 4/5] arm64: perf: Cavium ThunderX LMC " Jan Glauber
2016-10-20 9:30 ` Jan Glauber
2016-10-20 9:30 ` [PATCH v3 5/5] arm64: perf: Cavium ThunderX OCX TLK " Jan Glauber
2016-10-20 9:30 ` Jan Glauber
2016-10-20 10:37 ` [PATCH v3 0/5] Cavium ThunderX uncore PMU support Peter Zijlstra
2016-10-20 10:37 ` Peter Zijlstra
2016-10-20 10:44 ` Mark Rutland
2016-10-20 10:44 ` Mark Rutland
2016-10-20 10:55 ` Peter Zijlstra
2016-10-20 10:55 ` Peter Zijlstra
2016-10-20 11:01 ` Mark Rutland
2016-10-20 11:01 ` Mark Rutland
2016-10-20 11:02 ` Jan Glauber
2016-10-20 11:02 ` Jan Glauber
2016-10-20 11:23 ` Jan Glauber
2016-10-20 11:23 ` Jan Glauber
2016-10-20 11:30 ` Peter Zijlstra
2016-10-20 11:30 ` Peter Zijlstra
2016-10-28 15:17 ` Will Deacon
2016-10-28 15:17 ` Will Deacon
2016-10-28 15:36 ` Jan Glauber [this message]
2016-10-28 15:36 ` Jan Glauber
2016-10-28 15:42 ` Mark Rutland
2016-10-28 15:42 ` Mark Rutland
2016-10-20 10:41 ` Mark Rutland
2016-10-20 10:41 ` Mark Rutland
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