* [PATCH 00/76] DAL Patches Nov 21, 2016
@ 2016-11-21 23:00 Harry Wentland
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
DAL patches for the last 4 weeks.
- a bunch of cleanup to get rid of components like asic_capability
and adapter service
- some cleanup to use same HW programming sequences on different DCEs
with DCE specific register definitions
- some other minor bug fixes
I will start sending these on a regular basis, hopefully daily but at least twice a week.
Amy Zhang (1):
drm/amd/dal: PSR second monitor blackout fix
Andrey Grodzovsky (3):
drm/amd/dal: Refactor i2c_hw_engine
drm/amd/dal: Modify regsiter access to use macro.
drm/amd/dal: Fix MST crash by skipping branch connector.
Ding Wang (1):
drm/amd/dal: Remove unused function from dc
Dmytro Laktyushkin (7):
drm/amd/dal: bring all of dc under a single log category table
drm/amd/dal: fix dc creation
drm/amd/dal: add chroma support to program_size_and_rotation
drm/amd/dal: add meta address to video address struct
drm/amd/dal: add stoney bounding box to bw_calcs
drm/amd/dal: fix initial bw_calc parameters
drm/amd/dal: disable break_to_debugger for bandwidth failures in diags
Harry Wentland (10):
drm/amd/dal: Remove wireless_data_source
drm/amd/dal: Move gpio_service out of adapter_service
drm/amd/dal: Fix warning about comparing different types
drm/amd/dal: Use future proof reg access for HPD and DDC
drm/amd/dal: Remove adapter service dependency in power_down
drm/amd/dal: Make set_overscan_blank_color optional
drm/amd/dal: Fix null pointer missed in earlier refactor
drm/amd/dal: Don't read I2C_DATA register when in write mode
drm/amd/dal: Make bunch of scaler structs static
drm/amd/dal: Expose Polaris validate functions
Hersen Wu (2):
drm/amd/dal: modify DCE HW sequence to be re-usable for next gen HW
drm/amd/dal: Expose some HWS functions so we can re-use them
Jordan Lazare (1):
drm/amd/dal: Remove unnecessary increment in scaler ratio calculation
Tony Cheng (27):
drm/amd/dal: clean up asic cap
drm/amd/dal: DCC support
drm/amd/dal: refactor bios scratch register access
drm/amd/dal: remove unnessary AS dependency
drm/amd/dal: remove AS dependency from i2c_aux
drm/amd/dal: remove dal_adapter_service_get_integrated_info
drm/amd/dal: instantiate i2caux outside of AS
drm/amd/dal: fix DDC pad mode detection logic
drm/amd/dal: remove supported_stream_engines
drm/amd/dal: remove unnessary adapter service functions
drm/amd/dal: remove dal_override_parameters
drm/amd/dal: remove unnessary adapter service functions
drm/amd/dal: remove unnessary adapter service functions
drm/amd/dal: fix typo disalbe_dfs_bypass
drm/amd/dal: remove dal_adapter_service_should_optimize
drm/amd/dal: remove dal_adapter_service_get_feature_value
drm/amd/dal: remove adapter_service from
drm/amd/dal: remove adapter_service dependency
drm/amd/dal: remove SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT
drm/amd/dal: remove adapter_service and asic_capability
drm/amd/dal: consolidate DCE hw_sequencer
drm/amd/dal: consolidate DCE hw_sequencer
drm/amd/dal: debug options
drm/amd/dal: remove dc_clock_gating in gpu
drm/amd/dal: dce_crtc_switch_to_clk_src
drm/amd/dal: include dm_services.h in reg_helper.h
drm/amd/dal: consolidate mem_input
Vitaly Prosyak (3):
drm/amd/dal: rotation and mirror support
drm/amd/dal: Rotation and mirror support
drm/amd/dal: Rotation and mirror support
Wenjing Liu (7):
drm/amd/dal: Lower max link cap by reportedLinkCap
drm/amd/dal: Allow timing with req_bw equal to max_bw
drm/amd/dal: Perform link training in dp_retrain_link
drm/amd/dal: Poll AUX_SW_DONE to 0 before AUX_SW_GO
drm/amd/dal: Fallback LT without retry in verify_link_cap
drm/amd/dal: Disable bit depth reduction in set link test pattern
drm/amd/dal: Handle AUX error during RECIEVE state of transaction
Wesley Chalmers (1):
drm/amd/dal: Hard-coded LB_MEMORY_SIZE
Yongqiang Sun (5):
drm/amd/dal: Remove adapter service dependency from dc_link
drm/amd/dal: Fixed wrong return value check condition.
drm/amd/dal: Add surface log to dc
drm/amd/dal: Fixe linux compile error.
drm/amd/dal: Add reg check before access.
Zeyu Fan (8):
drm/amd/dal: Remove unused code in dce112 hwss.
drm/amd/dal: Consolidate link encoder from each dce version.
drm/amd/dal: Remove adapter service from display clock
drm/amd/dal: Pass in shift and mask for stream encoder.
drm/amd/dal: Update stream_encoder programming sequence
drm/amd/dal: Add YCBCR420 to stream encoder
drm/amd/dal: Implement DCHUB interface
drm/amd/dal: Fix typo in mem_input
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 22 -
.../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c | 60 -
.../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 6 +-
drivers/gpu/drm/amd/dal/dc/Makefile | 4 +-
drivers/gpu/drm/amd/dal/dc/adapter/Makefile | 10 -
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 1281 --------------------
.../gpu/drm/amd/dal/dc/adapter/adapter_service.h | 60 -
.../drm/amd/dal/dc/adapter/wireless_data_source.c | 208 ----
.../drm/amd/dal/dc/adapter/wireless_data_source.h | 79 --
.../gpu/drm/amd/dal/dc/asic_capability/Makefile | 50 -
.../amd/dal/dc/asic_capability/asic_capability.c | 192 ---
.../dc/asic_capability/carrizo_asic_capability.c | 147 ---
.../dc/asic_capability/carrizo_asic_capability.h | 36 -
.../dc/asic_capability/hawaii_asic_capability.c | 149 ---
.../dc/asic_capability/hawaii_asic_capability.h | 37 -
.../dc/asic_capability/polaris10_asic_capability.c | 146 ---
.../dc/asic_capability/polaris10_asic_capability.h | 36 -
.../dal/dc/asic_capability/tonga_asic_capability.c | 144 ---
.../dal/dc/asic_capability/tonga_asic_capability.h | 18 -
drivers/gpu/drm/amd/dal/dc/basics/Makefile | 3 +-
drivers/gpu/drm/amd/dal/dc/basics/log_helpers.c | 100 ++
drivers/gpu/drm/amd/dal/dc/basics/logger.c | 676 ++---------
drivers/gpu/drm/amd/dal/dc/basics/logger.h | 4 +-
drivers/gpu/drm/amd/dal/dc/bios/Makefile | 6 -
drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 72 +-
.../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c | 65 +-
.../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h | 26 +-
.../gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h | 6 -
.../dal/dc/bios/dce110/bios_parser_helper_dce110.c | 118 --
.../dal/dc/bios/dce110/bios_parser_helper_dce110.h | 34 -
.../dal/dc/bios/dce112/bios_parser_helper_dce112.c | 81 --
.../dal/dc/bios/dce112/bios_parser_helper_dce112.h | 34 -
.../dal/dc/bios/dce80/bios_parser_helper_dce80.c | 67 -
drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 114 +-
drivers/gpu/drm/amd/dal/dc/core/dc.c | 225 ++--
drivers/gpu/drm/amd/dal/dc/core/dc_debug.c | 270 +++++
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 103 +-
drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 39 +-
drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 168 +--
drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 10 +-
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 60 +-
drivers/gpu/drm/amd/dal/dc/core/dc_target.c | 30 +-
drivers/gpu/drm/amd/dal/dc/dc.h | 77 +-
drivers/gpu/drm/amd/dal/dc/dc_bios_types.h | 16 +-
drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h | 1 -
drivers/gpu/drm/amd/dal/dc/dc_helper.c | 28 +
drivers/gpu/drm/amd/dal/dc/dc_hw_types.h | 48 +-
drivers/gpu/drm/amd/dal/dc/dc_types.h | 101 +-
drivers/gpu/drm/amd/dal/dc/dce/Makefile | 3 +-
.../gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.h | 182 ---
drivers/gpu/drm/amd/dal/dc/dce/dce_audio.c | 11 +-
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c | 195 +++
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h | 250 ++++
.../dce_link_encoder.c} | 109 +-
.../dce_link_encoder.h} | 0
drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.c | 193 +++
drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h | 134 ++
...ce110_stream_encoder.c => dce_stream_encoder.c} | 290 ++---
.../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h | 560 +++++++++
drivers/gpu/drm/amd/dal/dc/dce100/Makefile | 2 +-
.../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c | 159 ---
.../drm/amd/dal/dc/dce100/dce100_link_encoder.c | 92 --
.../drm/amd/dal/dc/dce100/dce100_link_encoder.h | 42 -
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 133 +-
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.h | 2 -
drivers/gpu/drm/amd/dal/dc/dce110/Makefile | 2 +-
.../drm/amd/dal/dc/dce110/dce110_clock_source.c | 49 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c | 76 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_compressor.h | 5 +-
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 431 +++----
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.h | 26 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 312 +----
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 27 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c | 12 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h | 3 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c | 4 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 194 ++-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.h | 2 -
.../amd/dal/dc/dce110/dce110_timing_generator.c | 7 +-
.../amd/dal/dc/dce110/dce110_timing_generator.h | 1 -
.../amd/dal/dc/dce110/dce110_timing_generator_v.c | 22 +-
.../amd/dal/dc/dce110/dce110_timing_generator_v.h | 1 -
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.c | 2 +
.../amd/dal/dc/dce110/dce110_transform_bit_depth.c | 26 +-
.../drm/amd/dal/dc/dce110/dce110_transform_scl.c | 22 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c | 2 +-
drivers/gpu/drm/amd/dal/dc/dce112/Makefile | 2 +-
.../drm/amd/dal/dc/dce112/dce112_clock_source.c | 4 +-
.../gpu/drm/amd/dal/dc/dce112/dce112_compressor.c | 75 +-
.../gpu/drm/amd/dal/dc/dce112/dce112_compressor.h | 5 +-
.../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c | 214 ----
.../drm/amd/dal/dc/dce112/dce112_link_encoder.c | 191 ---
.../drm/amd/dal/dc/dce112/dce112_link_encoder.h | 41 -
.../gpu/drm/amd/dal/dc/dce112/dce112_mem_input.c | 3 +-
.../gpu/drm/amd/dal/dc/dce112/dce112_mem_input.h | 1 -
.../drm/amd/dal/dc/dce112/dce112_opp_formatter.c | 3 +-
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 179 ++-
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.h | 18 +-
drivers/gpu/drm/amd/dal/dc/dce80/Makefile | 2 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_compressor.c | 77 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_compressor.h | 5 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c | 117 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c | 339 ------
.../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h | 39 -
drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c | 25 +-
drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h | 1 -
.../gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c | 4 +-
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 133 +-
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h | 2 -
.../drm/amd/dal/dc/dce80/dce80_timing_generator.c | 5 -
.../drm/amd/dal/dc/dce80/dce80_timing_generator.h | 1 -
drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c | 2 +
.../amd/dal/dc/dce80/dce80_transform_bit_depth.c | 10 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c | 8 +-
drivers/gpu/drm/amd/dal/dc/dm_helpers.h | 38 -
drivers/gpu/drm/amd/dal/dc/dm_services.h | 93 +-
drivers/gpu/drm/amd/dal/dc/dm_services_types.h | 32 +-
.../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c | 14 +-
.../drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.c | 3 +
drivers/gpu/drm/amd/dal/dc/gpio/ddc_regs.h | 8 +-
drivers/gpu/drm/amd/dal/dc/gpio/hpd_regs.h | 6 +-
drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c | 78 +-
drivers/gpu/drm/amd/dal/dc/gpu/Makefile | 6 +-
.../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c | 105 --
.../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h | 33 -
.../amd/dal/dc/gpu/dce110/display_clock_dce110.c | 82 +-
.../amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c | 89 --
.../amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h | 33 -
.../amd/dal/dc/gpu/dce112/display_clock_dce112.c | 66 +-
.../amd/dal/dc/gpu/dce112/display_clock_dce112.h | 3 +-
.../amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c | 52 -
.../amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h | 31 -
.../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c | 65 +-
.../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.h | 3 +-
drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c | 6 +-
drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h | 4 +-
.../drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.c | 22 +-
.../drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.h | 1 -
.../amd/dal/dc/i2caux/dce110/aux_engine_dce110.c | 9 +-
.../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c | 612 ++--------
.../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c | 22 +-
.../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h | 6 +-
.../drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.c | 55 +-
.../drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.h | 1 -
.../gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c | 8 +-
.../gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.h | 1 -
.../amd/dal/dc/i2caux/diagnostics/i2caux_diag.c | 6 +-
.../amd/dal/dc/i2caux/diagnostics/i2caux_diag.h | 1 -
drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c | 32 +-
drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h | 3 +-
drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h | 1 +
drivers/gpu/drm/amd/dal/dc/inc/compressor.h | 1 +
drivers/gpu/drm/amd/dal/dc/inc/core_dc.h | 1 +
drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 7 +-
drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h | 2 -
drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h | 4 +-
drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h | 19 +-
drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h | 3 +-
drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h | 1 +
drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 31 +-
drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h | 121 +-
drivers/gpu/drm/amd/dal/dc/inc/resource.h | 13 +-
.../drm/amd/dal/dc/irq/dce110/irq_service_dce110.c | 12 +-
drivers/gpu/drm/amd/dal/dc/irq/irq_service.c | 12 +-
.../bios_parser_helper_dce80.h => os_types.h} | 38 +-
.../drm/amd/dal/dc/virtual/virtual_link_encoder.c | 2 -
.../amd/dal/dc/virtual/virtual_stream_encoder.c | 3 +-
.../amd/dal/include/adapter_service_interface.h | 149 +--
.../amd/dal/include/asic_capability_interface.h | 1 -
.../drm/amd/dal/include/asic_capability_types.h | 17 +-
.../drm/amd/dal/include/bios_parser_interface.h | 1 -
.../drm/amd/dal/include/display_clock_interface.h | 9 +-
drivers/gpu/drm/amd/dal/include/fixed31_32.h | 2 +
drivers/gpu/drm/amd/dal/include/fixed32_32.h | 3 +
.../drm/amd/dal/include/grph_object_ctrl_defs.h | 30 -
drivers/gpu/drm/amd/dal/include/grph_object_id.h | 16 -
drivers/gpu/drm/amd/dal/include/i2caux_interface.h | 2 -
.../gpu/drm/amd/dal/include/link_service_types.h | 1 -
drivers/gpu/drm/amd/dal/include/logger_interface.h | 130 +-
drivers/gpu/drm/amd/dal/include/logger_types.h | 352 +-----
180 files changed, 4101 insertions(+), 8868 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/Makefile
delete mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/log_helpers.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_debug.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
rename drivers/gpu/drm/amd/dal/dc/{dce110/dce110_link_encoder.c => dce/dce_link_encoder.c} (96%)
rename drivers/gpu/drm/amd/dal/dc/{dce110/dce110_link_encoder.h => dce/dce_link_encoder.h} (100%)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h
rename drivers/gpu/drm/amd/dal/dc/dce/{dce110_stream_encoder.c => dce_stream_encoder.c} (87%)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h
rename drivers/gpu/drm/amd/dal/dc/{bios/dce80/bios_parser_helper_dce80.h => os_types.h} (59%)
--
2.10.1
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* [PATCH 01/76] drm/amd/dal: bring all of dc under a single log category table
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 02/76] drm/amd/dal: clean up asic cap Harry Wentland
` (75 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c | 60 --
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 12 +-
.../amd/dal/dc/asic_capability/asic_capability.c | 4 +-
.../dc/asic_capability/hawaii_asic_capability.c | 4 +-
drivers/gpu/drm/amd/dal/dc/basics/Makefile | 3 +-
drivers/gpu/drm/amd/dal/dc/basics/log_helpers.c | 100 +++
drivers/gpu/drm/amd/dal/dc/basics/logger.c | 674 +++------------------
drivers/gpu/drm/amd/dal/dc/basics/logger.h | 4 +-
drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 4 +-
drivers/gpu/drm/amd/dal/dc/core/dc.c | 27 +-
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 59 +-
drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 6 +-
drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 68 +--
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 4 +-
drivers/gpu/drm/amd/dal/dc/core/dc_target.c | 30 +-
drivers/gpu/drm/amd/dal/dc/dc.h | 5 +-
.../gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.c | 6 +-
drivers/gpu/drm/amd/dal/dc/dce/dce_audio.c | 6 +-
.../drm/amd/dal/dc/dce110/dce110_clock_source.c | 48 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c | 48 +-
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 14 +-
.../drm/amd/dal/dc/dce110/dce110_link_encoder.c | 52 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 4 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c | 4 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 25 +-
.../amd/dal/dc/dce110/dce110_timing_generator.c | 3 +-
.../amd/dal/dc/dce110/dce110_timing_generator_v.c | 18 +-
.../amd/dal/dc/dce110/dce110_transform_bit_depth.c | 20 +-
.../drm/amd/dal/dc/dce112/dce112_clock_source.c | 4 +-
.../gpu/drm/amd/dal/dc/dce112/dce112_compressor.c | 48 +-
.../drm/amd/dal/dc/dce112/dce112_opp_formatter.c | 3 +-
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 25 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_compressor.c | 48 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c | 12 +-
drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c | 4 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c | 4 +-
.../amd/dal/dc/dce80/dce80_transform_bit_depth.c | 8 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c | 8 +-
drivers/gpu/drm/amd/dal/dc/dm_helpers.h | 38 --
drivers/gpu/drm/amd/dal/dc/dm_services_types.h | 32 +-
.../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c | 2 +-
.../amd/dal/dc/gpu/dce110/display_clock_dce110.c | 28 +-
.../amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c | 2 +-
.../amd/dal/dc/gpu/dce112/display_clock_dce112.c | 28 +-
.../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c | 12 +-
.../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c | 6 +-
.../drm/amd/dal/dc/irq/dce110/irq_service_dce110.c | 12 +-
drivers/gpu/drm/amd/dal/dc/irq/irq_service.c | 12 +-
drivers/gpu/drm/amd/dal/dc/os_types.h | 61 ++
drivers/gpu/drm/amd/dal/include/fixed31_32.h | 2 +
drivers/gpu/drm/amd/dal/include/fixed32_32.h | 3 +
drivers/gpu/drm/amd/dal/include/logger_interface.h | 116 ++--
drivers/gpu/drm/amd/dal/include/logger_types.h | 351 ++---------
53 files changed, 558 insertions(+), 1623 deletions(-)
create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/log_helpers.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/os_types.h
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
index 58863ce10304..e503677110c3 100644
--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
@@ -42,12 +42,6 @@
#include "dm_helpers.h"
-/* Maximum line char number for connectivity log,
- * in case of output EDID, needs at least 256x3 bytes plus some other
- * message, so set line size to 896.
- */
-#define CONN_MAX_LINE_SIZE 896
-
/* dm_helpers_parse_edid_caps
*
* Parse edid caps
@@ -487,57 +481,3 @@ bool dm_helpers_submit_i2c(
return result;
}
-
-void dm_helper_conn_log(struct dc_context *ctx,
- const struct dc_link *link,
- uint8_t *hex_data,
- int hex_data_count,
- enum conn_event event,
- const char *msg,
- ...)
-{
- struct amdgpu_device *adev = ctx->driver_context;
- struct drm_device *dev = adev->ddev;
- struct amdgpu_connector *aconnector = get_connector_for_link(dev, link);
- char buffer[CONN_MAX_LINE_SIZE] = { 0 };
- va_list args;
- int size;
- enum log_minor minor = event;
-
- if (!aconnector) {
- DRM_ERROR("Failed to found connector for link!");
- return;
- }
-
- va_start(args, msg);
-
- sprintf(buffer, "[%s] ", aconnector->base.name);
-
- size = strlen(buffer);
-
- size += dm_log_to_buffer(
- &buffer[size], CONN_MAX_LINE_SIZE, msg, args);
-
- if (buffer[strlen(buffer) - 1] == '\n') {
- buffer[strlen(buffer) - 1] = '\0';
- size--;
- }
-
- if (hex_data_count > (CONN_MAX_LINE_SIZE - size))
- return;
-
- if (hex_data) {
- int i;
-
- for (i = 0; i < hex_data_count; i++)
- sprintf(&buffer[size + i * 3], "%2.2X ", hex_data[i]);
- }
-
- strcat(buffer, "^\n");
-
- dal_logger_write(ctx->logger,
- LOG_MAJOR_CONNECTIVITY,
- minor,
- buffer);
- va_end(args);
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index c7904ca92ddf..57228a87d5a1 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -221,9 +221,7 @@ static void initialize_backlight_caps(
struct dc_bios *dcb = as->ctx->dc_bios;
if (!(PM_GET_EXTENDED_BRIGHNESS_CAPS & as->platform_methods_mask)) {
- dal_logger_write(as->ctx->logger,
- LOG_MAJOR_BACKLIGHT,
- LOG_MINOR_BACKLIGHT_BRIGHTESS_CAPS,
+ dm_logger_write(as->ctx->logger, LOG_BACKLIGHT,
"This method is not supported\n");
return;
}
@@ -362,16 +360,12 @@ static void log_overriden_features(
uint32_t value)
{
if (bool_feature)
- dal_logger_write(as->ctx->logger,
- LOG_MAJOR_FEATURE_OVERRIDE,
- LOG_MINOR_FEATURE_OVERRIDE,
+ dm_logger_write(as->ctx->logger, LOG_FEATURE_OVERRIDE,
"Overridden %s is %s now\n",
feature_name,
(value == 0) ? "disabled" : "enabled");
else
- dal_logger_write(as->ctx->logger,
- LOG_MAJOR_FEATURE_OVERRIDE,
- LOG_MINOR_FEATURE_OVERRIDE,
+ dm_logger_write(as->ctx->logger, LOG_FEATURE_OVERRIDE,
"Overridden %s new value: %d\n",
feature_name,
value);
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
index 540372b4626f..3e83b1e4ab9e 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
@@ -118,9 +118,7 @@ static bool construct(
}
if (false == asic_supported) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_MASK_ALL,
+ dm_logger_write(ctx->logger, LOG_ERROR,
"%s: ASIC not supported!\n", __func__);
}
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
index 2913e572975c..d5eb323f5e87 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
@@ -94,9 +94,7 @@ void dal_hawaii_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
break;
default:
- dal_logger_write(cap->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_MASK_ALL,
+ dm_logger_write(cap->ctx->logger, LOG_ERROR,
"%s:Unrecognized memory type!", __func__);
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
break;
diff --git a/drivers/gpu/drm/amd/dal/dc/basics/Makefile b/drivers/gpu/drm/amd/dal/dc/basics/Makefile
index 93e23714e411..ab37b670a6d3 100644
--- a/drivers/gpu/drm/amd/dal/dc/basics/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/basics/Makefile
@@ -3,7 +3,8 @@
# It provides the general basic services required by other DAL
# subcomponents.
-BASICS = conversion.o fixpt31_32.o fixpt32_32.o grph_object_id.o logger.o register_logger.o signal_types.o vector.o
+BASICS = conversion.o fixpt31_32.o fixpt32_32.o grph_object_id.o \
+ logger.o log_helpers.o register_logger.o signal_types.o vector.o
AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
diff --git a/drivers/gpu/drm/amd/dal/dc/basics/log_helpers.c b/drivers/gpu/drm/amd/dal/dc/basics/log_helpers.c
new file mode 100644
index 000000000000..61f36a7f322b
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/basics/log_helpers.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2012-16 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "core_types.h"
+#include "logger.h"
+#include "include/logger_interface.h"
+
+#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
+
+struct dc_signal_type_info {
+ enum signal_type type;
+ char name[MAX_NAME_LEN];
+};
+
+static const struct dc_signal_type_info signal_type_info_tbl[] = {
+ {SIGNAL_TYPE_NONE, "NC"},
+ {SIGNAL_TYPE_DVI_SINGLE_LINK, "DVI"},
+ {SIGNAL_TYPE_DVI_DUAL_LINK, "DDVI"},
+ {SIGNAL_TYPE_HDMI_TYPE_A, "HDMIA"},
+ {SIGNAL_TYPE_LVDS, "LVDS"},
+ {SIGNAL_TYPE_RGB, "VGA"},
+ {SIGNAL_TYPE_DISPLAY_PORT, "DP"},
+ {SIGNAL_TYPE_DISPLAY_PORT_MST, "MST"},
+ {SIGNAL_TYPE_EDP, "eDP"},
+ {SIGNAL_TYPE_WIRELESS, "Wireless"},
+ {SIGNAL_TYPE_VIRTUAL, "Virtual"}
+};
+
+void dc_conn_log(struct dc_context *ctx,
+ const struct dc_link *link,
+ uint8_t *hex_data,
+ int hex_data_count,
+ enum dc_log_type event,
+ const char *msg,
+ ...)
+{
+ int i;
+ va_list args;
+ struct log_entry entry = { 0 };
+ enum signal_type signal;
+
+ if (link->local_sink)
+ signal = link->local_sink->sink_signal;
+ else
+ signal = link->connector_signal;
+
+ if (link->type == dc_connection_mst_branch)
+ signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
+
+ dm_logger_open(ctx->logger, &entry, event);
+
+ for (i = 0; i < NUM_ELEMENTS(signal_type_info_tbl); i++)
+ if (signal == signal_type_info_tbl[i].type)
+ break;
+
+ dm_logger_append(&entry, "[%s][ConnIdx:%d] ",
+ signal_type_info_tbl[i].name,
+ link->link_index);
+
+ va_start(args, msg);
+ entry.buf_offset += dm_log_to_buffer(
+ &entry.buf[entry.buf_offset],
+ LOG_MAX_LINE_SIZE - entry.buf_offset,
+ msg, args);
+
+ if (entry.buf[strlen(entry.buf) - 1] == '\n') {
+ entry.buf[strlen(entry.buf) - 1] = '\0';
+ entry.buf_offset--;
+ }
+
+ if (hex_data)
+ for (i = 0; i < hex_data_count; i++)
+ dm_logger_append(&entry, "%2.2X ", hex_data[i]);
+
+ dm_logger_append(&entry, "^\n");
+ dm_logger_close(&entry);
+ va_end(args);
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
index 67a1ee241aa2..3c16fe1d91ff 100644
--- a/drivers/gpu/drm/amd/dal/dc/basics/logger.c
+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
@@ -22,276 +22,79 @@
* Authors: AMD
*
*/
-#include <stdarg.h>
#include "dm_services.h"
-#include "include/dal_types.h"
#include "include/logger_interface.h"
#include "logger.h"
-/* TODO: for now - empty, use DRM defines from dal services.
- Need to define appropriate levels of prints, and implement
- this component
-void dal_log(const char *format, ...)
-{
-}
-*/
-
-/* ----------- Logging Major/Minor names ------------ */
#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
-static const struct log_minor_info component_minor_info_tbl[] = {
- {LOG_MINOR_COMPONENT_LINK_SERVICE, "LS"},
- {LOG_MINOR_COMPONENT_DAL_INTERFACE, "DalIf"},
- {LOG_MINOR_COMPONENT_HWSS, "HWSS"},
- {LOG_MINOR_COMPONENT_ADAPTER_SERVICE, "AS"},
- {LOG_MINOR_COMPONENT_DISPLAY_SERVICE, "DS"},
- {LOG_MINOR_COMPONENT_TOPOLOGY_MANAGER, "TM"},
- {LOG_MINOR_COMPONENT_ENCODER, "Encoder"},
- {LOG_MINOR_COMPONENT_I2C_AUX, "I2cAux"},
- {LOG_MINOR_COMPONENT_AUDIO, "Audio"},
- {LOG_MINOR_COMPONENT_DISPLAY_CAPABILITY_SERVICE, "Dcs"},
- {LOG_MINOR_COMPONENT_DMCU, "Dmcu"},
- {LOG_MINOR_COMPONENT_GPU, "GPU"},
- {LOG_MINOR_COMPONENT_CONTROLLER, "Cntrlr"},
- {LOG_MINOR_COMPONENT_ISR, "ISR"},
- {LOG_MINOR_COMPONENT_BIOS, "BIOS"},
- {LOG_MINOR_COMPONENT_DC, "DC"},
- {LOG_MINOR_COMPONENT_IRQ_SERVICE, "IRQ SERVICE"},
-
-};
-
-static const struct log_minor_info hw_trace_minor_info_tbl[] = {
- {LOG_MINOR_HW_TRACE_MST, "Mst" },
- {LOG_MINOR_HW_TRACE_TRAVIS, "Travis" },
- {LOG_MINOR_HW_TRACE_HOTPLUG, "Hotplug" },
- {LOG_MINOR_HW_TRACE_LINK_TRAINING, "LinkTraining" },
- {LOG_MINOR_HW_TRACE_SET_MODE, "SetMode" },
- {LOG_MINOR_HW_TRACE_RESUME_S3, "ResumeS3" },
- {LOG_MINOR_HW_TRACE_RESUME_S4, "ResumeS4" },
- {LOG_MINOR_HW_TRACE_BOOTUP, "BootUp" },
- {LOG_MINOR_HW_TRACE_AUDIO, "Audio"},
- {LOG_MINOR_HW_TRACE_HPD_IRQ, "HpdIrq" },
- {LOG_MINOR_HW_TRACE_INTERRUPT, "Interrupt" },
- {LOG_MINOR_HW_TRACE_MPO, "Planes" },
-};
-
-static const struct log_minor_info mst_minor_info_tbl[] = {
- {LOG_MINOR_MST_IRQ_HPD_RX, "IrqHpdRx"},
- {LOG_MINOR_MST_IRQ_TIMER, "IrqTimer"},
- {LOG_MINOR_MST_NATIVE_AUX, "NativeAux"},
- {LOG_MINOR_MST_SIDEBAND_MSG, "SB"},
- {LOG_MINOR_MST_MSG_TRANSACTION, "MT"},
- {LOG_MINOR_MST_SIDEBAND_MSG_PARSED, "SB Parsed"},
- {LOG_MINOR_MST_MSG_TRANSACTION_PARSED, "MT Parsed"},
- {LOG_MINOR_MST_AUX_MSG_DPCD_ACCESS, "AuxMsgDpcdAccess"},
- {LOG_MINOR_MST_PROGRAMMING, "Programming"},
- {LOG_MINOR_MST_TOPOLOGY_DISCOVERY, "TopologyDiscovery"},
- {LOG_MINOR_MST_CONVERTER_CAPS, "ConverterCaps"},
-};
-
-static const struct log_minor_info dcs_minor_info_tbl[] = {
- {LOG_MINOR_DCS_EDID_EMULATOR, "EdidEmul"},
- {LOG_MINOR_DCS_DONGLE_DETECTION, "DongleDetect"},
-};
-
-static const struct log_minor_info dcp_minor_info_tbl[] = {
- { LOG_MINOR_DCP_GAMMA_GRPH, "GammaGrph"},
- { LOG_MINOR_DCP_GAMMA_OVL, "GammaOvl"},
- { LOG_MINOR_DCP_CSC_GRPH, "CscGrph"},
- { LOG_MINOR_DCP_CSC_OVL, "CscOvl"},
- { LOG_MINOR_DCP_SCALER, "Scaler"},
- { LOG_MINOR_DCP_SCALER_TABLES, "ScalerTables"},
+static const struct dc_log_type_info log_type_info_tbl[] = {
+ {LOG_ERROR, "Error"},
+ {LOG_WARNING, "Warning"},
+ {LOG_DC, "DC_Interface"},
+ {LOG_SURFACE, "Surface"},
+ {LOG_HW_HOTPLUG, "HW_Hotplug"},
+ {LOG_HW_LINK_TRAINING, "HW_LKTN"},
+ {LOG_HW_SET_MODE, "HW_Mode"},
+ {LOG_HW_RESUME_S3, "HW_Resume"},
+ {LOG_HW_AUDIO, "HW_Audio"},
+ {LOG_HW_HPD_IRQ, "HW_HPDIRQ"},
+ {LOG_MST, "MST"},
+ {LOG_SCALER, "Scaler"},
+ {LOG_BIOS, "BIOS"},
+ {LOG_BANDWIDTH_CALCS, "BWCalcs"},
+ {LOG_BANDWIDTH_VALIDATION, "BWValidation"},
+ {LOG_I2C_AUX, "I2C_AUX"},
+ {LOG_SYNC, "Sync"},
+ {LOG_BACKLIGHT, "Backlight"},
+ {LOG_FEATURE_OVERRIDE, "Override"},
+ {LOG_DETECTION_EDID_PARSER, "Edid"},
+ {LOG_DETECTION_DP_CAPS, "DP_Caps"},
+ {LOG_RESOURCE, "Resource"},
+ {LOG_DML, "DML"},
+ {LOG_EVENT_MODE_SET, "Mode"},
+ {LOG_EVENT_DETECTION, "Detect"},
+ {LOG_EVENT_LINK_TRAINING, "LKTN"},
+ {LOG_EVENT_LINK_LOSS, "LinkLoss"},
+ {LOG_EVENT_UNDERFLOW, "Underflow"}
};
-static const struct log_minor_info bios_minor_info_tbl[] = {
- {LOG_MINOR_BIOS_CMD_TABLE, "CmdTbl"},
-};
-
-static const struct log_minor_info reg_minor_info_tbl[] = {
- {LOG_MINOR_REGISTER_INDEX, "Index"},
-};
-
-static const struct log_minor_info info_packet_minor_info_tbl[] = {
- {LOG_MINOR_INFO_PACKETS_HDMI, "Hdmi"},
-};
-
-static const struct log_minor_info dsat_minor_info_tbl[] = {
- {LOG_MINOR_DSAT_LOGGER, "Logger"},
- {LOG_MINOR_DSAT_EDID_OVERRIDE, "EDID_Override"},
-};
-
-static const struct log_minor_info ec_minor_info_tbl[] = {
- {LOG_MINOR_EC_PPLIB_NOTIFY, "PPLib_Notify" }, /* PPLib notifies DAL */
- {LOG_MINOR_EC_PPLIB_QUERY, "PPLib_Query" } /* DAL requested info from
- PPLib */
-};
-static const struct log_minor_info bwm_minor_info_tbl[] = {
- {LOG_MINOR_BWM_MODE_VALIDATION, "ModeValidation"},
- {LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS, "Req_Bandw_Calcs"}
-};
-
-static const struct log_minor_info mode_enum_minor_info_tbl[] = {
- {LOG_MINOR_MODE_ENUM_BEST_VIEW_CANDIDATES, "BestviewCandidates"},
- {LOG_MINOR_MODE_ENUM_VIEW_SOLUTION, "ViewSolution"},
- {LOG_MINOR_MODE_ENUM_TS_LIST_BUILD, "TsListBuild"},
- {LOG_MINOR_MODE_ENUM_TS_LIST, "TsList"},
- {LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST, "MasterViewList"},
- {LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST_UPDATE, "MasterViewListUpdate"},
-};
-
-static const struct log_minor_info i2caux_minor_info_tbl[] = {
- {LOG_MINOR_I2C_AUX_LOG, "Log"},
- {LOG_MINOR_I2C_AUX_AUX_TIMESTAMP, "Timestamp"},
- {LOG_MINOR_I2C_AUX_CFG, "Config"}
-};
-
-static const struct log_minor_info line_buffer_minor_info_tbl[] = {
- {LOG_MINOR_LINE_BUFFER_POWERGATING, "PowerGating"}
-};
-
-static const struct log_minor_info hwss_minor_info_tbl[] = {
- {LOG_MINOR_HWSS_TAPS_VALIDATION, "HWSS Taps"}
-};
-
-static const struct log_minor_info optimization_minor_info_tbl[] = {
- {LOG_MINOR_OPTMZ_GENERAL, "General Optimizations"},
- {LOG_MINOR_OPTMZ_DO_NOT_TURN_OFF_VCC_DURING_SET_MODE,
- "Skip Vcc Off During Set Mode"}
-};
-
-static const struct log_minor_info perf_measure_minor_info_tbl[] = {
- {LOG_MINOR_PERF_MEASURE_GENERAL, "General Performance Measurement"},
- {LOG_MINOR_PERF_MEASURE_HEAP_MEMORY, "Heap Memory Management"}
-};
-
-static const struct log_minor_info sync_minor_info_tbl[] = {
- {LOG_MINOR_SYNC_HW_CLOCK_ADJUST, "Pixel Rate Tune-up"},
- {LOG_MINOR_SYNC_TIMING, "Timing"}
-};
-
-static const struct log_minor_info backlight_minor_info_tbl[] = {
- {LOG_MINOR_BACKLIGHT_BRIGHTESS_CAPS, "Caps"},
- {LOG_MINOR_BACKLIGHT_DMCU_DELTALUT, "DMCU Delta LUT"},
- {LOG_MINOR_BACKLIGHT_DMCU_BUILD_DELTALUT, "Build DMCU Delta LUT"},
- {LOG_MINOR_BACKLIGHT_INTERFACE, "Interface"},
- {LOG_MINOR_BACKLIGHT_LID, "Lid Status"}
-};
-
-static const struct log_minor_info override_feature_minor_info_tbl[] = {
- {LOG_MINOR_FEATURE_OVERRIDE, "overriden feature"},
-};
-
-static const struct log_minor_info detection_minor_info_tbl[] = {
- {LOG_MINOR_DETECTION_EDID_PARSER, "EDID Parser"},
- {LOG_MINOR_DETECTION_DP_CAPS, "DP caps"},
-};
-
-static const struct log_minor_info tm_minor_info_tbl[] = {
- {LOG_MINOR_TM_INFO, "INFO"},
- {LOG_MINOR_TM_IFACE_TRACE, "IFACE_TRACE"},
- {LOG_MINOR_TM_RESOURCES, "RESOURCES"},
- {LOG_MINOR_TM_ENCODER_CTL, "ENCODER_CTL"},
- {LOG_MINOR_TM_ENG_ASN, "ENG_ASN"},
- {LOG_MINOR_TM_CONTROLLER_ASN, "CONTROLLER_ASN"},
- {LOG_MINOR_TM_PWR_GATING, "PWR_GATING"},
- {LOG_MINOR_TM_BUILD_DSP_PATH, "BUILD_PATH"},
- {LOG_MINOR_TM_DISPLAY_DETECT, "DISPLAY_DETECT"},
- {LOG_MINOR_TM_LINK_SRV, "LINK_SRV"},
- {LOG_MINOR_TM_NOT_IMPLEMENTED, "NOT_IMPL"},
- {LOG_MINOR_TM_COFUNC_PATH, "COFUNC_PATH"}
-};
-
-static const struct log_minor_info ds_minor_info_tbl[] = {
- {LOG_MINOR_DS_MODE_SETTING, "Mode_Setting"},
-};
-
-static const struct log_minor_info connectivity_minor_info_tbl[] = {
- {LOG_MINOR_CONNECTIVITY_MODE_SET, "Mode"},
- {LOG_MINOR_CONNECTIVITY_DETECTION, "Detect"},
- {LOG_MINOR_CONNECTIVITY_LINK_TRAINING, "LKTN"},
- {LOG_MINOR_CONNECTIVITY_LINK_LOSS, "LinkLoss"},
- {LOG_MINOR_CONNECTIVITY_UNDERFLOW, "Underflow"},
-};
-
-struct log_major_mask_info {
- struct log_major_info major_info;
- uint32_t default_mask;
- const struct log_minor_info *minor_tbl;
- uint32_t tbl_element_cnt;
-};
-
-/* A mask for each Major.
- * Use a mask or zero. */
-#define LG_ERR_MSK 0xffffffff
-#define LG_WRN_MSK 0xffffffff
-#define LG_TM_MSK (1 << LOG_MINOR_TM_RESOURCES)
-#define LG_FO_MSK (1 << LOG_MINOR_FEATURE_OVERRIDE)
-#define LG_EC_MSK ((1 << LOG_MINOR_EC_PPLIB_NOTIFY) | \
- (1 << LOG_MINOR_EC_PPLIB_QUERY))
-#define LG_DSAT_MSK (1 << LOG_MINOR_DSAT_EDID_OVERRIDE)
-#define LG_DT_MSK (1 << LOG_MINOR_DETECTION_EDID_PARSER)
-
-/* IFT - InterFaceTrace */
-#define LG_IFT_MSK (1 << LOG_MINOR_COMPONENT_DC)
-
-#define LG_HW_TR_AUD_MSK (1 << LOG_MINOR_HW_TRACE_AUDIO)
-#define LG_HW_TR_INTERRUPT_MSK (1 << LOG_MINOR_HW_TRACE_INTERRUPT) | \
- (1 << LOG_MINOR_HW_TRACE_HPD_IRQ)
-#define LG_HW_TR_PLANES_MSK (1 << LOG_MINOR_HW_TRACE_MPO)
-#define LG_ALL_MSK 0xffffffff
-#define LG_DCP_MSK ~(1 << LOG_MINOR_DCP_SCALER)
-
-#define LG_SYNC_MSK (1 << LOG_MINOR_SYNC_TIMING)
-
-#define LG_BWM_MSK (1 << LOG_MINOR_BWM_MODE_VALIDATION)
-
-#define LG_WARN_MSK ~(1 << LOG_MINOR_COMPONENT_TOPOLOGY_MANAGER)
-
-#define LG_IF_MSK ~(1 << LOG_MINOR_COMPONENT_SURFACE)
-
-#define LG_HW_TRACE_MSK (LG_ALL_MSK & \
- ~((1 << LOG_MINOR_HW_TRACE_LINK_TRAINING) \
- | (1 << LOG_MINOR_HW_TRACE_AUDIO)))
-
-static const struct log_major_mask_info log_major_mask_info_tbl[] = {
- /* LogMajor major name default MinorTble tblElementCnt */
- {{LOG_MAJOR_ERROR, "Error" }, LG_ALL_MSK, component_minor_info_tbl, NUM_ELEMENTS(component_minor_info_tbl)},
- {{LOG_MAJOR_WARNING, "Warning" }, LG_WARN_MSK, component_minor_info_tbl, NUM_ELEMENTS(component_minor_info_tbl)},
- {{LOG_MAJOR_INTERFACE_TRACE, "IfTrace" }, LG_IF_MSK, component_minor_info_tbl, NUM_ELEMENTS(component_minor_info_tbl)},
- {{LOG_MAJOR_HW_TRACE, "HwTrace" }, LG_HW_TRACE_MSK, hw_trace_minor_info_tbl, NUM_ELEMENTS(hw_trace_minor_info_tbl)},
- {{LOG_MAJOR_MST, "MST" }, LG_ALL_MSK, mst_minor_info_tbl, NUM_ELEMENTS(mst_minor_info_tbl)},
- {{LOG_MAJOR_DCS, "DCS" }, LG_ALL_MSK, dcs_minor_info_tbl, NUM_ELEMENTS(dcs_minor_info_tbl)},
- {{LOG_MAJOR_DCP, "DCP" }, LG_DCP_MSK, dcp_minor_info_tbl, NUM_ELEMENTS(dcp_minor_info_tbl)},
- {{LOG_MAJOR_BIOS, "Bios" }, LG_ALL_MSK, bios_minor_info_tbl, NUM_ELEMENTS(bios_minor_info_tbl)},
- {{LOG_MAJOR_REGISTER, "Register" }, LG_ALL_MSK, reg_minor_info_tbl, NUM_ELEMENTS(reg_minor_info_tbl)},
- {{LOG_MAJOR_INFO_PACKETS, "InfoPacket" }, LG_ALL_MSK, info_packet_minor_info_tbl, NUM_ELEMENTS(info_packet_minor_info_tbl)},
- {{LOG_MAJOR_DSAT, "DSAT" }, LG_ALL_MSK, dsat_minor_info_tbl, NUM_ELEMENTS(dsat_minor_info_tbl)},
- {{LOG_MAJOR_EC, "EC" }, LG_ALL_MSK, ec_minor_info_tbl, NUM_ELEMENTS(ec_minor_info_tbl)},
- {{LOG_MAJOR_BWM, "BWM" }, LG_BWM_MSK, bwm_minor_info_tbl, NUM_ELEMENTS(bwm_minor_info_tbl)},
- {{LOG_MAJOR_MODE_ENUM, "ModeEnum" }, LG_ALL_MSK, mode_enum_minor_info_tbl, NUM_ELEMENTS(mode_enum_minor_info_tbl)},
- {{LOG_MAJOR_I2C_AUX, "I2cAux" }, LG_ALL_MSK, i2caux_minor_info_tbl, NUM_ELEMENTS(i2caux_minor_info_tbl)},
- {{LOG_MAJOR_LINE_BUFFER, "LineBuffer" }, LG_ALL_MSK, line_buffer_minor_info_tbl, NUM_ELEMENTS(line_buffer_minor_info_tbl)},
- {{LOG_MAJOR_HWSS, "HWSS" }, LG_ALL_MSK, hwss_minor_info_tbl, NUM_ELEMENTS(hwss_minor_info_tbl)},
- {{LOG_MAJOR_OPTIMIZATION, "Optimization"}, LG_ALL_MSK, optimization_minor_info_tbl, NUM_ELEMENTS(optimization_minor_info_tbl)},
- {{LOG_MAJOR_PERF_MEASURE, "PerfMeasure" }, LG_ALL_MSK, perf_measure_minor_info_tbl, NUM_ELEMENTS(perf_measure_minor_info_tbl)},
- {{LOG_MAJOR_SYNC, "Sync" }, LG_SYNC_MSK,sync_minor_info_tbl, NUM_ELEMENTS(sync_minor_info_tbl)},
- {{LOG_MAJOR_BACKLIGHT, "Backlight" }, LG_ALL_MSK, backlight_minor_info_tbl, NUM_ELEMENTS(backlight_minor_info_tbl)},
- {{LOG_MAJOR_INTERRUPTS, "Interrupts" }, LG_ALL_MSK, component_minor_info_tbl, NUM_ELEMENTS(component_minor_info_tbl)},
- {{LOG_MAJOR_TM, "TM" }, LG_TM_MSK, tm_minor_info_tbl, NUM_ELEMENTS(tm_minor_info_tbl)},
- {{LOG_MAJOR_DISPLAY_SERVICE, "DS" }, LG_ALL_MSK, ds_minor_info_tbl, NUM_ELEMENTS(ds_minor_info_tbl)},
- {{LOG_MAJOR_FEATURE_OVERRIDE, "FeatureOverride" }, LG_ALL_MSK, override_feature_minor_info_tbl, NUM_ELEMENTS(override_feature_minor_info_tbl)},
- {{LOG_MAJOR_DETECTION, "Detection" }, LG_ALL_MSK, detection_minor_info_tbl, NUM_ELEMENTS(detection_minor_info_tbl)},
- {{LOG_MAJOR_CONNECTIVITY, "Conn" }, LG_ALL_MSK, connectivity_minor_info_tbl, NUM_ELEMENTS(connectivity_minor_info_tbl)},
-};
+#define DC_DEFAULT_LOG_MASK ((1 << LOG_ERROR) | \
+ (1 << LOG_WARNING) | \
+ (1 << LOG_EVENT_MODE_SET) | \
+ (1 << LOG_EVENT_DETECTION) | \
+ (1 << LOG_EVENT_LINK_TRAINING) | \
+ (1 << LOG_EVENT_LINK_LOSS) | \
+ (1 << LOG_EVENT_UNDERFLOW) | \
+ (1 << LOG_RESOURCE) | \
+ (1 << LOG_FEATURE_OVERRIDE) | \
+ (1 << LOG_DETECTION_EDID_PARSER) | \
+ (1 << LOG_DC) | \
+ (1 << LOG_HW_HOTPLUG) | \
+ (1 << LOG_HW_SET_MODE) | \
+ (1 << LOG_HW_RESUME_S3) | \
+ (1 << LOG_HW_HPD_IRQ) | \
+ (1 << LOG_SYNC) | \
+ (1 << LOG_BANDWIDTH_VALIDATION) | \
+ (1 << LOG_MST) | \
+ (1 << LOG_BIOS) | \
+ (1 << LOG_DETECTION_EDID_PARSER) | \
+ (1 << LOG_DETECTION_DP_CAPS) | \
+ (1 << LOG_BACKLIGHT)) | \
+ (1 << LOG_I2C_AUX)/* | \
+ (1 << LOG_SURFACE) | \
+ (1 << LOG_SCALER) | \
+ (1 << LOG_DML) | \
+ (1 << LOG_HW_LINK_TRAINING) | \
+ (1 << LOG_HW_AUDIO)| \
+ (1 << LOG_BANDWIDTH_CALCS)*/
/* ----------- Object init and destruction ----------- */
static bool construct(struct dc_context *ctx, struct dal_logger *logger)
{
- uint32_t i;
/* malloc buffer and init offsets */
-
logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE;
logger->log_buffer = (char *)dm_alloc(logger->log_buffer_size *
sizeof(char));
@@ -299,8 +102,6 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger)
if (!logger->log_buffer)
return false;
- /* todo: Fill buffer with \0 if not done by dal_alloc */
-
/* Initialize both offsets to start of buffer (empty) */
logger->buffer_read_offset = 0;
logger->buffer_write_offset = 0;
@@ -314,20 +115,7 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger)
logger->ctx = ctx;
- /* malloc and init minor mask array */
- logger->log_enable_mask_minors =
- (uint32_t *)dm_alloc(NUM_ELEMENTS(log_major_mask_info_tbl)
- * sizeof(uint32_t));
- if (!logger->log_enable_mask_minors)
- return false;
-
- /* Set default values for mask */
- for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
-
- uint32_t dflt_mask = log_major_mask_info_tbl[i].default_mask;
-
- logger->log_enable_mask_minors[i] = dflt_mask;
- }
+ logger->mask = DC_DEFAULT_LOG_MASK;
return true;
}
@@ -338,11 +126,6 @@ static void destruct(struct dal_logger *logger)
dm_free(logger->log_buffer);
logger->log_buffer = NULL;
}
-
- if (logger->log_enable_mask_minors) {
- dm_free(logger->log_enable_mask_minors);
- logger->log_enable_mask_minors = NULL;
- }
}
struct dal_logger *dal_logger_create(struct dc_context *ctx)
@@ -373,28 +156,13 @@ uint32_t dal_logger_destroy(struct dal_logger **logger)
/* ------------------------------------------------------------------------ */
-static void lock(struct dal_logger *logger)
-{
- /* Todo: lock mutex? */
-}
-static void unlock(struct dal_logger *logger)
-{
- /* Todo: unlock mutex */
-}
-
-bool dal_logger_should_log(
+static bool dal_logger_should_log(
struct dal_logger *logger,
- enum log_major major,
- enum log_minor minor)
+ enum dc_log_type log_type)
{
- if (major < LOG_MAJOR_COUNT) {
-
- uint32_t minor_mask = logger->log_enable_mask_minors[major];
-
- if ((minor_mask & (1 << minor)) != 0)
- return true;
- }
+ if (logger->mask & (1 << log_type))
+ return true;
return false;
}
@@ -407,8 +175,8 @@ static void log_to_debug_console(struct log_entry *entry)
return;
if (entry->buf_offset) {
- switch (entry->major) {
- case LOG_MAJOR_ERROR:
+ switch (entry->type) {
+ case LOG_ERROR:
dm_error("%s", entry->buf);
break;
default:
@@ -519,56 +287,21 @@ static void log_to_internal_buffer(struct log_entry *entry)
}
}
-
- unlock(logger);
}
-static void log_timestamp(struct log_entry *entry)
+static void log_heading(struct log_entry *entry)
{
-/* dal_logger_append(entry, "00:00:00 ");*/
-}
-
-static void log_major_minor(struct log_entry *entry)
-{
- uint32_t i;
- enum log_major major = entry->major;
- enum log_minor minor = entry->minor;
-
- for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
-
- const struct log_major_mask_info *maj_mask_info =
- &log_major_mask_info_tbl[i];
-
- if (maj_mask_info->major_info.major == major) {
+ int j;
- dal_logger_append(entry, "[%s_",
- maj_mask_info->major_info.major_name);
+ for (j = 0; j < NUM_ELEMENTS(log_type_info_tbl); j++) {
- if (maj_mask_info->minor_tbl != NULL) {
- uint32_t j;
+ const struct dc_log_type_info *info = &log_type_info_tbl[j];
- for (j = 0; j < maj_mask_info->tbl_element_cnt; j++) {
-
- const struct log_minor_info *min_info = &maj_mask_info->minor_tbl[j];
-
- if (min_info->minor == minor)
- dal_logger_append(entry, "%s]\t", min_info->minor_name);
- }
- }
-
- break;
- }
+ if (info->type == entry->type)
+ dm_logger_append(entry, "[%s]\t", info->name);
}
}
-static void log_heading(struct log_entry *entry,
- enum log_major major,
- enum log_minor minor)
-{
- log_timestamp(entry);
- log_major_minor(entry);
-}
-
static void append_entry(
struct log_entry *entry,
char *buffer,
@@ -591,23 +324,20 @@ static void append_entry(
/* Warning: Be careful that 'msg' is null terminated and the total size is
* less than DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE (256) including '\0'
*/
-void dal_logger_write(
+void dm_logger_write(
struct dal_logger *logger,
- enum log_major major,
- enum log_minor minor,
+ enum dc_log_type log_type,
const char *msg,
...)
{
- if (logger && dal_logger_should_log(logger, major, minor)) {
+ if (logger && dal_logger_should_log(logger, log_type)) {
uint32_t size;
va_list args;
- char buffer[DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE];
+ char buffer[LOG_MAX_LINE_SIZE];
struct log_entry entry;
va_start(args, msg);
- entry.major = LOG_MAJOR_COUNT;
- entry.minor = 0;
entry.logger = logger;
entry.buf = buffer;
@@ -615,13 +345,12 @@ void dal_logger_write(
entry.buf_offset = 0;
entry.max_buf_bytes = DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char);
- entry.major = major;
- entry.minor = minor;
+ entry.type = log_type;
- log_heading(&entry, major, minor);
+ log_heading(&entry);
size = dm_log_to_buffer(
- buffer, DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE, msg, args);
+ buffer, LOG_MAX_LINE_SIZE, msg, args);
entry.buf_offset += size;
@@ -635,10 +364,10 @@ void dal_logger_write(
}
}
-/* Same as dal_logger_write, except without open() and close(), which must
+/* Same as dm_logger_write, except without open() and close(), which must
* be done separately.
*/
-void dal_logger_append(
+void dm_logger_append(
struct log_entry *entry,
const char *msg,
...)
@@ -653,18 +382,18 @@ void dal_logger_append(
logger = entry->logger;
if (logger && logger->open_count > 0 &&
- dal_logger_should_log(logger, entry->major, entry->minor)) {
+ dal_logger_should_log(logger, entry->type)) {
uint32_t size;
va_list args;
- char buffer[DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE];
+ char buffer[LOG_MAX_LINE_SIZE];
va_start(args, msg);
size = dm_log_to_buffer(
- buffer, DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE, msg, args);
+ buffer, LOG_MAX_LINE_SIZE, msg, args);
- if (size < DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE - 1) {
+ if (size < LOG_MAX_LINE_SIZE - 1) {
append_entry(entry, buffer, size);
} else {
append_entry(entry, "LOG_ERROR, line too long\n", 27);
@@ -674,95 +403,17 @@ void dal_logger_append(
}
}
-uint32_t dal_logger_read(
- struct dal_logger *logger, /* <[in] */
- uint32_t output_buffer_size, /* <[in] */
- char *output_buffer, /* >[out] */
- uint32_t *bytes_read, /* >[out] */
- bool single_line)
-{
- uint32_t bytes_remaining = 0;
- uint32_t bytes_read_count = 0;
- bool keep_reading = true;
-
- if (!logger || output_buffer == NULL || output_buffer_size == 0) {
- BREAK_TO_DEBUGGER();
- *bytes_read = 0;
- return 0;
- }
-
- lock(logger);
-
- /* Read until null terminator (if single_line==true,
- * max buffer size, or until we've read everything new
- */
-
- do {
- char cur;
-
- /* Stop when we've read everything */
- if (logger->buffer_read_offset ==
- logger->buffer_write_offset) {
-
- break;
- }
-
- cur = logger->log_buffer[logger->buffer_read_offset];
- logger->buffer_read_offset++;
-
- /* Wrap read pointer if at end */
- if (logger->buffer_read_offset == logger->log_buffer_size) {
-
- logger->buffer_read_offset = 0;
- logger->read_wrap_count++;
- }
-
- /* Don't send null terminators to buffer */
- if (cur != '\0') {
- output_buffer[bytes_read_count] = cur;
- bytes_read_count++;
- } else if (single_line) {
- keep_reading = false;
- }
-
- } while (bytes_read_count <= output_buffer_size && keep_reading);
-
- /* We assume that reading can never be ahead of writing */
- if (logger->write_wrap_count > logger->read_wrap_count) {
- bytes_remaining = logger->log_buffer_size -
- logger->buffer_read_offset +
- logger->buffer_write_offset;
- } else {
- bytes_remaining = logger->buffer_write_offset -
- logger->buffer_read_offset;
- }
-
- /* reset write/read wrap count to 0 if we've read everything */
- if (bytes_remaining == 0) {
-
- logger->write_wrap_count = 0;
- logger->read_wrap_count = 0;
- }
-
- *bytes_read = bytes_read_count;
- unlock(logger);
-
- return bytes_remaining;
-}
-
-void dal_logger_open(
+void dm_logger_open(
struct dal_logger *logger,
struct log_entry *entry, /* out */
- enum log_major major,
- enum log_minor minor)
+ enum dc_log_type log_type)
{
if (!entry) {
BREAK_TO_DEBUGGER();
return;
}
- entry->major = LOG_MAJOR_COUNT;
- entry->minor = 0;
+ entry->type = log_type;
entry->logger = logger;
entry->buf = dm_alloc(DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char));
@@ -771,13 +422,11 @@ void dal_logger_open(
entry->max_buf_bytes = DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char);
logger->open_count++;
- entry->major = major;
- entry->minor = minor;
- log_heading(entry, major, minor);
+ log_heading(entry);
}
-void dal_logger_close(struct log_entry *entry)
+void dm_logger_close(struct log_entry *entry)
{
struct dal_logger *logger = entry->logger;
@@ -804,148 +453,3 @@ cleanup:
entry->max_buf_bytes = 0;
}
}
-
-uint32_t dal_logger_get_mask(
- struct dal_logger *logger,
- enum log_major lvl_major, enum log_minor lvl_minor)
-{
- uint32_t log_mask = 0;
-
- if (logger && lvl_major < LOG_MAJOR_COUNT)
- log_mask = logger->log_enable_mask_minors[lvl_major];
-
- log_mask &= 1 << lvl_minor;
- return log_mask;
-}
-
-uint32_t dal_logger_set_mask(
- struct dal_logger *logger,
- enum log_major lvl_major, enum log_minor lvl_minor)
-{
-
- if (logger && lvl_major < LOG_MAJOR_COUNT) {
- if (lvl_minor == LOG_MINOR_MASK_ALL) {
- logger->log_enable_mask_minors[lvl_major] = 0xFFFFFFFF;
- } else {
- logger->log_enable_mask_minors[lvl_major] |=
- (1 << lvl_minor);
- }
- return 0;
- }
- return 1;
-}
-
-uint32_t dal_logger_get_masks(
- struct dal_logger *logger,
- enum log_major lvl_major)
-{
- uint32_t log_mask = 0;
-
- if (logger && lvl_major < LOG_MAJOR_COUNT)
- log_mask = logger->log_enable_mask_minors[lvl_major];
-
- return log_mask;
-}
-
-void dal_logger_set_masks(
- struct dal_logger *logger,
- enum log_major lvl_major, uint32_t log_mask)
-{
- if (logger && lvl_major < LOG_MAJOR_COUNT)
- logger->log_enable_mask_minors[lvl_major] = log_mask;
-}
-
-uint32_t dal_logger_unset_mask(
- struct dal_logger *logger,
- enum log_major lvl_major, enum log_minor lvl_minor)
-{
-
- if (lvl_major < LOG_MAJOR_COUNT) {
- if (lvl_minor == LOG_MINOR_MASK_ALL) {
- logger->log_enable_mask_minors[lvl_major] = 0;
- } else {
- logger->log_enable_mask_minors[lvl_major] &=
- ~(1 << lvl_minor);
- }
- return 0;
- }
- return 1;
-}
-
-uint32_t dal_logger_get_flags(
- struct dal_logger *logger)
-{
-
- return logger->flags.value;
-}
-
-void dal_logger_set_flags(
- struct dal_logger *logger,
- union logger_flags flags)
-{
-
- logger->flags = flags;
-}
-
-uint32_t dal_logger_get_buffer_size(struct dal_logger *logger)
-{
- return DAL_LOGGER_BUFFER_MAX_SIZE;
-}
-
-uint32_t dal_logger_set_buffer_size(
- struct dal_logger *logger,
- uint32_t new_size)
-{
- /* ToDo: implement dynamic size */
-
- /* return new size */
- return DAL_LOGGER_BUFFER_MAX_SIZE;
-}
-
-const struct log_major_info *dal_logger_enum_log_major_info(
- struct dal_logger *logger,
- unsigned int enum_index)
-{
- const struct log_major_info *major_info;
-
- if (enum_index >= NUM_ELEMENTS(log_major_mask_info_tbl))
- return NULL;
-
- major_info = &log_major_mask_info_tbl[enum_index].major_info;
- return major_info;
-}
-
-const struct log_minor_info *dal_logger_enum_log_minor_info(
- struct dal_logger *logger,
- enum log_major major,
- unsigned int enum_index)
-{
- const struct log_minor_info *minor_info = NULL;
- uint32_t i;
-
- for (i = 0; i < NUM_ELEMENTS(log_major_mask_info_tbl); i++) {
-
- const struct log_major_mask_info *maj_mask_info =
- &log_major_mask_info_tbl[i];
-
- if (maj_mask_info->major_info.major == major) {
-
- if (maj_mask_info->minor_tbl != NULL) {
- uint32_t j;
-
- for (j = 0; j < maj_mask_info->tbl_element_cnt; j++) {
-
- minor_info = &maj_mask_info->minor_tbl[j];
-
- if (minor_info->minor == enum_index)
- return minor_info;
- }
- }
-
- break;
- }
- }
- return NULL;
-
-}
-
diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.h b/drivers/gpu/drm/amd/dal/dc/basics/logger.h
index 12d8ae6b18bb..2f7a5df4c811 100644
--- a/drivers/gpu/drm/amd/dal/dc/basics/logger.h
+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.h
@@ -33,7 +33,7 @@
/*Connectivity log needs to output EDID, which needs at lease 256x3 bytes,
* change log line size to 896 to meet the request.
*/
-#define DAL_LOGGER_BUFFER_MAX_LOG_LINE_SIZE 896
+#define LOG_MAX_LINE_SIZE 896
#include "include/logger_types.h"
@@ -58,7 +58,7 @@ struct dal_logger {
char *log_buffer; /* Pointer to malloc'ed buffer */
uint32_t log_buffer_size; /* Size of circular buffer */
- uint32_t *log_enable_mask_minors; /*array of masks for major elements*/
+ uint32_t mask; /*array of masks for major elements*/
union logger_flags flags;
struct dc_context *ctx;
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
index f98f2882b0fd..0647156f313c 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
@@ -3374,9 +3374,7 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
opm_object,
&ext_display_connection_info_tbl) != BP_RESULT_OK) {
- dal_logger_write(bp->base.ctx->logger,
- LOG_MAJOR_BIOS,
- LOG_MINOR_BIOS_CMD_TABLE,
+ dm_logger_write(bp->base.ctx->logger, LOG_BIOS,
"%s: Failed to read Connection Info Table", __func__);
return BP_RESULT_UNSUPPORTED;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index e039cc4ec54c..47db0fd82fe6 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -653,9 +653,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
core_dc->public.config.gpu_vm_support = init_params->flags.gpu_vm_support;
- dal_logger_write(core_dc->ctx->logger,
- LOG_MAJOR_INTERFACE_TRACE,
- LOG_MINOR_COMPONENT_DC,
+ dm_logger_write(core_dc->ctx->logger, LOG_DC,
"Display Core initialized\n");
return &core_dc->public;
@@ -733,9 +731,7 @@ bool dc_validate_resources(
context_alloc_fail:
if (result != DC_OK) {
- dal_logger_write(core_dc->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_TOPOLOGY_MANAGER,
+ dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
"%s:resource validation failed, dc_status:%d\n",
__func__,
result);
@@ -765,9 +761,7 @@ bool dc_validate_guaranteed(
context_alloc_fail:
if (result != DC_OK) {
- dal_logger_write(core_dc->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_TOPOLOGY_MANAGER,
+ dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
"%s:guaranteed validation failed, dc_status:%d\n",
__func__,
result);
@@ -1044,9 +1038,7 @@ bool dc_commit_targets(
if (false == targets_changed(core_dc, targets, target_count))
return DC_OK;
- dal_logger_write(core_dc->ctx->logger,
- LOG_MAJOR_INTERFACE_TRACE,
- LOG_MINOR_COMPONENT_DC,
+ dm_logger_write(core_dc->ctx->logger, LOG_DC,
"%s: %d targets\n",
__func__,
target_count);
@@ -1056,8 +1048,7 @@ bool dc_commit_targets(
dc_target_log(target,
core_dc->ctx->logger,
- LOG_MAJOR_INTERFACE_TRACE,
- LOG_MINOR_COMPONENT_DC);
+ LOG_DC);
set[i].target = targets[i];
set[i].surface_count = 0;
@@ -1070,9 +1061,7 @@ bool dc_commit_targets(
result = core_dc->res_pool->funcs->validate_with_context(core_dc, set, target_count, context);
if (result != DC_OK){
- dal_logger_write(core_dc->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_DC,
+ dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
"%s: Context validation failed! dc_status:%d\n",
__func__,
result);
@@ -1196,9 +1185,7 @@ bool dc_pre_update_surfaces_to_target(
resource_validate_ctx_copy_construct(core_dc->current_context, context);
- dal_logger_write(core_dc->ctx->logger,
- LOG_MAJOR_INTERFACE_TRACE,
- LOG_MINOR_COMPONENT_DC,
+ dm_logger_write(core_dc->ctx->logger, LOG_DC,
"%s: commit %d surfaces to target 0x%x\n",
__func__,
new_surface_count,
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index 39bf829a9fa6..44ed32575b02 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -58,8 +58,7 @@
#endif
#define LINK_INFO(...) \
- dal_logger_write(dc_ctx->logger, \
- LOG_MAJOR_HW_TRACE, LOG_MINOR_HW_TRACE_HOTPLUG, \
+ dm_logger_write(dc_ctx->logger, LOG_HW_HOTPLUG, \
__VA_ARGS__)
/*******************************************************************************
@@ -499,9 +498,7 @@ static enum dc_edid_status read_edid(
&sink->public.edid_caps);
--edid_retry;
if (edid_status == EDID_BAD_CHECKSUM)
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_DETECTION_EDID_PARSER,
+ dm_logger_write(link->ctx->logger, LOG_WARNING,
"Bad EDID checksum, retry remain: %d\n",
edid_retry);
} while (edid_status == EDID_BAD_CHECKSUM && edid_retry > 0);
@@ -705,15 +702,11 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
switch (edid_status) {
case EDID_BAD_CHECKSUM:
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_DETECTION_EDID_PARSER,
+ dm_logger_write(link->ctx->logger, LOG_ERROR,
"EDID checksum invalid.\n");
break;
case EDID_NO_RESPONSE:
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_DETECTION_EDID_PARSER,
+ dm_logger_write(link->ctx->logger, LOG_ERROR,
"No EDID read.\n");
return false;
@@ -734,9 +727,7 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
"%s: [Block %d] ", sink->public.edid_caps.display_name, i);
}
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_DETECTION,
- LOG_MINOR_DETECTION_EDID_PARSER,
+ dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER,
"%s: "
"manufacturer_id = %X, "
"product_id = %X, "
@@ -757,9 +748,7 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
sink->public.edid_caps.audio_mode_count);
for (i = 0; i < sink->public.edid_caps.audio_mode_count; i++) {
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_DETECTION,
- LOG_MINOR_DETECTION_EDID_PARSER,
+ dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER,
"%s: mode number = %d, "
"format_code = %d, "
"channel_count = %d, "
@@ -1010,8 +999,7 @@ static bool construct(
}
break;
default:
- dal_logger_write(dc_ctx->logger,
- LOG_MAJOR_WARNING, LOG_MINOR_TM_LINK_SRV,
+ dm_logger_write(dc_ctx->logger, LOG_WARNING,
"Unsupported Connector type:%d!\n", link->link_id.id);
goto create_fail;
}
@@ -1198,8 +1186,7 @@ static void dpcd_configure_panel_mode(
ASSERT(result == DDC_RESULT_SUCESSFULL);
}
}
- dal_logger_write(link->ctx->logger, LOG_MAJOR_DETECTION,
- LOG_MINOR_DETECTION_DP_CAPS,
+ dm_logger_write(link->ctx->logger, LOG_DETECTION_DP_CAPS,
"Link: %d eDP panel mode supported: %d "
"eDP panel mode enabled: %d \n",
link->public.link_index,
@@ -1430,8 +1417,7 @@ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level,
int i;
uint32_t dmcu_status;
- dal_logger_write(ctx->logger, LOG_MAJOR_BACKLIGHT,
- LOG_MINOR_BACKLIGHT_INTERFACE,
+ dm_logger_write(ctx->logger, LOG_BACKLIGHT,
"New Backlight level: %d (0x%X)\n", level, level);
dmcu_status = dm_read_reg(ctx, mmDMCU_STATUS);
@@ -1475,8 +1461,7 @@ bool dc_link_set_abm_level(const struct dc_link *dc_link, uint32_t level)
struct core_link *link = DC_LINK_TO_CORE(dc_link);
struct dc_context *ctx = link->ctx;
- dal_logger_write(ctx->logger, LOG_MAJOR_BACKLIGHT,
- LOG_MINOR_BACKLIGHT_INTERFACE,
+ dm_logger_write(ctx->logger, LOG_BACKLIGHT,
"New abm level: %d (0x%X)\n", level, level);
link->link_enc->funcs->set_dmcu_abm_level(link->link_enc, level);
@@ -1763,26 +1748,20 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
link, pipe_ctx->stream_enc, &proposed_table);
}
else
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_DC,
+ dm_logger_write(link->ctx->logger, LOG_WARNING,
"Failed to update"
"MST allocation table for"
"pipe idx:%d\n",
pipe_ctx->pipe_idx);
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_MST,
- LOG_MINOR_MST_PROGRAMMING,
+ dm_logger_write(link->ctx->logger, LOG_MST,
"%s "
"stream_count: %d: \n ",
__func__,
link->mst_stream_alloc_table.stream_count);
for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_MST,
- LOG_MINOR_MST_PROGRAMMING,
+ dm_logger_write(link->ctx->logger, LOG_MST,
"stream_enc[%d]: 0x%x "
"stream[%d].vcp_id: %d "
"stream[%d].slot_count: %d\n",
@@ -1859,9 +1838,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
link, pipe_ctx->stream_enc, &proposed_table);
}
else {
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_DC,
+ dm_logger_write(link->ctx->logger, LOG_WARNING,
"Failed to update"
"MST allocation table for"
"pipe idx:%d\n",
@@ -1869,18 +1846,14 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
}
}
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_MST,
- LOG_MINOR_MST_PROGRAMMING,
+ dm_logger_write(link->ctx->logger, LOG_MST,
"%s"
"stream_count: %d: ",
__func__,
link->mst_stream_alloc_table.stream_count);
for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_MST,
- LOG_MINOR_MST_PROGRAMMING,
+ dm_logger_write(link->ctx->logger, LOG_MST,
"stream_enc[%d]: 0x%x "
"stream[%d].vcp_id: %d "
"stream[%d].slot_count: %d\n",
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
index 1a7a871ab3e7..ffcd2a10d6f6 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
@@ -541,10 +541,8 @@ static uint8_t aux_read_edid_block(
&cmd);
if (false == result)
- dal_logger_write(
- ddc->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_DISPLAY_CAPABILITY_SERVICE,
+ dm_logger_write(
+ ddc->ctx->logger, LOG_ERROR,
"%s: Writing of EDID Segment (0x30) failed!\n",
__func__);
}
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
index 77b90ca4083f..a2064acffcaa 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
@@ -81,9 +81,7 @@ static void wait_for_training_aux_rd_interval(
udelay(default_wait_in_micro_secs);
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_LINK_TRAINING,
+ dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s:\n wait = %d\n",
__func__,
default_wait_in_micro_secs);
@@ -99,9 +97,7 @@ static void dpcd_set_training_pattern(
&dpcd_pattern.raw,
1);
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_LINK_TRAINING,
+ dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s\n %x pattern = %x\n",
__func__,
DPCD_ADDRESS_TRAINING_PATTERN_SET,
@@ -138,9 +134,7 @@ static void dpcd_set_link_settings(
core_link_write_dpcd(link, DPCD_ADDRESS_DOWNSPREAD_CNTL,
&downspread.raw, sizeof(downspread));
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_LINK_TRAINING,
+ dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
__func__,
DPCD_ADDRESS_LINK_BW_SET,
@@ -175,9 +169,7 @@ static enum dpcd_training_patterns
break;
default:
ASSERT(0);
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_LINK_TRAINING,
+ dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s: Invalid HW Training pattern: %d\n",
__func__, pattern);
break;
@@ -210,9 +202,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
dpcd_lt_buffer[DPCD_ADDRESS_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
= dpcd_pattern.raw;
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_LINK_TRAINING,
+ dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s\n %x pattern = %x\n",
__func__,
DPCD_ADDRESS_TRAINING_PATTERN_SET,
@@ -247,9 +237,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
dpcd_lane,
size_in_bytes);
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_LINK_TRAINING,
+ dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s:\n %x VS set = %x PE set = %x \
max VS Reached = %x max PE Reached = %x\n",
__func__,
@@ -487,17 +475,13 @@ static void get_lane_status_and_drive_settings(
ln_status_updated->raw = dpcd_buf[2];
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_LINK_TRAINING,
+ dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
__func__,
DPCD_ADDRESS_LANE_01_STATUS, dpcd_buf[0],
DPCD_ADDRESS_LANE_23_STATUS, dpcd_buf[1]);
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_LINK_TRAINING,
+ dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
__func__,
DPCD_ADDRESS_ADJUST_REQUEST_LANE0_1,
@@ -591,9 +575,7 @@ static void dpcd_set_lane_settings(
}
*/
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_LINK_TRAINING,
+ dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
"%s\n %x VS set = %x PE set = %x \
max VS Reached = %x max PE Reached = %x\n",
__func__,
@@ -708,9 +690,7 @@ static bool perform_post_lt_adj_req_sequence(
}
if (!req_drv_setting_changed) {
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_LINK_SERVICE,
+ dm_logger_write(link->ctx->logger, LOG_WARNING,
"%s: Post Link Training Adjust Request Timed out\n",
__func__);
@@ -718,9 +698,7 @@ static bool perform_post_lt_adj_req_sequence(
return true;
}
}
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_LINK_SERVICE,
+ dm_logger_write(link->ctx->logger, LOG_WARNING,
"%s: Post Link Training Adjust Request limit reached\n",
__func__);
@@ -912,9 +890,7 @@ static bool perform_clock_recovery_sequence(
if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
ASSERT(0);
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_LINK_SERVICE,
+ dm_logger_write(link->ctx->logger, LOG_ERROR,
"%s: Link Training Error, could not \
get CR after %d tries. \
Possibly voltage swing issue", __func__,
@@ -1404,9 +1380,7 @@ static bool hpd_rx_irq_check_link_loss_status(
if (dpcd_result != DC_OK) {
irq_reg_rx_power_state = DP_PWR_STATE_D0;
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_HPD_IRQ,
+ dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
"%s: DPCD read failed to obtain power state.\n",
__func__);
}
@@ -1444,9 +1418,7 @@ static bool hpd_rx_irq_check_link_loss_status(
!hpd_irq_dpcd_data->bytes.lane_status_updated.bits.
INTERLANE_ALIGN_DONE) {
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_HPD_IRQ,
+ dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
"%s: Link Status changed.\n",
__func__);
@@ -1807,9 +1779,7 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
* PSR and device auto test, refer to function handle_sst_hpd_irq
* in DAL2.1*/
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_HPD_IRQ,
+ dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
"%s: Got short pulse HPD on link %d\n",
__func__, link->public.link_index);
@@ -1821,9 +1791,7 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
if (result != DC_OK) {
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_HPD_IRQ,
+ dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
"%s: DPCD read failed to obtain irq data\n",
__func__);
return false;
@@ -1839,9 +1807,7 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
}
if (!allow_hpd_rx_irq(link)) {
- dal_logger_write(link->ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_HPD_IRQ,
+ dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
"%s: skipping HPD handling on %d\n",
__func__, link->public.link_index);
return false;
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index 1541913ff405..204b49bae9ee 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -559,9 +559,7 @@ bool resource_build_scaling_params(
pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality);
}
- dal_logger_write(pipe_ctx->stream->ctx->logger,
- LOG_MAJOR_DCP,
- LOG_MINOR_DCP_SCALER,
+ dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
"%s: Viewport:\nheight:%d width:%d x:%d "
"y:%d\n dst_rect:\nheight:%d width:%d x:%d "
"y:%d\n",
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
index bfc94d7fca06..48eb7b0e0350 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_target.c
@@ -285,18 +285,16 @@ uint32_t dc_target_get_scanoutpos(
void dc_target_log(
const struct dc_target *dc_target,
- struct dal_logger *dal_logger,
- enum log_major log_major,
- enum log_minor log_minor)
+ struct dal_logger *dm_logger,
+ enum dc_log_type log_type)
{
int i;
const struct core_target *core_target =
CONST_DC_TARGET_TO_CORE(dc_target);
- dal_logger_write(dal_logger,
- log_major,
- log_minor,
+ dm_logger_write(dm_logger,
+ log_type,
"core_target 0x%x: stream_count=%d\n",
core_target,
core_target->public.stream_count);
@@ -305,9 +303,8 @@ void dc_target_log(
const struct core_stream *core_stream =
DC_STREAM_TO_CORE(core_target->public.streams[i]);
- dal_logger_write(dal_logger,
- log_major,
- log_minor,
+ dm_logger_write(dm_logger,
+ log_type,
"core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d;\n",
core_stream,
core_stream->public.src.x,
@@ -318,22 +315,19 @@ void dc_target_log(
core_stream->public.dst.y,
core_stream->public.dst.width,
core_stream->public.dst.height);
- dal_logger_write(dal_logger,
- log_major,
- log_minor,
+ dm_logger_write(dm_logger,
+ log_type,
"\tpix_clk_khz: %d, h_total: %d, v_total: %d\n",
core_stream->public.timing.pix_clk_khz,
core_stream->public.timing.h_total,
core_stream->public.timing.v_total);
- dal_logger_write(dal_logger,
- log_major,
- log_minor,
+ dm_logger_write(dm_logger,
+ log_type,
"\tsink name: %s, serial: %d\n",
core_stream->sink->public.edid_caps.display_name,
core_stream->sink->public.edid_caps.serial_number);
- dal_logger_write(dal_logger,
- log_major,
- log_minor,
+ dm_logger_write(dm_logger,
+ log_type,
"\tlink: %d\n",
core_stream->sink->link->public.link_index);
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
index 2f8a552b9f71..2a6117ae85e3 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
@@ -342,9 +342,8 @@ void dc_target_retain(const struct dc_target *dc_target);
void dc_target_release(const struct dc_target *dc_target);
void dc_target_log(
const struct dc_target *dc_target,
- struct dal_logger *dal_logger,
- enum log_major log_major,
- enum log_minor log_minor);
+ struct dal_logger *dc_logger,
+ enum dc_log_type log_type);
uint8_t dc_get_current_target_count(const struct dc *dc);
struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.c
index 75bb309fe1d4..f2f66ea49fea 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.c
@@ -165,10 +165,8 @@ static void dce110_update_hdmi_info_packet(
break;
default:
/* invalid HW packet index */
- dal_logger_write(
- ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_ENCODER,
+ dm_logger_write(
+ ctx->logger, LOG_WARNING,
"Invalid HW packet index: %s()\n",
__func__);
return;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_audio.c
index 2701ece250d8..6296d8fda690 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_audio.c
@@ -66,8 +66,7 @@ static void write_indirect_azalia_reg(struct audio *audio,
REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
AZALIA_ENDPOINT_REG_DATA, reg_data);
- dal_logger_write(CTX->logger,
- LOG_MAJOR_HW_TRACE, LOG_MINOR_HW_TRACE_AUDIO,
+ dm_logger_write(CTX->logger, LOG_HW_AUDIO,
"AUDIO:write_indirect_azalia_reg: index: %u data: %u\n",
reg_index, reg_data);
}
@@ -85,8 +84,7 @@ static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index
/* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
- dal_logger_write(CTX->logger,
- LOG_MAJOR_HW_TRACE, LOG_MINOR_HW_TRACE_AUDIO,
+ dm_logger_write(CTX->logger, LOG_HW_AUDIO,
"AUDIO:read_indirect_azalia_reg: index: %u data: %u\n",
reg_index, value);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
index 5bc7f8d9455d..0e81aec6ef78 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
@@ -280,9 +280,7 @@ static uint32_t calculate_pixel_clock_pll_dividers(
uint32_t max_ref_divider;
if (pll_settings->adjusted_pix_clk == 0) {
- dal_logger_write(calc_pll_cs->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
"%s Bad requested pixel clock", __func__);
return MAX_PLL_CALC_ERROR;
}
@@ -343,17 +341,13 @@ static uint32_t calculate_pixel_clock_pll_dividers(
* ## SVS Wed 15 Jul 2009 */
if (min_post_divider > max_post_divider) {
- dal_logger_write(calc_pll_cs->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
"%s Post divider range is invalid", __func__);
return MAX_PLL_CALC_ERROR;
}
if (min_ref_divider > max_ref_divider) {
- dal_logger_write(calc_pll_cs->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
"%s Reference divider range is invalid", __func__);
return MAX_PLL_CALC_ERROR;
}
@@ -470,9 +464,7 @@ static uint32_t dce110_get_pix_clk_dividers(
if (pix_clk_params == NULL || pll_settings == NULL
|| pix_clk_params->requested_pix_clk == 0) {
- dal_logger_write(clk_src->base.ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(clk_src->base.ctx->logger, LOG_ERROR,
"%s: Invalid parameters!!\n", __func__);
return pll_calc_error;
}
@@ -516,9 +508,7 @@ static uint32_t dce110_get_pix_clk_dividers(
if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
/* Should never happen, ASSERT and fill up values to be able
* to continue. */
- dal_logger_write(clk_src->base.ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(clk_src->base.ctx->logger, LOG_ERROR,
"%s: Failed to adjust pixel clock!!", __func__);
pll_settings->actual_pix_clk =
pix_clk_params->requested_pix_clk;
@@ -840,16 +830,12 @@ static void get_ss_info_from_atombios(
uint32_t i;
if (ss_entries_num == NULL) {
- dal_logger_write(clk_src->base.ctx->logger,
- LOG_MAJOR_SYNC,
- LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
+ dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
"Invalid entry !!!\n");
return;
}
if (spread_spectrum_data == NULL) {
- dal_logger_write(clk_src->base.ctx->logger,
- LOG_MAJOR_SYNC,
- LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
+ dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
"Invalid array pointer!!!\n");
return;
}
@@ -892,9 +878,7 @@ static void get_ss_info_from_atombios(
++i, ++ss_info_cur, ++ss_data_cur) {
if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
- dal_logger_write(clk_src->base.ctx->logger,
- LOG_MAJOR_SYNC,
- LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
+ dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
"Invalid ATOMBIOS SS Table!!!\n");
goto out_free_data;
}
@@ -904,13 +888,9 @@ static void get_ss_info_from_atombios(
if (as_signal == AS_SIGNAL_TYPE_HDMI
&& ss_info_cur->spread_spectrum_percentage > 6){
/* invalid input, do nothing */
- dal_logger_write(clk_src->base.ctx->logger,
- LOG_MAJOR_SYNC,
- LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
+ dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
"Invalid SS percentage ");
- dal_logger_write(clk_src->base.ctx->logger,
- LOG_MAJOR_SYNC,
- LOG_MINOR_SYNC_HW_CLOCK_ADJUST,
+ dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
"for HDMI in ATOMBIOS info Table!!!\n");
continue;
}
@@ -1022,16 +1002,12 @@ static bool calc_pll_max_vco_construct(
if (init_data->num_fract_fb_divider_decimal_point == 0 ||
init_data->num_fract_fb_divider_decimal_point_precision >
init_data->num_fract_fb_divider_decimal_point) {
- dal_logger_write(calc_pll_cs->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
"The dec point num or precision is incorrect!");
return false;
}
if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
- dal_logger_write(calc_pll_cs->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
"Incorrect fract feedback divider precision num!");
return false;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
index 8597d82b89b4..7612efb27939 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
@@ -130,10 +130,8 @@ static uint32_t lpt_memory_control_config(struct dce110_compressor *cp110,
LOW_POWER_TILING_NUM_PIPES);
break;
default:
- dal_logger_write(
- cp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp110->base.ctx->logger, LOG_WARNING,
"%s: Invalid LPT NUM_PIPES!!!",
__func__);
break;
@@ -178,10 +176,8 @@ static uint32_t lpt_memory_control_config(struct dce110_compressor *cp110,
LOW_POWER_TILING_NUM_BANKS);
break;
default:
- dal_logger_write(
- cp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp110->base.ctx->logger, LOG_WARNING,
"%s: Invalid LPT NUM_BANKS!!!",
__func__);
break;
@@ -214,10 +210,8 @@ static uint32_t lpt_memory_control_config(struct dce110_compressor *cp110,
LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
break;
default:
- dal_logger_write(
- cp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp110->base.ctx->logger, LOG_WARNING,
"%s: Invalid LPT INTERLEAVE_SIZE!!!",
__func__);
break;
@@ -260,19 +254,15 @@ static uint32_t lpt_memory_control_config(struct dce110_compressor *cp110,
LOW_POWER_TILING_ROW_SIZE);
break;
default:
- dal_logger_write(
- cp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp110->base.ctx->logger, LOG_WARNING,
"%s: Invalid LPT ROW_SIZE!!!",
__func__);
break;
}
} else {
- dal_logger_write(
- cp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp110->base.ctx->logger, LOG_WARNING,
"%s: LPT MC Configuration is not provided",
__func__);
}
@@ -322,10 +312,8 @@ static void wait_for_fbc_state_changed(
}
if (counter == 10) {
- dal_logger_write(
- cp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp110->base.ctx->logger, LOG_WARNING,
"%s: wait counter exceeded, changes to HW not applied",
__func__);
}
@@ -538,10 +526,8 @@ void dce110_compressor_program_compressed_surface_address_and_pitch(
if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
fbc_pitch = fbc_pitch / 8;
else
- dal_logger_write(
- compressor->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ compressor->ctx->logger, LOG_WARNING,
"%s: Unexpected DCE11 compression ratio",
__func__);
@@ -705,10 +691,8 @@ void dce110_compressor_program_lpt_control(
LOW_POWER_TILING_MODE);
break;
default:
- dal_logger_write(
- compressor->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ compressor->ctx->logger, LOG_WARNING,
"%s: Invalid selected DRAM channels for LPT!!!",
__func__);
break;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 169077062854..2fd2bc794de4 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -1534,18 +1534,12 @@ static void set_plane_config(
struct resource_context *res_ctx)
{
struct mem_input *mi = pipe_ctx->mi;
- struct pipe_ctx *old_pipe = NULL;
struct dc_context *ctx = pipe_ctx->stream->ctx;
struct core_surface *surface = pipe_ctx->surface;
struct xfm_grph_csc_adjustment adjust;
struct out_csc_color_matrix tbl_entry;
unsigned int i;
- if (dc->current_context)
- old_pipe =
- &dc->current_context->
- res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
-
memset(&adjust, 0, sizeof(adjust));
memset(&tbl_entry, 0, sizeof(tbl_entry));
adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
@@ -1963,9 +1957,7 @@ static void dce110_program_front_end_for_pipe(
&surface->public.tiling_info,
surface->public.rotation);
- dal_logger_write(dc->ctx->logger,
- LOG_MAJOR_INTERFACE_TRACE,
- LOG_MINOR_COMPONENT_SURFACE,
+ dm_logger_write(dc->ctx->logger, LOG_SURFACE,
"Pipe:%d 0x%x: addr hi:0x%x, "
"addr low:0x%x, "
"src: %d, %d, %d,"
@@ -1988,9 +1980,7 @@ static void dce110_program_front_end_for_pipe(
pipe_ctx->surface->public.clip_rect.width,
pipe_ctx->surface->public.clip_rect.height);
- dal_logger_write(dc->ctx->logger,
- LOG_MAJOR_INTERFACE_TRACE,
- LOG_MINOR_COMPONENT_SURFACE,
+ dm_logger_write(dc->ctx->logger, LOG_SURFACE,
"Pipe %d: width, height, x, y\n"
"viewport:%d, %d, %d, %d\n"
"recout: %d, %d, %d, %d\n",
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
index 6bdb2023b63a..c36cdadf35f2 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
@@ -651,9 +651,7 @@ static void link_encoder_edp_wait_for_hpd_ready(
dal_gpio_destroy_irq(&hpd);
if (false == edp_hpd_high) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_HW_TRACE_RESUME_S3,
+ dm_logger_write(ctx->logger, LOG_ERROR,
"%s: wait timed out!\n", __func__);
}
}
@@ -682,9 +680,7 @@ void dce110_link_encoder_edp_power_control(
/* Send VBIOS command to prompt eDP panel power */
- dal_logger_write(ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_RESUME_S3,
+ dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
"%s: Panel Power action: %s\n",
__func__, (power_up ? "On":"Off"));
@@ -701,16 +697,12 @@ void dce110_link_encoder_edp_power_control(
if (BP_RESULT_OK != bp_result) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_HW_TRACE_RESUME_S3,
+ dm_logger_write(ctx->logger, LOG_ERROR,
"%s: Panel Power bp_result: %d\n",
__func__, bp_result);
}
} else {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_RESUME_S3,
+ dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
"%s: Skipping Panel Power action: %s\n",
__func__, (power_up ? "On":"Off"));
}
@@ -770,18 +762,14 @@ void dce110_link_encoder_edp_backlight_control(
}
if (enable && is_panel_backlight_on(enc110)) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_RESUME_S3,
+ dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
"%s: panel already powered up. Do nothing.\n",
__func__);
return;
}
if (!enable && !is_panel_powered_on(enc110)) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_RESUME_S3,
+ dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
"%s: panel already powered down. Do nothing.\n",
__func__);
return;
@@ -789,9 +777,7 @@ void dce110_link_encoder_edp_backlight_control(
/* Send VBIOS command to control eDP panel backlight */
- dal_logger_write(ctx->logger,
- LOG_MAJOR_HW_TRACE,
- LOG_MINOR_HW_TRACE_RESUME_S3,
+ dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
"%s: backlight action: %s\n",
__func__, (enable ? "On":"Off"));
@@ -1069,9 +1055,7 @@ bool dce110_link_encoder_construct(
enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
}
- dal_logger_write(init_data->ctx->logger,
- LOG_MAJOR_I2C_AUX,
- LOG_MINOR_I2C_AUX_CFG,
+ dm_logger_write(init_data->ctx->logger, LOG_I2C_AUX,
"Using channel: %s [%d]\n",
DECODE_CHANNEL_ID(init_data->channel),
init_data->channel);
@@ -1160,9 +1144,7 @@ void dce110_link_encoder_hw_init(
result = link_transmitter_control(enc110, &cntl);
if (result != BP_RESULT_OK) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_ENCODER,
+ dm_logger_write(ctx->logger, LOG_ERROR,
"%s: Failed to execute VBIOS command table!\n",
__func__);
BREAK_TO_DEBUGGER();
@@ -1270,9 +1252,7 @@ void dce110_link_encoder_enable_tmds_output(
result = link_transmitter_control(enc110, &cntl);
if (result != BP_RESULT_OK) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_ENCODER,
+ dm_logger_write(ctx->logger, LOG_ERROR,
"%s: Failed to execute VBIOS command table!\n",
__func__);
BREAK_TO_DEBUGGER();
@@ -1313,9 +1293,7 @@ void dce110_link_encoder_enable_dp_output(
result = link_transmitter_control(enc110, &cntl);
if (result != BP_RESULT_OK) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_ENCODER,
+ dm_logger_write(ctx->logger, LOG_ERROR,
"%s: Failed to execute VBIOS command table!\n",
__func__);
BREAK_TO_DEBUGGER();
@@ -1356,9 +1334,7 @@ void dce110_link_encoder_enable_dp_mst_output(
result = link_transmitter_control(enc110, &cntl);
if (result != BP_RESULT_OK) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_ENCODER,
+ dm_logger_write(ctx->logger, LOG_ERROR,
"%s: Failed to execute VBIOS command table!\n",
__func__);
BREAK_TO_DEBUGGER();
@@ -1403,9 +1379,7 @@ void dce110_link_encoder_disable_output(
result = link_transmitter_control(enc110, &cntl);
if (result != BP_RESULT_OK) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_ENCODER,
+ dm_logger_write(ctx->logger, LOG_ERROR,
"%s: Failed to execute VBIOS command table!\n",
__func__);
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
index 6da8310c6b88..758884803ef3 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
@@ -870,9 +870,7 @@ void dce110_allocate_mem_input(
} while (retry_count > 0);
if (field == 0)
- dal_logger_write(mi->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(mi->ctx->logger, LOG_ERROR,
"%s: DMIF allocation failed",
__func__);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
index 8b9725c57e1e..62051abcfe2f 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
@@ -422,9 +422,7 @@ static void program_pwl(
}
if (counter == max_tries) {
- dal_logger_write(opp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(opp110->base.ctx->logger, LOG_WARNING,
"%s: regamma lut was not powered on "
"in a timely manner,"
" programming still proceeds\n",
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index be67f04642da..db7686842e36 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -778,10 +778,8 @@ enum dc_status dce110_validate_bandwidth(
{
enum dc_status result = DC_ERROR_UNEXPECTED;
- dal_logger_write(
- dc->ctx->logger,
- LOG_MAJOR_BWM,
- LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
+ dm_logger_write(
+ dc->ctx->logger, LOG_BANDWIDTH_CALCS,
"%s: start",
__func__);
@@ -797,9 +795,7 @@ enum dc_status dce110_validate_bandwidth(
result = DC_OK;
if (result == DC_FAIL_BANDWIDTH_VALIDATE)
- dal_logger_write(dc->ctx->logger,
- LOG_MAJOR_BWM,
- LOG_MINOR_BWM_MODE_VALIDATION,
+ dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
"%s: %dx%d@%d Bandwidth validation failed!\n",
__func__,
context->targets[0]->public.streams[0]->timing.h_addressable,
@@ -809,12 +805,11 @@ enum dc_status dce110_validate_bandwidth(
if (memcmp(&dc->current_context->bw_results,
&context->bw_results, sizeof(context->bw_results))) {
struct log_entry log_entry;
- dal_logger_open(
+ dm_logger_open(
dc->ctx->logger,
&log_entry,
- LOG_MAJOR_BWM,
- LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS);
- dal_logger_append(&log_entry, "%s: finish,\n"
+ LOG_BANDWIDTH_CALCS);
+ dm_logger_append(&log_entry, "%s: finish,\n"
"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
"stutMark_b: %d stutMark_a: %d\n",
__func__,
@@ -824,7 +819,7 @@ enum dc_status dce110_validate_bandwidth(
context->bw_results.urgent_wm_ns[0].a_mark,
context->bw_results.stutter_exit_wm_ns[0].b_mark,
context->bw_results.stutter_exit_wm_ns[0].a_mark);
- dal_logger_append(&log_entry,
+ dm_logger_append(&log_entry,
"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
"stutMark_b: %d stutMark_a: %d\n",
context->bw_results.nbp_state_change_wm_ns[1].b_mark,
@@ -833,7 +828,7 @@ enum dc_status dce110_validate_bandwidth(
context->bw_results.urgent_wm_ns[1].a_mark,
context->bw_results.stutter_exit_wm_ns[1].b_mark,
context->bw_results.stutter_exit_wm_ns[1].a_mark);
- dal_logger_append(&log_entry,
+ dm_logger_append(&log_entry,
"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
context->bw_results.nbp_state_change_wm_ns[2].b_mark,
@@ -843,7 +838,7 @@ enum dc_status dce110_validate_bandwidth(
context->bw_results.stutter_exit_wm_ns[2].b_mark,
context->bw_results.stutter_exit_wm_ns[2].a_mark,
context->bw_results.stutter_mode_enable);
- dal_logger_append(&log_entry,
+ dm_logger_append(&log_entry,
"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
"sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
context->bw_results.cpuc_state_change_enable,
@@ -855,7 +850,7 @@ enum dc_status dce110_validate_bandwidth(
context->bw_results.required_sclk_deep_sleep,
context->bw_results.required_yclk,
context->bw_results.blackout_recovery_time_us);
- dal_logger_close(&log_entry);
+ dm_logger_close(&log_entry);
}
return result;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
index de948452cd7a..120f4bd619b5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
@@ -1844,8 +1844,7 @@ bool dce110_tg_set_blank(struct timing_generator *tg,
}
if (counter == 100) {
- dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(tg->ctx->logger, LOG_ERROR,
"timing generator %d blank timing out.\n",
tg110->controller_id);
return false;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
index a34025aa8a34..aadeeb33c53f 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
@@ -112,8 +112,7 @@ static bool dce110_timing_generator_v_blank_crtc(struct timing_generator *tg)
}
if (!counter) {
- dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(tg->ctx->logger, LOG_ERROR,
"timing generator %d blank timing out.\n",
tg110->controller_id);
return false;
@@ -635,8 +634,7 @@ static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_gener
static bool dce110_timing_generator_v_did_triggered_reset_occur(
struct timing_generator *tg)
{
- dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(tg->ctx->logger, LOG_ERROR,
"Timing Sync not supported on underlay pipe\n");
return false;
}
@@ -645,8 +643,7 @@ static void dce110_timing_generator_v_setup_global_swap_lock(
struct timing_generator *tg,
const struct dcp_gsl_params *gsl_params)
{
- dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(tg->ctx->logger, LOG_ERROR,
"Timing Sync not supported on underlay pipe\n");
return;
}
@@ -655,8 +652,7 @@ static void dce110_timing_generator_v_enable_reset_trigger(
struct timing_generator *tg,
int source_tg_inst)
{
- dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(tg->ctx->logger, LOG_ERROR,
"Timing Sync not supported on underlay pipe\n");
return;
}
@@ -664,8 +660,7 @@ static void dce110_timing_generator_v_enable_reset_trigger(
static void dce110_timing_generator_v_disable_reset_trigger(
struct timing_generator *tg)
{
- dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(tg->ctx->logger, LOG_ERROR,
"Timing Sync not supported on underlay pipe\n");
return;
}
@@ -673,8 +668,7 @@ static void dce110_timing_generator_v_disable_reset_trigger(
static void dce110_timing_generator_v_tear_down_global_swap_lock(
struct timing_generator *tg)
{
- dal_logger_write(tg->ctx->logger, LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(tg->ctx->logger, LOG_ERROR,
"Timing Sync not supported on underlay pipe\n");
return;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
index 20d680ab0942..01168b46df84 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
@@ -566,9 +566,7 @@ int32_t dce110_transform_get_max_num_of_supported_lines(
break;
default:
- dal_logger_write(xfm->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(xfm->ctx->logger, LOG_WARNING,
"%s: Invalid LB pixel depth",
__func__);
ASSERT_CRITICAL(false);
@@ -649,9 +647,7 @@ bool dce110_transform_get_current_pixel_storage_depth(
*depth = LB_PIXEL_DEPTH_36BPP;
break;
default:
- dal_logger_write(xfm->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(xfm->ctx->logger, LOG_WARNING,
"%s: Invalid LB pixel depth",
__func__);
*depth = LB_PIXEL_DEPTH_30BPP;
@@ -762,9 +758,7 @@ bool dce110_transform_set_pixel_storage_depth(
if (!(xfm110->lb_pixel_depth_supported & depth)) {
/*we should use unsupported capabilities
* unless it is required by w/a*/
- dal_logger_write(xfm->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(xfm->ctx->logger, LOG_WARNING,
"%s: Capability not supported",
__func__);
}
@@ -829,9 +823,7 @@ bool dce110_transform_v_get_current_pixel_storage_depth(
*depth = LB_PIXEL_DEPTH_36BPP;
break;
default:
- dal_logger_write(xfm->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(xfm->ctx->logger, LOG_WARNING,
"%s: Invalid LB pixel depth",
__func__);
*depth = LB_PIXEL_DEPTH_30BPP;
@@ -900,9 +892,7 @@ bool dce110_transform_v_set_pixel_storage_depth(
if (!(xfm110->lb_pixel_depth_supported & depth)) {
/*we should use unsupported capabilities
* unless it is required by w/a*/
- dal_logger_write(xfm->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(xfm->ctx->logger, LOG_WARNING,
"%s: Capability not supported",
__func__);
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c
index 80aa6df99fc9..d9db22607300 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_clock_source.c
@@ -58,9 +58,7 @@ uint32_t dce112_get_pix_clk_dividers(
if (pix_clk_params == NULL || pll_settings == NULL
|| pix_clk_params->requested_pix_clk == 0) {
- dal_logger_write(cs->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(cs->ctx->logger, LOG_ERROR,
"%s: Invalid parameters!!\n", __func__);
return 0;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
index 1940d9868e90..1b0792e0219a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
@@ -130,10 +130,8 @@ static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
LOW_POWER_TILING_NUM_PIPES);
break;
default:
- dal_logger_write(
- cp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp110->base.ctx->logger, LOG_WARNING,
"%s: Invalid LPT NUM_PIPES!!!",
__func__);
break;
@@ -178,10 +176,8 @@ static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
LOW_POWER_TILING_NUM_BANKS);
break;
default:
- dal_logger_write(
- cp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp110->base.ctx->logger, LOG_WARNING,
"%s: Invalid LPT NUM_BANKS!!!",
__func__);
break;
@@ -214,10 +210,8 @@ static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
break;
default:
- dal_logger_write(
- cp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp110->base.ctx->logger, LOG_WARNING,
"%s: Invalid LPT INTERLEAVE_SIZE!!!",
__func__);
break;
@@ -260,19 +254,15 @@ static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
LOW_POWER_TILING_ROW_SIZE);
break;
default:
- dal_logger_write(
- cp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp110->base.ctx->logger, LOG_WARNING,
"%s: Invalid LPT ROW_SIZE!!!",
__func__);
break;
}
} else {
- dal_logger_write(
- cp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp110->base.ctx->logger, LOG_WARNING,
"%s: LPT MC Configuration is not provided",
__func__);
}
@@ -322,10 +312,8 @@ static void wait_for_fbc_state_changed(
}
if (counter == 10) {
- dal_logger_write(
- cp110->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp110->base.ctx->logger, LOG_WARNING,
"%s: wait counter exceeded, changes to HW not applied",
__func__);
}
@@ -538,10 +526,8 @@ void dce112_compressor_program_compressed_surface_address_and_pitch(
if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
fbc_pitch = fbc_pitch / 8;
else
- dal_logger_write(
- compressor->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ compressor->ctx->logger, LOG_WARNING,
"%s: Unexpected DCE11 compression ratio",
__func__);
@@ -705,10 +691,8 @@ void dce112_compressor_program_lpt_control(
LOW_POWER_TILING_MODE);
break;
default:
- dal_logger_write(
- compressor->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ compressor->ctx->logger, LOG_WARNING,
"%s: Invalid selected DRAM channels for LPT!!!",
__func__);
break;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_opp_formatter.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_opp_formatter.c
index c39251a287af..2d9072138834 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_opp_formatter.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_opp_formatter.c
@@ -184,8 +184,7 @@ static void program_formatter_reset_dig_resync_fifo(struct output_pixel_processo
}
if (counter == 0)
- dal_logger_write(opp->ctx->logger, LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(opp->ctx->logger, LOG_ERROR,
"%s:opp program formattter reset dig resync info time out.\n",
__func__);
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 0c976efb6178..ab203dfd2914 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -768,10 +768,8 @@ enum dc_status dce112_validate_bandwidth(
{
enum dc_status result = DC_ERROR_UNEXPECTED;
- dal_logger_write(
- dc->ctx->logger,
- LOG_MAJOR_BWM,
- LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
+ dm_logger_write(
+ dc->ctx->logger, LOG_BANDWIDTH_CALCS,
"%s: start",
__func__);
@@ -787,21 +785,18 @@ enum dc_status dce112_validate_bandwidth(
result = DC_OK;
if (result == DC_FAIL_BANDWIDTH_VALIDATE)
- dal_logger_write(dc->ctx->logger,
- LOG_MAJOR_BWM,
- LOG_MINOR_BWM_MODE_VALIDATION,
+ dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
"%s: Bandwidth validation failed!",
__func__);
if (memcmp(&dc->current_context->bw_results,
&context->bw_results, sizeof(context->bw_results))) {
struct log_entry log_entry;
- dal_logger_open(
+ dm_logger_open(
dc->ctx->logger,
&log_entry,
- LOG_MAJOR_BWM,
- LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS);
- dal_logger_append(&log_entry, "%s: finish,\n"
+ LOG_BANDWIDTH_CALCS);
+ dm_logger_append(&log_entry, "%s: finish,\n"
"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
"stutMark_b: %d stutMark_a: %d\n",
__func__,
@@ -811,7 +806,7 @@ enum dc_status dce112_validate_bandwidth(
context->bw_results.urgent_wm_ns[0].a_mark,
context->bw_results.stutter_exit_wm_ns[0].b_mark,
context->bw_results.stutter_exit_wm_ns[0].a_mark);
- dal_logger_append(&log_entry,
+ dm_logger_append(&log_entry,
"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
"stutMark_b: %d stutMark_a: %d\n",
context->bw_results.nbp_state_change_wm_ns[1].b_mark,
@@ -820,7 +815,7 @@ enum dc_status dce112_validate_bandwidth(
context->bw_results.urgent_wm_ns[1].a_mark,
context->bw_results.stutter_exit_wm_ns[1].b_mark,
context->bw_results.stutter_exit_wm_ns[1].a_mark);
- dal_logger_append(&log_entry,
+ dm_logger_append(&log_entry,
"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
context->bw_results.nbp_state_change_wm_ns[2].b_mark,
@@ -830,7 +825,7 @@ enum dc_status dce112_validate_bandwidth(
context->bw_results.stutter_exit_wm_ns[2].b_mark,
context->bw_results.stutter_exit_wm_ns[2].a_mark,
context->bw_results.stutter_mode_enable);
- dal_logger_append(&log_entry,
+ dm_logger_append(&log_entry,
"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
"sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
context->bw_results.cpuc_state_change_enable,
@@ -842,7 +837,7 @@ enum dc_status dce112_validate_bandwidth(
context->bw_results.required_sclk_deep_sleep,
context->bw_results.required_yclk,
context->bw_results.blackout_recovery_time_us);
- dal_logger_close(&log_entry);
+ dm_logger_close(&log_entry);
}
return result;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
index a05a3cb7b7d2..667be43aaa07 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
@@ -142,10 +142,8 @@ static uint32_t lpt_memory_control_config(struct dce80_compressor *cp80,
LOW_POWER_TILING_NUM_PIPES);
break;
default:
- dal_logger_write(
- cp80->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp80->base.ctx->logger, LOG_WARNING,
"%s: Invalid LPT NUM_PIPES!!!",
__func__);
break;
@@ -190,10 +188,8 @@ static uint32_t lpt_memory_control_config(struct dce80_compressor *cp80,
LOW_POWER_TILING_NUM_BANKS);
break;
default:
- dal_logger_write(
- cp80->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp80->base.ctx->logger, LOG_WARNING,
"%s: Invalid LPT NUM_BANKS!!!",
__func__);
break;
@@ -226,10 +222,8 @@ static uint32_t lpt_memory_control_config(struct dce80_compressor *cp80,
LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
break;
default:
- dal_logger_write(
- cp80->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp80->base.ctx->logger, LOG_WARNING,
"%s: Invalid LPT INTERLEAVE_SIZE!!!",
__func__);
break;
@@ -272,19 +266,15 @@ static uint32_t lpt_memory_control_config(struct dce80_compressor *cp80,
LOW_POWER_TILING_ROW_SIZE);
break;
default:
- dal_logger_write(
- cp80->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp80->base.ctx->logger, LOG_WARNING,
"%s: Invalid LPT ROW_SIZE!!!",
__func__);
break;
}
} else {
- dal_logger_write(
- cp80->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp80->base.ctx->logger, LOG_WARNING,
"%s: LPT MC Configuration is not provided",
__func__);
}
@@ -334,10 +324,8 @@ static void wait_for_fbc_state_changed(
}
if (counter == 10) {
- dal_logger_write(
- cp80->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ cp80->base.ctx->logger, LOG_WARNING,
"%s: wait counter exceeded, changes to HW not applied",
__func__);
}
@@ -538,10 +526,8 @@ void dce80_compressor_program_compressed_surface_address_and_pitch(
if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
fbc_pitch = fbc_pitch / 8;
else
- dal_logger_write(
- compressor->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ compressor->ctx->logger, LOG_WARNING,
"%s: Unexpected DCE8 compression ratio",
__func__);
@@ -686,10 +672,8 @@ void dce80_compressor_program_lpt_control(
LOW_POWER_TILING_MODE);
break;
default:
- dal_logger_write(
- compressor->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(
+ compressor->ctx->logger, LOG_WARNING,
"%s: Invalid selected DRAM channels for LPT!!!",
__func__);
break;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
index fab427cf926f..bd364eeb6916 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
@@ -123,9 +123,7 @@ static void dce80_link_encoder_enable_tmds_output(
result = link_transmitter_control(enc110, &cntl);
if (result != BP_RESULT_OK) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_ENCODER,
+ dm_logger_write(ctx->logger, LOG_ERROR,
"%s: Failed to execute VBIOS command table!\n",
__func__);
BREAK_TO_DEBUGGER();
@@ -183,9 +181,7 @@ static void dce80_link_encoder_enable_dp_output(
result = link_transmitter_control(enc110, &cntl);
if (result != BP_RESULT_OK) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_ENCODER,
+ dm_logger_write(ctx->logger, LOG_ERROR,
"%s: Failed to execute VBIOS command table!\n",
__func__);
BREAK_TO_DEBUGGER();
@@ -308,9 +304,7 @@ bool dce80_link_encoder_construct(
break;
}
- dal_logger_write(init_data->ctx->logger,
- LOG_MAJOR_I2C_AUX,
- LOG_MINOR_I2C_AUX_CFG,
+ dm_logger_write(init_data->ctx->logger, LOG_I2C_AUX,
"Using channel: %s [%d]\n",
DECODE_CHANNEL_ID(init_data->channel),
init_data->channel);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
index c8841c17cb64..5e08a2dfb039 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
@@ -143,9 +143,7 @@ static void allocate_mem_input(
} while (retry_count > 0);
if (field == 0)
- dal_logger_write(mi->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(mi->ctx->logger, LOG_ERROR,
"%s: DMIF allocation failed",
__func__);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c
index 14362b40f68b..648e3ef35d91 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_regamma.c
@@ -427,9 +427,7 @@ static void program_pwl(
}
if (counter == max_tries) {
- dal_logger_write(opp80->base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_CONTROLLER,
+ dm_logger_write(opp80->base.ctx->logger, LOG_WARNING,
"%s: regamma lut was not powered on "
"in a timely manner,"
" programming still proceeds\n",
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
index fd29892c5402..264d260320a6 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
@@ -591,9 +591,7 @@ bool dce80_transform_get_current_pixel_storage_depth(
*depth = LB_PIXEL_DEPTH_36BPP;
break;
default:
- dal_logger_write(xfm->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(xfm->ctx->logger, LOG_WARNING,
"%s: Invalid LB pixel depth",
__func__);
*depth = LB_PIXEL_DEPTH_30BPP;
@@ -706,9 +704,7 @@ bool dce80_transform_set_pixel_storage_depth(
if (!(xfm80->lb_pixel_depth_supported & depth)) {
/*we should use unsupported capabilities
* unless it is required by w/a*/
- dal_logger_write(xfm->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(xfm->ctx->logger, LOG_WARNING,
"%s: Capability not supported",
__func__);
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
index 1e30bbb58efc..140acc1993f3 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_scl.c
@@ -666,9 +666,7 @@ bool dce80_transform_set_scaler(
program_two_taps_filter(xfm80, false, true);
if (!program_multi_taps_filter(xfm80, data, false)) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_DCP,
- LOG_MINOR_DCP_SCALER,
+ dm_logger_write(ctx->logger, LOG_SCALER,
"Failed vertical taps programming\n");
return false;
}
@@ -680,9 +678,7 @@ bool dce80_transform_set_scaler(
program_two_taps_filter(xfm80, false, false);
if (!program_multi_taps_filter(xfm80, data, true)) {
- dal_logger_write(ctx->logger,
- LOG_MAJOR_DCP,
- LOG_MINOR_DCP_SCALER,
+ dm_logger_write(ctx->logger, LOG_SCALER,
"Failed horizontal taps programming\n");
return false;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dm_helpers.h b/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
index 6fa69703f929..d6c52d31f0f0 100644
--- a/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/dal/dc/dm_helpers.h
@@ -35,42 +35,11 @@
struct dp_mst_stream_allocation_table;
-enum conn_event {
- CONN_EVENT_MODE_SET,
- CONN_EVENT_DETECTION,
- CONN_EVENT_LINK_TRAINING,
- CONN_EVENT_LINK_LOSS,
- CONN_EVENT_UNDERFLOW,
-};
-
enum dc_edid_status dm_helpers_parse_edid_caps(
struct dc_context *ctx,
const struct dc_edid *edid,
struct dc_edid_caps *edid_caps);
-
-/* Connectivity log format:
- * [time stamp] [drm] [Major_minor] [connector name] message.....
- * eg:
- * [ 26.590965] [drm] [Conn_LKTN] [DP-1] HBRx4 pass VS=0, PE=0^
- * [ 26.881060] [drm] [Conn_Mode] [DP-1] {2560x1080, 2784x1111@185580Khz}^
- */
-
-#define CONN_DATA_DETECT(link, hex_data, hex_len, ...) \
- dm_helper_conn_log(link->ctx, &link->public, hex_data, hex_len, \
- CONN_EVENT_DETECTION, ##__VA_ARGS__)
-
-#define CONN_DATA_LINK_LOSS(link, hex_data, hex_len, ...) \
- dm_helper_conn_log(link->ctx, &link->public, hex_data, hex_len, \
- CONN_EVENT_LINK_LOSS, ##__VA_ARGS__)
-
-#define CONN_MSG_LT(link, ...) \
- dm_helper_conn_log(link->ctx, &link->public, NULL, 0, \
- CONN_EVENT_LINK_TRAINING, ##__VA_ARGS__)
-
-#define CONN_MSG_MODE(link, ...) \
- dm_helper_conn_log(link->ctx, &link->public, NULL, 0, \
- CONN_EVENT_MODE_SET, ##__VA_ARGS__)
/*
* Writes payload allocation table in immediate downstream device.
*/
@@ -128,12 +97,5 @@ bool dm_helpers_submit_i2c(
const struct dc_link *link,
struct i2c_command *cmd);
-void dm_helper_conn_log(struct dc_context *ctx,
- const struct dc_link *link,
- uint8_t *hex_data,
- int hex_data_count,
- enum conn_event event,
- const char *msg,
- ...);
#endif /* __DM_HELPERS__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
index 0223053767f6..44bad17fa318 100644
--- a/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dm_services_types.h
@@ -26,37 +26,7 @@
#ifndef __DM_SERVICES_TYPES_H__
#define __DM_SERVICES_TYPES_H__
-#if defined __KERNEL__
-
-#include <asm/byteorder.h>
-#include <linux/types.h>
-#include <drm/drmP.h>
-
-#include "cgs_linux.h"
-
-#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU)
-#define BIGENDIAN_CPU
-#elif defined(__LITTLE_ENDIAN) && !defined(LITTLEENDIAN_CPU)
-#define LITTLEENDIAN_CPU
-#endif
-
-#undef READ
-#undef WRITE
-#undef FRAME_SIZE
-
-#define dm_output_to_console(fmt, ...) DRM_INFO(fmt, ##__VA_ARGS__)
-
-#define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
-
-#define dm_debug(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
-
-#define dm_vlog(fmt, args) vprintk(fmt, args)
-
-#define dm_min(x, y) min(x, y)
-#define dm_max(x, y) max(x, y)
-
-#endif
-
+#include "os_types.h"
#include "dc_types.h"
struct dm_pp_clock_range {
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
index 36a08a5a8164..7671e49ffa49 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
@@ -35,7 +35,7 @@
* Macro definitions
*****************************************************************************/
-#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_GPU, \
+#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL( \
"%s:%s()\n", __FILE__, __func__)
/******************************************************************************
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
index 1f5bed80bdea..024972ee0242 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
@@ -150,9 +150,7 @@ static bool set_min_clocks_state(
if (clocks_state > dc->max_clks_state) {
/*Requested state exceeds max supported state.*/
- dal_logger_write(base->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(base->ctx->logger, LOG_WARNING,
"Requested state exceeds max supported state");
return false;
} else if (clocks_state == base->cur_min_clks_state) {
@@ -176,9 +174,7 @@ static bool set_min_clocks_state(
break;
case CLOCKS_STATE_INVALID:
default:
- dal_logger_write(base->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(base->ctx->logger, LOG_WARNING,
"Requested state invalid state");
return false;
}
@@ -298,9 +294,7 @@ static uint32_t get_validation_clock(struct display_clock *dc)
case CLOCKS_STATE_INVALID:
default:
/*Invalid Clocks State*/
- dal_logger_write(dc->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(dc->ctx->logger, LOG_WARNING,
"Invalid clock state");
/* just return the display engine clock for
* lowest supported state*/
@@ -461,9 +455,7 @@ static uint32_t calc_single_display_min_clks(
bool panning_allowed = false; /* TODO: receive this value from AS */
if (params == NULL) {
- dal_logger_write(base->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(base->ctx->logger, LOG_WARNING,
"Invalid input parameter in %s",
__func__);
return 0;
@@ -483,9 +475,7 @@ static uint32_t calc_single_display_min_clks(
params->source_view.height,
params->dest_view.height);
} else {
- dal_logger_write(base->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(base->ctx->logger, LOG_WARNING,
"Destination height or width is 0!\n");
}
@@ -790,9 +780,7 @@ static enum clocks_state get_required_clocks_state(
if (!req_clocks) {
/* NULL pointer*/
- dal_logger_write(dc->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(dc->ctx->logger, LOG_WARNING,
"%s: Invalid parameter",
__func__);
return CLOCKS_STATE_INVALID;
@@ -949,9 +937,7 @@ static bool dal_display_clock_dce110_construct(
dc110->dfs_bypass_disp_clk = 0;
if (!display_clock_integrated_info_construct(dc110, as))
- dal_logger_write(dc_base->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(dc_base->ctx->logger, LOG_WARNING,
"Cannot obtain VBIOS integrated info\n");
dc110->gpu_pll_ss_percentage = 0;
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
index bf244579e0f1..cef5008cd08d 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
@@ -35,7 +35,7 @@
* Macro definitions
*****************************************************************************/
-#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL(LOG_MINOR_COMPONENT_GPU, \
+#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL(\
"%s:%s()\n", __FILE__, __func__)
/******************************************************************************
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
index 77ccb92da623..73f30ddf2d52 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
@@ -125,9 +125,7 @@ bool dispclk_dce112_set_min_clocks_state(
if (clocks_state > dc->max_clks_state) {
/*Requested state exceeds max supported state.*/
- dal_logger_write(base->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(base->ctx->logger, LOG_WARNING,
"Requested state exceeds max supported state");
return false;
} else if (clocks_state == base->cur_min_clks_state) {
@@ -151,9 +149,7 @@ bool dispclk_dce112_set_min_clocks_state(
break;
case CLOCKS_STATE_INVALID:
default:
- dal_logger_write(base->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(base->ctx->logger, LOG_WARNING,
"Requested state invalid state");
return false;
}
@@ -275,9 +271,7 @@ uint32_t dispclk_dce112_get_validation_clock(struct display_clock *dc)
case CLOCKS_STATE_INVALID:
default:
/*Invalid Clocks State*/
- dal_logger_write(dc->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(dc->ctx->logger, LOG_WARNING,
"Invalid clock state");
/* just return the display engine clock for
* lowest supported state*/
@@ -438,9 +432,7 @@ static uint32_t calc_single_display_min_clks(
bool panning_allowed = false; /* TODO: receive this value from AS */
if (params == NULL) {
- dal_logger_write(base->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(base->ctx->logger, LOG_WARNING,
"Invalid input parameter in %s",
__func__);
return 0;
@@ -460,9 +452,7 @@ static uint32_t calc_single_display_min_clks(
params->source_view.height,
params->dest_view.height);
} else {
- dal_logger_write(base->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(base->ctx->logger, LOG_WARNING,
"Destination height or width is 0!\n");
}
@@ -754,9 +744,7 @@ enum clocks_state dispclk_dce112_get_required_clocks_state(
if (!req_clocks) {
/* NULL pointer*/
- dal_logger_write(dc->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(dc->ctx->logger, LOG_WARNING,
"%s: Invalid parameter",
__func__);
return CLOCKS_STATE_INVALID;
@@ -876,9 +864,7 @@ bool dal_display_clock_dce112_construct(
dc112->dfs_bypass_disp_clk = 0;
if (!display_clock_integrated_info_construct(dc112, as))
- dal_logger_write(dc_base->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(dc_base->ctx->logger, LOG_WARNING,
"Cannot obtain VBIOS integrated info\n");
dc112->gpu_pll_ss_percentage = 0;
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
index 109e249c39ec..6c5c656c0166 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
@@ -587,9 +587,7 @@ static bool set_min_clocks_state(
if (clocks_state > disp_clk->max_clks_state) {
/*Requested state exceeds max supported state.*/
- dal_logger_write(dc->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(dc->ctx->logger, LOG_WARNING,
"Requested state exceeds max supported state");
return false;
} else if (clocks_state == dc->cur_min_clks_state) {
@@ -613,9 +611,7 @@ static bool set_min_clocks_state(
break;
case CLOCKS_STATE_INVALID:
default:
- dal_logger_write(dc->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(dc->ctx->logger, LOG_WARNING,
"Requested state invalid state");
return false;
}
@@ -897,9 +893,7 @@ static bool display_clock_construct(
display_clock_ss_construct(disp_clk, as);
if (!display_clock_integrated_info_construct(disp_clk, as)) {
- dal_logger_write(dc_base->ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_GPU,
+ dm_logger_write(dc_base->ctx->logger, LOG_WARNING,
"Cannot obtain VBIOS integrated info");
}
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
index 3a20c4342774..b4ced869c4bd 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
@@ -898,10 +898,8 @@ bool i2c_hw_engine_dce110_construct(
XTAL_REF_DIV);
if (xtal_ref_div == 0) {
- dal_logger_write(
- hw_engine->base.base.base.ctx->logger,
- LOG_MAJOR_WARNING,
- LOG_MINOR_COMPONENT_I2C_AUX,
+ dm_logger_write(
+ hw_engine->base.base.base.ctx->logger, LOG_WARNING,
"Invalid base timer divider\n",
__func__);
xtal_ref_div = 2;
diff --git a/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
index 32af9b45c858..f3eda1b4eebf 100644
--- a/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
@@ -161,10 +161,8 @@ bool dal_irq_service_dummy_set(
const struct irq_source_info *info,
bool enable)
{
- dal_logger_write(
- irq_service->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_IRQ_SERVICE,
+ dm_logger_write(
+ irq_service->ctx->logger, LOG_ERROR,
"%s: called for non-implemented irq source\n",
__func__);
return false;
@@ -174,10 +172,8 @@ bool dal_irq_service_dummy_ack(
struct irq_service *irq_service,
const struct irq_source_info *info)
{
- dal_logger_write(
- irq_service->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_IRQ_SERVICE,
+ dm_logger_write(
+ irq_service->ctx->logger, LOG_ERROR,
"%s: called for non-implemented irq source\n",
__func__);
return false;
diff --git a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
index 328c77034bc5..fbaa2fc00ddb 100644
--- a/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
@@ -97,10 +97,8 @@ bool dal_irq_service_set(
find_irq_source_info(irq_service, source);
if (!info) {
- dal_logger_write(
- irq_service->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_IRQ_SERVICE,
+ dm_logger_write(
+ irq_service->ctx->logger, LOG_ERROR,
"%s: cannot find irq info table entry for %d\n",
__func__,
source);
@@ -137,10 +135,8 @@ bool dal_irq_service_ack(
find_irq_source_info(irq_service, source);
if (!info) {
- dal_logger_write(
- irq_service->ctx->logger,
- LOG_MAJOR_ERROR,
- LOG_MINOR_COMPONENT_IRQ_SERVICE,
+ dm_logger_write(
+ irq_service->ctx->logger, LOG_ERROR,
"%s: cannot find irq info table entry for %d\n",
__func__,
source);
diff --git a/drivers/gpu/drm/amd/dal/dc/os_types.h b/drivers/gpu/drm/amd/dal/dc/os_types.h
new file mode 100644
index 000000000000..459a2741eccb
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/os_types.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2012-16 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _OS_TYPES_H_
+#define _OS_TYPES_H_
+
+#if defined __KERNEL__
+
+#include <asm/byteorder.h>
+#include <linux/types.h>
+#include <drm/drmP.h>
+
+#include "cgs_linux.h"
+
+#if defined(__BIG_ENDIAN) && !defined(BIGENDIAN_CPU)
+#define BIGENDIAN_CPU
+#elif defined(__LITTLE_ENDIAN) && !defined(LITTLEENDIAN_CPU)
+#define LITTLEENDIAN_CPU
+#endif
+
+#undef READ
+#undef WRITE
+#undef FRAME_SIZE
+
+#define dm_output_to_console(fmt, ...) DRM_INFO(fmt, ##__VA_ARGS__)
+
+#define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
+
+#define dm_debug(fmt, ...) DRM_DEBUG_KMS(fmt, ##__VA_ARGS__)
+
+#define dm_vlog(fmt, args) vprintk(fmt, args)
+
+#define dm_min(x, y) min(x, y)
+#define dm_max(x, y) max(x, y)
+
+#endif
+
+
+#endif /* _OS_TYPES_H_ */
diff --git a/drivers/gpu/drm/amd/dal/include/fixed31_32.h b/drivers/gpu/drm/amd/dal/include/fixed31_32.h
index 05f04a68232a..c28de167250f 100644
--- a/drivers/gpu/drm/amd/dal/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/dal/include/fixed31_32.h
@@ -26,6 +26,8 @@
#ifndef __DAL_FIXED31_32_H__
#define __DAL_FIXED31_32_H__
+#include "os_types.h"
+
/*
* @brief
* Arithmetic operations on real numbers
diff --git a/drivers/gpu/drm/amd/dal/include/fixed32_32.h b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
index 5fca9573930b..c7ddd0e435eb 100644
--- a/drivers/gpu/drm/amd/dal/include/fixed32_32.h
+++ b/drivers/gpu/drm/amd/dal/include/fixed32_32.h
@@ -23,9 +23,12 @@
*
*/
+
#ifndef __DAL_FIXED32_32_H__
#define __DAL_FIXED32_32_H__
+#include "os_types.h"
+
struct fixed32_32 {
uint64_t value;
};
diff --git a/drivers/gpu/drm/amd/dal/include/logger_interface.h b/drivers/gpu/drm/amd/dal/include/logger_interface.h
index e4e6b3a62044..859215630914 100644
--- a/drivers/gpu/drm/amd/dal/include/logger_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/logger_interface.h
@@ -28,13 +28,8 @@
#include "logger_types.h"
-struct dal_logger;
struct dc_context;
-union logger_flags;
-
-/*
- * TODO: This logger functionality needs to be implemented and reworked.
- */
+struct dc_link;
/*
*
@@ -46,92 +41,45 @@ struct dal_logger *dal_logger_create(struct dc_context *ctx);
uint32_t dal_logger_destroy(struct dal_logger **logger);
-uint32_t dal_logger_get_mask(
- struct dal_logger *logger,
- enum log_major lvl_major, enum log_minor lvl_minor);
-
-uint32_t dal_logger_set_mask(
- struct dal_logger *logger,
- enum log_major lvl_major, enum log_minor lvl_minor);
-
-uint32_t dal_logger_get_masks(
- struct dal_logger *logger,
- enum log_major lvl_major);
-
-void dal_logger_set_masks(
- struct dal_logger *logger,
- enum log_major lvl_major, uint32_t log_mask);
-
-uint32_t dal_logger_unset_mask(
+void dm_logger_write(
struct dal_logger *logger,
- enum log_major lvl_major, enum log_minor lvl_minor);
-
-bool dal_logger_should_log(
- struct dal_logger *logger,
- enum log_major major,
- enum log_minor minor);
-
-uint32_t dal_logger_get_flags(
- struct dal_logger *logger);
-
-void dal_logger_set_flags(
- struct dal_logger *logger,
- union logger_flags flags);
-
-void dal_logger_write(
- struct dal_logger *logger,
- enum log_major major,
- enum log_minor minor,
+ enum dc_log_type log_type,
const char *msg,
...);
-void dal_logger_append(
+void dm_logger_append(
struct log_entry *entry,
const char *msg,
...);
-uint32_t dal_logger_read(
- struct dal_logger *logger,
- uint32_t output_buffer_size,
- char *output_buffer,
- uint32_t *bytes_read,
- bool single_line);
-
-void dal_logger_open(
+void dm_logger_open(
struct dal_logger *logger,
struct log_entry *entry,
- enum log_major major,
- enum log_minor minor);
-
-void dal_logger_close(struct log_entry *entry);
+ enum dc_log_type log_type);
-uint32_t dal_logger_get_buffer_size(struct dal_logger *logger);
-
-uint32_t dal_logger_set_buffer_size(
- struct dal_logger *logger,
- uint32_t new_size);
+void dm_logger_close(struct log_entry *entry);
-const struct log_major_info *dal_logger_enum_log_major_info(
- struct dal_logger *logger,
- unsigned int enum_index);
+void dc_conn_log(struct dc_context *ctx,
+ const struct dc_link *link,
+ uint8_t *hex_data,
+ int hex_data_count,
+ enum dc_log_type event,
+ const char *msg,
+ ...);
-const struct log_minor_info *dal_logger_enum_log_minor_info(
- struct dal_logger *logger,
- enum log_major major,
- unsigned int enum_index);
/* Any function which is empty or have incomplete implementation should be
* marked by this macro.
* Note that the message will be printed exactly once for every function
* it is used in order to avoid repeating of the same message. */
-#define DAL_LOGGER_NOT_IMPL(log_minor, fmt, ...) \
+#define DAL_LOGGER_NOT_IMPL(fmt, ...) \
{ \
static bool print_not_impl = true; \
\
if (print_not_impl == true) { \
print_not_impl = false; \
- dal_logger_write(ctx->logger, LOG_MAJOR_WARNING, \
- log_minor, "DAL_NOT_IMPL: " fmt, ##__VA_ARGS__); \
+ dm_logger_write(ctx->logger, LOG_WARNING, \
+ "DAL_NOT_IMPL: " fmt, ##__VA_ARGS__); \
} \
}
@@ -140,13 +88,35 @@ const struct log_minor_info *dal_logger_enum_log_minor_info(
*****************************************************************************/
#define DC_ERROR(...) \
- dal_logger_write(dc_ctx->logger, \
- LOG_MAJOR_ERROR, LOG_MINOR_COMPONENT_DC, \
+ dm_logger_write(dc_ctx->logger, LOG_ERROR, \
__VA_ARGS__);
#define DC_SYNC_INFO(...) \
- dal_logger_write(dc_ctx->logger, \
- LOG_MAJOR_SYNC, LOG_MINOR_SYNC_TIMING, \
+ dm_logger_write(dc_ctx->logger, LOG_SYNC, \
__VA_ARGS__);
+
+/* Connectivity log format:
+ * [time stamp] [drm] [Major_minor] [connector name] message.....
+ * eg:
+ * [ 26.590965] [drm] [Conn_LKTN] [DP-1] HBRx4 pass VS=0, PE=0^
+ * [ 26.881060] [drm] [Conn_Mode] [DP-1] {2560x1080, 2784x1111@185580Khz}^
+ */
+
+#define CONN_DATA_DETECT(link, hex_data, hex_len, ...) \
+ dc_conn_log(link->ctx, &link->public, hex_data, hex_len, \
+ LOG_EVENT_DETECTION, ##__VA_ARGS__)
+
+#define CONN_DATA_LINK_LOSS(link, hex_data, hex_len, ...) \
+ dc_conn_log(link->ctx, &link->public, hex_data, hex_len, \
+ LOG_EVENT_LINK_LOSS, ##__VA_ARGS__)
+
+#define CONN_MSG_LT(link, ...) \
+ dc_conn_log(link->ctx, &link->public, NULL, 0, \
+ LOG_EVENT_LINK_TRAINING, ##__VA_ARGS__)
+
+#define CONN_MSG_MODE(link, ...) \
+ dc_conn_log(link->ctx, &link->public, NULL, 0, \
+ LOG_EVENT_MODE_SET, ##__VA_ARGS__)
+
#endif /* __DAL_LOGGER_INTERFACE_H__ */
diff --git a/drivers/gpu/drm/amd/dal/include/logger_types.h b/drivers/gpu/drm/amd/dal/include/logger_types.h
index ce2b649fad7b..1ea60bb9e716 100644
--- a/drivers/gpu/drm/amd/dal/include/logger_types.h
+++ b/drivers/gpu/drm/amd/dal/include/logger_types.h
@@ -26,305 +26,43 @@
#ifndef __DAL_LOGGER_TYPES_H__
#define __DAL_LOGGER_TYPES_H__
-/*
- * TODO: This logger functionality needs to be implemented and reworked.
- */
-
-struct dal_logger;
-
-enum log_major {
-/*00*/
- LOG_MAJOR_ERROR = 0, /*< DAL subcomponent error MSG*/
-/*01*/ LOG_MAJOR_WARNING, /*< DAL subcomponent warning MSG*/
-/*02*/ LOG_MAJOR_INTERFACE_TRACE,/*< DAL subcomponent interface tracing*/
-/*03*/ LOG_MAJOR_HW_TRACE, /*< Log ASIC register read/write,
- * ATOMBIOS exec table call and delays*/
-
-/*04*/ LOG_MAJOR_MST, /*< related to multi-stream*/
-/*05*/ LOG_MAJOR_DCS, /*< related to Dcs*/
-/*06*/ LOG_MAJOR_DCP, /*< related to Dcp grph and ovl,gamam and csc*/
-/*07*/ LOG_MAJOR_BIOS, /*< related to BiosParser*/
-/*08*/ LOG_MAJOR_REGISTER, /*< register access*/
-/*09*/ LOG_MAJOR_INFO_PACKETS, /*< info packets*/
-/*10*/ LOG_MAJOR_DSAT, /*< related
- * to Display System Analysis Tool*/
-/*11*/ LOG_MAJOR_EC, /*< External Components - MCIL Events/queries,
- * PPLib notifications/queries*/
-/*12*/ LOG_MAJOR_BWM, /*< related to Bandwidth Manager*/
-/*13*/ LOG_MAJOR_MODE_ENUM, /*< related to mode enumeration*/
-/*14*/ LOG_MAJOR_I2C_AUX, /*< i2c and aux channel log*/
-/*15*/ LOG_MAJOR_LINE_BUFFER, /*< Line Buffer object logging activity*/
-/*16*/ LOG_MAJOR_HWSS, /*< HWSS object logging activity*/
-/*17*/ LOG_MAJOR_OPTIMIZATION, /*< Optimization code path*/
-/*18*/ LOG_MAJOR_PERF_MEASURE, /*< Performance measurement dumps*/
-/*19*/ LOG_MAJOR_SYNC, /*< related to HW and SW Synchronization*/
-/*20*/ LOG_MAJOR_BACKLIGHT, /*< related to backlight */
-/*21*/ LOG_MAJOR_INTERRUPTS, /*< logging for all interrupts */
-
-/*22*/ LOG_MAJOR_TM, /*< related to Topology Manager*/
-/*23*/ LOG_MAJOR_DISPLAY_SERVICE, /*< related to Display Service*/
-/*24*/ LOG_MAJOR_FEATURE_OVERRIDE, /*< related to features*/
-/*25*/ LOG_MAJOR_DETECTION, /*< related to detection*/
-/*26*/ LOG_MAJOR_CONNECTIVITY, /*< related to connectivity*/
- LOG_MAJOR_COUNT, /*< count of the Major categories*/
-};
-
-/**
-* @brief defines minor switch for logging. each of these define sub category
-* of log message per LogMajor
-*/
+#include "os_types.h"
-enum log_minor {
+#define MAX_NAME_LEN 32
- /* Special case for 'all' checkbox */
- LOG_MINOR_MASK_ALL = (uint32_t)-1, /* 0xFFFFFFFF */
-/**
-* @brief defines minor category for
-* LOG_MAJOR_ERROR,
-* LOG_MAJOR_WARNING,
-* LOG_MAJOR_INTERFACE_TRACE
-*
-* @note each DAL subcomponent should have a corresponding enum
-*/
- LOG_MINOR_COMPONENT_LINK_SERVICE = 0,
- LOG_MINOR_COMPONENT_DAL_INTERFACE,
- LOG_MINOR_COMPONENT_HWSS,
- LOG_MINOR_COMPONENT_ADAPTER_SERVICE,
- LOG_MINOR_COMPONENT_DISPLAY_SERVICE,
- LOG_MINOR_COMPONENT_TOPOLOGY_MANAGER,
- LOG_MINOR_COMPONENT_ENCODER,
- LOG_MINOR_COMPONENT_I2C_AUX,
- LOG_MINOR_COMPONENT_AUDIO,
- LOG_MINOR_COMPONENT_DISPLAY_CAPABILITY_SERVICE,
- LOG_MINOR_COMPONENT_DMCU,
- LOG_MINOR_COMPONENT_GPU,
- LOG_MINOR_COMPONENT_CONTROLLER,
- LOG_MINOR_COMPONENT_ISR,
- LOG_MINOR_COMPONENT_BIOS,
- LOG_MINOR_COMPONENT_DC,
- LOG_MINOR_COMPONENT_SURFACE,
- LOG_MINOR_COMPONENT_IRQ_SERVICE,
-
-/**
-* @brief define minor category for LogMajor_HardwareTrace
-*
-* @note defines functionality based HW programming trace
-*/
- LOG_MINOR_HW_TRACE_MST = 0,
- LOG_MINOR_HW_TRACE_TRAVIS,
- LOG_MINOR_HW_TRACE_HOTPLUG,
- LOG_MINOR_HW_TRACE_LINK_TRAINING,
- LOG_MINOR_HW_TRACE_SET_MODE,
- LOG_MINOR_HW_TRACE_RESUME_S3,
- LOG_MINOR_HW_TRACE_RESUME_S4,
- LOG_MINOR_HW_TRACE_BOOTUP,
- LOG_MINOR_HW_TRACE_AUDIO,
- LOG_MINOR_HW_TRACE_HPD_IRQ,
- LOG_MINOR_HW_TRACE_INTERRUPT,
- LOG_MINOR_HW_TRACE_MPO,
-
-/**
-* @brief defines minor category for LogMajor_Mst
-*
-* @note define sub functionality related to MST
-*/
- LOG_MINOR_MST_IRQ_HPD_RX = 0,
- LOG_MINOR_MST_IRQ_TIMER,
- LOG_MINOR_MST_NATIVE_AUX,
- LOG_MINOR_MST_SIDEBAND_MSG,
- LOG_MINOR_MST_MSG_TRANSACTION,
- LOG_MINOR_MST_SIDEBAND_MSG_PARSED,
- LOG_MINOR_MST_MSG_TRANSACTION_PARSED,
- LOG_MINOR_MST_AUX_MSG_DPCD_ACCESS,
- LOG_MINOR_MST_PROGRAMMING,
- LOG_MINOR_MST_TOPOLOGY_DISCOVERY,
- LOG_MINOR_MST_CONVERTER_CAPS,
-
-/**
-* @brief defines minor category for LogMajor_DCS
-*
-* @note should define sub functionality related to Dcs
-*/
- LOG_MINOR_DCS_EDID_EMULATOR = 0,
- LOG_MINOR_DCS_DONGLE_DETECTION,
-
-/**
-* @brief defines minor category for DCP
-*
-* @note should define sub functionality related to Dcp
-*/
- LOG_MINOR_DCP_GAMMA_GRPH = 0,
- LOG_MINOR_DCP_GAMMA_OVL,
- LOG_MINOR_DCP_CSC_GRPH,
- LOG_MINOR_DCP_CSC_OVL,
- LOG_MINOR_DCP_SCALER,
- LOG_MINOR_DCP_SCALER_TABLES,
-/**
-* @brief defines minor category for LogMajor_Bios
-*
-* @note define sub functionality related to BiosParser
-*/
- LOG_MINOR_BIOS_CMD_TABLE = 0,
-/**
-* @brief defines minor category for LogMajor_Bios
-*
-* @note define sub functionality related to BiosParser
-*/
- LOG_MINOR_REGISTER_INDEX = 0,
-/**
-* @brief defines minor category for info packets
-*
-*/
- LOG_MINOR_INFO_PACKETS_HDMI = 0,
-
-/**
-* @brief defines minor category for LOG_MAJOR_DSAT
-*
-* @note define sub functionality related to Display System Analysis Tool
-*/
- LOG_MINOR_DSAT_LOGGER = 0,
- LOG_MINOR_DSAT_GET_EDID,
- LOG_MINOR_DSAT_EDID_OVERRIDE,
- LOG_MINOR_DSAT_SET_ADJUSTMENTS,
- LOG_MINOR_DSAT_GET_ADJUSTMENTS,
-
-/**
-* @brief defines minor category for LOG_MAJOR_EC
-*
-* @note define sub functionality related to External components notifications
-*/
- LOG_MINOR_EC_PPLIB_NOTIFY = 0,
- LOG_MINOR_EC_PPLIB_QUERY,
-
-/**
-* @brief defines minor category for LOG_MAJOR_BWM
-*
-* @note define sub functionality related to Bandwidth Manager
-*/
- LOG_MINOR_BWM_MODE_VALIDATION = 0,
- LOG_MINOR_BWM_REQUIRED_BANDWIDTH_CALCS,
-
-/**
-* @brief define minor category for LogMajor_ModeEnum
-*
-* @note defines functionality mode enumeration trace
-*/
- LOG_MINOR_MODE_ENUM_BEST_VIEW_CANDIDATES = 0,
- LOG_MINOR_MODE_ENUM_VIEW_SOLUTION,
- LOG_MINOR_MODE_ENUM_TS_LIST_BUILD,
- LOG_MINOR_MODE_ENUM_TS_LIST,
- LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST,
- LOG_MINOR_MODE_ENUM_MASTER_VIEW_LIST_UPDATE,
-
-/**
-* @brief defines minor category for LogMajor_I2C_AUX
-*
-* @note define sub functionality related to I2c and Aux Channel Log
-*/
- LOG_MINOR_I2C_AUX_LOG = 0,
- LOG_MINOR_I2C_AUX_AUX_TIMESTAMP,
- LOG_MINOR_I2C_AUX_CFG,
-
-/**
-* @brief defines minor category for LogMajor_LineBuffer
-*
-* @note define sub functionality related to LineBuffer
-*/
- LOG_MINOR_LINE_BUFFER_POWERGATING = 0,
-
-/**
-* @brief defines minor category for LogMajor_HWSS
-*
-* @note define sub functionality related to HWSS
-*/
- LOG_MINOR_HWSS_TAPS_VALIDATION = 0,
-
-/**
-* @brief defines minor category for LogMajor_Optimization
-*
-* @note define sub functionality related to Optimization
-*/
- LOG_MINOR_OPTMZ_GENERAL = 0,
- LOG_MINOR_OPTMZ_DO_NOT_TURN_OFF_VCC_DURING_SET_MODE,
-
-/**
-* @brief defines minor category for LogMajor_PerfMeasure
-*
-* @note define sub functionality related to Performance measurement dumps
-*/
- LOG_MINOR_PERF_MEASURE_GENERAL = 0,
- LOG_MINOR_PERF_MEASURE_HEAP_MEMORY,
-
-/**
-* @brief defines minor category for LogMajor_Sync
-*
-* @note define sub functionality related to HW and SW Synchronization
-*/
- LOG_MINOR_SYNC_HW_CLOCK_ADJUST = 0,
- LOG_MINOR_SYNC_TIMING,
-
-/**
-* @brief defines minor category for LogMajor_Backlight
-*
-* @note define sub functionality related to backlight (including VariBright)
-*/
- LOG_MINOR_BACKLIGHT_BRIGHTESS_CAPS = 0,
- LOG_MINOR_BACKLIGHT_DMCU_DELTALUT,
- LOG_MINOR_BACKLIGHT_DMCU_BUILD_DELTALUT,
- LOG_MINOR_BACKLIGHT_INTERFACE,
- LOG_MINOR_BACKLIGHT_LID,
-
-/**
-* @brief defines minor category for LOG_MAJOR_TM
-*
-* @note define sub functionality related to Topology Manager
-*/
- LOG_MINOR_TM_INFO = 0,
- LOG_MINOR_TM_IFACE_TRACE,
- LOG_MINOR_TM_RESOURCES,
- LOG_MINOR_TM_ENCODER_CTL,
- LOG_MINOR_TM_ENG_ASN,
- LOG_MINOR_TM_CONTROLLER_ASN,
- LOG_MINOR_TM_PWR_GATING,
- LOG_MINOR_TM_BUILD_DSP_PATH,
- LOG_MINOR_TM_DISPLAY_DETECT,
- LOG_MINOR_TM_LINK_SRV,
- LOG_MINOR_TM_NOT_IMPLEMENTED,
- LOG_MINOR_TM_COFUNC_PATH,
-
-/**
-* @brief defines minor category for LOG_MAJOR_DISPLAY_SERVICE
-*
-* @note define sub functionality related to Display Service
-*/
- LOG_MINOR_DS_MODE_SETTING = 0,
-
-/**
-* @brief defines minor category for LOG_MAJOR_FEATURE_OVERRIDE
-*
-* @note define sub functionality related to features in adapter service
-*/
- LOG_MINOR_FEATURE_OVERRIDE = 0,
-
-/**
-* @brief defines minor category for LOG_MAJOR_DETECTION
-*
-* @note define sub functionality related to detection
-*/
- LOG_MINOR_DETECTION_EDID_PARSER = 0,
- LOG_MINOR_DETECTION_DP_CAPS,
-
-/**
-* @brief defines minor category for LOG_MAJOR_CONNECTIVITY
-*
-* @note define sub functionality related to connectivity
-*/
- LOG_MINOR_CONNECTIVITY_MODE_SET = 0,
- LOG_MINOR_CONNECTIVITY_DETECTION,
- LOG_MINOR_CONNECTIVITY_LINK_TRAINING,
- LOG_MINOR_CONNECTIVITY_LINK_LOSS,
- LOG_MINOR_CONNECTIVITY_UNDERFLOW,
+struct dal_logger;
+enum dc_log_type {
+ LOG_ERROR = 0,
+ LOG_WARNING,
+ LOG_DC,
+ LOG_SURFACE,
+ LOG_HW_HOTPLUG,
+ LOG_HW_LINK_TRAINING,
+ LOG_HW_SET_MODE,
+ LOG_HW_RESUME_S3,
+ LOG_HW_AUDIO,
+ LOG_HW_HPD_IRQ,
+ LOG_MST,
+ LOG_SCALER,
+ LOG_BIOS,
+ LOG_BANDWIDTH_CALCS,
+ LOG_BANDWIDTH_VALIDATION,
+ LOG_I2C_AUX,
+ LOG_SYNC,
+ LOG_BACKLIGHT,
+ LOG_FEATURE_OVERRIDE,
+ LOG_DETECTION_EDID_PARSER,
+ LOG_DETECTION_DP_CAPS,
+ LOG_RESOURCE,
+ LOG_DML,
+ LOG_EVENT_MODE_SET,
+ LOG_EVENT_DETECTION,
+ LOG_EVENT_LINK_TRAINING,
+ LOG_EVENT_LINK_LOSS,
+ LOG_EVENT_UNDERFLOW,
+
+ LOG_SECTION_TOTAL_COUNT
};
union logger_flags {
@@ -337,10 +75,8 @@ union logger_flags {
};
struct log_entry {
-
struct dal_logger *logger;
- enum log_major major;
- enum log_minor minor;
+ enum dc_log_type type;
char *buf;
uint32_t buf_offset;
@@ -348,20 +84,11 @@ struct log_entry {
};
/**
-* Structure for enumerating LogMajors and LogMinors
+* Structure for enumerating log types
*/
-
-#define MAX_MAJOR_NAME_LEN 32
-#define MAX_MINOR_NAME_LEN 32
-
-struct log_major_info {
- enum log_major major;
- char major_name[MAX_MAJOR_NAME_LEN];
-};
-
-struct log_minor_info {
- enum log_minor minor;
- char minor_name[MAX_MINOR_NAME_LEN];
+struct dc_log_type_info {
+ enum dc_log_type type;
+ char name[MAX_NAME_LEN];
};
#endif /* __DAL_LOGGER_TYPES_H__ */
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 02/76] drm/amd/dal: clean up asic cap
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2016-11-21 23:00 ` [PATCH 01/76] drm/amd/dal: bring all of dc under a single log category table Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 03/76] drm/amd/dal: Remove unused code in dce112 hwss Harry Wentland
` (74 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
ASIC_DATA_LINEBUFFER_NUM:
not used. each pipe has it's own lb.
ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS:
not needed. clk_src management algorithm take care of this.
ASIC_DATA_CLOCKSOURCES_NUM:
verify correct num of clk to create is already baked in resource.
remove duplicate information from hw_asic_id.
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 88 ----------------------
.../amd/dal/dc/asic_capability/asic_capability.c | 5 --
.../dc/asic_capability/carrizo_asic_capability.c | 11 ---
.../dc/asic_capability/hawaii_asic_capability.c | 9 ---
.../dc/asic_capability/polaris10_asic_capability.c | 18 -----
.../dal/dc/asic_capability/tonga_asic_capability.c | 9 ---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 2 +
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 4 +-
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 2 +-
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 9 ++-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 40 ++++++----
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 32 ++++++--
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 11 ++-
drivers/gpu/drm/amd/dal/dc/inc/core_dc.h | 1 +
drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 1 +
drivers/gpu/drm/amd/dal/dc/inc/resource.h | 4 +-
.../amd/dal/include/adapter_service_interface.h | 20 +----
.../drm/amd/dal/include/asic_capability_types.h | 13 +---
18 files changed, 77 insertions(+), 202 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index 57228a87d5a1..4c2c2fc164be 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -109,10 +109,8 @@ static const struct feature_source_entry feature_entry_table[] = {
{FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, false, true},
{FEATURE_ENABLE_DFS_BYPASS, false, true},
{FEATURE_WIRELESS_FULL_TIMING_ADJUSTMENT, false, true},
- {FEATURE_MAX_COFUNC_NON_DP_DISPLAYS, 2, false},
{FEATURE_WIRELESS_LIMIT_720P, false, true},
{FEATURE_MODIFY_TIMINGS_FOR_WIRELESS, false, true},
- {FEATURE_SUPPORTED_HDMI_CONNECTION_NUM, 0, false},
{FEATURE_DETECT_REQUIRE_HPD_HIGH, false, true},
{FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, false, true},
{FEATURE_LB_HIGH_RESOLUTION, false, true},
@@ -453,10 +451,6 @@ static bool get_feature_value_from_data_sources(
}
switch (feature_entry_table[idx].feature_id) {
- case FEATURE_MAX_COFUNC_NON_DP_DISPLAYS:
- *data = as->asic_cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS];
- break;
-
case FEATURE_WIRELESS_LIMIT_720P:
*data = as->asic_cap->caps.WIRELESS_LIMIT_TO_720P;
break;
@@ -469,11 +463,6 @@ static bool get_feature_value_from_data_sources(
*data = as->asic_cap->caps.WIRELESS_TIMING_ADJUSTMENT;
break;
- case FEATURE_SUPPORTED_HDMI_CONNECTION_NUM:
- *data =
- as->asic_cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM];
- break;
-
case FEATURE_DETECT_REQUIRE_HPD_HIGH:
*data = as->asic_cap->caps.HPD_CHECK_FOR_EDID;
break;
@@ -893,72 +882,6 @@ bool dal_adapter_service_is_device_id_supported(struct adapter_service *as,
}
/*
- * dal_adapter_service_get_clock_sources_num
- *
- * Get number of clock sources
- */
-uint8_t dal_adapter_service_get_clock_sources_num(
- struct adapter_service *as)
-{
- struct firmware_info fw_info;
- uint32_t max_clk_src = 0;
- uint32_t num = as->asic_cap->data[ASIC_DATA_CLOCKSOURCES_NUM];
- struct dc_bios *dcb = as->ctx->dc_bios;
-
- /*
- * Check is system supports the use of the External clock source
- * as a clock source for DP
- */
- enum bp_result bp_result = dcb->funcs->get_firmware_info(dcb, &fw_info);
-
- if (BP_RESULT_OK == bp_result &&
- fw_info.external_clock_source_frequency_for_dp != 0)
- ++num;
-
- /*
- * Add clock source for wireless if supported
- */
- num += (uint32_t)wireless_get_clocks_num(as);
-
- /* Check the "max number of clock sources" feature */
- if (dal_adapter_service_get_feature_value(as,
- FEATURE_MAX_CLOCK_SOURCE_NUM,
- &max_clk_src,
- sizeof(uint32_t)))
- if ((max_clk_src != 0) && (max_clk_src < num))
- num = max_clk_src;
-
- return num;
-}
-
-/*
- * dal_adapter_service_get_func_controllers_num
- *
- * Get number of controllers
- */
-uint8_t dal_adapter_service_get_func_controllers_num(
- struct adapter_service *as)
-{
- uint32_t result =
- as->asic_cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM];
-
- /* Check the "max num of controllers" feature,
- * use it for debugging purposes only */
-
- /* Limit number of controllers by OS */
-
- struct asic_feature_flags flags;
-
- flags.raw = as->asic_cap->data[ASIC_DATA_FEATURE_FLAGS];
-
- if (flags.bits.LEGACY_CLIENT &&
- (result > LEGACY_MAX_NUM_OF_CONTROLLERS))
- result = LEGACY_MAX_NUM_OF_CONTROLLERS;
-
- return result;
-}
-
-/*
* dal_adapter_service_is_feature_supported
*
* Return if a given feature is supported by the ASIC. The feature has to be
@@ -1098,17 +1021,6 @@ bool dal_adapter_service_get_firmware_info(
}
/*
- * dal_adapter_service_get_stream_engines_num
- *
- * Get number of stream engines
- */
-uint8_t dal_adapter_service_get_stream_engines_num(
- struct adapter_service *as)
-{
- return as->asic_cap->data[ASIC_DATA_DIGFE_NUM];
-}
-
-/*
* dal_adapter_service_get_feature_value
*
* Get the cached value of a given feature. This value can be a boolean, int,
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
index 3e83b1e4ab9e..24ab4a5b5232 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
@@ -54,15 +54,10 @@ static bool construct(
memset(cap->data, 0, sizeof(cap->data));
/* ASIC data */
- cap->data[ASIC_DATA_VRAM_TYPE] = init->vram_type;
cap->data[ASIC_DATA_VRAM_BITWIDTH] = init->vram_width;
- cap->data[ASIC_DATA_FEATURE_FLAGS] = init->feature_flags;
cap->runtime_flags = init->runtime_flags;
- cap->data[ASIC_DATA_REVISION_ID] = init->hw_internal_rev;
cap->data[ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE] = 10;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 4;
- cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 1;
- cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 0;
cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 25;
cap->data[ASIC_DATA_DOWNSCALE_LIMIT] = 200;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
index 340c1f1a41d6..d23d186c670f 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
@@ -48,23 +48,15 @@ void carrizo_asic_capability_create(struct asic_capability *cap,
{
uint32_t e_fuse_setting;
/* ASIC data */
- cap->data[ASIC_DATA_CONTROLLERS_NUM] = 3;
- cap->data[ASIC_DATA_DIGFE_NUM] = 3;
- cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 3;
- cap->data[ASIC_DATA_LINEBUFFER_NUM] = 3;
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
cap->data[ASIC_DATA_DCE_VERSION] = 0x110; /* DCE 11 */
cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 45;
- cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 2;
cap->data[ASIC_DATA_MC_LATENCY] = 5000;
cap->data[ASIC_DATA_STUTTERMODE] = 0x200A;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
- cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 100;
- cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 1;
- cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
cap->data[ASIC_DATA_DOWNSCALE_LIMIT] = 150;
/* ASIC basic capability */
@@ -135,9 +127,6 @@ void carrizo_asic_capability_create(struct asic_capability *cap,
{
/* Stoney is the same DCE11, but only two pipes, three digs.
* and HW added 64bit back for non SG */
- cap->data[ASIC_DATA_CONTROLLERS_NUM] = 2;
- cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 2;
- cap->data[ASIC_DATA_LINEBUFFER_NUM] = 2;
/*3 DP MST per connector, limited by number of pipe and number
* of Dig.*/
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 2;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
index d5eb323f5e87..6678053d4601 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
@@ -54,11 +54,6 @@ void dal_hawaii_asic_capability_create(struct asic_capability *cap,
uint32_t mc_seq_misc0;
/* ASIC data */
- cap->data[ASIC_DATA_CONTROLLERS_NUM] = 6;
- cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 6;
- cap->data[ASIC_DATA_DIGFE_NUM] = 6;
- cap->data[ASIC_DATA_LINEBUFFER_NUM] = 6;
- cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
cap->data[ASIC_DATA_DCE_VERSION] = 0x80; /* DCE 8.0 */
@@ -67,7 +62,6 @@ void dal_hawaii_asic_capability_create(struct asic_capability *cap,
* in other words 246528 bits. */
cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
- cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 3;
cap->data[ASIC_DATA_MC_LATENCY] = 5000; /* units of ns */
/* StutterModeEnhanced; Quad DMIF Buffer */
@@ -75,9 +69,6 @@ void dal_hawaii_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
- /* 3 HDMI support by default */
- cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
-
cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 40;
mc_seq_misc0 = dm_read_reg(cap->ctx, mmMC_SEQ_MISC0);
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
index 9e4fdfaaf76c..15b1f7a59066 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
@@ -47,23 +47,6 @@ void polaris10_asic_capability_create(struct asic_capability *cap,
{
uint32_t e_fuse_setting;
/* ASIC data */
- if (ASIC_REV_IS_POLARIS11_M(init->hw_internal_rev)) {
- cap->data[ASIC_DATA_CONTROLLERS_NUM] = 5;
- cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 5;
- cap->data[ASIC_DATA_LINEBUFFER_NUM] = 5;
- cap->data[ASIC_DATA_DIGFE_NUM] = 5;
- cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 7;
- cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 5;
- cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 5;
- } else {
- cap->data[ASIC_DATA_CONTROLLERS_NUM] = 6;
- cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 6;
- cap->data[ASIC_DATA_LINEBUFFER_NUM] = 6;
- cap->data[ASIC_DATA_DIGFE_NUM] = 6;
- cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 8;
- cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 6;
- cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 6;
- }
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
cap->data[ASIC_DATA_DCE_VERSION] = 0x112; /* DCE 11 */
@@ -76,7 +59,6 @@ void polaris10_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 100;
- cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 0;
cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
index 8fa4d856a134..2475de9c0bf5 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
@@ -47,27 +47,18 @@ void tonga_asic_capability_create(struct asic_capability *cap,
{
uint32_t e_fuse_setting;
/* ASIC data */
- cap->data[ASIC_DATA_CONTROLLERS_NUM] = 6;
- cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 6;
- cap->data[ASIC_DATA_DIGFE_NUM] = 6;
- cap->data[ASIC_DATA_LINEBUFFER_NUM] = 6;
-
cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
- cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 3;
cap->data[ASIC_DATA_MC_LATENCY] = 5000;
cap->data[ASIC_DATA_STUTTERMODE] = 0x2002;
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
- cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
cap->data[ASIC_DATA_DCE_VERSION] = 0x100; /* DCE 11 */
- cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 40;
- cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 0;
/* ASIC basic capability */
cap->caps.IS_FUSION = true;
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index 47db0fd82fe6..c66cb6607752 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -504,6 +504,8 @@ static bool construct(struct core_dc *dc,
dc_ctx->driver_context = init_params->driver;
dc_ctx->dc = &dc->public;
+ dc->asic_id = init_params->asic_id;
+
/* Create logger */
logger = dal_logger_create(dc_ctx);
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index 44ed32575b02..c2eb27a257d6 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -37,6 +37,7 @@
#include "stream_encoder.h"
#include "link_encoder.h"
#include "hw_sequencer.h"
+#include "resource.h"
#include "fixed31_32.h"
#include "adapter/adapter_service.h"
#include "include/asic_capability_interface.h"
@@ -1566,8 +1567,7 @@ bool dc_link_setup_psr(const struct dc_link *dc_link,
asic_cap->caps.SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT;
psr_context.numberOfControllers =
- link->link_enc->adapter_service->asic_cap->
- data[ASIC_DATA_CONTROLLERS_NUM];
+ link->dc->res_pool->res_cap->num_timing_generator;
psr_context.rfb_update_auto_en = true;
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index 204b49bae9ee..276833847c4d 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -133,10 +133,10 @@ bool resource_construct(
unsigned int num_virtual_links,
struct core_dc *dc,
struct resource_pool *pool,
- const struct resource_caps *caps,
const struct resource_create_funcs *create_funcs)
{
struct dc_context *ctx = dc->ctx;
+ const struct resource_caps *caps = pool->res_cap;
int i;
unsigned int num_audio = caps->num_audio;
struct resource_straps straps = {0};
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index f1ca073fcaa7..42c1eff389a3 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -360,8 +360,10 @@ static const struct dce110_opp_reg_offsets dce100_opp_reg_offsets[] = {
};
static const struct resource_caps res_cap = {
+ .num_timing_generator = 6,
.num_audio = 6,
- .num_stream_encoder = 6
+ .num_stream_encoder = 6,
+ .num_pll = 3
};
#define CTX ctx
@@ -855,6 +857,7 @@ static bool construct(
struct dm_pp_static_clock_info static_clk_info = {0};
pool->base.adapter_srv = as;
+ pool->base.res_cap = &res_cap;
pool->base.funcs = &dce100_res_pool_funcs;
pool->base.underlay_pipe_index = -1;
@@ -936,7 +939,7 @@ static bool construct(
* Resource + asic cap harcoding *
*************************************************/
pool->base.underlay_pipe_index = -1;
- pool->base.pipe_count = dal_adapter_service_get_func_controllers_num(as);
+ pool->base.pipe_count = res_cap.num_timing_generator;
pool->base.scaler_filter = dal_scaler_filter_create(ctx);
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;
@@ -1000,7 +1003,7 @@ static bool construct(
}
if (!resource_construct(num_virtual_links, dc, &pool->base,
- &res_cap, &res_create_funcs))
+ &res_create_funcs))
goto res_create_fail;
/* Create hardware sequencer */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index db7686842e36..6e6e2a629175 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -325,9 +325,20 @@ static const struct dce110_clk_src_reg_offsets dce110_clk_src_reg_offsets[] = {
};
-static const struct resource_caps res_cap = {
- .num_audio = 3,
- .num_stream_encoder = 3
+static const struct resource_caps carrizo_resource_cap = {
+ .num_timing_generator = 3,
+ .num_video_plane = 1,
+ .num_audio = 3,
+ .num_stream_encoder = 3,
+ .num_pll = 2,
+};
+
+static const struct resource_caps stoney_resource_cap = {
+ .num_timing_generator = 2,
+ .num_video_plane = 1,
+ .num_audio = 3,
+ .num_stream_encoder = 3,
+ .num_pll = 2,
};
#define CTX ctx
@@ -1140,6 +1151,15 @@ enum clocks_state dce110_resource_convert_clock_state_pp_to_dc(
return dc_clocks_state;
}
+const struct resource_caps *dce110_resource_cap(
+ struct hw_asic_id *asic_id)
+{
+ if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
+ return &stoney_resource_cap;
+ else
+ return &carrizo_resource_cap;
+}
+
static bool construct(
struct adapter_service *as,
uint8_t num_virtual_links,
@@ -1155,19 +1175,15 @@ static bool construct(
struct resource_straps straps = {0};
pool->base.adapter_srv = as;
+ pool->base.res_cap = dce110_resource_cap(&dc->asic_id);
pool->base.funcs = &dce110_res_pool_funcs;
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
- pool->base.pipe_count = 3;
- pool->base.underlay_pipe_index = 3;
-
- if (ASIC_REV_IS_STONEY(asic_id.hw_internal_rev)) {
- pool->base.pipe_count = 2;
- pool->base.underlay_pipe_index = 2;
- }
+ pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+ pool->base.underlay_pipe_index = pool->base.pipe_count;
dc->public.caps.max_downscale_ratio = 150;
dc->public.caps.i2c_speed_in_khz = 100;
@@ -1175,8 +1191,6 @@ static bool construct(
/*************************************************
* Create resources *
*************************************************/
-
-
pool->base.stream_engines.engine.ENGINE_ID_DIGA = 1;
pool->base.stream_engines.engine.ENGINE_ID_DIGB = 1;
pool->base.stream_engines.engine.ENGINE_ID_DIGC = 1;
@@ -1299,7 +1313,7 @@ static bool construct(
underlay_create(ctx, &pool->base);
if (!resource_construct(num_virtual_links, dc, &pool->base,
- &res_cap, &res_create_funcs))
+ &res_create_funcs))
goto res_create_fail;
/* Create hardware sequencer */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index ab203dfd2914..485221696c26 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -375,9 +375,18 @@ static const struct dce112_clk_src_reg_offsets dce112_clk_src_reg_offsets[] = {
}
};
-static const struct resource_caps res_cap = {
- .num_audio = 6,
- .num_stream_encoder = 6
+static const struct resource_caps polaris_10_resource_cap = {
+ .num_timing_generator = 6,
+ .num_audio = 6,
+ .num_stream_encoder = 6,
+ .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
+};
+
+static const struct resource_caps polaris_11_resource_cap = {
+ .num_timing_generator = 5,
+ .num_audio = 5,
+ .num_stream_encoder = 5,
+ .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
};
#define CTX ctx
@@ -1155,6 +1164,15 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
}
+const struct resource_caps *dce112_resource_cap(
+ struct hw_asic_id *asic_id)
+{
+ if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev))
+ return &polaris_11_resource_cap;
+ else
+ return &polaris_10_resource_cap;
+}
+
static bool construct(
struct adapter_service *adapter_serv,
uint8_t num_virtual_links,
@@ -1166,14 +1184,14 @@ static bool construct(
struct dm_pp_static_clock_info static_clk_info = {0};
pool->base.adapter_srv = adapter_serv;
+ pool->base.res_cap = dce112_resource_cap(&dc->asic_id);
pool->base.funcs = &dce112_res_pool_funcs;
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
pool->base.underlay_pipe_index = -1;
- pool->base.pipe_count =
- dal_adapter_service_get_func_controllers_num(adapter_serv);
+ pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 100;
@@ -1332,8 +1350,8 @@ static bool construct(
}
}
- if (!resource_construct(num_virtual_links, dc,
- &pool->base, &res_cap, &res_create_funcs))
+ if (!resource_construct(num_virtual_links, dc, &pool->base,
+ &res_create_funcs))
goto res_create_fail;
/* Create hardware sequencer */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index 506b93f816df..d557fcc40ccb 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -350,8 +350,10 @@ static const struct dce110_clk_src_reg_offsets dce80_clk_src_reg_offsets[] = {
};
static const struct resource_caps res_cap = {
- .num_audio = 6,
- .num_stream_encoder = 6
+ .num_timing_generator = 6,
+ .num_audio = 6,
+ .num_stream_encoder = 6,
+ .num_pll = 3,
};
#define CTX ctx
@@ -848,6 +850,7 @@ static bool construct(
struct dm_pp_static_clock_info static_clk_info = {0};
pool->base.adapter_srv = as;
+ pool->base.res_cap = &res_cap;
pool->base.funcs = &dce80_res_pool_funcs;
@@ -855,7 +858,7 @@ static bool construct(
* Resource + asic cap harcoding *
*************************************************/
pool->base.underlay_pipe_index = -1;
- pool->base.pipe_count = dal_adapter_service_get_func_controllers_num(as);
+ pool->base.pipe_count = res_cap.num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;
@@ -986,7 +989,7 @@ static bool construct(
}
if (!resource_construct(num_virtual_links, dc, &pool->base,
- &res_cap, &res_create_funcs))
+ &res_create_funcs))
goto res_create_fail;
/* Create hardware sequencer */
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
index 826ae7a8998f..668e6c826090 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
@@ -17,6 +17,7 @@
struct core_dc {
struct dc public;
struct dc_context *ctx;
+ struct hw_asic_id asic_id;
uint8_t link_count;
struct core_link *links[MAX_PIPES * 2];
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
index 5ae6ed603d62..2c0072265d8b 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
@@ -270,6 +270,7 @@ struct resource_pool {
struct irq_service *irqs;
const struct resource_funcs *funcs;
+ const struct resource_caps *res_cap;
};
struct pipe_ctx {
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
index 20a3b08442de..4e64e45e897b 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
@@ -37,8 +37,11 @@ enum dce_version resource_parse_asic_id(
struct hw_asic_id asic_id);
struct resource_caps {
+ int num_timing_generator;
+ int num_video_plane;
int num_audio;
int num_stream_encoder;
+ int num_pll;
};
struct resource_straps {
@@ -64,7 +67,6 @@ bool resource_construct(
unsigned int num_virtual_links,
struct core_dc *dc,
struct resource_pool *pool,
- const struct resource_caps *caps,
const struct resource_create_funcs *create_funcs);
struct resource_pool *dc_create_resource_pool(struct adapter_service *adapter_serv,
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index e9c31c32cc25..52bf06b8b507 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -145,18 +145,8 @@ enum adapter_feature_id {
FEATURE_SET_06_START = FEATURE_DCP_PROGRAMMING_WA,
FEATURE_SET_06_END = FEATURE_SET_06_START + 31,
- /* UInt set, 1 entry: Maximum co-functional non-DP displays */
- FEATURE_MAX_COFUNC_NON_DP_DISPLAYS = FEATURE_SET_06_END + 1,
- FEATURE_SET_07_START = FEATURE_MAX_COFUNC_NON_DP_DISPLAYS,
- FEATURE_SET_07_END = FEATURE_SET_07_START + 31,
-
- /* UInt set, 1 entry: Number of supported HDMI connection */
- FEATURE_SUPPORTED_HDMI_CONNECTION_NUM = FEATURE_SET_07_END + 1,
- FEATURE_SET_08_START = FEATURE_SUPPORTED_HDMI_CONNECTION_NUM,
- FEATURE_SET_08_END = FEATURE_SET_08_START + 31,
-
/* UInt set, 1 entry: Maximum number of controllers */
- FEATURE_MAX_CONTROLLER_NUM = FEATURE_SET_08_END + 1,
+ FEATURE_MAX_CONTROLLER_NUM = FEATURE_SET_06_END + 1,
FEATURE_SET_09_START = FEATURE_MAX_CONTROLLER_NUM,
FEATURE_SET_09_END = FEATURE_SET_09_START + 31,
@@ -336,14 +326,6 @@ bool dal_adapter_service_get_firmware_info(
struct adapter_service *as,
struct firmware_info *info);
-/* Get number of controllers */
-uint8_t dal_adapter_service_get_func_controllers_num(
- struct adapter_service *as);
-
-/* Get number of stream engines */
-uint8_t dal_adapter_service_get_stream_engines_num(
- struct adapter_service *as);
-
/* Get number of spread spectrum entries from BIOS */
uint32_t dal_adapter_service_get_ss_info_num(
struct adapter_service *as,
diff --git a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
index 7841662108e8..1f78dc9f52f3 100644
--- a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
+++ b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
@@ -84,30 +84,19 @@ struct asic_bugs {
*/
enum asic_data {
ASIC_DATA_FIRST = 0,
- ASIC_DATA_CONTROLLERS_NUM = ASIC_DATA_FIRST,
- ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM,
- ASIC_DATA_DCE_VERSION,
+ ASIC_DATA_DCE_VERSION = ASIC_DATA_FIRST,
ASIC_DATA_DCE_VERSION_MINOR,
- ASIC_DATA_VRAM_TYPE,
ASIC_DATA_VRAM_BITWIDTH,
- ASIC_DATA_FEATURE_FLAGS,
- ASIC_DATA_LINEBUFFER_NUM,
ASIC_DATA_LINEBUFFER_SIZE,
ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY,
ASIC_DATA_MC_LATENCY,
ASIC_DATA_MC_LATENCY_SLOW,
- ASIC_DATA_CLOCKSOURCES_NUM,
ASIC_DATA_MEMORYTYPE_MULTIPLIER,
ASIC_DATA_STUTTERMODE,
ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR,
- ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS,
- ASIC_DATA_REVISION_ID,
ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE,
ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY,
- ASIC_DATA_DIGFE_NUM,
- ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM,
ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN,
- ASIC_DATA_NUM_OF_VIDEO_PLANES,
ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ,
ASIC_DATA_DOWNSCALE_LIMIT,
ASIC_DATA_MAX_NUMBER /* end of enum */
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 03/76] drm/amd/dal: Remove unused code in dce112 hwss.
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2016-11-21 23:00 ` [PATCH 01/76] drm/amd/dal: bring all of dc under a single log category table Harry Wentland
2016-11-21 23:00 ` [PATCH 02/76] drm/amd/dal: clean up asic cap Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 04/76] drm/amd/dal: Consolidate link encoder from each dce version Harry Wentland
` (73 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zeyu Fan
From: Zeyu Fan <Zeyu.Fan@amd.com>
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c | 23 ----------------------
1 file changed, 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
index 8ec1aaed98e0..f5611d14dbc9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
@@ -260,29 +260,6 @@ static void dce112_init_pte(struct dc_context *ctx)
uint32_t chunk_int = 0;
uint32_t chunk_mul = 0;
- addr = mmUNP_DVMM_PTE_CONTROL;
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- 0,
- DVMM_PTE_CONTROL,
- DVMM_USE_SINGLE_PTE);
-
- set_reg_field_value(
- value,
- 1,
- DVMM_PTE_CONTROL,
- DVMM_PTE_BUFFER_MODE0);
-
- set_reg_field_value(
- value,
- 1,
- DVMM_PTE_CONTROL,
- DVMM_PTE_BUFFER_MODE1);
-
- dm_write_reg(ctx, addr, value);
-
addr = mmDVMM_PTE_REQ;
value = dm_read_reg(ctx, addr);
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 04/76] drm/amd/dal: Consolidate link encoder from each dce version.
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 03/76] drm/amd/dal: Remove unused code in dce112 hwss Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 05/76] drm/amd/dal: Remove wireless_data_source Harry Wentland
` (72 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zeyu Fan
From: Zeyu Fan <Zeyu.Fan@amd.com>
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 5 +-
drivers/gpu/drm/amd/dal/dc/dce/Makefile | 2 +-
.../dce_link_encoder.c} | 10 +-
.../dce_link_encoder.h} | 0
...ce110_stream_encoder.c => dce_stream_encoder.c} | 4 +-
...ce110_stream_encoder.h => dce_stream_encoder.h} | 0
drivers/gpu/drm/amd/dal/dc/dce100/Makefile | 2 +-
.../drm/amd/dal/dc/dce100/dce100_link_encoder.c | 92 ------
.../drm/amd/dal/dc/dce100/dce100_link_encoder.h | 42 ---
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 13 +-
drivers/gpu/drm/amd/dal/dc/dce110/Makefile | 2 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 11 +-
drivers/gpu/drm/amd/dal/dc/dce112/Makefile | 2 +-
.../drm/amd/dal/dc/dce112/dce112_link_encoder.c | 191 ------------
.../drm/amd/dal/dc/dce112/dce112_link_encoder.h | 41 ---
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 14 +-
drivers/gpu/drm/amd/dal/dc/dce80/Makefile | 2 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c | 333 ---------------------
.../gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h | 39 ---
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 14 +-
drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h | 1 +
21 files changed, 50 insertions(+), 770 deletions(-)
rename drivers/gpu/drm/amd/dal/dc/{dce110/dce110_link_encoder.c => dce/dce_link_encoder.c} (99%)
rename drivers/gpu/drm/amd/dal/dc/{dce110/dce110_link_encoder.h => dce/dce_link_encoder.h} (100%)
rename drivers/gpu/drm/amd/dal/dc/dce/{dce110_stream_encoder.c => dce_stream_encoder.c} (99%)
rename drivers/gpu/drm/amd/dal/dc/dce/{dce110_stream_encoder.h => dce_stream_encoder.h} (100%)
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
index f01338671143..bc240981d276 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
@@ -1,5 +1,6 @@
/* Copyright 2015 Advanced Micro Devices, Inc. */
+
#include "dm_services.h"
#include "dc.h"
#include "inc/core_dc.h"
@@ -9,8 +10,8 @@
#include "hw_sequencer.h"
#include "dc_link_ddc.h"
#include "dm_helpers.h"
-#include "dce110/dce110_link_encoder.h"
-#include "dce/dce110_stream_encoder.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
enum dc_status core_link_read_dpcd(
struct core_link* link,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/Makefile b/drivers/gpu/drm/amd/dal/dc/dce/Makefile
index 04d9a351388a..306070dd5455 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce/Makefile
@@ -5,7 +5,7 @@
# - register programming through common macros that look up register
# offset/shift/mask stored in dce_hw struct
-DCE = dce_audio.o dce110_stream_encoder.o
+DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
similarity index 99%
rename from drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
rename to drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
index c36cdadf35f2..8a9060601005 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
@@ -23,12 +23,13 @@
*
*/
+
+
#include "dm_services.h"
#include "core_types.h"
#include "link_encoder.h"
+#include "dce_link_encoder.h"
#include "stream_encoder.h"
-#include "dce110_link_encoder.h"
-
#include "i2caux_interface.h"
#include "dc_bios_types.h"
@@ -907,7 +908,8 @@ static bool dce110_link_encoder_validate_hdmi_output(
return false;
/* DCE11 HW does not support 420 */
- if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ if (!enc110->base.features.ycbcr420_supported &&
+ crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
return false;
return true;
@@ -993,8 +995,6 @@ bool dce110_link_encoder_construct(
enc110->base.features.max_pixel_clock =
MAX_ENCODER_CLK;
- enc110->base.features.max_hdmi_pixel_clock =
- DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.h
similarity index 100%
rename from drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
rename to drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
similarity index 99%
rename from drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.c
rename to drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
index f2f66ea49fea..079734700c15 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
@@ -23,10 +23,10 @@
*
*/
+
#include "dm_services.h"
#include "dc_bios_types.h"
-#include "dce110_stream_encoder.h"
-
+#include "dce_stream_encoder.h"
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
#include "dce/dce_11_0_enum.h"
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
similarity index 100%
rename from drivers/gpu/drm/amd/dal/dc/dce/dce110_stream_encoder.h
rename to drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
index 5fb7e7b702b7..656c38e1b0f5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
@@ -2,7 +2,7 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
-DCE100 = dce100_resource.o dce100_hw_sequencer.o dce100_link_encoder.o
+DCE100 = dce100_resource.o dce100_hw_sequencer.o
AMD_DAL_DCE100 = $(addprefix $(AMDDALPATH)/dc/dce100/,$(DCE100))
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c
deleted file mode 100644
index 0e85ce2862cd..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "core_types.h"
-#include "dce100_link_encoder.h"
-#include "stream_encoder.h"
-#include "../dce110/dce110_link_encoder.h"
-#include "i2caux_interface.h"
-
-/* TODO: change to dce80 header file */
-#include "dce/dce_10_0_d.h"
-#include "dce/dce_10_0_sh_mask.h"
-#include "dce/dce_10_0_enum.h"
-
-#define LINK_REG(reg)\
- (enc110->link_regs->reg)
-
-#define DCE10_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 300000
-
-
-static const struct link_encoder_funcs dce100_lnk_enc_funcs = {
- .validate_output_with_stream =
- dce110_link_encoder_validate_output_with_stream,
- .hw_init = dce110_link_encoder_hw_init,
- .setup = dce110_link_encoder_setup,
- .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
- .enable_dp_output = dce110_link_encoder_enable_dp_output,
- .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
- .disable_output = dce110_link_encoder_disable_output,
- .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
- .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
- .update_mst_stream_allocation_table =
- dce110_link_encoder_update_mst_stream_allocation_table,
- .set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
- .set_dmcu_backlight_level =
- dce110_link_encoder_set_dmcu_backlight_level,
- .set_dmcu_abm_level = dce110_link_encoder_set_dmcu_abm_level,
- .backlight_control = dce110_link_encoder_edp_backlight_control,
- .power_control = dce110_link_encoder_edp_power_control,
- .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
- .destroy = dce110_link_encoder_destroy
-};
-
-bool dce100_link_encoder_construct(
- struct dce110_link_encoder *enc110,
- const struct encoder_init_data *init_data,
- const struct dce110_link_enc_registers *link_regs,
- const struct dce110_link_enc_aux_registers *aux_regs,
- const struct dce110_link_enc_hpd_registers *hpd_regs)
-{
- dce110_link_encoder_construct(
- enc110,
- init_data,
- link_regs,
- aux_regs,
- hpd_regs);
-
- enc110->base.funcs = &dce100_lnk_enc_funcs;
-
- enc110->base.features.flags.bits.IS_HBR3_CAPABLE = false;
- enc110->base.features.flags.bits.IS_TPS4_CAPABLE = false;
-
- enc110->base.features.max_hdmi_pixel_clock =
- DCE10_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
- enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
- enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
-
- return true;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h
deleted file mode 100644
index af5b8648ef7d..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_link_encoder.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_LINK_ENCODER__DCE100_H__
-#define __DC_LINK_ENCODER__DCE100_H__
-
-#include "link_encoder.h"
-#include "../dce110/dce110_link_encoder.h"
-
-#define TO_DCE100_LINK_ENC(link_encoder)\
- container_of(link_encoder, struct dce100_link_encoder, base)
-
-bool dce100_link_encoder_construct(
- struct dce110_link_encoder *enc110,
- const struct encoder_init_data *init_data,
- const struct dce110_link_enc_registers *link_regs,
- const struct dce110_link_enc_aux_registers *aux_regs,
- const struct dce110_link_enc_hpd_registers *hpd_regs);
-
-#endif /* __DC_LINK_ENCODER__DCE100_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 42c1eff389a3..ea7e12d8a1e4 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -34,13 +34,12 @@
#include "dce110/dce110_resource.h"
#include "dce110/dce110_timing_generator.h"
#include "irq/dce110/irq_service_dce110.h"
-#include "dce110/dce110_link_encoder.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
#include "dce110/dce110_mem_input.h"
#include "dce110/dce110_mem_input_v.h"
#include "dce110/dce110_ipp.h"
#include "dce110/dce110_transform.h"
-#include "dce100/dce100_link_encoder.h"
-#include "dce/dce110_stream_encoder.h"
#include "dce110/dce110_opp.h"
#include "dce110/dce110_clock_source.h"
#include "dce/dce_audio.h"
@@ -515,13 +514,17 @@ struct link_encoder *dce100_link_encoder_create(
if (!enc110)
return NULL;
- if (dce100_link_encoder_construct(
+ if (dce110_link_encoder_construct(
enc110,
enc_init_data,
&link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1],
- &link_enc_hpd_regs[enc_init_data->hpd_source]))
+ &link_enc_hpd_regs[enc_init_data->hpd_source])) {
+
+ enc110->base.features.ycbcr420_supported = false;
+ enc110->base.features.max_hdmi_pixel_clock = 300000;
return &enc110->base;
+ }
BREAK_TO_DEBUGGER();
dm_free(enc110);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
index 5393a685e9c3..ed271240cbdf 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
@@ -3,7 +3,7 @@
# It provides the control and status of HW CRTC block.
DCE110 = dce110_ipp.o dce110_ipp_cursor.o \
-dce110_ipp_gamma.o dce110_link_encoder.o dce110_opp.o \
+dce110_ipp_gamma.o dce110_opp.o \
dce110_opp_formatter.o dce110_opp_regamma.o \
dce110_timing_generator.o dce110_transform.o dce110_transform_v.o \
dce110_transform_gamut.o dce110_transform_scl.o dce110_opp_csc.o\
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 6e6e2a629175..0404122cf31e 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -30,18 +30,19 @@
#include "resource.h"
#include "dce110/dce110_resource.h"
+
#include "include/irq_service_interface.h"
#include "dce/dce_audio.h"
#include "dce110/dce110_timing_generator.h"
#include "irq/dce110/irq_service_dce110.h"
#include "dce110/dce110_timing_generator_v.h"
-#include "dce110/dce110_link_encoder.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
#include "dce110/dce110_mem_input.h"
#include "dce110/dce110_mem_input_v.h"
#include "dce110/dce110_ipp.h"
#include "dce110/dce110_transform.h"
#include "dce110/dce110_transform_v.h"
-#include "dce/dce110_stream_encoder.h"
#include "dce110/dce110_opp.h"
#include "dce110/dce110_opp_v.h"
#include "dce110/dce110_clock_source.h"
@@ -495,8 +496,12 @@ struct link_encoder *dce110_link_encoder_create(
enc_init_data,
&link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1],
- &link_enc_hpd_regs[enc_init_data->hpd_source]))
+ &link_enc_hpd_regs[enc_init_data->hpd_source])) {
+
+ enc110->base.features.ycbcr420_supported = false;
+ enc110->base.features.max_hdmi_pixel_clock = 594000;
return &enc110->base;
+ }
BREAK_TO_DEBUGGER();
dm_free(enc110);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/Makefile b/drivers/gpu/drm/amd/dal/dc/dce112/Makefile
index c6e3c8c2133a..010e10b48042 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/Makefile
@@ -2,7 +2,7 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
-DCE112 = dce112_link_encoder.o dce112_compressor.o dce112_hw_sequencer.o \
+DCE112 = dce112_compressor.o dce112_hw_sequencer.o \
dce112_resource.o dce112_clock_source.o dce112_mem_input.o dce112_opp_formatter.o \
dce112_opp.o
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c
deleted file mode 100644
index 88ed54f48755..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "core_types.h"
-#include "link_encoder.h"
-#include "stream_encoder.h"
-#include "dce112_link_encoder.h"
-#include "../dce110/dce110_link_encoder.h"
-#include "i2caux_interface.h"
-#include "dce/dce_11_2_sh_mask.h"
-
-/* For current ASICs pixel clock - 600MHz */
-#define MAX_ENCODER_CLK 600000
-
-#define DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 600000
-
-#define DEFAULT_AUX_MAX_DATA_SIZE 16
-#define AUX_MAX_DEFER_WRITE_RETRY 20
-
-/* all values are in milliseconds */
-/* For eDP, after power-up/power/down,
- * 300/500 msec max. delay from LCDVCC to black video generation */
-#define PANEL_POWER_UP_TIMEOUT 300
-#define PANEL_POWER_DOWN_TIMEOUT 500
-#define HPD_CHECK_INTERVAL 10
-
-/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
-#define TMDS_MIN_PIXEL_CLOCK 25000
-/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
-#define TMDS_MAX_PIXEL_CLOCK 165000
-/* For current ASICs pixel clock - 600MHz */
-#define MAX_ENCODER_CLOCK 600000
-
-enum {
- DP_MST_UPDATE_MAX_RETRY = 50
-};
-
-static void dce112_link_encoder_dp_set_phy_pattern(
- struct link_encoder *enc,
- const struct encoder_set_dp_phy_pattern_param *param)
-{
- switch (param->dp_phy_pattern) {
- case DP_TEST_PATTERN_TRAINING_PATTERN4:
- dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
- break;
- default:
- dce110_link_encoder_dp_set_phy_pattern(enc, param);
- break;
- }
-}
-
-static bool dce112_link_encoder_validate_hdmi_output(
- const struct dce110_link_encoder *enc110,
- const struct dc_crtc_timing *crtc_timing,
- int adjusted_pix_clk_khz)
-{
- enum dc_color_depth max_deep_color =
- enc110->base.features.max_hdmi_deep_color;
-
- if (max_deep_color > enc110->base.features.max_deep_color)
- max_deep_color = enc110->base.features.max_deep_color;
-
- if (max_deep_color < crtc_timing->display_color_depth)
- return false;
-
- if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
- return false;
-
- if ((adjusted_pix_clk_khz == 0) ||
- (adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock) ||
- (adjusted_pix_clk_khz > enc110->base.features.max_pixel_clock))
- return false;
-
- return true;
-}
-
-bool dce112_link_encoder_validate_output_with_stream(
- struct link_encoder *enc,
- struct pipe_ctx *pipe_ctx)
-{
- struct core_stream *stream = pipe_ctx->stream;
- struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- bool is_valid;
-
- switch (pipe_ctx->stream->signal) {
- case SIGNAL_TYPE_DVI_SINGLE_LINK:
- case SIGNAL_TYPE_DVI_DUAL_LINK:
- is_valid = dce110_link_encoder_validate_dvi_output(
- enc110,
- stream->sink->link->public.connector_signal,
- pipe_ctx->stream->signal,
- &stream->public.timing);
- break;
- case SIGNAL_TYPE_HDMI_TYPE_A:
- is_valid = dce112_link_encoder_validate_hdmi_output(
- enc110,
- &stream->public.timing,
- stream->phy_pix_clk);
- break;
- case SIGNAL_TYPE_RGB:
- is_valid = dce110_link_encoder_validate_rgb_output(
- enc110, &stream->public.timing);
- break;
- case SIGNAL_TYPE_DISPLAY_PORT:
- case SIGNAL_TYPE_DISPLAY_PORT_MST:
- case SIGNAL_TYPE_EDP:
- is_valid = dce110_link_encoder_validate_dp_output(
- enc110, &stream->public.timing);
- break;
- case SIGNAL_TYPE_WIRELESS:
- is_valid = dce110_link_encoder_validate_wireless_output(
- enc110, &stream->public.timing);
- break;
- default:
- is_valid = true;
- break;
- }
-
- return is_valid;
-}
-
-static const struct link_encoder_funcs dce112_lnk_enc_funcs = {
- .validate_output_with_stream =
- dce112_link_encoder_validate_output_with_stream,
- .hw_init = dce110_link_encoder_hw_init,
- .setup = dce110_link_encoder_setup,
- .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
- .enable_dp_output = dce110_link_encoder_enable_dp_output,
- .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
- .disable_output = dce110_link_encoder_disable_output,
- .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
- .dp_set_phy_pattern = dce112_link_encoder_dp_set_phy_pattern,
- .update_mst_stream_allocation_table =
- dce110_link_encoder_update_mst_stream_allocation_table,
- .set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
- .set_dmcu_backlight_level =
- dce110_link_encoder_set_dmcu_backlight_level,
- .set_dmcu_abm_level = dce110_link_encoder_set_dmcu_abm_level,
- .backlight_control = dce110_link_encoder_edp_backlight_control,
- .power_control = dce110_link_encoder_edp_power_control,
- .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
- .enable_hpd = dce110_link_encoder_enable_hpd,
- .disable_hpd = dce110_link_encoder_disable_hpd,
- .destroy = dce110_link_encoder_destroy
-};
-
-bool dce112_link_encoder_construct(
- struct dce110_link_encoder *enc110,
- const struct encoder_init_data *init_data,
- const struct dce110_link_enc_registers *link_regs,
- const struct dce110_link_enc_aux_registers *aux_regs,
- const struct dce110_link_enc_hpd_registers *hpd_regs)
-{
- dce110_link_encoder_construct(
- enc110,
- init_data,
- link_regs,
- aux_regs,
- hpd_regs);
-
- enc110->base.funcs = &dce112_lnk_enc_funcs;
-
- enc110->base.features.flags.bits.IS_HBR3_CAPABLE = false;
-
- enc110->base.features.flags.bits.IS_TPS4_CAPABLE = false;
-
- return true;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h
deleted file mode 100644
index ab373359dd9e..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_link_encoder.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_LINK_ENCODER__DCE112_H__
-#define __DC_LINK_ENCODER__DCE112_H__
-
-#include "link_encoder.h"
-#include "../dce110/dce110_link_encoder.h"
-
-bool dce112_link_encoder_construct(
- struct dce110_link_encoder *enc110,
- const struct encoder_init_data *init_data,
- const struct dce110_link_enc_registers *link_regs,
- const struct dce110_link_enc_aux_registers *aux_regs,
- const struct dce110_link_enc_hpd_registers *hpd_regs);
-
-/****************** HW programming ************************/
-
-#endif /* __DC_LINK_ENCODER__DCE112_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 485221696c26..8588a94e0fc5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -34,11 +34,11 @@
#include "dce110/dce110_resource.h"
#include "dce110/dce110_timing_generator.h"
#include "dce112/dce112_mem_input.h"
-#include "dce112/dce112_link_encoder.h"
-#include "dce110/dce110_link_encoder.h"
+
#include "irq/dce110/irq_service_dce110.h"
#include "dce110/dce110_transform.h"
-#include "dce/dce110_stream_encoder.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
#include "dce/dce_audio.h"
#include "dce112/dce112_opp.h"
#include "dce110/dce110_ipp.h"
@@ -518,13 +518,17 @@ struct link_encoder *dce112_link_encoder_create(
if (!enc110)
return NULL;
- if (dce112_link_encoder_construct(
+ if (dce110_link_encoder_construct(
enc110,
enc_init_data,
&link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1],
- &link_enc_hpd_regs[enc_init_data->hpd_source]))
+ &link_enc_hpd_regs[enc_init_data->hpd_source])) {
+
+ enc110->base.features.ycbcr420_supported = false;
+ enc110->base.features.max_hdmi_pixel_clock = 600000;
return &enc110->base;
+ }
BREAK_TO_DEBUGGER();
dm_free(enc110);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/Makefile b/drivers/gpu/drm/amd/dal/dc/dce80/Makefile
index 00a7b65d9809..863641ca07a6 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/Makefile
@@ -2,7 +2,7 @@
# Makefile for the 'controller' sub-component of DAL.
# It provides the control and status of HW CRTC block.
-DCE80 = dce80_ipp.o dce80_ipp_gamma.o dce80_link_encoder.o dce80_opp.o \
+DCE80 = dce80_ipp.o dce80_ipp_gamma.o dce80_opp.o \
dce80_opp_formatter.o dce80_opp_regamma.o \
dce80_timing_generator.o dce80_transform.o dce80_transform_gamut.o \
dce80_transform_scl.o dce80_opp_csc.o\
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
deleted file mode 100644
index bd364eeb6916..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "core_types.h"
-#include "dce80_link_encoder.h"
-#include "stream_encoder.h"
-#include "../dce110/dce110_link_encoder.h"
-#include "i2caux_interface.h"
-
-/* TODO: change to dce80 header file */
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
-#include "dce/dce_11_0_enum.h"
-
-#define LINK_REG(reg)\
- (enc110->link_regs->reg)
-
-/* For current ASICs pixel clock - 600MHz */
-#define MAX_ENCODER_CLK 600000
-
-#define DCE8_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 297000
-
-#define DEFAULT_AUX_MAX_DATA_SIZE 16
-#define AUX_MAX_DEFER_WRITE_RETRY 20
-/*
- * @brief
- * Trigger Source Select
- * ASIC-dependent, actual values for register programming
- */
-#define DCE80_DIG_FE_SOURCE_SELECT_INVALID 0x0
-#define DCE80_DIG_FE_SOURCE_SELECT_DIGA 0x01
-#define DCE80_DIG_FE_SOURCE_SELECT_DIGB 0x02
-#define DCE80_DIG_FE_SOURCE_SELECT_DIGC 0x04
-#define DCE80_DIG_FE_SOURCE_SELECT_DIGD 0x08
-#define DCE80_DIG_FE_SOURCE_SELECT_DIGE 0x10
-#define DCE80_DIG_FE_SOURCE_SELECT_DIGF 0x20
-
-/* all values are in milliseconds */
-/* For eDP, after power-up/power/down,
- * 300/500 msec max. delay from LCDVCC to black video generation */
-#define PANEL_POWER_UP_TIMEOUT 300
-#define PANEL_POWER_DOWN_TIMEOUT 500
-#define HPD_CHECK_INTERVAL 10
-
-/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
-#define TMDS_MIN_PIXEL_CLOCK 25000
-/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
-#define TMDS_MAX_PIXEL_CLOCK 165000
-
-enum {
- DP_MST_UPDATE_MAX_RETRY = 50
-};
-
-static enum bp_result link_transmitter_control(
- struct dce110_link_encoder *enc110,
- struct bp_transmitter_control *cntl)
-{
- enum bp_result result;
- struct dc_bios *bp = enc110->base.ctx->dc_bios;
-
- result = bp->funcs->transmitter_control(bp, cntl);
-
- return result;
-}
-
-static void dce80_link_encoder_enable_tmds_output(
- struct link_encoder *enc,
- enum clock_source_id clock_source,
- enum dc_color_depth color_depth,
- bool hdmi,
- bool dual_link,
- uint32_t pixel_clock)
-{
- struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- struct dc_context *ctx = enc110->base.ctx;
- struct bp_transmitter_control cntl = { 0 };
- enum bp_result result;
-
- /* Enable the PHY */
-
- cntl.action = TRANSMITTER_CONTROL_ENABLE;
- cntl.engine_id = enc->preferred_engine;
- cntl.transmitter = enc110->base.transmitter;
- cntl.pll_id = clock_source;
- if (hdmi) {
- cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
- cntl.lanes_number = 4;
- } else if (dual_link) {
- cntl.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
- cntl.lanes_number = 8;
- } else {
- cntl.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
- cntl.lanes_number = 4;
- }
- cntl.hpd_sel = enc110->base.hpd_source;
-
- cntl.pixel_clock = pixel_clock;
- cntl.color_depth = color_depth;
-
- result = link_transmitter_control(enc110, &cntl);
-
- if (result != BP_RESULT_OK) {
- dm_logger_write(ctx->logger, LOG_ERROR,
- "%s: Failed to execute VBIOS command table!\n",
- __func__);
- BREAK_TO_DEBUGGER();
- }
-}
-
-static void configure_encoder(
- struct dce110_link_encoder *enc110,
- const struct dc_link_settings *link_settings)
-{
- struct dc_context *ctx = enc110->base.ctx;
- uint32_t addr;
- uint32_t value;
-
- /* set number of lanes */
- addr = LINK_REG(DP_CONFIG);
- value = dm_read_reg(ctx, addr);
- set_reg_field_value(value, link_settings->lane_count - LANE_COUNT_ONE,
- DP_CONFIG, DP_UDI_LANES);
- dm_write_reg(ctx, addr, value);
-
-}
-
-/* enables DP PHY output */
-static void dce80_link_encoder_enable_dp_output(
- struct link_encoder *enc,
- const struct dc_link_settings *link_settings,
- enum clock_source_id clock_source)
-{
- struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
- struct dc_context *ctx = enc110->base.ctx;
- struct bp_transmitter_control cntl = { 0 };
- enum bp_result result;
-
- /* Enable the PHY */
-
- /* number_of_lanes is used for pixel clock adjust,
- * but it's not passed to asic_control.
- * We need to set number of lanes manually.
- */
- configure_encoder(enc110, link_settings);
-
- cntl.action = TRANSMITTER_CONTROL_ENABLE;
- cntl.engine_id = enc->preferred_engine;
- cntl.transmitter = enc110->base.transmitter;
- cntl.pll_id = clock_source;
- cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
- cntl.lanes_number = link_settings->lane_count;
- cntl.hpd_sel = enc110->base.hpd_source;
- cntl.pixel_clock = link_settings->link_rate
- * LINK_RATE_REF_FREQ_IN_KHZ;
- /* TODO: check if undefined works */
- cntl.color_depth = COLOR_DEPTH_UNDEFINED;
-
- result = link_transmitter_control(enc110, &cntl);
-
- if (result != BP_RESULT_OK) {
- dm_logger_write(ctx->logger, LOG_ERROR,
- "%s: Failed to execute VBIOS command table!\n",
- __func__);
- BREAK_TO_DEBUGGER();
- }
-}
-
-static const struct link_encoder_funcs dce80_lnk_enc_funcs = {
- .validate_output_with_stream =
- dce110_link_encoder_validate_output_with_stream,
- .hw_init = dce110_link_encoder_hw_init,
- .setup = dce110_link_encoder_setup,
- .enable_tmds_output = dce80_link_encoder_enable_tmds_output,
- .enable_dp_output = dce80_link_encoder_enable_dp_output,
- .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
- .disable_output = dce110_link_encoder_disable_output,
- .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
- .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
- .update_mst_stream_allocation_table =
- dce110_link_encoder_update_mst_stream_allocation_table,
- .set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
- .set_dmcu_backlight_level =
- dce110_link_encoder_set_dmcu_backlight_level,
- .set_dmcu_abm_level = dce110_link_encoder_set_dmcu_abm_level,
- .backlight_control = dce110_link_encoder_edp_backlight_control,
- .power_control = dce110_link_encoder_edp_power_control,
- .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
- .destroy = dce110_link_encoder_destroy
-};
-
-bool dce80_link_encoder_construct(
- struct dce110_link_encoder *enc110,
- const struct encoder_init_data *init_data,
- const struct dce110_link_enc_registers *link_regs,
- const struct dce110_link_enc_aux_registers *aux_regs,
- const struct dce110_link_enc_hpd_registers *hpd_regs)
-{
- struct graphics_object_encoder_cap_info enc_cap_info = {0};
-
- enc110->base.funcs = &dce80_lnk_enc_funcs;
- enc110->base.ctx = init_data->ctx;
- enc110->base.id = init_data->encoder;
-
- enc110->base.hpd_source = init_data->hpd_source;
- enc110->base.connector = init_data->connector;
- enc110->base.input_signals = SIGNAL_TYPE_ALL;
-
- enc110->base.adapter_service = init_data->adapter_service;
-
- enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
-
- enc110->base.features.flags.raw = 0;
-
- enc110->base.transmitter = init_data->transmitter;
-
- enc110->base.features.flags.bits.IS_AUDIO_CAPABLE = true;
-
- enc110->base.features.max_pixel_clock = MAX_ENCODER_CLK;
-
- enc110->base.features.max_hdmi_pixel_clock =
- DCE8_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
- enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
- enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
-
- /* set the flag to indicate whether driver poll the I2C data pin
- * while doing the DP sink detect
- */
-
- if (dal_adapter_service_is_feature_supported(enc110->base.adapter_service,
- FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
- enc110->base.features.flags.bits.
- DP_SINK_DETECT_POLL_DATA_PIN = true;
-
- enc110->base.output_signals =
- SIGNAL_TYPE_DVI_SINGLE_LINK |
- SIGNAL_TYPE_DVI_DUAL_LINK |
- SIGNAL_TYPE_LVDS |
- SIGNAL_TYPE_DISPLAY_PORT |
- SIGNAL_TYPE_DISPLAY_PORT_MST |
- SIGNAL_TYPE_EDP |
- SIGNAL_TYPE_HDMI_TYPE_A;
-
- /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
- * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
- * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
- * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
- * Prefer DIG assignment is decided by board design.
- * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
- * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
- * By this, adding DIGG should not hurt DCE 8.0.
- * This will let DCE 8.1 share DCE 8.0 as much as possible
- */
-
- enc110->link_regs = link_regs;
- enc110->aux_regs = aux_regs;
- enc110->hpd_regs = hpd_regs;
-
- switch (enc110->base.transmitter) {
- case TRANSMITTER_UNIPHY_A:
- enc110->base.preferred_engine = ENGINE_ID_DIGA;
- break;
- case TRANSMITTER_UNIPHY_B:
- enc110->base.preferred_engine = ENGINE_ID_DIGB;
-
- break;
- case TRANSMITTER_UNIPHY_C:
- enc110->base.preferred_engine = ENGINE_ID_DIGC;
- break;
- case TRANSMITTER_UNIPHY_D:
- enc110->base.preferred_engine = ENGINE_ID_DIGD;
- break;
- case TRANSMITTER_UNIPHY_E:
- enc110->base.preferred_engine = ENGINE_ID_DIGE;
- break;
- case TRANSMITTER_UNIPHY_F:
- enc110->base.preferred_engine = ENGINE_ID_DIGF;
- break;
- default:
- ASSERT_CRITICAL(false);
- enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
- break;
- }
-
- dm_logger_write(init_data->ctx->logger, LOG_I2C_AUX,
- "Using channel: %s [%d]\n",
- DECODE_CHANNEL_ID(init_data->channel),
- init_data->channel);
-
- /* Override features with DCE-specific values */
- if (dal_adapter_service_get_encoder_cap_info(
- enc110->base.adapter_service,
- enc110->base.id, &enc_cap_info))
- enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
- enc_cap_info.dp_hbr2_cap;
-
- /* test pattern 3 support */
- enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
- enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
-
- enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE =
- dal_adapter_service_is_feature_supported(enc110->base.adapter_service,
- FEATURE_SUPPORT_DP_Y_ONLY);
-
- enc110->base.features.flags.bits.IS_YCBCR_CAPABLE =
- dal_adapter_service_is_feature_supported(enc110->base.adapter_service,
- FEATURE_SUPPORT_DP_YUV);
-
- return true;
-}
-
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
deleted file mode 100644
index 326409bc159c..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_link_encoder.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_LINK_ENCODER__DCE80_H__
-#define __DC_LINK_ENCODER__DCE80_H__
-
-#include "link_encoder.h"
-#include "../dce110/dce110_link_encoder.h"
-
-bool dce80_link_encoder_construct(
- struct dce110_link_encoder *enc110,
- const struct encoder_init_data *init_data,
- const struct dce110_link_enc_registers *link_regs,
- const struct dce110_link_enc_aux_registers *aux_regs,
- const struct dce110_link_enc_hpd_registers *hpd_regs);
-
-#endif /* __DC_LINK_ENCODER__DCE80_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index d557fcc40ccb..0023ed344467 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -23,6 +23,7 @@
*
*/
+
#include "dm_services.h"
#include "link_encoder.h"
@@ -36,12 +37,11 @@
#include "dce110/dce110_mem_input.h"
#include "dce110/dce110_resource.h"
#include "dce80/dce80_timing_generator.h"
-#include "dce80/dce80_link_encoder.h"
-#include "dce110/dce110_link_encoder.h"
+#include "dce/dce_link_encoder.h"
+#include "dce/dce_stream_encoder.h"
#include "dce80/dce80_mem_input.h"
#include "dce80/dce80_ipp.h"
#include "dce80/dce80_transform.h"
-#include "dce/dce110_stream_encoder.h"
#include "dce80/dce80_opp.h"
#include "dce110/dce110_ipp.h"
#include "dce110/dce110_clock_source.h"
@@ -504,13 +504,17 @@ struct link_encoder *dce80_link_encoder_create(
if (!enc110)
return NULL;
- if (dce80_link_encoder_construct(
+ if (dce110_link_encoder_construct(
enc110,
enc_init_data,
&link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1],
- &link_enc_hpd_regs[enc_init_data->hpd_source]))
+ &link_enc_hpd_regs[enc_init_data->hpd_source])) {
+
+ enc110->base.features.ycbcr420_supported = false;
+ enc110->base.features.max_hdmi_pixel_clock = 297000;
return &enc110->base;
+ }
BREAK_TO_DEBUGGER();
dm_free(enc110);
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
index 02fa1d24f7f0..9667f00e9447 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
@@ -64,6 +64,7 @@ struct encoder_feature_support {
/* maximum supported clock */
unsigned int max_pixel_clock;
unsigned int max_hdmi_pixel_clock;
+ bool ycbcr420_supported;
};
enum physical_phy_id {
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 05/76] drm/amd/dal: Remove wireless_data_source
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 04/76] drm/amd/dal: Consolidate link encoder from each dce version Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 06/76] drm/amd/dal: Move gpio_service out of adapter_service Harry Wentland
` (71 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/adapter/Makefile | 2 +-
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 36 +---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.h | 2 -
.../drm/amd/dal/dc/adapter/wireless_data_source.c | 208 ---------------------
.../drm/amd/dal/dc/adapter/wireless_data_source.h | 79 --------
5 files changed, 8 insertions(+), 319 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
index a70cf1363a90..3297656bf948 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
@@ -2,7 +2,7 @@
# Makefile for the 'adapter' sub-component of DAL.
# It provides the control and status of HW adapter.
-ADAPTER = adapter_service.o wireless_data_source.o
+ADAPTER = adapter_service.o
AMD_DAL_ADAPTER = $(addprefix $(AMDDALPATH)/dc/adapter/,$(ADAPTER))
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index 4c2c2fc164be..119b763b2e90 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -36,8 +36,6 @@
#include "adapter_service.h"
-#include "wireless_data_source.h"
-
#include "atom.h"
#define ABSOLUTE_BACKLIGHT_MAX 255
@@ -475,10 +473,6 @@ static bool get_feature_value_from_data_sources(
*data = as->asic_cap->data[ASIC_DATA_STUTTERMODE];
break;
- case FEATURE_WIRELESS_ENABLE:
- *data = as->wireless_data.wireless_enable;
- break;
-
case FEATURE_8BPP_SUPPORTED:
*data = as->asic_cap->caps.SUPPORT_8BPP;
break;
@@ -810,18 +804,6 @@ enum dce_version dal_adapter_service_get_dce_version(
}
}
-static bool is_wireless_object(struct graphics_object_id id)
-{
- if ((id.type == OBJECT_TYPE_ENCODER &&
- id.id == ENCODER_ID_INTERNAL_WIRELESS) ||
- (id.type == OBJECT_TYPE_CONNECTOR && id.id ==
- CONNECTOR_ID_WIRELESS) ||
- (id.type == OBJECT_TYPE_CONNECTOR && id.id ==
- CONNECTOR_ID_MIRACAST))
- return true;
- return false;
-}
-
/**
* Get the source objects of an object
*
@@ -841,17 +823,13 @@ struct graphics_object_id dal_adapter_service_get_src_obj(
struct graphics_object_id src_object_id;
struct dc_bios *dcb = as->ctx->dc_bios;
- if (is_wireless_object(id))
- src_object_id = wireless_get_src_obj_id(as, id, index);
- else {
- if (BP_RESULT_OK != dcb->funcs->get_src_obj(dcb, id, index,
- &src_object_id)) {
- src_object_id =
- dal_graphics_object_id_init(
- 0,
- ENUM_ID_UNKNOWN,
- OBJECT_TYPE_UNKNOWN);
- }
+ if (BP_RESULT_OK != dcb->funcs->get_src_obj(dcb, id, index,
+ &src_object_id)) {
+ src_object_id =
+ dal_graphics_object_id_init(
+ 0,
+ ENUM_ID_UNKNOWN,
+ OBJECT_TYPE_UNKNOWN);
}
return src_object_id;
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
index 957bc25c563c..0e651206af16 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
@@ -29,7 +29,6 @@
/* Include */
#include "dc_bios_types.h"
#include "include/adapter_service_interface.h"
-#include "wireless_data_source.h"
#define SIZEOF_BACKLIGHT_LUT 101
@@ -46,7 +45,6 @@ struct adapter_service {
enum dce_environment dce_environment;
struct gpio_service *gpio_service;
struct i2caux *i2caux;
- struct wireless_data wireless_data;
struct integrated_info *integrated_info;
uint32_t platform_methods_mask;
uint32_t ac_level_percentage;
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
deleted file mode 100644
index 0b1151ec5a2c..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-
-#include "dm_services.h"
-#include "adapter_service.h"
-#include "wireless_data_source.h"
-
-#include "atom.h"
-
-/*construct wireless data*/
-bool wireless_data_init(struct wireless_data *data,
- struct dc_bios *dcb,
- struct wireless_init_data *init_data)
-{
- struct firmware_info info;
-
- if (data == NULL || dcb == NULL || init_data == NULL) {
- ASSERT_CRITICAL(false);
- return false;
- }
-
- data->miracast_connector_enable = false;
- data->wireless_disp_path_enable = false;
- data->wireless_enable = false;
-
- /* Wireless it not supported if VCE is not supported */
- if (!init_data->vce_supported)
- return true;
-
- if (init_data->miracast_target_required)
- data->miracast_connector_enable = true;
-
- /*
- * If override is in place for platform support, we will both
- * enable wireless display as a feature (i.e. CCC aspect) and
- * enable the wireless display path without any further checks.
- */
- if (init_data->platform_override) {
- data->wireless_enable = true;
- data->wireless_disp_path_enable = true;
- } else {
- /*
- * Check if SBIOS sets remote display enable, exposed
- * through VBIOS. This is only valid for APU, not dGPU
- */
- dcb->funcs->get_firmware_info(dcb, &info);
-
- if ((REMOTE_DISPLAY_ENABLE == info.remote_display_config) &&
- init_data->fusion) {
- data->wireless_enable = true;
- data->wireless_disp_path_enable = true;
- }
- }
-
- /*
- * If remote display path override is enabled, we enable just the
- * remote display path. This is mainly used for testing purposes
- */
- if (init_data->remote_disp_path_override)
- data->wireless_disp_path_enable = true;
-
- return true;
-}
-
-uint8_t wireless_get_clocks_num(
- struct adapter_service *as)
-{
- if (as->wireless_data.wireless_enable ||
- as->wireless_data.wireless_disp_path_enable)
- return 1;
- else
- return 0;
-}
-
-static uint8_t wireless_get_encoders_num(
- struct adapter_service *as)
-{
- if (as->wireless_data.wireless_enable ||
- as->wireless_data.wireless_disp_path_enable)
- return 1;
- else
- return 0;
-}
-
-uint8_t wireless_get_connectors_num(
- struct adapter_service *as)
-{
- uint8_t wireless_connectors_num = 0;
-
- if (as->wireless_data.wireless_enable &&
- as->wireless_data.miracast_connector_enable)
- wireless_connectors_num++;
-
- if (as->wireless_data.wireless_disp_path_enable)
- wireless_connectors_num++;
-
- return wireless_connectors_num;
-}
-
-struct graphics_object_id wireless_get_connector_id(
- struct adapter_service *as,
- uint8_t index)
-{
- struct graphics_object_id unknown_object_id =
- dal_graphics_object_id_init(
- 0,
- ENUM_ID_UNKNOWN,
- OBJECT_TYPE_UNKNOWN);
-
- if (!as->wireless_data.wireless_enable &&
- !as->wireless_data.wireless_disp_path_enable)
- return unknown_object_id;
-
- else if (!as->wireless_data.miracast_connector_enable)
- return dal_graphics_object_id_init(
- CONNECTOR_ID_WIRELESS,
- ENUM_ID_1,
- OBJECT_TYPE_CONNECTOR);
-
- switch (index) {
- case 0:
- return dal_graphics_object_id_init(
- CONNECTOR_ID_WIRELESS,
- ENUM_ID_1,
- OBJECT_TYPE_CONNECTOR);
- break;
- case 1:
- return dal_graphics_object_id_init(
- CONNECTOR_ID_MIRACAST,
- ENUM_ID_1,
- OBJECT_TYPE_CONNECTOR);
- break;
- default:
- return unknown_object_id;
- }
-}
-
-uint8_t wireless_get_srcs_num(
- struct adapter_service *as,
- struct graphics_object_id id)
-{
- switch (id.type) {
- case OBJECT_TYPE_CONNECTOR:
- return wireless_get_encoders_num(as);
- case OBJECT_TYPE_ENCODER:
- return 1;
-
- default:
- ASSERT_CRITICAL(false);
- break;
- }
-
- return 0;
-}
-
-struct graphics_object_id wireless_get_src_obj_id(
- struct adapter_service *as,
- struct graphics_object_id id,
- uint8_t index)
-{
- if (index < wireless_get_srcs_num(as, id)) {
- switch (id.type) {
- case OBJECT_TYPE_CONNECTOR:
- return dal_graphics_object_id_init(
- ENCODER_ID_INTERNAL_WIRELESS,
- ENUM_ID_1,
- OBJECT_TYPE_ENCODER);
- break;
- case OBJECT_TYPE_ENCODER:
- return dal_graphics_object_id_init(
- 0,
- ENUM_ID_1,
- OBJECT_TYPE_GPU);
- break;
- default:
- ASSERT_CRITICAL(false);
- break;
- }
- }
-
- return dal_graphics_object_id_init(
- 0,
- ENUM_ID_UNKNOWN,
- OBJECT_TYPE_UNKNOWN);
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h b/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
deleted file mode 100644
index 972ada80cf65..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_WIRELESS_DATA_SOURCE_H__
-#define __DAL_WIRELESS_DATA_SOURCE_H__
-
-/* Include */
-#include "include/grph_object_id.h"
-
-/*
- * Forward declaration
- */
-struct adapter_service;
-struct dc_bios;
-
-/* Wireless data init structure */
-struct wireless_init_data {
- bool fusion; /* Fusion flag */
- bool platform_override; /* Override for platform BIOS option */
- bool remote_disp_path_override; /* Override enabling wireless path */
- bool vce_supported; /* Existence of VCE block on this DCE */
- bool miracast_target_required; /* OS requires Miracast target */
-};
-
-/* Wireless data */
-struct wireless_data {
- bool wireless_enable;
- bool wireless_disp_path_enable;
- bool miracast_connector_enable;
-};
-
-/*construct wireless data*/
-bool wireless_data_init(
- struct wireless_data *data,
- struct dc_bios *dcb,
- struct wireless_init_data *init_data);
-
-uint8_t wireless_get_clocks_num(
- struct adapter_service *as);
-
-uint8_t wireless_get_connectors_num(
- struct adapter_service *as);
-
-struct graphics_object_id wireless_get_connector_id(
- struct adapter_service *as,
- uint8_t connector_index);
-
-uint8_t wireless_get_srcs_num(
- struct adapter_service *as,
- struct graphics_object_id id);
-
-struct graphics_object_id wireless_get_src_obj_id(
- struct adapter_service *as,
- struct graphics_object_id id,
- uint8_t index);
-
-#endif /* __DAL_WIRELESS_DATA_SOURCE_H__ */
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 06/76] drm/amd/dal: Move gpio_service out of adapter_service
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 05/76] drm/amd/dal: Remove wireless_data_source Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 07/76] drm/amd/dal: Fix warning about comparing different types Harry Wentland
` (70 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 16 ---------------
.../gpu/drm/amd/dal/dc/adapter/adapter_service.h | 24 ----------------------
drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 2 +-
drivers/gpu/drm/amd/dal/dc/core/dc.c | 20 +++++++++++++++++-
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 2 +-
drivers/gpu/drm/amd/dal/dc/dc_types.h | 1 +
drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c | 2 +-
.../amd/dal/include/adapter_service_interface.h | 20 +++++++++++++++++-
9 files changed, 43 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index 119b763b2e90..6d2f5762ef63 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -610,7 +610,6 @@ static void adapter_service_destruct(
struct dc_bios *dcb = as->ctx->dc_bios;
dal_i2caux_destroy(&as->i2caux);
- dal_gpio_service_destroy(&as->gpio_service);
dal_asic_capability_destroy(&as->asic_cap);
dcb->funcs->destroy_integrated_info(dcb, &as->integrated_info);
@@ -674,18 +673,6 @@ static bool adapter_service_construct(
dcb = as->ctx->dc_bios;
-
- /* Create GPIO service */
- as->gpio_service = dal_gpio_service_create(
- dce_version,
- as->dce_environment,
- as->ctx);
-
- if (!as->gpio_service) {
- ASSERT_CRITICAL(false);
- goto failed_to_create_gpio_service;
- }
-
/* Create I2C AUX */
as->i2caux = dal_i2caux_create(as, as->ctx);
@@ -714,9 +701,6 @@ failed_to_generate_features:
dal_i2caux_destroy(&as->i2caux);
failed_to_create_i2caux:
- dal_gpio_service_destroy(&as->gpio_service);
-
-failed_to_create_gpio_service:
dal_asic_capability_destroy(&as->asic_cap);
return false;
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
index 0e651206af16..823322bfc3a2 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
@@ -30,29 +30,5 @@
#include "dc_bios_types.h"
#include "include/adapter_service_interface.h"
-#define SIZEOF_BACKLIGHT_LUT 101
-
-/*
- * Forward declaration
- */
-struct gpio_service;
-struct asic_cap;
-
-/* Adapter service */
-struct adapter_service {
- struct dc_context *ctx;
- struct asic_capability *asic_cap;
- enum dce_environment dce_environment;
- struct gpio_service *gpio_service;
- struct i2caux *i2caux;
- struct integrated_info *integrated_info;
- uint32_t platform_methods_mask;
- uint32_t ac_level_percentage;
- uint32_t dc_level_percentage;
- uint32_t backlight_caps_initialized;
- uint32_t backlight_8bit_lut[SIZEOF_BACKLIGHT_LUT];
- uint32_t adapter_feature_set[FEATURE_MAXIMUM/32];
- uint32_t default_values[FEATURE_MAXIMUM];
-};
#endif /* __DAL_ADAPTER_SERVICE_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
index 0647156f313c..1080c6c5527b 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
@@ -2932,7 +2932,7 @@ static bool i2c_read(
i2c_info->i2c_hw_assist,
i2c_info->i2c_line };
- ddc = dal_gpio_create_ddc(as->gpio_service,
+ ddc = dal_gpio_create_ddc(as->ctx->gpio_service,
i2c_info->gpio_info.clk_a_register_index,
(1 << i2c_info->gpio_info.clk_a_shift), &hw_info);
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index c66cb6607752..e4990983924e 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -537,7 +537,7 @@ static bool construct(struct core_dc *dc,
if (!dc_ctx->dc_bios) {
ASSERT_CRITICAL(false);
- goto as_fail;
+ goto bios_fail;
}
dc_ctx->created_bios = true;
@@ -554,6 +554,17 @@ static bool construct(struct core_dc *dc,
}
}
+ /* Create GPIO service */
+ dc_ctx->gpio_service = dal_gpio_service_create(
+ dc_version,
+ as->dce_environment,
+ as->ctx);
+
+ if (!dc_ctx->gpio_service) {
+ ASSERT_CRITICAL(false);
+ goto gpio_fail;
+ }
+
dc->res_pool = dc_create_resource_pool(
as,
dc,
@@ -574,9 +585,15 @@ static bool construct(struct core_dc *dc,
create_links_fail:
dc->res_pool->funcs->destroy(&dc->res_pool);
create_resource_fail:
+ if (dc->ctx->gpio_service)
+ dal_gpio_service_destroy(&dc_ctx->gpio_service);
+gpio_fail:
if (as)
dal_adapter_service_destroy(&as);
as_fail:
+ if (dc->ctx->created_bios)
+ dal_bios_parser_destroy(&dc->ctx->dc_bios);
+bios_fail:
dal_logger_destroy(&dc_ctx->logger);
logger_fail:
dm_free(dc->current_context);
@@ -588,6 +605,7 @@ ctx_fail:
static void destruct(struct core_dc *dc)
{
+ dal_gpio_service_destroy(&dc->ctx->gpio_service);
resource_validate_ctx_destruct(dc->current_context);
dm_free(dc->current_context);
dm_free(dc->temp_flip_context);
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index c2eb27a257d6..fb902558d6a2 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -110,7 +110,7 @@ static struct gpio *get_hpd_gpio(const struct core_link *link)
}
return dal_gpio_service_create_irq(
- link->adapter_srv->gpio_service,
+ link->ctx->gpio_service,
pin_info.offset,
pin_info.mask);
}
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
index ffcd2a10d6f6..fd60a4c6d2a3 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
@@ -280,7 +280,7 @@ static bool construct(
enum connector_id connector_id =
dal_graphics_object_id_get_connector_id(init_data->id);
- struct gpio_service *gpio_service = init_data->as->gpio_service;
+ struct gpio_service *gpio_service = init_data->ctx->gpio_service;
struct graphics_object_i2c_info i2c_info;
struct gpio_ddc_hw_info hw_info;
struct dc_bios *dcb = init_data->ctx->dc_bios;
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
index c71f81f0cd95..573db6ef5a1d 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
@@ -75,6 +75,7 @@ struct dc_context {
struct dc_bios *dc_bios;
bool created_bios;
+ struct gpio_service *gpio_service;
};
/*
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
index 8a9060601005..ae9de4824378 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
@@ -582,7 +582,7 @@ static struct gpio *get_hpd_gpio(const struct link_encoder *enc)
}
return dal_gpio_service_create_irq(
- enc->adapter_service->gpio_service,
+ enc->ctx->gpio_service,
pin_info.offset,
pin_info.mask);
}
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index 52bf06b8b507..052cd9ab5cf3 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -33,9 +33,11 @@
#include "dal_types.h"
#include "asic_capability_types.h"
+#define SIZEOF_BACKLIGHT_LUT 101
+
/* forward declaration */
struct i2caux;
-struct adapter_service;
+struct asic_cap;
/*
* enum adapter_feature_id
@@ -293,6 +295,22 @@ enum adapter_feature_id {
FEATURE_MAXIMUM
};
+/* Adapter service */
+struct adapter_service {
+ struct dc_context *ctx;
+ struct asic_capability *asic_cap;
+ enum dce_environment dce_environment;
+ struct i2caux *i2caux;
+ struct integrated_info *integrated_info;
+ uint32_t platform_methods_mask;
+ uint32_t ac_level_percentage;
+ uint32_t dc_level_percentage;
+ uint32_t backlight_caps_initialized;
+ uint32_t backlight_8bit_lut[SIZEOF_BACKLIGHT_LUT];
+ uint32_t adapter_feature_set[FEATURE_MAXIMUM/32];
+ uint32_t default_values[FEATURE_MAXIMUM];
+};
+
/* Adapter Service type of DRR support*/
enum as_drr_support {
AS_DRR_SUPPORT_DISABLED = 0x0,
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 07/76] drm/amd/dal: Fix warning about comparing different types
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 06/76] drm/amd/dal: Move gpio_service out of adapter_service Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 08/76] drm/amd/dal: fix dc creation Harry Wentland
` (69 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index e4990983924e..ad4884a6f98d 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -650,7 +650,7 @@ void ProgramPixelDurationV(unsigned int pixelClockInKHz )
struct dc *dc_create(const struct dc_init_data *init_params)
{
struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
- int full_pipe_count;
+ unsigned int full_pipe_count;
if (NULL == core_dc)
goto alloc_fail;
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 08/76] drm/amd/dal: fix dc creation
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 07/76] drm/amd/dal: Fix warning about comparing different types Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 09/76] drm/amd/dal: add chroma support to program_size_and_rotation Harry Wentland
` (68 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index ad4884a6f98d..a65950bf771b 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -557,8 +557,8 @@ static bool construct(struct core_dc *dc,
/* Create GPIO service */
dc_ctx->gpio_service = dal_gpio_service_create(
dc_version,
- as->dce_environment,
- as->ctx);
+ dc_ctx->dce_environment,
+ dc_ctx);
if (!dc_ctx->gpio_service) {
ASSERT_CRITICAL(false);
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 09/76] drm/amd/dal: add chroma support to program_size_and_rotation
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 08/76] drm/amd/dal: fix dc creation Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 10/76] drm/amd/dal: add meta address to video address struct Harry Wentland
` (67 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dc_hw_types.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
index 0a6510d2ad96..13b43dd6b921 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
@@ -114,6 +114,7 @@ union plane_size {
* 32 pixel aligned.
*/
uint32_t luma_pitch;
+ uint32_t meta_luma_pitch;
struct rect chroma_size;
/* Graphic surface pitch in pixels.
@@ -121,6 +122,7 @@ union plane_size {
* 32 pixel aligned.
*/
uint32_t chroma_pitch;
+ uint32_t meta_chroma_pitch;
} video;
};
--
2.10.1
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* [PATCH 10/76] drm/amd/dal: add meta address to video address struct
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 09/76] drm/amd/dal: add chroma support to program_size_and_rotation Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 11/76] drm/amd/dal: Refactor i2c_hw_engine Harry Wentland
` (66 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dc_hw_types.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
index 13b43dd6b921..246110201c10 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
@@ -76,6 +76,8 @@ struct dc_plane_address {
/*video progressive*/
struct {
+ PHYSICAL_ADDRESS_LOC meta_chroma;
+ PHYSICAL_ADDRESS_LOC meta_luma;
PHYSICAL_ADDRESS_LOC chroma_addr;
PHYSICAL_ADDRESS_LOC luma_addr;
} video_progressive;
--
2.10.1
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* [PATCH 11/76] drm/amd/dal: Refactor i2c_hw_engine
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 10/76] drm/amd/dal: add meta address to video address struct Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 12/76] drm/amd/dal: modify DCE HW sequence to be re-usable for next gen HW Harry Wentland
` (65 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Pass dce110_i2c_hw_engine_registers as parameter.
Fixup hw_engine regs set. asssign registers array starting from element 0 and not 1
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.c | 22 ++++++++-
.../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c | 14 ++++--
.../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h | 4 +-
.../drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.c | 52 +++-------------------
4 files changed, 40 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.c
index 917896fa1bce..e3ababdfe7aa 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.c
@@ -33,6 +33,7 @@
#include "../i2c_hw_engine.h"
#include "../dce110/aux_engine_dce110.h"
+#include "../dce110/i2c_hw_engine_dce110.h"
#include "../dce110/i2caux_dce110.h"
#include "dce/dce_10_0_d.h"
@@ -52,6 +53,11 @@
.AUX_RESET_MASK = 0 \
}
+#define hw_engine_regs(id)\
+{\
+ I2C_HW_ENGINE_COMMON_REG_LIST(id) \
+}
+
static const struct dce110_aux_registers dce100_aux_regs[] = {
aux_regs(0),
aux_regs(1),
@@ -61,6 +67,15 @@ static const struct dce110_aux_registers dce100_aux_regs[] = {
aux_regs(5),
};
+static const struct dce110_i2c_hw_engine_registers dce100_hw_engine_regs[] = {
+ hw_engine_regs(1),
+ hw_engine_regs(2),
+ hw_engine_regs(3),
+ hw_engine_regs(4),
+ hw_engine_regs(5),
+ hw_engine_regs(6)
+};
+
struct i2caux *dal_i2caux_dce100_create(
struct adapter_service *as,
struct dc_context *ctx)
@@ -73,7 +88,12 @@ struct i2caux *dal_i2caux_dce100_create(
return NULL;
}
- if (dal_i2caux_dce110_construct(i2caux_dce110, as, ctx, dce100_aux_regs))
+ if (dal_i2caux_dce110_construct(
+ i2caux_dce110,
+ as,
+ ctx,
+ dce100_aux_regs,
+ dce100_hw_engine_regs))
return &i2caux_dce110->base;
ASSERT_CRITICAL(false);
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
index 650474bbdcb5..566056b6782f 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
@@ -166,7 +166,7 @@ static const struct i2caux_funcs i2caux_funcs = {
}
#define hw_engine_regs(id)\
-[id] = {\
+{\
I2C_HW_ENGINE_COMMON_REG_LIST(id) \
}
@@ -192,7 +192,8 @@ bool dal_i2caux_dce110_construct(
struct i2caux_dce110 *i2caux_dce110,
struct adapter_service *as,
struct dc_context *ctx,
- const struct dce110_aux_registers aux_regs[])
+ const struct dce110_aux_registers aux_regs[],
+ const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[])
{
uint32_t i = 0;
uint32_t reference_frequency = 0;
@@ -239,7 +240,7 @@ bool dal_i2caux_dce110_construct(
hw_arg_dce110.reference_frequency = reference_frequency;
hw_arg_dce110.default_speed = base->default_i2c_hw_speed;
hw_arg_dce110.ctx = ctx;
- hw_arg_dce110.regs = &i2c_hw_engine_regs[i + 1];
+ hw_arg_dce110.regs = &i2c_hw_engine_regs[i];
base->i2c_hw_engines[line_id] =
dal_i2c_hw_engine_dce110_create(&hw_arg_dce110);
@@ -298,7 +299,12 @@ struct i2caux *dal_i2caux_dce110_create(
return NULL;
}
- if (dal_i2caux_dce110_construct(i2caux_dce110, as, ctx, dce110_aux_regs))
+ if (dal_i2caux_dce110_construct(
+ i2caux_dce110,
+ as,
+ ctx,
+ dce110_aux_regs,
+ i2c_hw_engine_regs))
return &i2caux_dce110->base;
ASSERT_CRITICAL(false);
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h
index b4ca557de804..d26eec0ff12c 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h
@@ -35,6 +35,7 @@ struct i2caux_dce110 {
};
struct dce110_aux_registers;
+struct dce110_i2c_hw_engine_registers;
struct i2caux *dal_i2caux_dce110_create(
struct adapter_service *as,
@@ -44,6 +45,7 @@ bool dal_i2caux_dce110_construct(
struct i2caux_dce110 *i2caux_dce110,
struct adapter_service *as,
struct dc_context *ctx,
- const struct dce110_aux_registers *aux_regs);
+ const struct dce110_aux_registers *aux_regs,
+ const struct dce110_i2c_hw_engine_registers *i2c_hw_engine_regs);
#endif /* __DAL_I2C_AUX_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.c
index a3478f0a9cab..748f0c4c3968 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.c
@@ -39,15 +39,6 @@
#include "../dce110/i2c_hw_engine_dce110.h"
-static const enum gpio_ddc_line hw_ddc_lines[] = {
- GPIO_DDC_LINE_DDC1,
- GPIO_DDC_LINE_DDC2,
- GPIO_DDC_LINE_DDC3,
- GPIO_DDC_LINE_DDC4,
- GPIO_DDC_LINE_DDC5,
- GPIO_DDC_LINE_DDC6,
-};
-
#include "dce/dce_11_2_d.h"
#include "dce/dce_11_2_sh_mask.h"
@@ -93,47 +84,16 @@ static bool construct(
struct adapter_service *as,
struct dc_context *ctx)
{
- int i = 0;
- uint32_t reference_frequency = 0;
- struct i2caux *base = NULL;
-
- if (!dal_i2caux_dce110_construct(i2caux_dce110, as, ctx, dce112_aux_regs)) {
+ if (!dal_i2caux_dce110_construct(
+ i2caux_dce110,
+ as,
+ ctx,
+ dce112_aux_regs,
+ dce112_hw_engine_regs)) {
ASSERT_CRITICAL(false);
return false;
}
- /*TODO: For CZ bring up, if dal_i2caux_get_reference_clock
- * does not return 48KHz, we need hard coded for 48Khz.
- * Some BIOS setting incorrect cause this
- * For production, we always get value from BIOS*/
- reference_frequency =
- dal_i2caux_get_reference_clock(as) >> 1;
-
- base = &i2caux_dce110->base;
-
- /* Create I2C engines (DDC lines per connector)
- * different I2C/AUX usage cases, DDC, Generic GPIO, AUX.
- */
- do {
- enum gpio_ddc_line line_id = hw_ddc_lines[i];
-
- struct i2c_hw_engine_dce110_create_arg hw_arg_dce110;
-
- hw_arg_dce110.engine_id = i;
- hw_arg_dce110.reference_frequency = reference_frequency;
- hw_arg_dce110.default_speed = base->default_i2c_hw_speed;
- hw_arg_dce110.ctx = ctx;
- hw_arg_dce110.regs = &dce112_hw_engine_regs[i];
-
- if (base->i2c_hw_engines[line_id])
- base->i2c_hw_engines[line_id]->funcs->destroy(&base->i2c_hw_engines[line_id]);
-
- base->i2c_hw_engines[line_id] =
- dal_i2c_hw_engine_dce110_create(&hw_arg_dce110);
-
- ++i;
- } while (i < ARRAY_SIZE(hw_ddc_lines));
-
return true;
}
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 12/76] drm/amd/dal: modify DCE HW sequence to be re-usable for next gen HW
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 11/76] drm/amd/dal: Refactor i2c_hw_engine Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 13/76] drm/amd/dal: DCC support Harry Wentland
` (64 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hersen Wu
From: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 50 +++++++++++-----------
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 2fd2bc794de4..1da40156cb9a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -774,6 +774,12 @@ static enum dc_status apply_single_controller_ctx_to_hw(
struct tg_color black_color = {0};
if (!pipe_ctx_old->stream) {
+
+ /* program blank color */
+ color_space_to_black_color(stream->public.output_color_space, &black_color);
+ pipe_ctx->tg->funcs->set_blank_color(
+ pipe_ctx->tg,
+ &black_color);
/*
* Must blank CRTC after disabling power gating and before any
* programming, otherwise CRTC will be hung in bad state
@@ -794,14 +800,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
true);
}
- /*TODO: mst support - use total stream count*/
- pipe_ctx->mi->funcs->allocate_mem_input(
- pipe_ctx->mi,
- stream->public.timing.h_total,
- stream->public.timing.v_total,
- stream->public.timing.pix_clk_khz,
- context->target_count);
-
if (!pipe_ctx_old->stream) {
if (false == pipe_ctx->tg->funcs->enable_crtc(
pipe_ctx->tg)) {
@@ -810,13 +808,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
}
}
- /* TODO: move to stream encoder */
- if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
- if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
- BREAK_TO_DEBUGGER();
- return DC_ERROR_UNEXPECTED;
- }
-
pipe_ctx->opp->funcs->opp_set_dyn_expansion(
pipe_ctx->opp,
COLOR_SPACE_YCBCR601,
@@ -828,6 +819,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
&stream->bit_depth_params,
&stream->clamping);
+ /* TODO: move to stream encoder */
+ if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
+ if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
+ BREAK_TO_DEBUGGER();
+ return DC_ERROR_UNEXPECTED;
+ }
+
if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
stream->sink->link->link_enc->funcs->setup(
stream->sink->link->link_enc,
@@ -852,12 +850,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
(pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
true : false);
- /* program blank color */
- color_space_to_black_color(stream->public.output_color_space, &black_color);
- pipe_ctx->tg->funcs->set_blank_color(
- pipe_ctx->tg,
- &black_color);
-
if (!pipe_ctx_old->stream) {
core_link_enable_stream(pipe_ctx);
@@ -871,6 +863,14 @@ static enum dc_status apply_single_controller_ctx_to_hw(
sizeof(struct scaler_data)) != 0)
program_scaler(dc, pipe_ctx);
+ /*TODO: mst support - use total stream count*/
+ pipe_ctx->mi->funcs->allocate_mem_input(
+ pipe_ctx->mi,
+ stream->public.timing.h_total,
+ stream->public.timing.v_total,
+ stream->public.timing.pix_clk_khz,
+ context->target_count);
+
return DC_OK;
}
@@ -1335,7 +1335,7 @@ static enum dc_status apply_ctx_to_hw(
/* Reset old context */
/* look up the targets that have been removed since last commit */
- for (i = 0; i < MAX_PIPES; i++) {
+ for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx_old =
&dc->current_context->res_ctx.pipe_ctx[i];
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
@@ -1362,7 +1362,7 @@ static enum dc_status apply_ctx_to_hw(
/* Apply new context */
dcb->funcs->set_scratch_critical_state(dcb, true);
- for (i = 0; i < MAX_PIPES; i++) {
+ for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx_old =
&dc->current_context->res_ctx.pipe_ctx[i];
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
@@ -1390,7 +1390,7 @@ static enum dc_status apply_ctx_to_hw(
> dc->current_context->bw_results.dispclk_khz)
set_display_clock(context);
- for (i = 0; i < MAX_PIPES; i++) {
+ for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx_old =
&dc->current_context->res_ctx.pipe_ctx[i];
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
@@ -1428,7 +1428,7 @@ static enum dc_status apply_ctx_to_hw(
* find first available pipe with audio, setup audio wall DTO per topology
* instead of per pipe.
*/
- for (i = 0; i < MAX_PIPES; i++) {
+ for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
if (context->res_ctx.pipe_ctx[i].audio != NULL) {
struct audio_output audio_output;
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
--
2.10.1
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* [PATCH 13/76] drm/amd/dal: DCC support
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (11 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 12/76] drm/amd/dal: modify DCE HW sequence to be re-usable for next gen HW Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 14/76] drm/amd/dal: Expose some HWS functions so we can re-use them Harry Wentland
` (63 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dc.h | 43 ++++++++++++++++---
drivers/gpu/drm/amd/dal/dc/dc_hw_types.h | 48 ++++++++++++++++++++--
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 2 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 2 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 2 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c | 2 +-
drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h | 2 +-
7 files changed, 87 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
index 2a6117ae85e3..0451b610b3e2 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
@@ -50,21 +50,52 @@ struct dc_caps {
uint32_t i2c_speed_in_khz;
};
+
+struct dc_dcc_surface_param {
+ enum surface_pixel_format format;
+ struct dc_size surface_size;
+ enum dc_scan_direction scan;
+};
+
+struct dc_dcc_setting {
+ unsigned int max_compressed_blk_size;
+ unsigned int max_uncompressed_blk_size;
+ bool independent_64b_blks;
+};
+
+struct dc_surface_dcc_cap {
+ bool capable;
+ bool const_color_support;
+
+ union {
+ struct {
+ struct dc_dcc_setting rgb;
+ } grph;
+
+ struct {
+ struct dc_dcc_setting luma;
+ struct dc_dcc_setting chroma;
+ } video;
+ };
+};
+
/* Forward declaration*/
struct dc;
struct dc_surface;
struct validate_context;
+struct dc_cap_funcs {
+ int i;
+};
+
struct dc_stream_funcs {
- bool (*adjust_vmin_vmax)(
- struct dc *dc,
+ bool (*adjust_vmin_vmax)(struct dc *dc,
const struct dc_stream **stream,
int num_streams,
int vmin,
int vmax);
- void (*stream_update_scaling)(
- const struct dc *dc,
+ void (*stream_update_scaling)(const struct dc *dc,
const struct dc_stream *dc_stream,
const struct rect *src,
const struct rect *dst);
@@ -106,10 +137,12 @@ struct dc_config {
struct dc_debug {
bool surface_visual_confirm;
bool disable_stutter;
+ bool disable_dcc;
};
struct dc {
struct dc_caps caps;
+ struct dc_cap_funcs cap_funcs;
struct dc_stream_funcs stream_funcs;
struct dc_link_funcs link_funcs;
struct dc_config config;
@@ -189,8 +222,8 @@ struct dc_surface {
union plane_size plane_size;
union dc_tiling_info tiling_info;
+ struct dc_plane_dcc_param dcc;
enum dc_color_space color_space;
- bool compressed;
enum surface_pixel_format format;
enum dc_rotation_angle rotation;
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
index 246110201c10..29e65a42930c 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_hw_types.h
@@ -65,25 +65,40 @@ struct dc_plane_address {
union {
struct{
PHYSICAL_ADDRESS_LOC addr;
- PHYSICAL_ADDRESS_LOC meta;
+ PHYSICAL_ADDRESS_LOC meta_addr;
+ union large_integer dcc_const_color;
} grph;
/*stereo*/
struct {
PHYSICAL_ADDRESS_LOC left_addr;
+ PHYSICAL_ADDRESS_LOC left_meta_addr;
+ union large_integer left_dcc_const_color;
+
PHYSICAL_ADDRESS_LOC right_addr;
+ PHYSICAL_ADDRESS_LOC right_meta_addr;
+ union large_integer right_dcc_const_color;
+
} grph_stereo;
/*video progressive*/
struct {
- PHYSICAL_ADDRESS_LOC meta_chroma;
- PHYSICAL_ADDRESS_LOC meta_luma;
- PHYSICAL_ADDRESS_LOC chroma_addr;
PHYSICAL_ADDRESS_LOC luma_addr;
+ PHYSICAL_ADDRESS_LOC luma_meta_addr;
+ union large_integer luma_dcc_const_color;
+
+ PHYSICAL_ADDRESS_LOC chroma_addr;
+ PHYSICAL_ADDRESS_LOC chroma_meta_addr;
+ union large_integer chroma_dcc_const_color;
} video_progressive;
};
};
+struct dc_size {
+ uint32_t width;
+ uint32_t height;
+};
+
struct rect {
int x;
int y;
@@ -128,6 +143,25 @@ union plane_size {
} video;
};
+struct dc_plane_dcc_param {
+ bool enable;
+
+ union {
+ struct {
+ uint32_t meta_pitch;
+ bool independent_64b_blks;
+ } grph;
+
+ struct {
+ uint32_t meta_pitch_l;
+ bool independent_64b_blks_l;
+
+ uint32_t meta_pitch_c;
+ bool independent_64b_blks_c;
+ } video;
+ };
+};
+
/*Displayable pixel format in fb*/
enum surface_pixel_format {
SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
@@ -298,6 +332,12 @@ enum dc_rotation_angle {
ROTATION_ANGLE_COUNT
};
+enum dc_scan_direction {
+ SCAN_DIRECTION_UNKNOWN = 0,
+ SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */
+ SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */
+};
+
struct dc_cursor_position {
uint32_t x;
uint32_t y;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 1da40156cb9a..123881f426fe 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -1606,7 +1606,7 @@ static void set_plane_config(
&surface->public.tiling_info,
&surface->public.plane_size,
surface->public.rotation,
- false);
+ NULL);
if (dc->public.config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
index 758884803ef3..3183728ed417 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
@@ -525,7 +525,7 @@ bool dce110_mem_input_program_surface_config(
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
- bool compressed)
+ struct dc_plane_dcc_param *dcc)
{
struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
index 4eeca44d20c7..c9e3f5c1fa22 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
@@ -128,7 +128,7 @@ bool dce110_mem_input_program_surface_config(
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
- bool compressed);
+ struct dc_plane_dcc_param *dcc);
/*
* dce110_mem_input_program_pte_vm
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
index 2af14f7558bd..5376fed66c29 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
@@ -666,7 +666,7 @@ bool dce110_mem_input_v_program_surface_config(
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
- bool compressed)
+ struct dc_plane_dcc_param *dcc)
{
struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
index fd68dc037a83..9ad3b4218cb0 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
@@ -80,7 +80,7 @@ struct mem_input_funcs {
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
- bool compressed);
+ struct dc_plane_dcc_param *dcc);
bool (*mem_input_is_flip_pending)(struct mem_input *mem_input);
};
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 14/76] drm/amd/dal: Expose some HWS functions so we can re-use them
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (12 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 13/76] drm/amd/dal: DCC support Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 15/76] drm/amd/dal: Modify regsiter access to use macro Harry Wentland
` (62 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hersen Wu
From: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 134 ++++++++++++++++-----
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.h | 25 ++++
drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 8 ++
3 files changed, 136 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 123881f426fe..f010a785c4e2 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -502,7 +502,7 @@ static enum dc_status bios_parser_crtc_source_select(
return DC_OK;
}
-static void update_info_frame(struct pipe_ctx *pipe_ctx)
+void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
{
if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_enc->funcs->update_hdmi_info_packets(
@@ -514,7 +514,7 @@ static void update_info_frame(struct pipe_ctx *pipe_ctx)
&pipe_ctx->encoder_info_frame);
}
-static void enable_stream(struct pipe_ctx *pipe_ctx)
+void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
{
enum dc_lane_count lane_count =
pipe_ctx->stream->sink->link->public.cur_link_settings.lane_count;
@@ -529,7 +529,8 @@ static void enable_stream(struct pipe_ctx *pipe_ctx)
uint32_t early_control = 0;
struct timing_generator *tg = pipe_ctx->tg;
- update_info_frame(pipe_ctx);
+ /* TODOFPGA may change to hwss.update_info_frame */
+ dce110_update_info_frame(pipe_ctx);
/* enable early control to avoid corruption on DP monitor*/
active_total_with_borders =
timing->h_addressable
@@ -559,7 +560,7 @@ static void enable_stream(struct pipe_ctx *pipe_ctx)
}
-static void disable_stream(struct pipe_ctx *pipe_ctx)
+void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
{
struct core_stream *stream = pipe_ctx->stream;
struct core_link *link = stream->sink->link;
@@ -606,7 +607,7 @@ static void disable_stream(struct pipe_ctx *pipe_ctx)
}
-static void unblank_stream(struct pipe_ctx *pipe_ctx,
+void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
struct dc_link_settings *link_settings)
{
struct encoder_unblank_param params = { { 0 } };
@@ -763,7 +764,7 @@ static void program_scaler(const struct core_dc *dc,
&pipe_ctx->scl_data);
}
-static enum dc_status apply_single_controller_ctx_to_hw(
+static enum dc_status prog_pixclk_crtc_otg(
struct pipe_ctx *pipe_ctx,
struct validate_context *context,
struct core_dc *dc)
@@ -808,6 +809,21 @@ static enum dc_status apply_single_controller_ctx_to_hw(
}
}
+ return DC_OK;
+}
+
+static enum dc_status apply_single_controller_ctx_to_hw(
+ struct pipe_ctx *pipe_ctx,
+ struct validate_context *context,
+ struct core_dc *dc)
+{
+ struct core_stream *stream = pipe_ctx->stream;
+ struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
+ pipe_ctx[pipe_ctx->pipe_idx];
+
+ /* */
+ dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
+
pipe_ctx->opp->funcs->opp_set_dyn_expansion(
pipe_ctx->opp,
COLOR_SPACE_YCBCR601,
@@ -819,6 +835,10 @@ static enum dc_status apply_single_controller_ctx_to_hw(
&stream->bit_depth_params,
&stream->clamping);
+ /* FPGA does not program backend */
+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+ return DC_OK;
+
/* TODO: move to stream encoder */
if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
@@ -854,17 +874,18 @@ static enum dc_status apply_single_controller_ctx_to_hw(
core_link_enable_stream(pipe_ctx);
if (dc_is_dp_signal(pipe_ctx->stream->signal))
- unblank_stream(pipe_ctx,
+ dce110_unblank_stream(pipe_ctx,
&stream->sink->link->public.cur_link_settings);
}
+ /* program_scaler and allocate_mem_input are not new asic */
if (!pipe_ctx_old || memcmp(&pipe_ctx_old->scl_data,
&pipe_ctx->scl_data,
sizeof(struct scaler_data)) != 0)
program_scaler(dc, pipe_ctx);
- /*TODO: mst support - use total stream count*/
- pipe_ctx->mi->funcs->allocate_mem_input(
+ /* mst support - use total stream count */
+ pipe_ctx->mi->funcs->allocate_mem_input(
pipe_ctx->mi,
stream->public.timing.h_total,
stream->public.timing.v_total,
@@ -949,7 +970,7 @@ static void disable_vga_and_power_gate_all_controllers(
* 3. Enable power gating for controller
* 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
*/
-static void enable_accelerated_mode(struct core_dc *dc)
+void dce110_enable_accelerated_mode(struct core_dc *dc)
{
power_down_all_hw_blocks(dc);
@@ -960,7 +981,7 @@ static void enable_accelerated_mode(struct core_dc *dc)
/**
* Call display_engine_clock_dce80 to perform the Dclk programming.
*/
-static void set_display_clock(struct validate_context *context)
+void dce110_set_display_clock(struct validate_context *context)
{
/* Program the display engine clock.
* Check DFS bypass mode support or not. DFSbypass feature is only when
@@ -1094,7 +1115,7 @@ static void program_wm_for_pipe(struct core_dc *dc,
total_dest_line_time_ns);
}
-static void set_displaymarks(
+void dce110_set_displaymarks(
const struct core_dc *dc,
struct validate_context *context)
{
@@ -1304,6 +1325,7 @@ static void apply_min_clocks(
pipe_ctx->dis_clk, *clocks_state))
return;
+ /* TODOFPGA */
}
/* get the required state based on state dependent clocks:
@@ -1322,16 +1344,42 @@ static void apply_min_clocks(
}
}
-/*TODO: const validate_context*/
-static enum dc_status apply_ctx_to_hw(
+static enum dc_status apply_ctx_to_hw_fpga(
struct core_dc *dc,
struct validate_context *context)
{
+ enum dc_status status = DC_ERROR_UNEXPECTED;
+ int i;
struct dc_bios *dcb = dc->ctx->dc_bios;
- enum dc_status status;
+
+ for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
+ struct pipe_ctx *pipe_ctx_old =
+ &dc->current_context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+ if (pipe_ctx->stream == NULL)
+ continue;
+
+ if (pipe_ctx->stream == pipe_ctx_old->stream)
+ continue;
+
+ status = apply_single_controller_ctx_to_hw(
+ pipe_ctx,
+ context,
+ dc);
+
+ if (status != DC_OK)
+ return status;
+ }
+
+ return DC_OK;
+}
+
+static void reset_hw_ctx_wrap(
+ struct core_dc *dc,
+ struct validate_context *context)
+{
int i;
- bool programmed_audio_dto = false;
- enum clocks_state clocks_state = CLOCKS_STATE_INVALID;
/* Reset old context */
/* look up the targets that have been removed since last commit */
@@ -1354,14 +1402,36 @@ static enum dc_status apply_ctx_to_hw(
reset_single_pipe_hw_ctx(
dc, pipe_ctx_old, dc->current_context);
}
+}
+
+/*TODO: const validate_context*/
+enum dc_status dce110_apply_ctx_to_hw(
+ struct core_dc *dc,
+ struct validate_context *context)
+{
+ struct dc_bios *dcb = dc->ctx->dc_bios;
+ enum dc_status status;
+ int i;
+ bool programmed_audio_dto = false;
+ enum clocks_state clocks_state = CLOCKS_STATE_INVALID;
+
+ /* Reset old context */
+ /* look up the targets that have been removed since last commit */
+ dc->hwss.reset_hw_ctx_wrap(dc, context);
/* Skip applying if no targets */
if (context->target_count <= 0)
return DC_OK;
+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+ apply_ctx_to_hw_fpga(dc, context);
+ return DC_OK;
+ }
+
/* Apply new context */
dcb->funcs->set_scratch_critical_state(dcb, true);
+ /* below is for real asic only */
for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx_old =
&dc->current_context->res_ctx.pipe_ctx[i];
@@ -1388,7 +1458,7 @@ static enum dc_status apply_ctx_to_hw(
if (context->bw_results.dispclk_khz
> dc->current_context->bw_results.dispclk_khz)
- set_display_clock(context);
+ dc->hwss.set_display_clock(context);
for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx_old =
@@ -1635,7 +1705,7 @@ static void update_plane_addr(const struct core_dc *dc,
pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, false);
}
-static void update_pending_status(struct pipe_ctx *pipe_ctx)
+void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
{
struct core_surface *surface = pipe_ctx->surface;
@@ -1652,7 +1722,7 @@ static void update_pending_status(struct pipe_ctx *pipe_ctx)
surface->status.current_address = pipe_ctx->mi->current_address;
}
-static void power_down(struct core_dc *dc)
+void dce110_power_down(struct core_dc *dc)
{
power_down_all_hw_blocks(dc);
disable_vga_and_power_gate_all_controllers(dc);
@@ -2068,20 +2138,20 @@ static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe)
static const struct hw_sequencer_funcs dce110_funcs = {
.init_hw = init_hw,
- .apply_ctx_to_hw = apply_ctx_to_hw,
+ .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.prepare_pipe_for_context = dce110_prepare_pipe_for_context,
.apply_ctx_for_surface = dce110_apply_ctx_for_surface,
.set_plane_config = set_plane_config,
.update_plane_addr = update_plane_addr,
- .update_pending_status = update_pending_status,
+ .update_pending_status = dce110_update_pending_status,
.set_gamma_correction = set_gamma_ramp,
- .power_down = power_down,
- .enable_accelerated_mode = enable_accelerated_mode,
+ .power_down = dce110_power_down,
+ .enable_accelerated_mode = dce110_enable_accelerated_mode,
.enable_timing_synchronization = dce110_enable_timing_synchronization,
- .update_info_frame = update_info_frame,
- .enable_stream = enable_stream,
- .disable_stream = disable_stream,
- .unblank_stream = unblank_stream,
+ .update_info_frame = dce110_update_info_frame,
+ .enable_stream = dce110_enable_stream,
+ .disable_stream = dce110_disable_stream,
+ .unblank_stream = dce110_unblank_stream,
.enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
.crtc_switch_to_clk_src = dce110_crtc_switch_to_clk_src,
.enable_display_power_gating = dce110_enable_display_power_gating,
@@ -2090,12 +2160,14 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.pipe_control_lock = dce110_pipe_control_lock,
.set_blender_mode = dce110_set_blender_mode,
.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,
- .set_display_clock = set_display_clock,
- .set_displaymarks = set_displaymarks,
+ .set_display_clock = dce110_set_display_clock,
+ .set_displaymarks = dce110_set_displaymarks,
.increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe,
.set_bandwidth = dce110_set_bandwidth,
.set_drr = set_drr,
- .set_static_screen_control = set_static_screen_control
+ .set_static_screen_control = set_static_screen_control,
+ .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
+ .prog_pixclk_crtc_otg = prog_pixclk_crtc_otg,
};
bool dce110_hw_sequencer_construct(struct core_dc *dc)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
index 38550ac23d06..4405bdbb3bb8 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
@@ -34,5 +34,30 @@ struct core_dc;
bool dce110_hw_sequencer_construct(struct core_dc *dc);
+enum dc_status dce110_apply_ctx_to_hw(
+ struct core_dc *dc,
+ struct validate_context *context);
+
+void dce110_set_display_clock(struct validate_context *context);
+
+void dce110_set_displaymarks(
+ const struct core_dc *dc,
+ struct validate_context *context);
+
+void dce110_enable_stream(struct pipe_ctx *pipe_ctx);
+
+void dce110_disable_stream(struct pipe_ctx *pipe_ctx);
+
+void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
+ struct dc_link_settings *link_settings);
+
+void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
+
+void dce110_enable_accelerated_mode(struct core_dc *dc);
+
+void dce110_power_down(struct core_dc *dc);
+
+void dce110_update_pending_status(struct pipe_ctx *pipe_ctx);
+
#endif /* __DC_HWSS_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index cb382e9e1b34..6435247a41e8 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -51,6 +51,9 @@ struct hw_sequencer_funcs {
enum dc_status (*apply_ctx_to_hw)(
struct core_dc *dc, struct validate_context *context);
+ void (*reset_hw_ctx_wrap)(
+ struct core_dc *dc, struct validate_context *context);
+
void (*prepare_pipe_for_context)(
struct core_dc *dc,
struct pipe_ctx *pipe_ctx,
@@ -149,6 +152,11 @@ struct hw_sequencer_funcs {
void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
int num_pipes, int value);
+
+ enum dc_status (*prog_pixclk_crtc_otg)(
+ struct pipe_ctx *pipe_ctx,
+ struct validate_context *context,
+ struct core_dc *dc);
};
void color_space_to_black_color(
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 15/76] drm/amd/dal: Modify regsiter access to use macro.
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (13 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 14/76] drm/amd/dal: Expose some HWS functions so we can re-use them Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 16/76] drm/amd/dal: refactor bios scratch register access Harry Wentland
` (61 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c | 607 ++++-----------------
1 file changed, 115 insertions(+), 492 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
index b4ced869c4bd..17758ab2e9fb 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
@@ -98,20 +98,10 @@ enum {
(hw_engine->regs->reg_name)
#include "reg_helper.h"
-
static void disable_i2c_hw_engine(
struct i2c_hw_engine_dce110 *hw_engine)
{
- uint32_t value = 0;
- value = REG_READ(SETUP);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_ENABLE);
-
- REG_WRITE(SETUP, value);
+ REG_UPDATE_N(SETUP, 1, FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 0);
}
static void release_engine(
@@ -121,7 +111,6 @@ static void release_engine(
struct i2c_engine *base = NULL;
bool safe_to_reset;
- uint32_t value = 0;
base = &hw_engine->base.base;
@@ -130,49 +119,23 @@ static void release_engine(
base->funcs->set_speed(base, hw_engine->base.original_speed);
/* Release I2C */
- {
- value = REG_READ(DC_I2C_ARBITRATION);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_ARBITRATION,
- DC_I2C_SW_DONE_USING_I2C_REG);
-
- REG_WRITE(DC_I2C_ARBITRATION, value);
- }
+ REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1);
/* Reset HW engine */
{
uint32_t i2c_sw_status = 0;
-
- value = REG_READ(DC_I2C_SW_STATUS);
-
- i2c_sw_status = get_reg_field_value(
- value,
- DC_I2C_SW_STATUS,
- DC_I2C_SW_STATUS);
+ REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
/* if used by SW, safe to reset */
safe_to_reset = (i2c_sw_status == 1);
}
- {
- value = REG_READ(DC_I2C_CONTROL);
if (safe_to_reset)
- set_reg_field_value(
- value,
- 1,
- DC_I2C_CONTROL,
- DC_I2C_SOFT_RESET);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_CONTROL,
- DC_I2C_SW_STATUS_RESET);
-
- REG_WRITE(DC_I2C_CONTROL, value);
- }
+ REG_UPDATE_2(
+ DC_I2C_CONTROL,
+ DC_I2C_SOFT_RESET, 1,
+ DC_I2C_SW_STATUS_RESET, 1);
+ else
+ REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
/* HW I2c engine - clock gating feature */
if (!hw_engine->engine_keep_power_up_count)
@@ -182,92 +145,32 @@ static void release_engine(
static bool setup_engine(
struct i2c_engine *i2c_engine)
{
- uint32_t value = 0;
struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine);
/* Program pin select */
- {
- value = REG_READ(DC_I2C_CONTROL);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_GO);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_SOFT_RESET);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_SEND_RESET);
-
- set_reg_field_value(
- value,
- 1,
+ REG_UPDATE_6(
DC_I2C_CONTROL,
- DC_I2C_SW_STATUS_RESET);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_TRANSACTION_COUNT);
-
- set_reg_field_value(
- value,
- hw_engine->engine_id,
- DC_I2C_CONTROL,
- DC_I2C_DDC_SELECT);
-
- REG_WRITE(DC_I2C_CONTROL, value);
- }
+ DC_I2C_GO, 0,
+ DC_I2C_SOFT_RESET, 0,
+ DC_I2C_SEND_RESET, 0,
+ DC_I2C_SW_STATUS_RESET, 1,
+ DC_I2C_TRANSACTION_COUNT, 0,
+ DC_I2C_DDC_SELECT, hw_engine->engine_id);
/* Program time limit */
- {
- value = REG_READ(SETUP);
-
- set_reg_field_value(
- value,
- I2C_SETUP_TIME_LIMIT,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_TIME_LIMIT);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_ENABLE);
-
- REG_WRITE(SETUP, value);
- }
+ REG_UPDATE_N(
+ SETUP, 2,
+ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), I2C_SETUP_TIME_LIMIT,
+ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
/* Program HW priority
* set to High - interrupt software I2C at any time
* Enable restart of SW I2C that was interrupted by HW
* disable queuing of software while I2C is in use by HW */
- {
- value = REG_READ(DC_I2C_ARBITRATION);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_ARBITRATION,
- DC_I2C_NO_QUEUED_SW_GO);
-
- set_reg_field_value(
- value,
- DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
+ REG_UPDATE_2(
DC_I2C_ARBITRATION,
- DC_I2C_SW_PRIORITY);
-
- REG_WRITE(DC_I2C_ARBITRATION, value);
- }
+ DC_I2C_NO_QUEUED_SW_GO, 0,
+ DC_I2C_SW_PRIORITY, DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL);
return true;
}
@@ -277,16 +180,13 @@ static uint32_t get_speed(
{
const struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine);
uint32_t pre_scale = 0;
- uint32_t value = REG_READ(SPEED);
- pre_scale = get_reg_field_value(
- value,
- DC_I2C_DDC1_SPEED,
- DC_I2C_DDC1_PRESCALE);
+ generic_reg_get(
+ CTX, REG(SPEED),
+ FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), &pre_scale);
/* [anaumov] it seems following is unnecessary */
/*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/
-
return pre_scale ?
hw_engine->reference_frequency / pre_scale :
hw_engine->base.default_speed;
@@ -298,58 +198,22 @@ static void set_speed(
{
struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine);
- if (speed) {
- uint32_t value = REG_READ(SPEED);
-
- set_reg_field_value(
- value,
- hw_engine->reference_frequency / speed,
- DC_I2C_DDC1_SPEED,
- DC_I2C_DDC1_PRESCALE);
-
- set_reg_field_value(
- value,
- 2,
- DC_I2C_DDC1_SPEED,
- DC_I2C_DDC1_THRESHOLD);
-
- /*DCE11, HW add 100Khz support for I2c*/
- if (speed > 50) {
- set_reg_field_value(
- value,
- 2,
- DC_I2C_DDC1_SPEED,
- DC_I2C_DDC1_START_STOP_TIMING_CNTL);
- } else {
- set_reg_field_value(
- value,
- 1,
- DC_I2C_DDC1_SPEED,
- DC_I2C_DDC1_START_STOP_TIMING_CNTL);
- }
-
- REG_WRITE(SPEED, value);
- }
+ if (speed)
+ REG_UPDATE_N(
+ SPEED, 3,
+ FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), hw_engine->reference_frequency / speed,
+ FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2,
+ FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL), speed > 50 ? 2:1);
}
static inline void reset_hw_engine(struct engine *engine)
{
struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
- uint32_t value = REG_READ(DC_I2C_CONTROL);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_CONTROL,
- DC_I2C_SOFT_RESET);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_CONTROL,
- DC_I2C_SW_STATUS_RESET);
- REG_WRITE(DC_I2C_CONTROL, value);
+ REG_UPDATE_2(
+ DC_I2C_CONTROL,
+ DC_I2C_SW_STATUS_RESET, 1,
+ DC_I2C_SW_STATUS_RESET, 1);
}
static bool is_hw_busy(struct engine *engine)
@@ -357,70 +221,34 @@ static bool is_hw_busy(struct engine *engine)
struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
uint32_t i2c_sw_status = 0;
- uint32_t value = REG_READ(DC_I2C_SW_STATUS);
-
- i2c_sw_status = get_reg_field_value(
- value,
- DC_I2C_SW_STATUS,
- DC_I2C_SW_STATUS);
-
+ REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
return false;
reset_hw_engine(engine);
- value = REG_READ(DC_I2C_SW_STATUS);
-
- i2c_sw_status = get_reg_field_value(
- value,
- DC_I2C_SW_STATUS,
- DC_I2C_SW_STATUS);
-
+ REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
}
-/*
- * @brief
- * DC_GPIO_DDC MM register offsets
- */
-static uint32_t transaction_reg_read(struct i2c_hw_engine_dce110 *hw_engine,
- uint32_t transaction_count)
-{
- switch (transaction_count) {
- case 0:
- return REG_READ(DC_I2C_TRANSACTION0);
- case 1:
- return REG_READ(DC_I2C_TRANSACTION1);
- case 2:
- return REG_READ(DC_I2C_TRANSACTION2);
- case 3:
- return REG_READ(DC_I2C_TRANSACTION3);
- default:
- return 0;
- }
-}
-static void transcation_reg_write(struct i2c_hw_engine_dce110 *hw_engine,
- uint32_t transaction_count, uint32_t value)
-{
- switch (transaction_count) {
- case 0:
- REG_WRITE(DC_I2C_TRANSACTION0, value);
- break;
- case 1:
- REG_WRITE(DC_I2C_TRANSACTION1, value);
- break;
- case 2:
- REG_WRITE(DC_I2C_TRANSACTION2, value);
- break;
- case 3:
- REG_WRITE(DC_I2C_TRANSACTION3, value);
- break;
+#define STOP_TRANS_PREDICAT \
+ ((hw_engine->transaction_count == 3) || \
+ (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) || \
+ (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ))
+
+#define SET_I2C_TRANSACTION(id) \
+ do { \
+ REG_UPDATE_N(DC_I2C_TRANSACTION##id, 5, \
+ FN(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0), 1, \
+ FN(DC_I2C_TRANSACTION0, DC_I2C_START0), 1, \
+ FN(DC_I2C_TRANSACTION0, DC_I2C_STOP0), STOP_TRANS_PREDICAT ? 1:0, \
+ FN(DC_I2C_TRANSACTION0, DC_I2C_RW0), (0 != (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)), \
+ FN(DC_I2C_TRANSACTION0, DC_I2C_COUNT0), length); \
+ if (STOP_TRANS_PREDICAT) \
+ last_transaction = true; \
+ } while (false)
- default:
- break;
- }
-}
static bool process_transaction(
struct i2c_hw_engine_dce110 *hw_engine,
@@ -430,125 +258,61 @@ static bool process_transaction(
uint8_t *buffer = request->data;
bool last_transaction = false;
- uint32_t value = 0;
struct dc_context *ctx = NULL;
ctx = hw_engine->base.base.base.ctx;
- {
- value = transaction_reg_read(hw_engine, hw_engine->transaction_count);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_TRANSACTION0,
- DC_I2C_STOP_ON_NACK0);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_TRANSACTION0,
- DC_I2C_START0);
- if ((hw_engine->transaction_count == 3) ||
- (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
- (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_TRANSACTION0,
- DC_I2C_STOP0);
- last_transaction = true;
- } else
- set_reg_field_value(
- value,
- 0,
- DC_I2C_TRANSACTION0,
- DC_I2C_STOP0);
-
- set_reg_field_value(
- value,
- (0 != (request->action &
- I2CAUX_TRANSACTION_ACTION_I2C_READ)),
- DC_I2C_TRANSACTION0,
- DC_I2C_RW0);
-
- set_reg_field_value(
- value,
- length,
- DC_I2C_TRANSACTION0,
- DC_I2C_COUNT0);
-
- transcation_reg_write(hw_engine, hw_engine->transaction_count, value);
+ switch (hw_engine->transaction_count) {
+ case 0:
+ SET_I2C_TRANSACTION(0);
+ break;
+ case 1:
+ SET_I2C_TRANSACTION(1);
+ break;
+ case 2:
+ SET_I2C_TRANSACTION(2);
+ break;
+ case 3:
+ SET_I2C_TRANSACTION(3);
+ break;
+ default:
+ /* TODO Warning ? */
+ break;
}
+
/* Write the I2C address and I2C data
* into the hardware circular buffer, one byte per entry.
* As an example, the 7-bit I2C slave address for CRT monitor
* for reading DDC/EDID information is 0b1010001.
* For an I2C send operation, the LSB must be programmed to 0;
* for I2C receive operation, the LSB must be programmed to 1. */
-
- {
- value = 0;
-
- set_reg_field_value(
- value,
- false,
- DC_I2C_DATA,
- DC_I2C_DATA_RW);
-
- set_reg_field_value(
- value,
- request->address,
- DC_I2C_DATA,
- DC_I2C_DATA);
-
- if (hw_engine->transaction_count == 0) {
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DATA,
- DC_I2C_INDEX);
-
- /*enable index write*/
- set_reg_field_value(
- value,
- 1,
- DC_I2C_DATA,
- DC_I2C_INDEX_WRITE);
-
- hw_engine->buffer_used_write = 0;
- }
-
- REG_WRITE(DC_I2C_DATA, value);
-
- hw_engine->buffer_used_write++;
-
- if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DATA,
- DC_I2C_INDEX_WRITE);
-
- while (length) {
-
- set_reg_field_value(
- value,
- *buffer++,
- DC_I2C_DATA,
- DC_I2C_DATA);
-
- REG_WRITE(DC_I2C_DATA, value);
-
- hw_engine->buffer_used_write++;
- --length;
- }
+ if (hw_engine->transaction_count == 0) {
+ REG_SET_4(DC_I2C_DATA, 0,
+ DC_I2C_DATA_RW, false,
+ DC_I2C_DATA, request->address,
+ DC_I2C_INDEX, 0,
+ DC_I2C_INDEX_WRITE, 1);
+ hw_engine->buffer_used_write = 0;
+ } else
+ REG_SET_2(DC_I2C_DATA, 0,
+ DC_I2C_DATA_RW, false,
+ DC_I2C_DATA, request->address);
+
+ hw_engine->buffer_used_write++;
+
+ if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
+ while (length) {
+
+ REG_UPDATE_2(DC_I2C_DATA,
+ DC_I2C_INDEX_WRITE, 0,
+ DC_I2C_DATA, *buffer++);
+
+ hw_engine->buffer_used_write++;
+ --length;
}
}
@@ -561,92 +325,23 @@ static bool process_transaction(
static void execute_transaction(
struct i2c_hw_engine_dce110 *hw_engine)
{
- uint32_t value = 0;
-
- {
- value = REG_READ(SETUP);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_DATA_DRIVE_EN);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_CLK_DRIVE_EN);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_DATA_DRIVE_SEL);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_INTRA_TRANSACTION_DELAY);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_INTRA_BYTE_DELAY);
-
- REG_WRITE(SETUP, value);
- }
-
- {
- value = REG_READ(DC_I2C_CONTROL);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_SOFT_RESET);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_SW_STATUS_RESET);
+ REG_UPDATE_N(SETUP, 5,
+ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN), 0,
+ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN), 0,
+ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL), 0,
+ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY), 0,
+ FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY), 0);
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_SEND_RESET);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_GO);
-
- set_reg_field_value(
- value,
- hw_engine->transaction_count - 1,
- DC_I2C_CONTROL,
- DC_I2C_TRANSACTION_COUNT);
- REG_WRITE(DC_I2C_CONTROL, value);
- }
+ REG_UPDATE_5(DC_I2C_CONTROL,
+ DC_I2C_SOFT_RESET, 0,
+ DC_I2C_SW_STATUS_RESET, 0,
+ DC_I2C_SEND_RESET, 0,
+ DC_I2C_GO, 0,
+ DC_I2C_TRANSACTION_COUNT, hw_engine->transaction_count - 1);
/* start I2C transfer */
- {
- value = REG_READ(DC_I2C_CONTROL);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_CONTROL,
- DC_I2C_GO);
-
- REG_WRITE(DC_I2C_CONTROL, value);
- }
+ REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1);
/* all transactions were executed and HW buffer became empty
* (even though it actually happens when status becomes DONE) */
@@ -681,28 +376,11 @@ static void process_channel_reply(
struct i2c_hw_engine_dce110 *hw_engine =
FROM_I2C_ENGINE(engine);
- uint32_t value = 0;
-
- /*set index*/
- set_reg_field_value(
- value,
- hw_engine->buffer_used_write,
- DC_I2C_DATA,
- DC_I2C_INDEX);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_DATA,
- DC_I2C_DATA_RW);
- set_reg_field_value(
- value,
- 1,
- DC_I2C_DATA,
- DC_I2C_INDEX_WRITE);
-
- REG_WRITE(DC_I2C_DATA, value);
+ REG_SET_3(DC_I2C_DATA, 0,
+ DC_I2C_INDEX, hw_engine->buffer_used_write,
+ DC_I2C_DATA_RW, 1,
+ DC_I2C_INDEX_WRITE, 1);
while (length) {
/* after reading the status,
@@ -710,7 +388,7 @@ static void process_channel_reply(
* (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
* should read data bytes from I2C circular data buffer */
- value = REG_READ(DC_I2C_DATA);
+ uint32_t value = REG_READ(DC_I2C_DATA);
*buffer++ = get_reg_field_value(
value,
@@ -727,12 +405,8 @@ static enum i2c_channel_operation_result get_channel_status(
{
uint32_t i2c_sw_status = 0;
struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine);
- uint32_t value = REG_READ(DC_I2C_SW_STATUS);
-
- i2c_sw_status = get_reg_field_value(
- value,
- DC_I2C_SW_STATUS,
- DC_I2C_SW_STATUS);
+ uint32_t value =
+ REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
@@ -793,40 +467,6 @@ static void destroy(
*i2c_engine = NULL;
}
-/*
- * @brief
- * DC_I2C_DDC1_SETUP MM register offsets
- *
- * @note
- * The indices of this offset array are DDC engine IDs
- */
-static const int32_t ddc_setup_offset[] = {
-
- mmDC_I2C_DDC1_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 1 */
- mmDC_I2C_DDC2_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 2 */
- mmDC_I2C_DDC3_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 3 */
- mmDC_I2C_DDC4_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 4 */
- mmDC_I2C_DDC5_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 5 */
- mmDC_I2C_DDC6_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 6 */
- mmDC_I2C_DDCVGA_SETUP - mmDC_I2C_DDC1_SETUP /* DDC Engine 7 */
-};
-
-/*
- * @brief
- * DC_I2C_DDC1_SPEED MM register offsets
- *
- * @note
- * The indices of this offset array are DDC engine IDs
- */
-static const int32_t ddc_speed_offset[] = {
- mmDC_I2C_DDC1_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 1 */
- mmDC_I2C_DDC2_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 2 */
- mmDC_I2C_DDC3_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 3 */
- mmDC_I2C_DDC4_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 4 */
- mmDC_I2C_DDC5_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 5 */
- mmDC_I2C_DDC6_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 6 */
- mmDC_I2C_DDCVGA_SPEED - mmDC_I2C_DDC1_SPEED /* DDC Engine 7 */
-};
static const struct i2c_engine_funcs i2c_engine_funcs = {
.destroy = destroy,
@@ -857,14 +497,7 @@ bool i2c_hw_engine_dce110_construct(
const struct i2c_hw_engine_dce110_create_arg *arg)
{
uint32_t xtal_ref_div = 0;
- uint32_t value = 0;
- /*ddc_setup_offset of dce80 and dce110 have the same register name
- * but different offset. Do not need different array*/
- if (arg->engine_id >= sizeof(ddc_setup_offset) / sizeof(int32_t))
- return false;
- if (arg->engine_id >= sizeof(ddc_speed_offset) / sizeof(int32_t))
- return false;
if (!arg->reference_frequency)
return false;
@@ -884,18 +517,8 @@ bool i2c_hw_engine_dce110_construct(
hw_engine->transaction_count = 0;
hw_engine->engine_keep_power_up_count = 1;
- /*values which are not included by arg*/
- hw_engine->addr.DC_I2C_DDCX_SETUP =
- mmDC_I2C_DDC1_SETUP + ddc_setup_offset[arg->engine_id];
- hw_engine->addr.DC_I2C_DDCX_SPEED =
- mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];
-
- value = REG_READ(MICROSECOND_TIME_BASE_DIV);
- xtal_ref_div = get_reg_field_value(
- value,
- MICROSECOND_TIME_BASE_DIV,
- XTAL_REF_DIV);
+ REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
if (xtal_ref_div == 0) {
dm_logger_write(
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 16/76] drm/amd/dal: refactor bios scratch register access
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (14 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 15/76] drm/amd/dal: Modify regsiter access to use macro Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 17/76] drm/amd/dal: Remove adapter service from display clock Harry Wentland
` (60 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- offset of scratch register stored in dc_bios and assigned by resource.
- common code to set various of bits to communicate with bios.
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/bios/Makefile | 6 --
drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 14 +--
.../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c | 65 +++++++-----
.../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h | 26 +----
.../gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h | 6 --
.../dal/dc/bios/dce110/bios_parser_helper_dce110.c | 118 ---------------------
.../dal/dc/bios/dce110/bios_parser_helper_dce110.h | 34 ------
.../dal/dc/bios/dce112/bios_parser_helper_dce112.c | 81 --------------
.../dal/dc/bios/dce112/bios_parser_helper_dce112.h | 34 ------
.../dal/dc/bios/dce80/bios_parser_helper_dce80.c | 67 ------------
.../dal/dc/bios/dce80/bios_parser_helper_dce80.h | 33 ------
drivers/gpu/drm/amd/dal/dc/dc_bios_types.h | 5 +
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 7 ++
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 4 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 6 ++
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 7 ++
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 7 ++
17 files changed, 80 insertions(+), 440 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.h
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/Makefile b/drivers/gpu/drm/amd/dal/dc/bios/Makefile
index 328215a1c00b..20480d6e2a02 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/bios/Makefile
@@ -13,18 +13,12 @@ AMD_DAL_FILES += $(AMD_DAL_BIOS)
###############################################################################
# All DCE8.x are derived from DCE8.0, so 8.0 MUST be defined if ANY of
# DCE8.x is compiled.
-AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce80/bios_parser_helper_dce80.o
-
AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce80/command_table_helper_dce80.o
###############################################################################
# DCE 11x
###############################################################################
-AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce110/bios_parser_helper_dce110.o
-
AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o
ccflags-y += -DLATEST_ATOM_BIOS_SUPPORT
-AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce112/bios_parser_helper_dce112.o
-
AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper_dce112.o
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
index 1080c6c5527b..79669d9516cb 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
@@ -37,7 +37,6 @@
#include "command_table.h"
#include "bios_parser_helper.h"
-#include "dce110/bios_dce110.h"
#include "command_table_helper.h"
#include "bios_parser.h"
#include "bios_parser_types_internal.h"
@@ -3667,10 +3666,7 @@ static void bios_parser_post_init(struct dc_bios *dcb,
static bool bios_parser_is_accelerated_mode(
struct dc_bios *dcb)
{
- struct bios_parser *bp = BP_FROM_DCB(dcb);
-
- return bp->bios_helper->is_accelerated_mode(
- bp->base.ctx);
+ bios_is_accelerated_mode(dcb);
}
/**
@@ -3686,10 +3682,7 @@ static void bios_parser_set_scratch_critical_state(
struct dc_bios *dcb,
bool state)
{
- struct bios_parser *bp = BP_FROM_DCB(dcb);
-
- dce110_set_scratch_critical_state(
- bp->base.ctx, state);
+ bios_set_scratch_critical_state(dcb, state);
}
/*
@@ -4127,7 +4120,7 @@ static const struct dc_vbios_funcs vbios_funcs = {
.get_encoder_cap_info = bios_parser_get_encoder_cap_info,
/* bios scratch register communication */
- .is_accelerated_mode = bios_parser_is_accelerated_mode,
+ .is_accelerated_mode = bios_is_accelerated_mode,
.set_scratch_critical_state = bios_parser_set_scratch_critical_state,
@@ -4243,7 +4236,6 @@ static bool bios_parser_construct(
else
return false;
- dal_bios_parser_init_bios_helper(bp, dce_version);
dal_bios_parser_init_cmd_tbl(bp);
dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version);
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
index 15d57badd716..8e56d2f25dea 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c
@@ -33,33 +33,6 @@
#include "command_table.h"
#include "bios_parser_types_internal.h"
-bool dal_bios_parser_init_bios_helper(
- struct bios_parser *bp,
- enum dce_version version)
-{
- switch (version) {
- case DCE_VERSION_8_0:
- bp->bios_helper = dal_bios_parser_helper_dce80_get_table();
- return true;
- case DCE_VERSION_10_0:
- bp->bios_helper = dal_bios_parser_helper_dce110_get_table();
- return true;
-
- case DCE_VERSION_11_0:
- bp->bios_helper = dal_bios_parser_helper_dce110_get_table();
- return true;
-
- case DCE_VERSION_11_2:
- bp->bios_helper = dal_bios_parser_helper_dce112_get_table();
- return true;
-
- default:
- BREAK_TO_DEBUGGER();
- return false;
- }
-}
-
-
uint8_t *get_image(struct dc_bios *bp,
uint32_t offset,
uint32_t size)
@@ -69,3 +42,41 @@ uint8_t *get_image(struct dc_bios *bp,
else
return NULL;
}
+
+#include "reg_helper.h"
+
+#define CTX \
+ bios->ctx
+#define REG(reg)\
+ (bios->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+ ATOM_ ## field_name ## _SHIFT, ATOM_ ## field_name
+
+bool bios_is_accelerated_mode(
+ struct dc_bios *bios)
+{
+ uint32_t acc_mode;
+ REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode);
+ return (acc_mode == 1);
+}
+
+
+void bios_set_scratch_acc_mode_change(
+ struct dc_bios *bios)
+{
+ REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, 1);
+}
+
+
+void bios_set_scratch_critical_state(
+ struct dc_bios *bios,
+ bool state)
+{
+ uint32_t critial_state = state ? 1 : 0;
+ REG_UPDATE(BIOS_SCRATCH_6, S6_CRITICAL_STATE, critial_state);
+}
+
+
+
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
index 3b70a123f3f3..a8fbb82b8c8e 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2012-16 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -26,31 +26,15 @@
#ifndef __DAL_BIOS_PARSER_HELPER_H__
#define __DAL_BIOS_PARSER_HELPER_H__
-#include "dce80/bios_parser_helper_dce80.h"
-
-#include "dce110/bios_parser_helper_dce110.h"
-
-#include "dce112/bios_parser_helper_dce112.h"
-
struct bios_parser;
-struct bios_parser_helper {
- bool (*is_accelerated_mode)(
- struct dc_context *ctx);
-};
-
-bool dal_bios_parser_init_bios_helper(
- struct bios_parser *bp,
- enum dce_version ver);
-
-
uint8_t *get_image(struct dc_bios *bp, uint32_t offset,
uint32_t size);
-#define GET_IMAGE(type, offset) ((type *) get_image(&bp->base, offset, sizeof(type)))
-
-
-
+bool bios_is_accelerated_mode(struct dc_bios *bios);
+void bios_set_scratch_acc_mode_change(struct dc_bios *bios);
+void bios_set_scratch_critical_state(struct dc_bios *bios, bool state);
+#define GET_IMAGE(type, offset) ((type *) get_image(&bp->base, offset, sizeof(type)))
#endif
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h
deleted file mode 100644
index fd8629603aa6..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_dce110.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef BIOS_DCE110_H
-#define BIOS_DCE110_H
-void dce110_set_scratch_critical_state(struct dc_context *ctx,
- bool state);
-void dce110_set_scratch_acc_mode_change(struct dc_context *ctx);
-#endif
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
deleted file mode 100644
index 5b7c13f59b8c..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "atom.h"
-
-#include "include/bios_parser_types.h"
-#include "include/adapter_service_types.h"
-#include "include/logger_interface.h"
-
-#include "../bios_parser_helper.h"
-
-#include "dce/dce_11_0_d.h"
-#include "bif/bif_5_1_d.h"
-
-/**
- * set_scratch_acc_mode_change
- *
- * @brief
- * set Accelerated Mode in VBIOS scratch register, VBIOS will clean it when
- * VGA/non-Accelerated mode is set
- *
- * @param
- * struct dc_context *ctx - [in] DAL context
- */
-void dce110_set_scratch_acc_mode_change(struct dc_context *ctx)
-{
- uint32_t addr = mmBIOS_SCRATCH_6;
- uint32_t value = 0;
-
- value = dm_read_reg(ctx, addr);
-
- value |= ATOM_S6_ACC_MODE;
-
- dm_write_reg(ctx, addr, value);
-}
-
-/*
- * is_accelerated_mode
- *
- * @brief
- * set Accelerated Mode in VBIOS scratch register, VBIOS will clean it when
- * VGA/non-Accelerated mode is set
- *
- * @param
- * struct dc_context *ctx
- *
- * @return
- * true if in acceleration mode, false otherwise.
- */
-static bool is_accelerated_mode(
- struct dc_context *ctx)
-{
- uint32_t addr = mmBIOS_SCRATCH_6;
- uint32_t value = dm_read_reg(ctx, addr);
-
- return (value & ATOM_S6_ACC_MODE) ? true : false;
-}
-
-#define BIOS_SCRATCH0_DAC_B_SHIFT 8
-
-void dce110_set_scratch_critical_state(struct dc_context *ctx,
- bool state)
-{
- uint32_t addr = mmBIOS_SCRATCH_6;
- uint32_t value = dm_read_reg(ctx, addr);
-
- if (state)
- value |= ATOM_S6_CRITICAL_STATE;
- else
- value &= ~ATOM_S6_CRITICAL_STATE;
-
- dm_write_reg(ctx, addr, value);
-}
-
-/* function table */
-static const struct bios_parser_helper bios_parser_helper_funcs = {
- .is_accelerated_mode = is_accelerated_mode,
-};
-
-/*
- * dal_bios_parser_dce110_init_bios_helper
- *
- * @brief
- * Initialize BIOS helper functions
- *
- * @param
- * const struct command_table_helper **h - [out] struct of functions
- *
- */
-
-const struct bios_parser_helper *dal_bios_parser_helper_dce110_get_table()
-{
- return &bios_parser_helper_funcs;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.h b/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.h
deleted file mode 100644
index 915f31ab9c1a..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_BIOS_PARSER_HELPER_DCE110_H__
-#define __DAL_BIOS_PARSER_HELPER_DCE110_H__
-
-struct bios_parser_helper;
-
-/* Initialize BIOS helper functions */
-const struct bios_parser_helper *dal_bios_parser_helper_dce110_get_table(void);
-
-#endif /* __DAL_BIOS_PARSER_HELPER_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c b/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c
deleted file mode 100644
index 0e3b1e6525bc..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "atom.h"
-
-#include "include/bios_parser_types.h"
-#include "include/adapter_service_types.h"
-#include "include/logger_interface.h"
-
-#include "../bios_parser_helper.h"
-
-#include "dce/dce_11_0_d.h"
-#include "bif/bif_5_1_d.h"
-
-
-/*
- * is_accelerated_mode
- *
- * @brief
- * set Accelerated Mode in VBIOS scratch register, VBIOS will clean it when
- * VGA/non-Accelerated mode is set
- *
- * @param
- * struct dc_context *ctx
- *
- * @return
- * true if in acceleration mode, false otherwise.
- */
-static bool is_accelerated_mode(
- struct dc_context *ctx)
-{
- uint32_t addr = mmBIOS_SCRATCH_6;
- uint32_t value = dm_read_reg(ctx, addr);
-
- return (value & ATOM_S6_ACC_MODE) ? true : false;
-}
-
-/* function table */
-static const struct bios_parser_helper bios_parser_helper_funcs = {
- .is_accelerated_mode = is_accelerated_mode,
-};
-
-/*
- * dal_bios_parser_dce112_init_bios_helper
- *
- * @brief
- * Initialize BIOS helper functions
- *
- * @param
- * const struct command_table_helper **h - [out] struct of functions
- *
- */
-
-const struct bios_parser_helper *dal_bios_parser_helper_dce112_get_table()
-{
- return &bios_parser_helper_funcs;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.h b/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.h
deleted file mode 100644
index 044327ea250b..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/bios/dce112/bios_parser_helper_dce112.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_BIOS_PARSER_HELPER_DCE112_H__
-#define __DAL_BIOS_PARSER_HELPER_DCE112_H__
-
-struct bios_parser_helper;
-
-/* Initialize BIOS helper functions */
-const struct bios_parser_helper *dal_bios_parser_helper_dce112_get_table(void);
-
-#endif /* __DAL_BIOS_PARSER_HELPER_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
deleted file mode 100644
index a919e626d4ec..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "atom.h"
-
-#include "dce/dce_8_0_d.h"
-#include "bif/bif_4_1_d.h"
-
-#include "include/grph_object_id.h"
-#include "include/grph_object_defs.h"
-#include "include/grph_object_ctrl_defs.h"
-#include "include/bios_parser_types.h"
-#include "include/adapter_service_types.h"
-
-#include "../bios_parser_helper.h"
-
-/**
- * is_accelerated_mode
- *
- * @brief
- * set Accelerated Mode in VBIOS scratch register, VBIOS will clean it when
- * VGA/non-Accelerated mode is set
- *
- * @param
- * NONE
- */
-static bool is_accelerated_mode(
- struct dc_context *ctx)
-{
- uint32_t addr = mmBIOS_SCRATCH_6;
- uint32_t value = dm_read_reg(ctx, addr);
-
- return (value & ATOM_S6_ACC_MODE) ? true : false;
-}
-
-static const struct bios_parser_helper bios_parser_helper_funcs = {
- .is_accelerated_mode = is_accelerated_mode,
-};
-
-const struct bios_parser_helper *dal_bios_parser_helper_dce80_get_table()
-{
- return &bios_parser_helper_funcs;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.h b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.h
deleted file mode 100644
index db671be8025d..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_BIOS_PARSER_HELPER_DCE80_H__
-#define __DAL_BIOS_PARSER_HELPER_DCE80_H__
-
-struct bios_parser_helper;
-
-const struct bios_parser_helper *dal_bios_parser_helper_dce80_get_table(void);
-
-#endif
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
index 3d2efa8d2bde..2d598d004281 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
@@ -212,6 +212,10 @@ struct dc_vbios_funcs {
void (*bios_parser_destroy)(struct dc_bios **dcb);
};
+struct bios_registers {
+ uint32_t BIOS_SCRATCH_6;
+};
+
struct dc_bios {
const struct dc_vbios_funcs *funcs;
@@ -221,6 +225,7 @@ struct dc_bios {
uint8_t *bios_local_image;
struct dc_context *ctx;
+ const struct bios_registers *regs;
};
#endif /* DC_BIOS_TYPES_H */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index ea7e12d8a1e4..c8c83e86eb53 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -66,6 +66,7 @@
#ifndef mmBIOS_SCRATCH_2
#define mmBIOS_SCRATCH_2 0x05CB
+ #define mmBIOS_SCRATCH_6 0x05CF
#endif
#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
@@ -358,6 +359,10 @@ static const struct dce110_opp_reg_offsets dce100_opp_reg_offsets[] = {
}
};
+static const struct bios_registers bios_regs = {
+ .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
+};
+
static const struct resource_caps res_cap = {
.num_timing_generator = 6,
.num_audio = 6,
@@ -859,6 +864,8 @@ static bool construct(
struct dc_bios *bp;
struct dm_pp_static_clock_info static_clk_info = {0};
+ ctx->dc_bios->regs = &bios_regs;
+
pool->base.adapter_srv = as;
pool->base.res_cap = &res_cap;
pool->base.funcs = &dce100_res_pool_funcs;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index f010a785c4e2..4181a2207dc4 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -35,7 +35,7 @@
#include "gpu/dce110/dc_clock_gating_dce110.h"
-#include "bios/dce110/bios_dce110.h"
+#include "bios/bios_parser_helper.h"
#include "timing_generator.h"
#include "mem_input.h"
#include "opp.h"
@@ -975,7 +975,7 @@ void dce110_enable_accelerated_mode(struct core_dc *dc)
power_down_all_hw_blocks(dc);
disable_vga_and_power_gate_all_controllers(dc);
- dce110_set_scratch_acc_mode_change(dc->ctx);
+ bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
}
/**
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 0404122cf31e..82cdcb5c2eb1 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -69,6 +69,7 @@
#ifndef mmBIOS_SCRATCH_2
#define mmBIOS_SCRATCH_2 0x05CB
+ #define mmBIOS_SCRATCH_6 0x05CF
#endif
#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
@@ -325,6 +326,9 @@ static const struct dce110_clk_src_reg_offsets dce110_clk_src_reg_offsets[] = {
}
};
+static const struct bios_registers bios_regs = {
+ .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
+};
static const struct resource_caps carrizo_resource_cap = {
.num_timing_generator = 3,
@@ -1179,6 +1183,8 @@ static bool construct(
struct dm_pp_static_clock_info static_clk_info = {0};
struct resource_straps straps = {0};
+ ctx->dc_bios->regs = &bios_regs;
+
pool->base.adapter_srv = as;
pool->base.res_cap = dce110_resource_cap(&dc->asic_id);
pool->base.funcs = &dce110_res_pool_funcs;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 8588a94e0fc5..5d53a0b9e8e1 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -66,6 +66,7 @@
#ifndef mmBIOS_SCRATCH_2
#define mmBIOS_SCRATCH_2 0x05CB
+ #define mmBIOS_SCRATCH_6 0x05CF
#endif
#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
@@ -375,6 +376,10 @@ static const struct dce112_clk_src_reg_offsets dce112_clk_src_reg_offsets[] = {
}
};
+static const struct bios_registers bios_regs = {
+ .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
+};
+
static const struct resource_caps polaris_10_resource_cap = {
.num_timing_generator = 6,
.num_audio = 6,
@@ -1187,6 +1192,8 @@ static bool construct(
struct dc_context *ctx = dc->ctx;
struct dm_pp_static_clock_info static_clk_info = {0};
+ ctx->dc_bios->regs = &bios_regs;
+
pool->base.adapter_srv = adapter_serv;
pool->base.res_cap = dce112_resource_cap(&dc->asic_id);
pool->base.funcs = &dce112_res_pool_funcs;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index 0023ed344467..705c69a8a5c4 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -69,6 +69,7 @@
#ifndef mmBIOS_SCRATCH_2
#define mmBIOS_SCRATCH_2 0x05CB
+ #define mmBIOS_SCRATCH_6 0x05CF
#endif
#ifndef mmDP_DPHY_FAST_TRAINING
@@ -349,6 +350,10 @@ static const struct dce110_clk_src_reg_offsets dce80_clk_src_reg_offsets[] = {
}
};
+static const struct bios_registers bios_regs = {
+ .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
+};
+
static const struct resource_caps res_cap = {
.num_timing_generator = 6,
.num_audio = 6,
@@ -853,6 +858,8 @@ static bool construct(
struct dc_bios *bp;
struct dm_pp_static_clock_info static_clk_info = {0};
+ ctx->dc_bios->regs = &bios_regs;
+
pool->base.adapter_srv = as;
pool->base.res_cap = &res_cap;
pool->base.funcs = &dce80_res_pool_funcs;
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 17/76] drm/amd/dal: Remove adapter service from display clock
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (15 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 16/76] drm/amd/dal: refactor bios scratch register access Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 18/76] drm/amd/dal: Use future proof reg access for HPD and DDC Harry Wentland
` (59 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zeyu Fan
From: Zeyu Fan <Zeyu.Fan@amd.com>
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../amd/dal/dc/gpu/dce110/display_clock_dce110.c | 2 +-
.../amd/dal/dc/gpu/dce112/display_clock_dce112.c | 35 ++++++++--------------
.../amd/dal/dc/gpu/dce112/display_clock_dce112.h | 3 +-
.../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c | 2 +-
drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c | 4 +--
drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h | 3 +-
6 files changed, 18 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
index 024972ee0242..d422294715ce 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
@@ -929,7 +929,7 @@ static bool dal_display_clock_dce110_construct(
if (NULL == as)
return false;
- if (!dal_display_clock_construct_base(dc_base, ctx, as))
+ if (!dal_display_clock_construct_base(dc_base, ctx))
return false;
dc_base->funcs = &funcs;
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
index 73f30ddf2d52..f94da476c9a5 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
@@ -644,8 +644,7 @@ uint32_t dispclk_dce112_calculate_min_clock(
}
static bool display_clock_integrated_info_construct(
- struct display_clock_dce112 *disp_clk,
- struct adapter_service *as)
+ struct display_clock_dce112 *disp_clk)
{
struct integrated_info info;
uint32_t i;
@@ -696,11 +695,6 @@ static bool display_clock_integrated_info_construct(
info.disp_clk_voltage[i].max_supported_clk;
}
}
- disp_clk->dfs_bypass_enabled =
- dal_adapter_service_is_dfs_bypass_enabled(as);
- disp_clk->use_max_disp_clk =
- dal_adapter_service_is_feature_supported(as,
- FEATURE_USE_MAX_DISPLAY_CLK);
return true;
}
@@ -847,23 +841,22 @@ static const struct display_clock_funcs funcs = {
bool dal_display_clock_dce112_construct(
struct display_clock_dce112 *dc112,
- struct dc_context *ctx,
- struct adapter_service *as)
+ struct dc_context *ctx)
{
struct dm_pp_static_clock_info *static_clk_info = {0};
struct display_clock *dc_base = &dc112->disp_clk_base;
- if (NULL == as)
- return false;
+ /*if (NULL == as)
+ return false;*/
- if (!dal_display_clock_construct_base(dc_base, ctx, as))
+ if (!dal_display_clock_construct_base(dc_base, ctx))
return false;
dc_base->funcs = &funcs;
dc112->dfs_bypass_disp_clk = 0;
- if (!display_clock_integrated_info_construct(dc112, as))
+ if (!display_clock_integrated_info_construct(dc112))
dm_logger_write(dc_base->ctx->logger, LOG_WARNING,
"Cannot obtain VBIOS integrated info\n");
@@ -907,9 +900,8 @@ bool dal_display_clock_dce112_construct(
{
uint32_t ss_info_num =
- dal_adapter_service_get_ss_info_num(
- as,
- AS_SIGNAL_TYPE_GPU_PLL);
+ ctx->dc_bios->funcs->
+ get_ss_entry_number(ctx->dc_bios, AS_SIGNAL_TYPE_GPU_PLL);
if (ss_info_num) {
struct spread_spectrum_info info;
@@ -918,11 +910,10 @@ bool dal_display_clock_dce112_construct(
memset(&info, 0, sizeof(info));
result =
- dal_adapter_service_get_ss_info(
- as,
- AS_SIGNAL_TYPE_GPU_PLL,
- 0,
- &info);
+ (BP_RESULT_OK == ctx->dc_bios->funcs->
+ get_spread_spectrum_info(ctx->dc_bios,
+ AS_SIGNAL_TYPE_GPU_PLL, 0, &info)) ? true : false;
+
/* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
* even if SS not enabled and in that case
@@ -967,7 +958,7 @@ struct display_clock *dal_display_clock_dce112_create(
if (dc112 == NULL)
return NULL;
- if (dal_display_clock_dce112_construct(dc112, ctx, as))
+ if (dal_display_clock_dce112_construct(dc112, ctx))
return &dc112->disp_clk_base;
dm_free(dc112);
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.h
index 88b9214bd1b8..937e17929b7c 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.h
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.h
@@ -71,8 +71,7 @@ enum divider_range_start {
bool dal_display_clock_dce112_construct(
struct display_clock_dce112 *dc112,
- struct dc_context *ctx,
- struct adapter_service *as);
+ struct dc_context *ctx);
void dispclk_dce112_destroy(struct display_clock **base);
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
index 6c5c656c0166..e37b397bbd9f 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
@@ -860,7 +860,7 @@ static bool display_clock_construct(
if (NULL == as)
return false;
- if (!dal_display_clock_construct_base(dc_base, ctx, as))
+ if (!dal_display_clock_construct_base(dc_base, ctx))
return false;
dc_base->funcs = &funcs;
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
index 47734e551c2f..08586fb3d18a 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
@@ -56,13 +56,11 @@ uint32_t dal_display_clock_base_get_dfs_bypass_threshold(
bool dal_display_clock_construct_base(
struct display_clock *base,
- struct dc_context *ctx,
- struct adapter_service *as)
+ struct dc_context *ctx)
{
base->ctx = ctx;
base->id = CLOCK_SOURCE_ID_DCPLL;
base->min_display_clk_threshold_khz = 0;
- base->as = as;
/* Initially set current min clocks state to invalid since we
* cannot make any assumption about PPLIB's initial state. This will be updated
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h
index 52662b3919b1..18b79fd3fcb8 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h
@@ -78,8 +78,7 @@ void dal_display_clock_base_set_clock_state(struct display_clock *disp_clk,
struct display_clock_state clk_state);
bool dal_display_clock_construct_base(
struct display_clock *base,
- struct dc_context *ctx,
- struct adapter_service *as);
+ struct dc_context *ctx);
uint32_t dal_display_clock_get_validation_clock(struct display_clock *disp_clk);
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 18/76] drm/amd/dal: Use future proof reg access for HPD and DDC
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (16 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 17/76] drm/amd/dal: Remove adapter service from display clock Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 19/76] drm/amd/dal: Remove adapter service dependency from dc_link Harry Wentland
` (58 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c | 14 ++++++++++----
drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.c | 3 +++
drivers/gpu/drm/amd/dal/dc/gpio/ddc_regs.h | 8 ++++----
drivers/gpu/drm/amd/dal/dc/gpio/hpd_regs.h | 6 +++---
4 files changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
index 3ab6010f4641..20d81bca119c 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c
@@ -27,10 +27,6 @@
#include "include/gpio_types.h"
#include "../hw_factory.h"
-#include "../hw_gpio.h"
-#include "../hw_ddc.h"
-#include "../hw_hpd.h"
-
#include "hw_factory_dce110.h"
#include "dce/dce_11_0_d.h"
@@ -40,6 +36,16 @@
#define SF_HPD(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
+#define REG(reg_name)\
+ mm ## reg_name
+
+#define REGI(reg_name, block, id)\
+ mm ## block ## id ## _ ## reg_name
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+
#include "reg_helper.h"
#include "../hpd_regs.h"
diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.c
index 7065ba078ec7..48b67866377e 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpio/dce80/hw_factory_dce80.c
@@ -36,6 +36,9 @@
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"
+#define REG(reg_name)\
+ mm ## reg_name
+
#include "reg_helper.h"
#include "../hpd_regs.h"
diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/ddc_regs.h b/drivers/gpu/drm/amd/dal/dc/gpio/ddc_regs.h
index a3cd1c1f6daf..ddd0de0950a6 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpio/ddc_regs.h
+++ b/drivers/gpu/drm/amd/dal/dc/gpio/ddc_regs.h
@@ -32,7 +32,7 @@
/*** following in header */
#define DDC_GPIO_REG_LIST_ENTRY(type,cd,id) \
- .type ## _reg = mmDC_GPIO_DDC ## id ## _ ## type,\
+ .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\
.type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\
.type ## _shift = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## __SHIFT
@@ -46,10 +46,10 @@
#define DDC_REG_LIST(cd,id) \
DDC_GPIO_REG_LIST(cd,id),\
- .ddc_setup = mmDC_I2C_DDC ## id ## _SETUP
+ .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
#define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\
- .type ## _reg = mmDC_GPIO_DDCVGA_ ## type,\
+ .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\
.type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\
.type ## _shift = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## __SHIFT
@@ -66,7 +66,7 @@
.ddc_setup = mmDC_I2C_DDCVGA_SETUP
#define DDC_GPIO_I2C_REG_LIST_ENTRY(type,cd) \
- .type ## _reg = mmDC_GPIO_I2CPAD_ ## type,\
+ .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\
.type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\
.type ## _shift = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## __SHIFT
diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hpd_regs.h b/drivers/gpu/drm/amd/dal/dc/gpio/hpd_regs.h
index b5f9ed4cdf2e..f5cbe9ad00e6 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpio/hpd_regs.h
+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hpd_regs.h
@@ -37,7 +37,7 @@
#define HPD_GPIO_REG_LIST_ENTRY(type,cd,id) \
- .type ## _reg = mmDC_GPIO_HPD_## type,\
+ .type ## _reg = REG(DC_GPIO_HPD_## type),\
.type ## _mask = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## _MASK,\
.type ## _shift = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## __SHIFT
@@ -51,8 +51,8 @@
#define HPD_REG_LIST(id) \
HPD_GPIO_REG_LIST(ONE_MORE_ ## id), \
- .int_status = mmHPD ## id ## _DC_HPD_INT_STATUS,\
- .toggle_filt_cntl = mmHPD ## id ## _DC_HPD_TOGGLE_FILT_CNTL
+ .int_status = REGI(DC_HPD_INT_STATUS, HPD, id),\
+ .toggle_filt_cntl = REGI(DC_HPD_TOGGLE_FILT_CNTL, HPD, id)
#define HPD_MASK_SH_LIST(mask_sh) \
SF_HPD(DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED, mask_sh),\
--
2.10.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 19/76] drm/amd/dal: Remove adapter service dependency from dc_link
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (17 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 18/76] drm/amd/dal: Use future proof reg access for HPD and DDC Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 20/76] drm/amd/dal: rotation and mirror support Harry Wentland
` (57 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 14 ++++++------
drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 8 ++-----
drivers/gpu/drm/amd/dal/dc/dc_bios_types.h | 1 +
drivers/gpu/drm/amd/dal/dc/dc_types.h | 1 +
drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c | 27 ++++++++++++++---------
5 files changed, 28 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index fb902558d6a2..d86817606f39 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -945,6 +945,7 @@ static bool construct(
struct encoder_init_data enc_init_data = { 0 };
struct integrated_info info = {{{ 0 }}};
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
+ const struct dc_vbios_funcs *bp_funcs = bios->funcs;
link->public.irq_source_hpd = DC_IRQ_SOURCE_INVALID;
link->public.irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
@@ -1033,8 +1034,7 @@ static bool construct(
enc_init_data.adapter_service = as;
enc_init_data.ctx = dc_ctx;
- enc_init_data.encoder = dal_adapter_service_get_src_obj(
- as, link->link_id, 0);
+ bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
enc_init_data.connector = link->link_id;
enc_init_data.channel = get_ddc_line(link, as);
enc_init_data.hpd_source = get_hpd_line(link, as);
@@ -1050,11 +1050,12 @@ static bool construct(
link->public.link_enc_hw_inst = link->link_enc->transmitter;
- dal_adapter_service_get_integrated_info(as, &info);
+ /* TODO: refactor dal_adapter_service_get_integrated_info(as, &info); */
+ memmove(&info, dc_ctx->dc_bios->integrated_info, sizeof(struct integrated_info));
for (i = 0; ; i++) {
- if (!dal_adapter_service_get_device_tag(
- as, link->link_id, i, &link->device_tag)) {
+ if (BP_RESULT_OK !=
+ bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
DC_ERROR("Failed to find device tag!\n");
goto device_tag_fail;
}
@@ -1062,8 +1063,7 @@ static bool construct(
/* Look for device tag that matches connector signal,
* CRT for rgb, LCD for other supported signal tyes
*/
- if (!dal_adapter_service_is_device_id_supported(
- as, link->device_tag.dev_id))
+ if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
continue;
if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
&& link->public.connector_signal != SIGNAL_TYPE_RGB)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
index fd60a4c6d2a3..cc4c238ed0a6 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
@@ -304,13 +304,9 @@ static bool construct(
ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
- ddc_service->flags.FORCE_READ_REPEATED_START =
- dal_adapter_service_is_feature_supported(ddc_service->as,
- FEATURE_DDC_READ_FORCE_REPEATED_START);
+ ddc_service->flags.FORCE_READ_REPEATED_START = false;
- ddc_service->flags.EDID_STRESS_READ =
- dal_adapter_service_is_feature_supported(ddc_service->as,
- FEATURE_EDID_STRESS_READ);
+ ddc_service->flags.EDID_STRESS_READ = false;
ddc_service->flags.IS_INTERNAL_DISPLAY =
connector_id == CONNECTOR_ID_EDP ||
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
index 2d598d004281..7c1f9d817f9c 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
@@ -226,6 +226,7 @@ struct dc_bios {
struct dc_context *ctx;
const struct bios_registers *regs;
+ struct integrated_info *integrated_info;
};
#endif /* DC_BIOS_TYPES_H */
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
index 573db6ef5a1d..38ca365da1ad 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
@@ -76,6 +76,7 @@ struct dc_context {
struct dc_bios *dc_bios;
bool created_bios;
struct gpio_service *gpio_service;
+ struct i2caux *i2caux;
};
/*
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
index ae9de4824378..670d7f3987d0 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
@@ -1002,10 +1002,10 @@ bool dce110_link_encoder_construct(
* while doing the DP sink detect
*/
- if (dal_adapter_service_is_feature_supported(as,
+/* if (dal_adapter_service_is_feature_supported(as,
FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
enc110->base.features.flags.bits.
- DP_SINK_DETECT_POLL_DATA_PIN = true;
+ DP_SINK_DETECT_POLL_DATA_PIN = true;*/
enc110->base.output_signals =
SIGNAL_TYPE_DVI_SINGLE_LINK |
@@ -1061,22 +1061,29 @@ bool dce110_link_encoder_construct(
init_data->channel);
/* Override features with DCE-specific values */
- if (dal_adapter_service_get_encoder_cap_info(
- enc110->base.adapter_service,
- enc110->base.id, &enc_cap_info))
- enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
- enc_cap_info.dp_hbr2_cap;
+ {
+ struct bp_encoder_cap_info bp_cap_info = {0};
+ const struct dc_vbios_funcs *bp_funcs = enc110->base.ctx->dc_bios->funcs;
+ if (BP_RESULT_OK != bp_funcs->get_encoder_cap_info(
+ enc110->base.ctx->dc_bios, enc110->base.id,
+ &bp_cap_info))
+ enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
+ bp_cap_info.DP_HBR2_CAP;
+ }
/* test pattern 3 support */
enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
- enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE =
+ enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE = false;
+ /*
dal_adapter_service_is_feature_supported(as,
FEATURE_SUPPORT_DP_Y_ONLY);
-
- enc110->base.features.flags.bits.IS_YCBCR_CAPABLE =
+*/
+ enc110->base.features.flags.bits.IS_YCBCR_CAPABLE = true;
+ /*
dal_adapter_service_is_feature_supported(as,
FEATURE_SUPPORT_DP_YUV);
+ */
return true;
}
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 20/76] drm/amd/dal: rotation and mirror support
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (18 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 19/76] drm/amd/dal: Remove adapter service dependency from dc_link Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 21/76] drm/amd/dal: remove unnessary AS dependency Harry Wentland
` (56 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Vitaly Prosyak
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Fix rotation 90 and 270.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index 276833847c4d..0c02894cef26 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -444,11 +444,6 @@ static void calculate_recout(
struct core_stream *stream = pipe_ctx->stream;
struct rect clip = surface->clip_rect;
- if (surface->rotation == ROTATION_ANGLE_90 ||
- surface->rotation == ROTATION_ANGLE_270){
- rect_swap_helper(&clip);
- }
-
pipe_ctx->scl_data.recout.x = stream->public.dst.x;
if (stream->public.src.x < clip.x)
pipe_ctx->scl_data.recout.x += (clip.x
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 21/76] drm/amd/dal: remove unnessary AS dependency
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (19 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 20/76] drm/amd/dal: rotation and mirror support Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 22/76] drm/amd/dal: remove AS dependency from i2c_aux Harry Wentland
` (55 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- ddc instantiation
- default i2c speed from dc_cap.
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 26 ----------------------
.../amd/dal/dc/asic_capability/asic_capability.c | 1 -
.../dc/asic_capability/carrizo_asic_capability.c | 1 -
.../dc/asic_capability/hawaii_asic_capability.c | 2 --
.../dc/asic_capability/polaris10_asic_capability.c | 1 -
.../dal/dc/asic_capability/tonga_asic_capability.c | 1 -
drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 4 +++-
drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 9 +++-----
.../amd/dal/include/adapter_service_interface.h | 8 -------
.../drm/amd/dal/include/asic_capability_types.h | 1 -
10 files changed, 6 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index 6d2f5762ef63..d25f9da35b07 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -118,7 +118,6 @@ static const struct feature_source_entry feature_entry_table[] = {
{FEATURE_DP_DISPLAY_FORCE_SS_ENABLE, false, true},
{FEATURE_REPORT_CE_MODE_ONLY, false, true},
{FEATURE_ALLOW_OPTIMIZED_MODE_AS_DEFAULT, false, true},
- {FEATURE_DDC_READ_FORCE_REPEATED_START, false, true},
{FEATURE_FORCE_TIMING_RESYNC, false, true},
{FEATURE_TMDS_DISABLE_DITHERING, false, true},
{FEATURE_HDMI_DISABLE_DITHERING, false, true},
@@ -136,7 +135,6 @@ static const struct feature_source_entry feature_entry_table[] = {
{FEATURE_PSR_ENABLE, false, true},
{FEATURE_WIRELESS_ENABLE_COMPRESSED_AUDIO, false, true},
{FEATURE_WIRELESS_INCLUDE_UNVERIFIED_TIMINGS, true, true},
- {FEATURE_EDID_STRESS_READ, false, true},
{FEATURE_DP_FRAME_PACK_STEREO3D, false, true},
{FEATURE_DISPLAY_PREFERRED_VIEW, 0, false},
{FEATURE_ALLOW_HDMI_WITHOUT_AUDIO, false, true},
@@ -928,30 +926,6 @@ bool dal_adapter_service_is_dfs_bypass_enabled(
}
/*
- * dal_adapter_service_get_sw_i2c_speed
- *
- * Get SW I2C speed
- */
-uint32_t dal_adapter_service_get_sw_i2c_speed(
- struct adapter_service *as)
-{
- /* TODO: only from ASIC caps. Feature key is not implemented*/
- return as->asic_cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ];
-}
-
-/*
- * dal_adapter_service_get_hw_i2c_speed
- *
- * Get HW I2C speed
- */
-uint32_t dal_adapter_service_get_hw_i2c_speed(
- struct adapter_service *as)
-{
- /* TODO: only from ASIC caps. Feature key is not implemented*/
- return as->asic_cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ];
-}
-
-/*
* dal_adapter_service_get_asic_vram_bit_width
*
* Get the video RAM bit width set on the ASIC
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
index 24ab4a5b5232..543fee50c21a 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
@@ -58,7 +58,6 @@ static bool construct(
cap->runtime_flags = init->runtime_flags;
cap->data[ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE] = 10;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 4;
- cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 25;
cap->data[ASIC_DATA_DOWNSCALE_LIMIT] = 200;
/* ASIC basic capability */
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
index d23d186c670f..982d1cd5bad9 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
@@ -56,7 +56,6 @@ void carrizo_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_STUTTERMODE] = 0x200A;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
- cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 100;
cap->data[ASIC_DATA_DOWNSCALE_LIMIT] = 150;
/* ASIC basic capability */
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
index 6678053d4601..628f985acf23 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
@@ -69,8 +69,6 @@ void dal_hawaii_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
- cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 40;
-
mc_seq_misc0 = dm_read_reg(cap->ctx, mmMC_SEQ_MISC0);
switch (mc_seq_misc0 & MC_MISC0__MEMORY_TYPE_MASK) {
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
index 15b1f7a59066..1b1524b2e6e4 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
@@ -58,7 +58,6 @@ void polaris10_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
- cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 100;
cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
index 2475de9c0bf5..58d4913e3aea 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
@@ -58,7 +58,6 @@ void tonga_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_DCE_VERSION] = 0x100; /* DCE 11 */
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
- cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 40;
/* ASIC basic capability */
cap->caps.IS_FUSION = true;
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
index 79669d9516cb..eae92f53694f 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
@@ -44,6 +44,8 @@
/* TODO remove - only needed for gpio_service */
#include "adapter/adapter_service.h"
+/* TODO remove - only needed for default i2c speed */
+#include "dc.h"
#define THREE_PERCENT_OF_10000 300
@@ -2940,7 +2942,7 @@ static bool i2c_read(
/*Using SW engine */
cmd.engine = I2C_COMMAND_ENGINE_SW;
- cmd.speed = dal_adapter_service_get_sw_i2c_speed(as);
+ cmd.speed = ddc->ctx->dc->caps.i2c_speed_in_khz;
{
struct i2c_payload payloads[] = {
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
index cc4c238ed0a6..c440d9d123ad 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
@@ -303,9 +303,7 @@ static bool construct(
}
ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
-
ddc_service->flags.FORCE_READ_REPEATED_START = false;
-
ddc_service->flags.EDID_STRESS_READ = false;
ddc_service->flags.IS_INTERNAL_DISPLAY =
@@ -450,7 +448,7 @@ static bool i2c_read(
.payloads = payloads,
.number_of_payloads = 2,
.engine = DDC_I2C_COMMAND_ENGINE,
- .speed = dal_adapter_service_get_sw_i2c_speed(ddc->as) };
+ .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
return dm_helpers_submit_i2c(
ddc->ctx,
@@ -561,7 +559,7 @@ static uint8_t i2c_read_edid_block(
.payloads = NULL,
.number_of_payloads = 0,
.engine = DDC_I2C_COMMAND_ENGINE,
- .speed = dal_adapter_service_get_sw_i2c_speed(ddc->as) };
+ .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
struct i2c_payload payloads[3] = {
{
@@ -943,8 +941,7 @@ bool dal_ddc_service_query_ddc_data(
.payloads = dal_ddc_i2c_payloads_get(payloads),
.number_of_payloads = 0,
.engine = DDC_I2C_COMMAND_ENGINE,
- .speed =
- dal_adapter_service_get_sw_i2c_speed(ddc->as) };
+ .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
dal_ddc_i2c_payloads_add(
payloads, address, write_size, write_buf, true);
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index 052cd9ab5cf3..ef45693925d6 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -87,7 +87,6 @@ enum adapter_feature_id {
FEATURE_DP_DISPLAY_FORCE_SS_ENABLE,
FEATURE_REPORT_CE_MODE_ONLY,
FEATURE_ALLOW_OPTIMIZED_MODE_AS_DEFAULT,
- FEATURE_DDC_READ_FORCE_REPEATED_START,
FEATURE_FORCE_TIMING_RESYNC,
FEATURE_TMDS_DISABLE_DITHERING,
FEATURE_HDMI_DISABLE_DITHERING,
@@ -111,7 +110,6 @@ enum adapter_feature_id {
FEATURE_PREFER_3D_TIMING,
FEATURE_VARI_BRIGHT_ENABLE,
FEATURE_PSR_ENABLE,
- FEATURE_EDID_STRESS_READ,
FEATURE_DP_FRAME_PACK_STEREO3D,
FEATURE_ALLOW_HDMI_WITHOUT_AUDIO,
FEATURE_RESTORE_USAGE_I2C_SW_ENGING,
@@ -380,12 +378,6 @@ bool dal_adapter_service_get_feature_value(struct adapter_service *as,
void *data,
uint32_t size);
-/* Get SW I2C speed */
-uint32_t dal_adapter_service_get_sw_i2c_speed(struct adapter_service *as);
-
-/* Get HW I2C speed */
-uint32_t dal_adapter_service_get_hw_i2c_speed(struct adapter_service *as);
-
/* Get I2C information from BIOS */
bool dal_adapter_service_get_i2c_info(
struct adapter_service *as,
diff --git a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
index 1f78dc9f52f3..8c6c40247e02 100644
--- a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
+++ b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
@@ -97,7 +97,6 @@ enum asic_data {
ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE,
ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY,
ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN,
- ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ,
ASIC_DATA_DOWNSCALE_LIMIT,
ASIC_DATA_MAX_NUMBER /* end of enum */
};
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 22/76] drm/amd/dal: remove AS dependency from i2c_aux
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (20 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 21/76] drm/amd/dal: remove unnessary AS dependency Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 23/76] drm/amd/dal: remove dal_adapter_service_get_integrated_info Harry Wentland
` (54 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- remove dal_adapter_service_get_firmware_info. call bios directly
- remove dal_adapter_service_get_i2caux. get i2caux from dc_ctx
- remove FEATURE_RESTORE_USAGE_I2C_SW_ENGINE. always 0
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 26 +-----------------
drivers/gpu/drm/amd/dal/dc/core/dc.c | 2 +-
drivers/gpu/drm/amd/dal/dc/dc_types.h | 6 ++++-
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 2 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 2 +-
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 2 +-
.../amd/dal/dc/gpu/dce110/display_clock_dce110.c | 3 ++-
.../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c | 3 ++-
.../drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.c | 2 --
.../drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.h | 1 -
.../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c | 10 ++-----
.../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h | 2 --
.../drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.c | 5 +---
.../drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.h | 1 -
.../gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c | 8 +++---
.../gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.h | 1 -
.../amd/dal/dc/i2caux/diagnostics/i2caux_diag.c | 6 ++---
.../amd/dal/dc/i2caux/diagnostics/i2caux_diag.h | 1 -
drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c | 31 +++++++---------------
drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h | 3 +--
.../amd/dal/include/adapter_service_interface.h | 6 -----
drivers/gpu/drm/amd/dal/include/i2caux_interface.h | 1 -
22 files changed, 32 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index d25f9da35b07..328cc8a41770 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -86,16 +86,6 @@ static const struct feature_source_entry feature_entry_table[] = {
{FEATURE_MAXIMIZE_URGENCY_WATERMARKS, false, true},
{FEATURE_MAXIMIZE_STUTTER_MARKS, false, true},
{FEATURE_MAXIMIZE_NBP_MARKS, false, true},
- /*
- * We meet HW I2C issue when test S3 resume on KB.
- * An EPR is created for debug the issue.
- * Make Test has already been implemented
- * with HW I2C. The work load for revert back to SW I2C in make test
- * is big. Below is workaround for this issue.
- * Driver uses SW I2C.
- * Make Test uses HW I2C.
- */
- {FEATURE_RESTORE_USAGE_I2C_SW_ENGINE, false, true},
{FEATURE_USE_MAX_DISPLAY_CLK, false, true},
{FEATURE_ALLOW_EDP_RESOURCE_SHARING, false, true},
{FEATURE_SUPPORT_DP_YUV, false, true},
@@ -672,7 +662,7 @@ static bool adapter_service_construct(
dcb = as->ctx->dc_bios;
/* Create I2C AUX */
- as->i2caux = dal_i2caux_create(as, as->ctx);
+ as->i2caux = dal_i2caux_create(as->ctx);
if (!as->i2caux) {
ASSERT_CRITICAL(false);
@@ -943,20 +933,6 @@ struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags(
}
/*
- * dal_adapter_service_get_firmware_info
- *
- * Get firmware information from BIOS
- */
-bool dal_adapter_service_get_firmware_info(
- struct adapter_service *as,
- struct firmware_info *info)
-{
- struct dc_bios *dcb = as->ctx->dc_bios;
-
- return dcb->funcs->get_firmware_info(dcb, info) == BP_RESULT_OK;
-}
-
-/*
* dal_adapter_service_get_feature_value
*
* Get the cached value of a given feature. This value can be a boolean, int,
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index a65950bf771b..ec33cf9a7fd0 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -518,8 +518,8 @@ static bool construct(struct core_dc *dc,
dc->ctx = dc_ctx;
dc->ctx->dce_environment = init_params->dce_environment;
-
dc_version = resource_parse_asic_id(init_params->asic_id);
+ dc->ctx->dce_version = dc_version;
/* Resource should construct all asic specific resources.
* This should be the only place where we need to parse the asic id
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
index 38ca365da1ad..b30dfbf7281e 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
@@ -30,7 +30,7 @@
#include "irq_types.h"
#include "dc_dp_types.h"
#include "dc_hw_types.h"
-#include "signal_types.h"
+#include "dal_types.h"
/* forward declarations */
struct dc_surface;
@@ -73,6 +73,10 @@ struct dc_context {
enum dce_environment dce_environment;
+ /* todo: below should probably move to dc. to facilitate removal
+ * of AS we will store these here
+ */
+ enum dce_version dce_version;
struct dc_bios *dc_bios;
bool created_bios;
struct gpio_service *gpio_service;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index c8c83e86eb53..d1587fe3b854 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -880,7 +880,7 @@ static bool construct(
bp = ctx->dc_bios;
- if (dal_adapter_service_get_firmware_info(as, &info) &&
+ if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
info.external_clock_source_frequency_for_dp != 0) {
pool->base.dp_clock_source =
dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 82cdcb5c2eb1..33f4455e80f6 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -1211,7 +1211,7 @@ static bool construct(
bp = ctx->dc_bios;
- if (dal_adapter_service_get_firmware_info(as, &info) &&
+ if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
info.external_clock_source_frequency_for_dp != 0) {
pool->base.dp_clock_source =
dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index 705c69a8a5c4..932f37559da9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -886,7 +886,7 @@ static bool construct(
bp = ctx->dc_bios;
- if (dal_adapter_service_get_firmware_info(as, &info) &&
+ if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
info.external_clock_source_frequency_for_dp != 0) {
pool->base.dp_clock_source =
dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
index d422294715ce..8b9d984f3bb9 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
@@ -670,6 +670,7 @@ static bool display_clock_integrated_info_construct(
struct display_clock_dce110 *disp_clk,
struct adapter_service *as)
{
+ struct dc_bios *bp = disp_clk->disp_clk_base.ctx->dc_bios;
struct integrated_info info;
struct firmware_info fw_info;
uint32_t i;
@@ -683,7 +684,7 @@ static bool display_clock_integrated_info_construct(
disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq;
if (disp_clk->dentist_vco_freq_khz == 0) {
- dal_adapter_service_get_firmware_info(as, &fw_info);
+ bp->funcs->get_firmware_info(bp, &fw_info);
disp_clk->dentist_vco_freq_khz =
fw_info.smu_gpu_pll_output_freq;
if (disp_clk->dentist_vco_freq_khz == 0)
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
index e37b397bbd9f..b69e40493e27 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
@@ -753,6 +753,7 @@ static bool display_clock_integrated_info_construct(
struct display_clock_dce80 *disp_clk,
struct adapter_service *as)
{
+ struct dc_bios *bp = disp_clk->disp_clk.ctx->dc_bios;
struct integrated_info info = { { { 0 } } };
struct firmware_info fw_info = { { 0 } };
uint32_t i;
@@ -761,7 +762,7 @@ static bool display_clock_integrated_info_construct(
disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq;
if (disp_clk->dentist_vco_freq_khz == 0) {
- dal_adapter_service_get_firmware_info(as, &fw_info);
+ bp->funcs->get_firmware_info(bp, &fw_info);
disp_clk->dentist_vco_freq_khz =
fw_info.smu_gpu_pll_output_freq;
if (disp_clk->dentist_vco_freq_khz == 0)
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.c
index e3ababdfe7aa..ab138464aaa2 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.c
@@ -77,7 +77,6 @@ static const struct dce110_i2c_hw_engine_registers dce100_hw_engine_regs[] = {
};
struct i2caux *dal_i2caux_dce100_create(
- struct adapter_service *as,
struct dc_context *ctx)
{
struct i2caux_dce110 *i2caux_dce110 =
@@ -90,7 +89,6 @@ struct i2caux *dal_i2caux_dce100_create(
if (dal_i2caux_dce110_construct(
i2caux_dce110,
- as,
ctx,
dce100_aux_regs,
dce100_hw_engine_regs))
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.h
index b2902c65d645..2b508d3e0ef4 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.h
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce100/i2caux_dce100.h
@@ -27,7 +27,6 @@
#define __DAL_I2C_AUX_DCE100_H__
struct i2caux *dal_i2caux_dce100_create(
- struct adapter_service *as,
struct dc_context *ctx);
#endif /* __DAL_I2C_AUX_DCE100_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
index 566056b6782f..a66c365edfac 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c
@@ -190,7 +190,6 @@ static const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[] = {
bool dal_i2caux_dce110_construct(
struct i2caux_dce110 *i2caux_dce110,
- struct adapter_service *as,
struct dc_context *ctx,
const struct dce110_aux_registers aux_regs[],
const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[])
@@ -204,14 +203,11 @@ bool dal_i2caux_dce110_construct(
* Some BIOS setting incorrect cause this
* For production, we always get value from BIOS*/
reference_frequency =
- dal_i2caux_get_reference_clock(as) >> 1;
-
- use_i2c_sw_engine = dal_adapter_service_is_feature_supported(as,
- FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);
+ dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
base = &i2caux_dce110->base;
- if (!dal_i2caux_construct(base, as, ctx)) {
+ if (!dal_i2caux_construct(base, ctx)) {
ASSERT_CRITICAL(false);
return false;
}
@@ -288,7 +284,6 @@ bool dal_i2caux_dce110_construct(
* pointer to the base struct of DCE11 I2CAUX
*/
struct i2caux *dal_i2caux_dce110_create(
- struct adapter_service *as,
struct dc_context *ctx)
{
struct i2caux_dce110 *i2caux_dce110 =
@@ -301,7 +296,6 @@ struct i2caux *dal_i2caux_dce110_create(
if (dal_i2caux_dce110_construct(
i2caux_dce110,
- as,
ctx,
dce110_aux_regs,
i2c_hw_engine_regs))
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h
index d26eec0ff12c..4d544f4e6289 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h
@@ -38,12 +38,10 @@ struct dce110_aux_registers;
struct dce110_i2c_hw_engine_registers;
struct i2caux *dal_i2caux_dce110_create(
- struct adapter_service *as,
struct dc_context *ctx);
bool dal_i2caux_dce110_construct(
struct i2caux_dce110 *i2caux_dce110,
- struct adapter_service *as,
struct dc_context *ctx,
const struct dce110_aux_registers *aux_regs,
const struct dce110_i2c_hw_engine_registers *i2c_hw_engine_regs);
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.c
index 748f0c4c3968..2b1456e3d367 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.c
@@ -81,12 +81,10 @@ static const struct dce110_i2c_hw_engine_registers dce112_hw_engine_regs[] = {
static bool construct(
struct i2caux_dce110 *i2caux_dce110,
- struct adapter_service *as,
struct dc_context *ctx)
{
if (!dal_i2caux_dce110_construct(
i2caux_dce110,
- as,
ctx,
dce112_aux_regs,
dce112_hw_engine_regs)) {
@@ -111,7 +109,6 @@ static bool construct(
* pointer to the base struct of DCE11 I2CAUX
*/
struct i2caux *dal_i2caux_dce112_create(
- struct adapter_service *as,
struct dc_context *ctx)
{
struct i2caux_dce110 *i2caux_dce110 =
@@ -122,7 +119,7 @@ struct i2caux *dal_i2caux_dce112_create(
return NULL;
}
- if (construct(i2caux_dce110, as, ctx))
+ if (construct(i2caux_dce110, ctx))
return &i2caux_dce110->base;
ASSERT_CRITICAL(false);
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.h
index 06a530c7c996..8d35453c25b6 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.h
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce112/i2caux_dce112.h
@@ -27,7 +27,6 @@
#define __DAL_I2C_AUX_DCE112_H__
struct i2caux *dal_i2caux_dce112_create(
- struct adapter_service *as,
struct dc_context *ctx);
#endif /* __DAL_I2C_AUX_DCE112_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c
index be1d26408d97..5e71450c44e0 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.c
@@ -189,7 +189,6 @@ static const struct i2caux_funcs i2caux_funcs = {
static bool construct(
struct i2caux_dce80 *i2caux_dce80,
- struct adapter_service *as,
struct dc_context *ctx)
{
/* Entire family have I2C engine reference clock frequency
@@ -198,7 +197,7 @@ static bool construct(
struct i2caux *base = &i2caux_dce80->base;
uint32_t reference_frequency =
- dal_i2caux_get_reference_clock(as) >> 1;
+ dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
/*bool use_i2c_sw_engine = dal_adapter_service_is_feature_supported(as,
FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);*/
@@ -208,7 +207,7 @@ static bool construct(
uint32_t i;
- if (!dal_i2caux_construct(base, as, ctx)) {
+ if (!dal_i2caux_construct(base, ctx)) {
BREAK_TO_DEBUGGER();
return false;
}
@@ -275,7 +274,6 @@ static bool construct(
}
struct i2caux *dal_i2caux_dce80_create(
- struct adapter_service *as,
struct dc_context *ctx)
{
struct i2caux_dce80 *i2caux_dce80 =
@@ -286,7 +284,7 @@ struct i2caux *dal_i2caux_dce80_create(
return NULL;
}
- if (construct(i2caux_dce80, as, ctx))
+ if (construct(i2caux_dce80, ctx))
return &i2caux_dce80->base;
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.h b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.h
index 85417a896279..21908629e973 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.h
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce80/i2caux_dce80.h
@@ -33,7 +33,6 @@ struct i2caux_dce80 {
};
struct i2caux *dal_i2caux_dce80_create(
- struct adapter_service *as,
struct dc_context *ctx);
#endif
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
index 027b207654d2..029bf735036c 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c
@@ -75,10 +75,9 @@ static const struct i2caux_funcs i2caux_funcs = {
static bool construct(
struct i2caux *i2caux,
- struct adapter_service *as,
struct dc_context *ctx)
{
- if (!dal_i2caux_construct(i2caux, as, ctx)) {
+ if (!dal_i2caux_construct(i2caux, ctx)) {
ASSERT_CRITICAL(false);
return false;
}
@@ -89,7 +88,6 @@ static bool construct(
}
struct i2caux *dal_i2caux_diag_fpga_create(
- struct adapter_service *as,
struct dc_context *ctx)
{
struct i2caux *i2caux = dm_alloc(sizeof(struct i2caux));
@@ -99,7 +97,7 @@ struct i2caux *dal_i2caux_diag_fpga_create(
return NULL;
}
- if (construct(i2caux, as, ctx))
+ if (construct(i2caux, ctx))
return i2caux;
ASSERT_CRITICAL(false);
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.h b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.h
index 3de250bd7660..a83eeb748283 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.h
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.h
@@ -27,7 +27,6 @@
#define __DAL_I2C_AUX_DIAG_FPGA_H__
struct i2caux *dal_i2caux_diag_fpga_create(
- struct adapter_service *as,
struct dc_context *ctx);
#endif /* __DAL_I2C_AUX_DIAG_FPGA_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
index d9121316d255..63ffd7cb418d 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
@@ -64,33 +64,21 @@
*/
struct i2caux *dal_i2caux_create(
- struct adapter_service *as,
struct dc_context *ctx)
{
- enum dce_version dce_version;
- enum dce_environment dce_environment;
-
- if (!as) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- dce_version = dal_adapter_service_get_dce_version(as);
- dce_environment = ctx->dce_environment;
-
- if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
- return dal_i2caux_diag_fpga_create(as, ctx);
+ if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+ return dal_i2caux_diag_fpga_create(ctx);
}
- switch (dce_version) {
+ switch (ctx->dce_version) {
case DCE_VERSION_8_0:
- return dal_i2caux_dce80_create(as, ctx);
+ return dal_i2caux_dce80_create(ctx);
case DCE_VERSION_11_2:
- return dal_i2caux_dce112_create(as, ctx);
+ return dal_i2caux_dce112_create(ctx);
case DCE_VERSION_11_0:
- return dal_i2caux_dce110_create(as, ctx);
+ return dal_i2caux_dce110_create(ctx);
case DCE_VERSION_10_0:
- return dal_i2caux_dce100_create(as, ctx);
+ return dal_i2caux_dce100_create(ctx);
default:
BREAK_TO_DEBUGGER();
return NULL;
@@ -313,11 +301,11 @@ void dal_i2caux_destroy(
*/
uint32_t dal_i2caux_get_reference_clock(
- struct adapter_service *as)
+ struct dc_bios *bios)
{
struct firmware_info info = { { 0 } };
- if (!dal_adapter_service_get_firmware_info(as, &info))
+ if (bios->funcs->get_firmware_info(bios, &info) != BP_RESULT_OK)
return 0;
return info.pll_info.crystal_frequency;
@@ -413,7 +401,6 @@ void dal_i2caux_release_engine(
bool dal_i2caux_construct(
struct i2caux *i2caux,
- struct adapter_service *as,
struct dc_context *ctx)
{
uint32_t i = 0;
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h
index 76f5b637ec3f..bc20de3da1c4 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h
@@ -27,7 +27,7 @@
#define __DAL_I2C_AUX_H__
uint32_t dal_i2caux_get_reference_clock(
- struct adapter_service *as);
+ struct dc_bios *bios);
struct i2caux;
@@ -99,7 +99,6 @@ struct i2caux {
bool dal_i2caux_construct(
struct i2caux *i2caux,
- struct adapter_service *as,
struct dc_context *ctx);
void dal_i2caux_release_engine(
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index ef45693925d6..9de495532eb1 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -76,7 +76,6 @@ enum adapter_feature_id {
FEATURE_MAXIMIZE_URGENCY_WATERMARKS,
FEATURE_MAXIMIZE_STUTTER_MARKS,
FEATURE_MAXIMIZE_NBP_MARKS,
- FEATURE_RESTORE_USAGE_I2C_SW_ENGINE,
FEATURE_USE_MAX_DISPLAY_CLK,
FEATURE_ALLOW_EDP_RESOURCE_SHARING,
FEATURE_SUPPORT_DP_YUV,
@@ -337,11 +336,6 @@ void dal_adapter_service_destroy(
enum dce_version dal_adapter_service_get_dce_version(
const struct adapter_service *as);
-/* Get firmware information from BIOS */
-bool dal_adapter_service_get_firmware_info(
- struct adapter_service *as,
- struct firmware_info *info);
-
/* Get number of spread spectrum entries from BIOS */
uint32_t dal_adapter_service_get_ss_info_num(
struct adapter_service *as,
diff --git a/drivers/gpu/drm/amd/dal/include/i2caux_interface.h b/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
index ecbf84908b0b..a78576a38b36 100644
--- a/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
@@ -67,7 +67,6 @@ union aux_config {
struct i2caux;
struct i2caux *dal_i2caux_create(
- struct adapter_service *as,
struct dc_context *ctx);
bool dal_i2caux_submit_i2c_command(
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 23/76] drm/amd/dal: remove dal_adapter_service_get_integrated_info
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (21 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 22/76] drm/amd/dal: remove AS dependency from i2c_aux Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 24/76] drm/amd/dal: instantiate i2caux outside of AS Harry Wentland
` (53 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- cache integrated_info in bios.
- fix dGPU crash as dGPU does not have integrated_info
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 32 ++++------------------
drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 24 ++++------------
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 6 ++--
drivers/gpu/drm/amd/dal/dc/dc_bios_types.h | 7 -----
.../amd/dal/dc/gpu/dce110/display_clock_dce110.c | 6 ++--
.../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c | 3 +-
.../amd/dal/include/adapter_service_interface.h | 7 -----
7 files changed, 19 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index 328cc8a41770..f2e633e3ab74 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -599,8 +599,6 @@ static void adapter_service_destruct(
dal_i2caux_destroy(&as->i2caux);
dal_asic_capability_destroy(&as->asic_cap);
-
- dcb->funcs->destroy_integrated_info(dcb, &as->integrated_info);
}
/*
@@ -669,10 +667,6 @@ static bool adapter_service_construct(
goto failed_to_create_i2caux;
}
- /* Integrated info is not provided on discrete ASIC. NULL is allowed */
- if (dcb->funcs->create_integrated_info)
- as->integrated_info = dcb->funcs->create_integrated_info(dcb);
-
dcb->funcs->post_init(dcb, as);
/* Generate backlight translation table and initializes
@@ -881,23 +875,6 @@ bool dal_adapter_service_get_ss_info(
}
/*
- * dal_adapter_service_get_integrated_info
- *
- * Get integrated information on BIOS
- */
-bool dal_adapter_service_get_integrated_info(
- struct adapter_service *as,
- struct integrated_info *info)
-{
- if (info == NULL || as->integrated_info == NULL)
- return false;
-
- memmove(info, as->integrated_info, sizeof(struct integrated_info));
-
- return true;
-}
-
-/*
* dal_adapter_service_is_dfs_bypass_enabled
*
* Check if DFS bypass is enabled
@@ -905,9 +882,11 @@ bool dal_adapter_service_get_integrated_info(
bool dal_adapter_service_is_dfs_bypass_enabled(
struct adapter_service *as)
{
- if (as->integrated_info == NULL)
+ struct dc_bios *bp = as->ctx->dc_bios;
+
+ if (bp->integrated_info == NULL)
return false;
- if ((as->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) &&
+ if ((bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) &&
dal_adapter_service_is_feature_supported(as,
FEATURE_ENABLE_DFS_BYPASS))
return true;
@@ -1031,6 +1010,7 @@ bool dal_adapter_service_should_optimize(
{
uint32_t supported_optimization = 0;
struct dal_asic_runtime_flags flags;
+ struct dc_bios *bp = as->ctx->dc_bios;
if (!dal_adapter_service_get_feature_value(as, FEATURE_OPTIMIZATION,
&supported_optimization, sizeof(uint32_t)))
@@ -1047,7 +1027,7 @@ bool dal_adapter_service_should_optimize(
break;
case OF_SKIP_RESET_OF_ALL_HW_ON_S3RESUME:
- if (as->integrated_info == NULL ||
+ if (bp->integrated_info == NULL ||
!flags.flags.bits.SKIP_POWER_DOWN_ON_RESUME)
return false;
break;
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
index eae92f53694f..41093c21ce30 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
@@ -135,6 +135,9 @@ static void destruct(struct bios_parser *bp)
{
if (bp->base.bios_local_image)
dm_free(bp->base.bios_local_image);
+
+ if (bp->base.integrated_info)
+ dm_free(bp->base.integrated_info);
}
static void bios_parser_destroy(struct dc_bios **dcb)
@@ -4063,21 +4066,6 @@ static struct integrated_info *bios_parser_create_integrated_info(
return NULL;
}
-static void bios_parser_destroy_integrated_info(
- struct dc_bios *dcb,
- struct integrated_info **info)
-{
- if (info == NULL) {
- ASSERT_CRITICAL(0);
- return;
- }
-
- if (*info != NULL) {
- dm_free(*info);
- *info = NULL;
- }
-}
-
/******************************************************************************/
static const struct dc_vbios_funcs vbios_funcs = {
@@ -4156,10 +4144,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
/* SW init and patch */
.post_init = bios_parser_post_init, /* patch vbios table for mxm module by reading i2c */
- .create_integrated_info = bios_parser_create_integrated_info,
-
- .destroy_integrated_info = bios_parser_destroy_integrated_info,
-
.bios_parser_destroy = bios_parser_destroy,
};
@@ -4241,6 +4225,8 @@ static bool bios_parser_construct(
dal_bios_parser_init_cmd_tbl(bp);
dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version);
+ bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
+
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index d86817606f39..1eb1089a8288 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -1050,9 +1050,6 @@ static bool construct(
link->public.link_enc_hw_inst = link->link_enc->transmitter;
- /* TODO: refactor dal_adapter_service_get_integrated_info(as, &info); */
- memmove(&info, dc_ctx->dc_bios->integrated_info, sizeof(struct integrated_info));
-
for (i = 0; ; i++) {
if (BP_RESULT_OK !=
bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
@@ -1077,6 +1074,9 @@ static bool construct(
break;
}
+ if (bios->integrated_info)
+ info = *bios->integrated_info;
+
/* Look for channel mapping corresponding to connector and device tag */
for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
struct external_display_path *path =
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
index 7c1f9d817f9c..4771e415e33e 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
@@ -202,13 +202,6 @@ struct dc_vbios_funcs {
void (*post_init)(struct dc_bios *bios,
struct adapter_service *as);
- struct integrated_info *(*create_integrated_info)(
- struct dc_bios *bios);
-
- void (*destroy_integrated_info)(
- struct dc_bios *dcb,
- struct integrated_info **info);
-
void (*bios_parser_destroy)(struct dc_bios **dcb);
};
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
index 8b9d984f3bb9..9aa9b8fc927f 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
@@ -675,12 +675,12 @@ static bool display_clock_integrated_info_construct(
struct firmware_info fw_info;
uint32_t i;
struct display_clock *base = &disp_clk->disp_clk_base;
- bool res;
memset(&info, 0, sizeof(struct integrated_info));
memset(&fw_info, 0, sizeof(struct firmware_info));
- res = dal_adapter_service_get_integrated_info(as, &info);
+ if (bp->integrated_info)
+ info = *bp->integrated_info;
disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq;
if (disp_clk->dentist_vco_freq_khz == 0) {
@@ -694,7 +694,7 @@ static bool display_clock_integrated_info_construct(
base->min_display_clk_threshold_khz =
disp_clk->dentist_vco_freq_khz / 64;
- if (!res)
+ if (bp->integrated_info == NULL)
return false;
/*update the maximum display clock for each power state*/
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
index b69e40493e27..0741139db8b5 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
@@ -758,7 +758,8 @@ static bool display_clock_integrated_info_construct(
struct firmware_info fw_info = { { 0 } };
uint32_t i;
- dal_adapter_service_get_integrated_info(as, &info);
+ if (bp->integrated_info)
+ info = *bp->integrated_info;
disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq;
if (disp_clk->dentist_vco_freq_khz == 0) {
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index 9de495532eb1..7b001f0aa9db 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -298,7 +298,6 @@ struct adapter_service {
struct asic_capability *asic_cap;
enum dce_environment dce_environment;
struct i2caux *i2caux;
- struct integrated_info *integrated_info;
uint32_t platform_methods_mask;
uint32_t ac_level_percentage;
uint32_t dc_level_percentage;
@@ -356,12 +355,6 @@ bool dal_adapter_service_is_dfs_bypass_enabled(struct adapter_service *as);
uint32_t dal_adapter_service_get_asic_vram_bit_width(
struct adapter_service *as);
-
-/* Get integrated information on BIOS */
-bool dal_adapter_service_get_integrated_info(
- struct adapter_service *as,
- struct integrated_info *info);
-
/* Return if a given feature is supported by the ASIC */
bool dal_adapter_service_is_feature_supported(struct adapter_service *as,
enum adapter_feature_id feature_id);
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 24/76] drm/amd/dal: instantiate i2caux outside of AS
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (22 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 23/76] drm/amd/dal: remove dal_adapter_service_get_integrated_info Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 25/76] drm/amd/dal: fix DDC pad mode detection logic Harry Wentland
` (52 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- also consolidate dc create failure using destruct
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 25 --------
drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 2 +-
drivers/gpu/drm/amd/dal/dc/core/dc.c | 72 ++++++++++++++--------
drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 10 +--
drivers/gpu/drm/amd/dal/dc/dc_types.h | 1 +
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 3 -
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 4 --
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 4 --
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 4 --
.../amd/dal/include/adapter_service_interface.h | 5 --
10 files changed, 52 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index f2e633e3ab74..435b222c48a4 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -595,9 +595,6 @@ static bool generate_feature_set(
static void adapter_service_destruct(
struct adapter_service *as)
{
- struct dc_bios *dcb = as->ctx->dc_bios;
-
- dal_i2caux_destroy(&as->i2caux);
dal_asic_capability_destroy(&as->asic_cap);
}
@@ -659,14 +656,6 @@ static bool adapter_service_construct(
dcb = as->ctx->dc_bios;
- /* Create I2C AUX */
- as->i2caux = dal_i2caux_create(as->ctx);
-
- if (!as->i2caux) {
- ASSERT_CRITICAL(false);
- goto failed_to_create_i2caux;
- }
-
dcb->funcs->post_init(dcb, as);
/* Generate backlight translation table and initializes
@@ -680,9 +669,6 @@ static bool adapter_service_construct(
return true;
failed_to_generate_features:
- dal_i2caux_destroy(&as->i2caux);
-
-failed_to_create_i2caux:
dal_asic_capability_destroy(&as->asic_cap);
return false;
@@ -966,17 +952,6 @@ bool dal_adapter_service_get_feature_value(struct adapter_service *as,
return true;
}
-/*
- * dal_adapter_service_get_i2caux
- *
- * Get i2c aux handler
- */
-struct i2caux *dal_adapter_service_get_i2caux(
- struct adapter_service *as)
-{
- return as->i2caux;
-}
-
bool dal_adapter_service_get_embedded_panel_info(
struct adapter_service *as,
struct embedded_panel_info *info)
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
index 41093c21ce30..586df420f87b 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
@@ -2968,7 +2968,7 @@ static bool i2c_read(
/* TODO route this through drm i2c_adapter */
result = dal_i2caux_submit_i2c_command(
- dal_adapter_service_get_i2caux(as),
+ ddc->ctx->i2caux,
ddc,
&cmd);
}
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index ec33cf9a7fd0..766cdb1d4286 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -479,6 +479,39 @@ static void allocate_dc_stream_funcs(struct core_dc *core_dc)
set_test_pattern;
}
+static void destruct(struct core_dc *dc)
+{
+ resource_validate_ctx_destruct(dc->current_context);
+
+ dm_free(dc->temp_flip_context);
+ dc->current_context = NULL;
+
+ destroy_links(dc);
+
+ if (dc->res_pool)
+ dc->res_pool->funcs->destroy(&dc->res_pool);
+
+ if (dc->ctx->gpio_service)
+ dal_gpio_service_destroy(&dc->ctx->gpio_service);
+
+ if (dc->ctx->adapter_srv)
+ dal_adapter_service_destroy(&dc->ctx->adapter_srv);
+
+ if (dc->ctx->i2caux)
+ dal_i2caux_destroy(&dc->ctx->i2caux);
+
+ if (dc->ctx->created_bios)
+ dal_bios_parser_destroy(&dc->ctx->dc_bios);
+
+ if (dc->ctx->logger)
+ dal_logger_destroy(&dc->ctx->logger);
+
+ dm_free(dc->current_context);
+ dm_free(dc->ctx);
+
+ dc->ctx = NULL;
+}
+
static bool construct(struct core_dc *dc,
const struct dc_init_data *init_params)
{
@@ -543,6 +576,14 @@ static bool construct(struct core_dc *dc,
dc_ctx->created_bios = true;
}
+ /* Create I2C AUX */
+ dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
+
+ if (!dc_ctx->i2caux) {
+ ASSERT_CRITICAL(false);
+ goto failed_to_create_i2caux;
+ }
+
/* TODO: Refactor DCE code to remove AS and asic caps */
if (dc_version < DCE_VERSION_MAX) {
/* Create adapter service */
@@ -552,6 +593,7 @@ static bool construct(struct core_dc *dc,
dm_error("%s: create_as() failed!\n", __func__);
goto as_fail;
}
+ dc_ctx->adapter_srv = as;
}
/* Create GPIO service */
@@ -583,42 +625,18 @@ static bool construct(struct core_dc *dc,
/**** error handling here ****/
create_links_fail:
- dc->res_pool->funcs->destroy(&dc->res_pool);
create_resource_fail:
- if (dc->ctx->gpio_service)
- dal_gpio_service_destroy(&dc_ctx->gpio_service);
gpio_fail:
- if (as)
- dal_adapter_service_destroy(&as);
as_fail:
- if (dc->ctx->created_bios)
- dal_bios_parser_destroy(&dc->ctx->dc_bios);
+failed_to_create_i2caux:
bios_fail:
- dal_logger_destroy(&dc_ctx->logger);
logger_fail:
- dm_free(dc->current_context);
val_ctx_fail:
- dm_free(dc_ctx);
ctx_fail:
+ destruct(dc);
return false;
}
-static void destruct(struct core_dc *dc)
-{
- dal_gpio_service_destroy(&dc->ctx->gpio_service);
- resource_validate_ctx_destruct(dc->current_context);
- dm_free(dc->current_context);
- dm_free(dc->temp_flip_context);
- dc->current_context = NULL;
- destroy_links(dc);
- dc->res_pool->funcs->destroy(&dc->res_pool);
- dal_logger_destroy(&dc->ctx->logger);
- if (dc->ctx->created_bios)
- dal_bios_parser_destroy(&dc->ctx->dc_bios);
- dm_free(dc->ctx);
- dc->ctx = NULL;
-}
-
/*
void ProgramPixelDurationV(unsigned int pixelClockInKHz )
{
@@ -1710,7 +1728,7 @@ bool dc_submit_i2c(
struct ddc_service *ddc = link->ddc;
return dal_i2caux_submit_i2c_command(
- dal_adapter_service_get_i2caux(ddc->as),
+ ddc->ctx->i2caux,
ddc->ddc_pin,
cmd);
}
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
index c440d9d123ad..c945d4b27def 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
@@ -507,7 +507,7 @@ static uint8_t aux_read_edid_block(
}
if (!dal_i2caux_submit_aux_command(
- dal_adapter_service_get_i2caux(ddc->as),
+ ddc->ctx->i2caux,
ddc->ddc_pin,
&cmd))
/* cannot read, break*/
@@ -530,7 +530,7 @@ static uint8_t aux_read_edid_block(
cmd.payloads = payloads;
result = dal_i2caux_submit_aux_command(
- dal_adapter_service_get_i2caux(ddc->as),
+ ddc->ctx->i2caux,
ddc->ddc_pin,
&cmd);
@@ -927,7 +927,7 @@ bool dal_ddc_service_query_ddc_data(
dal_ddc_aux_payloads_get_count(payloads);
ret = dal_i2caux_submit_aux_command(
- dal_adapter_service_get_i2caux(ddc->as),
+ ddc->ctx->i2caux,
ddc->ddc_pin,
&command);
@@ -989,7 +989,7 @@ enum ddc_result dal_ddc_service_read_dpcd_data(
}
if (dal_i2caux_submit_aux_command(
- dal_adapter_service_get_i2caux(ddc->as),
+ ddc->ctx->i2caux,
ddc->ddc_pin,
&command))
return DDC_RESULT_SUCESSFULL;
@@ -1023,7 +1023,7 @@ enum ddc_result dal_ddc_service_write_dpcd_data(
}
if (dal_i2caux_submit_aux_command(
- dal_adapter_service_get_i2caux(ddc->as),
+ ddc->ctx->i2caux,
ddc->ddc_pin,
&command))
return DDC_RESULT_SUCESSFULL;
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
index b30dfbf7281e..15f45180a0cf 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
@@ -81,6 +81,7 @@ struct dc_context {
bool created_bios;
struct gpio_service *gpio_service;
struct i2caux *i2caux;
+ struct adapter_service *adapter_srv;
};
/*
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index d1587fe3b854..81319166ed16 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -659,9 +659,6 @@ static void destruct(struct dce110_resource_pool *pool)
if (pool->base.irqs != NULL)
dal_irq_service_destroy(&pool->base.irqs);
-
- if (pool->base.adapter_srv != NULL)
- dal_adapter_service_destroy(&pool->base.adapter_srv);
}
static enum dc_status validate_mapped_resource(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 33f4455e80f6..15958e6cedd1 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -631,10 +631,6 @@ static void destruct(struct dce110_resource_pool *pool)
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
}
-
- if (pool->base.adapter_srv != NULL) {
- dal_adapter_service_destroy(&pool->base.adapter_srv);
- }
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 5d53a0b9e8e1..950c505cde66 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -692,10 +692,6 @@ static void destruct(struct dce110_resource_pool *pool)
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
}
-
- if (pool->base.adapter_srv != NULL) {
- dal_adapter_service_destroy(&pool->base.adapter_srv);
- }
}
static struct clock_source *find_matching_pll(struct resource_context *res_ctx,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index 932f37559da9..1e38c9aacdad 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -609,10 +609,6 @@ static void destruct(struct dce110_resource_pool *pool)
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
}
-
- if (pool->base.adapter_srv != NULL) {
- dal_adapter_service_destroy(&pool->base.adapter_srv);
- }
}
static enum dc_status validate_mapped_resource(
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index 7b001f0aa9db..39adbbf25638 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -297,7 +297,6 @@ struct adapter_service {
struct dc_context *ctx;
struct asic_capability *asic_cap;
enum dce_environment dce_environment;
- struct i2caux *i2caux;
uint32_t platform_methods_mask;
uint32_t ac_level_percentage;
uint32_t dc_level_percentage;
@@ -371,10 +370,6 @@ bool dal_adapter_service_get_i2c_info(
struct graphics_object_id id,
struct graphics_object_i2c_info *i2c_info);
-/* Get i2c aux handler */
-struct i2caux *dal_adapter_service_get_i2caux(
- struct adapter_service *as);
-
struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags(
struct adapter_service *as);
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 25/76] drm/amd/dal: fix DDC pad mode detection logic
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (23 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 24/76] drm/amd/dal: instantiate i2caux outside of AS Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 26/76] drm/amd/dal: Fix MST crash by skipping branch connector Harry Wentland
` (51 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- use reg_helper macro for all register field access
- revise logic following golden CZ dal2 logic
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dc_helper.c | 12 +++++
drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c | 78 ++++++++++-------------------
drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h | 11 ++++
3 files changed, 50 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helper.c b/drivers/gpu/drm/amd/dal/dc/dc_helper.c
index 841d58b8cd7c..6ac801422c63 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/dal/dc/dc_helper.c
@@ -49,6 +49,18 @@ uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
return reg_val;
}
+uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
+ uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
+ uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
+ uint8_t shift3, uint32_t mask3, uint32_t *field_value3)
+{
+ uint32_t reg_val = dm_read_reg(ctx, addr);
+ *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
+ *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
+ *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
+ return reg_val;
+}
+
/* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer
* compiler won't be able to check for size match and is prone to stack corruption type of bugs
diff --git a/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
index e02843d32735..47e0f8f24a86 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c
@@ -66,7 +66,6 @@ static enum gpio_result set_config(
{
struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr);
struct hw_gpio *hw_gpio = NULL;
- uint32_t addr;
uint32_t regval;
uint32_t ddc_data_pd_en = 0;
uint32_t ddc_clk_pd_en = 0;
@@ -79,22 +78,10 @@ static enum gpio_result set_config(
return GPIO_RESULT_NULL_HANDLE;
}
- /* switch dual mode GPIO to I2C/AUX mode */
- addr = ddc->base.regs->MASK_reg;
-
- regval = REG_READ(gpio.MASK_reg);
-
- ddc_data_pd_en = get_reg_field_value_ex(
- regval,
- FN(,DC_GPIO_DDC1DATA_PD_EN));
-
- ddc_clk_pd_en = get_reg_field_value_ex(
- regval,
- FN(,DC_GPIO_DDC1CLK_PD_EN));
-
- aux_pad_mode = get_reg_field_value_ex(
- regval,
- FN(,AUX_PAD1_MODE));
+ regval = REG_GET_3(gpio.MASK_reg,
+ DC_GPIO_DDC1DATA_PD_EN, &ddc_data_pd_en,
+ DC_GPIO_DDC1CLK_PD_EN, &ddc_clk_pd_en,
+ AUX_PAD1_MODE, &aux_pad_mode);
switch (config_data->config.ddc.type) {
case GPIO_DDC_CONFIG_TYPE_MODE_I2C:
@@ -104,52 +91,39 @@ static enum gpio_result set_config(
* is required for detection of AUX mode */
if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) {
if (!ddc_data_pd_en || !ddc_clk_pd_en) {
- set_reg_field_value_ex(
- regval,
- 1,
- FN(,DC_GPIO_DDC1DATA_PD_EN));
-
- set_reg_field_value_ex(
- regval,
- 1,
- FN(,DC_GPIO_DDC1CLK_PD_EN));
- REG_WRITE(gpio.MASK_reg, regval);
+ REG_SET_2(gpio.MASK_reg, regval,
+ DC_GPIO_DDC1DATA_PD_EN, 1,
+ DC_GPIO_DDC1CLK_PD_EN, 1);
if (config_data->type ==
- GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
- /* should not affect normal I2C R/W */
- /* [anaumov] in DAL2, there was
- * dc_service_delay_in_microseconds(2500); */
+ GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
msleep(3);
}
} else {
- uint32_t reg2 = regval;
+ uint32_t reg2;
uint32_t sda_pd_dis = 0;
uint32_t scl_pd_dis = 0;
- sda_pd_dis = get_reg_field_value_ex(
- reg2,
- FN(,DC_GPIO_SDA_PD_DIS));
+ reg2 = REG_GET_2(gpio.MASK_reg,
+ DC_GPIO_SDA_PD_DIS, &sda_pd_dis,
+ DC_GPIO_SCL_PD_DIS, &scl_pd_dis);
- scl_pd_dis = get_reg_field_value_ex(
- reg2,
- FN(,DC_GPIO_SCL_PD_DIS));
+ if (sda_pd_dis) {
+ REG_SET(gpio.MASK_reg, regval,
+ DC_GPIO_SDA_PD_DIS, 0);
- if (sda_pd_dis)
- sda_pd_dis = 0;
-
- if (!scl_pd_dis)
- scl_pd_dis = 1;
+ if (config_data->type ==
+ GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
+ msleep(3);
+ }
- if (sda_pd_dis || !scl_pd_dis) {
- REG_WRITE(gpio.MASK_reg, reg2);
+ if (!scl_pd_dis) {
+ REG_SET(gpio.MASK_reg, regval,
+ DC_GPIO_SCL_PD_DIS, 1);
if (config_data->type ==
- GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
- /* should not affect normal I2C R/W */
- /* [anaumov] in DAL2, there was
- * dc_service_delay_in_microseconds(2500); */
+ GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE)
msleep(3);
}
}
@@ -166,14 +140,16 @@ static enum gpio_result set_config(
/* set the I2C pad mode */
/* read the register again,
* some bits may have been changed */
- REG_UPDATE(gpio.MASK_reg, AUX_PAD1_MODE, 1);
+ REG_UPDATE(gpio.MASK_reg,
+ AUX_PAD1_MODE, 0);
}
return GPIO_RESULT_OK;
case GPIO_DDC_CONFIG_TYPE_MODE_AUX:
/* set the AUX pad mode */
if (!aux_pad_mode) {
- REG_UPDATE(gpio.MASK_reg, AUX_PAD1_MODE, 1);
+ REG_SET(gpio.MASK_reg, regval,
+ AUX_PAD1_MODE, 1);
}
return GPIO_RESULT_OK;
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
index 1e3308dfb64a..ef652abcd276 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
@@ -113,6 +113,12 @@
FN(reg_name, f1), v1, \
FN(reg_name, f2), v2)
+#define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \
+ generic_reg_get3(CTX, REG(reg_name), \
+ FN(reg_name, f1), v1, \
+ FN(reg_name, f2), v2, \
+ FN(reg_name, f3), v3)
+
/* macro to poll and wait for a register field to read back given value */
#define REG_WAIT(reg_name, field, val, delay, max_try) \
@@ -224,4 +230,9 @@ uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2);
+uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
+ uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
+ uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
+ uint8_t shift3, uint32_t mask3, uint32_t *field_value3);
+
#endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_REG_HELPER_H_ */
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 26/76] drm/amd/dal: Fix MST crash by skipping branch connector.
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (24 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 25/76] drm/amd/dal: fix DDC pad mode detection logic Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 27/76] drm/amd/dal: Lower max link cap by reportedLinkCap Harry Wentland
` (50 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
index 66a6e5b566d9..6909dc80eb70 100644
--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -339,8 +339,10 @@ static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
drm_modeset_lock_all(dev);
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
aconnector = to_amdgpu_connector(connector);
- if (aconnector->port && aconnector->port->pdt != DP_PEER_DEVICE_NONE
- && !aconnector->dc_sink) {
+ if (aconnector->port &&
+ aconnector->port->pdt != DP_PEER_DEVICE_NONE &&
+ aconnector->port->pdt != DP_PEER_DEVICE_MST_BRANCHING &&
+ !aconnector->dc_sink) {
/*
* This is plug in case, where port has been created but
* sink hasn't been created yet
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 27/76] drm/amd/dal: Lower max link cap by reportedLinkCap
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (25 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 26/76] drm/amd/dal: Fix MST crash by skipping branch connector Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 28/76] drm/amd/dal: Allow timing with req_bw equal to max_bw Harry Wentland
` (49 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wenjing Liu
From: Wenjing Liu <Wenjing.Liu@amd.com>
[Description]
DP Compliance failure due to the max link cap is hard coded by feature
support.
Driver does not lower link cap based on receiver reported max link cap.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 30 +++++++++++++++++++---------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
index a2064acffcaa..c8de9af3a6c0 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
@@ -1076,17 +1076,31 @@ static bool exceeded_limit_link_setting(
true : false);
}
-static enum dc_link_rate get_max_link_rate(struct core_link *link)
+static struct dc_link_settings get_max_link_cap(struct core_link *link)
{
- enum dc_link_rate max_link_rate = LINK_RATE_HIGH;
+ /* Set Default link settings */
+ struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
+ LINK_SPREAD_05_DOWNSPREAD_30KHZ};
+ /* Higher link settings based on feature supported */
if (link->link_enc->features.flags.bits.IS_HBR2_CAPABLE)
- max_link_rate = LINK_RATE_HIGH2;
+ max_link_cap.link_rate = LINK_RATE_HIGH2;
if (link->link_enc->features.flags.bits.IS_HBR3_CAPABLE)
- max_link_rate = LINK_RATE_HIGH3;
-
- return max_link_rate;
+ max_link_cap.link_rate = LINK_RATE_HIGH3;
+
+ /* Lower link settings based on sink's link cap */
+ if (link->public.reported_link_cap.lane_count < max_link_cap.lane_count)
+ max_link_cap.lane_count =
+ link->public.reported_link_cap.lane_count;
+ if (link->public.reported_link_cap.link_rate < max_link_cap.link_rate)
+ max_link_cap.link_rate =
+ link->public.reported_link_cap.link_rate;
+ if (link->public.reported_link_cap.link_spread <
+ max_link_cap.link_spread)
+ max_link_cap.link_spread =
+ link->public.reported_link_cap.link_spread;
+ return max_link_cap;
}
bool dp_hbr_verify_link_cap(
@@ -1105,9 +1119,7 @@ bool dp_hbr_verify_link_cap(
success = false;
skip_link_training = false;
- max_link_cap.lane_count = LANE_COUNT_FOUR;
- max_link_cap.link_rate = get_max_link_rate(link);
- max_link_cap.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
+ max_link_cap = get_max_link_cap(link);
/* TODO implement override and monitor patch later */
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 28/76] drm/amd/dal: Allow timing with req_bw equal to max_bw
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (26 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 27/76] drm/amd/dal: Lower max link cap by reportedLinkCap Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 29/76] drm/amd/dal: Perform link training in dp_retrain_link Harry Wentland
` (48 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wenjing Liu
From: Wenjing Liu <Wenjing.Liu@amd.com>
[Description]
Dp compliance fails when receiver requests timing utilizing
the full bandwidth of the link
We report not supported if req_bw is equal to max_bw
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
index c8de9af3a6c0..80213a278d28 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
@@ -1285,7 +1285,7 @@ bool dp_validate_mode_timing(
req_bw = bandwidth_in_kbps_from_timing(timing);
max_bw = bandwidth_in_kbps_from_link_settings(link_setting);
- if (req_bw < max_bw) {
+ if (req_bw <= max_bw) {
/* remember the biggest mode here, during
* initial link training (to get
* verified_link_cap), LS sends event about
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 29/76] drm/amd/dal: Perform link training in dp_retrain_link
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (27 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 28/76] drm/amd/dal: Allow timing with req_bw equal to max_bw Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 30/76] drm/amd/dal: Poll AUX_SW_DONE to 0 before AUX_SW_GO Harry Wentland
` (47 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wenjing Liu
From: Wenjing Liu <Wenjing.Liu@amd.com>
[Description]
dp_retrain_link re-enables stream.
However dp link training is not included in enable_stream
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
index bc240981d276..e89f5f176ec3 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
@@ -8,6 +8,7 @@
#include "include/i2caux_interface.h"
#include "link_hwss.h"
#include "hw_sequencer.h"
+#include "dc_link_dp.h"
#include "dc_link_ddc.h"
#include "dm_helpers.h"
#include "dce/dce_link_encoder.h"
@@ -209,6 +210,10 @@ void dp_retrain_link(struct core_link *link)
dm_delay_in_microseconds(link->ctx, 100);
pipes->stream_enc->funcs->dp_blank(pipes[i].stream_enc);
link->dc->hwss.disable_stream(&pipes[i]);
+ dc_link_dp_perform_link_training(
+ &link->public,
+ &link->public.verified_link_cap,
+ true);
link->dc->hwss.enable_stream(&pipes[i]);
link->dc->hwss.unblank_stream(&pipes[i],
&link->public.verified_link_cap);
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 30/76] drm/amd/dal: Poll AUX_SW_DONE to 0 before AUX_SW_GO
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (28 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 29/76] drm/amd/dal: Perform link training in dp_retrain_link Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 31/76] drm/amd/dal: Fallback LT without retry in verify_link_cap Harry Wentland
` (46 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wenjing Liu
From: Wenjing Liu <Wenjing.Liu@amd.com>
[Description]
There is an intermittent issue where driver fails aux channel error DP
compliance test.
The test will fail to reply aux messages and expect driver to retry.
Driver misinterprets it as an Nack and doesn't retry.
Driver resets AUX_SW_DONE and assumes it will take effect immediately.
In some cases, the AUX_SW_DONE will not be updated
before drivers check if the current transaction is done.
Driver reads the previous set done bit and thinks reply is obtained.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
index 79d67691ca63..c112bdd5e7ab 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
@@ -249,7 +249,8 @@ static void submit_channel_request(
}
REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
-
+ REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
+ 10, aux110->timeout_period/10);
REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
}
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 31/76] drm/amd/dal: Fallback LT without retry in verify_link_cap
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (29 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 30/76] drm/amd/dal: Poll AUX_SW_DONE to 0 before AUX_SW_GO Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 32/76] drm/amd/dal: Remove adapter service dependency in power_down Harry Wentland
` (45 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wenjing Liu
From: Wenjing Liu <Wenjing.Liu@amd.com>
[Description]
Dp compliance test will test if LT fallback to the next lower link settings
by intentionally fails link training.
Due to the retry logic in verify link cap, driver retrains link with
the same settings.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
index 80213a278d28..b7c4b5899dcd 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
@@ -1166,11 +1166,10 @@ bool dp_hbr_verify_link_cap(
if (skip_link_training)
success = true;
else {
- success = perform_link_training_with_retries(
- link,
- cur,
- skip_video_pattern,
- LINK_TRAINING_ATTEMPTS);
+ success = dc_link_dp_perform_link_training(
+ &link->public,
+ cur,
+ skip_video_pattern);
}
if (success)
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 32/76] drm/amd/dal: Remove adapter service dependency in power_down
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (30 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 31/76] drm/amd/dal: Fallback LT without retry in verify_link_cap Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 33/76] drm/amd/dal: remove supported_stream_engines Harry Wentland
` (44 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
index 670d7f3987d0..fef7bc4c33cb 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
@@ -1360,7 +1360,7 @@ void dce110_link_encoder_disable_output(
struct bp_transmitter_control cntl = { 0 };
enum bp_result result;
- if (!is_dig_enabled(enc110) &&
+ if (!is_dig_enabled(enc110) && enc110->base.adapter_service &&
dal_adapter_service_should_optimize(
enc110->base.adapter_service,
OF_SKIP_POWER_DOWN_INACTIVE_ENCODER)) {
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 33/76] drm/amd/dal: remove supported_stream_engines
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (31 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 32/76] drm/amd/dal: Remove adapter service dependency in power_down Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 34/76] drm/amd/dal: Rotation and mirror support Harry Wentland
` (43 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- unnecesasry. DIG always start from instance 0
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 10 +++-------
drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 7 -------
drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 6 ------
drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 7 -------
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 7 -------
drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 3 ---
drivers/gpu/drm/amd/dal/include/grph_object_id.h | 16 ----------------
7 files changed, 3 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index 0c02894cef26..22bfa45292e6 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -175,13 +175,9 @@ bool resource_construct(
pool->stream_enc_count = 0;
if (create_funcs->create_stream_encoder) {
for (i = 0; i < caps->num_stream_encoder; i++) {
- /* TODO: rework fragile code*/
- if (pool->stream_engines.u_all & 1 << i) {
- pool->stream_enc[i] = create_funcs->create_stream_encoder(
- i, ctx);
- if (pool->stream_enc[i] == NULL)
- DC_ERR("DC: failed to create stream_encoder!\n");
- }
+ pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
+ if (pool->stream_enc[i] == NULL)
+ DC_ERR("DC: failed to create stream_encoder!\n");
pool->stream_enc_count++;
}
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 81319166ed16..5c97be9925f9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -868,13 +868,6 @@ static bool construct(
pool->base.funcs = &dce100_res_pool_funcs;
pool->base.underlay_pipe_index = -1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGA = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGB = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGC = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGD = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGE = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGF = 1;
-
bp = ctx->dc_bios;
if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 15958e6cedd1..ef0af3a72ccd 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -1198,12 +1198,6 @@ static bool construct(
/*************************************************
* Create resources *
*************************************************/
- pool->base.stream_engines.engine.ENGINE_ID_DIGA = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGB = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGC = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGD = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGE = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGF = 1;
bp = ctx->dc_bios;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 950c505cde66..6e6bd9c9568d 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -1206,13 +1206,6 @@ static bool construct(
* Create resources *
*************************************************/
- pool->base.stream_engines.engine.ENGINE_ID_DIGA = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGB = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGC = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGD = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGE = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGF = 1;
-
pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
dce112_clock_source_create(
ctx, ctx->dc_bios,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index 1e38c9aacdad..d470f5cd0942 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -873,13 +873,6 @@ static bool construct(
* Create resources *
*************************************************/
- pool->base.stream_engines.engine.ENGINE_ID_DIGA = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGB = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGC = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGD = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGE = 1;
- pool->base.stream_engines.engine.ENGINE_ID_DIGF = 1;
-
bp = ctx->dc_bios;
if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
index 2c0072265d8b..4ed88728a54d 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
@@ -251,8 +251,6 @@ struct resource_pool {
unsigned int underlay_pipe_index;
unsigned int stream_enc_count;
- union supported_stream_engines stream_engines;
-
/*
* reserved clock source for DP
*/
@@ -306,7 +304,6 @@ struct pipe_ctx {
struct resource_context {
const struct resource_pool *pool;
struct pipe_ctx pipe_ctx[MAX_PIPES];
- union supported_stream_engines used_stream_engines;
bool is_stream_enc_acquired[MAX_PIPES * 2];
bool is_audio_acquired[MAX_PIPES];
uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_id.h b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
index 9ad7620e8ee8..e4aa4ddf9d2a 100644
--- a/drivers/gpu/drm/amd/dal/include/grph_object_id.h
+++ b/drivers/gpu/drm/amd/dal/include/grph_object_id.h
@@ -190,22 +190,6 @@ enum engine_id {
ENGINE_ID_UNKNOWN = (-1L)
};
-union supported_stream_engines {
- struct {
- uint32_t ENGINE_ID_DIGA:1;
- uint32_t ENGINE_ID_DIGB:1;
- uint32_t ENGINE_ID_DIGC:1;
- uint32_t ENGINE_ID_DIGD:1;
- uint32_t ENGINE_ID_DIGE:1;
- uint32_t ENGINE_ID_DIGF:1;
- uint32_t ENGINE_ID_DIGG:1;
- uint32_t ENGINE_ID_DACA:1;
- uint32_t ENGINE_ID_DACB:1;
- uint32_t ENGINE_ID_VCE:1;
- } engine;
- uint32_t u_all;
-};
-
enum transmitter_color_depth {
TRANSMITTER_COLOR_DEPTH_24 = 0, /* 8 bits */
TRANSMITTER_COLOR_DEPTH_30, /* 10 bits */
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 34/76] drm/amd/dal: Rotation and mirror support
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (32 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 33/76] drm/amd/dal: remove supported_stream_engines Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 35/76] drm/amd/dal: Pass in shift and mask for stream encoder Harry Wentland
` (42 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Vitaly Prosyak
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
When rotation is 90 and 270 ,the stream dimentions
should be swaped for view port calculation
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index 22bfa45292e6..4c93d539ef8a 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -380,7 +380,7 @@ static void calculate_viewport(
const struct dc_surface *surface,
struct pipe_ctx *pipe_ctx)
{
- const struct rect stream_src = pipe_ctx->stream->public.src;
+ struct rect stream_src = pipe_ctx->stream->public.src;
struct rect src = surface->src_rect;
struct rect dst = surface->dst_rect;
struct rect surface_clip = surface->clip_rect;
@@ -388,10 +388,11 @@ static void calculate_viewport(
if (surface->rotation == ROTATION_ANGLE_90 ||
- surface->rotation == ROTATION_ANGLE_270){
+ surface->rotation == ROTATION_ANGLE_270) {
rect_swap_helper(&src);
rect_swap_helper(&dst);
rect_swap_helper(&surface_clip);
+ rect_swap_helper(&stream_src);
}
/* The actual clip is an intersection between stream
@@ -514,7 +515,6 @@ bool resource_build_scaling_params(
{
bool res;
struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing;
-
/* Important: scaling ratio calculation requires pixel format,
* lb depth calculation requires recout and taps require scaling ratios.
*/
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 35/76] drm/amd/dal: Pass in shift and mask for stream encoder.
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (33 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 34/76] drm/amd/dal: Rotation and mirror support Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 36/76] drm/amd/dal: Fixed wrong return value check condition Harry Wentland
` (41 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zeyu Fan
From: Zeyu Fan <Zeyu.Fan@amd.com>
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c | 175 ++++++-----
.../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h | 330 ++++++++++++++++++++-
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 12 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 11 +-
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 11 +-
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 11 +-
6 files changed, 449 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
index 079734700c15..e0654793e6b7 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
@@ -35,6 +35,10 @@
#define REG(reg)\
(enc110->regs->reg)
+#undef FN
+#define FN(reg_name, field_name) \
+ enc110->se_shift->field_name, enc110->se_mask->field_name
+
#define VBI_LINE_0 0
#define DP_BLANK_MAX_RETRY 20
#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
@@ -102,11 +106,14 @@ static void dce110_update_generic_info_packet(
}
/* force double-buffered packet update */
- {
+ if (enc110->se_mask->AFMT_GENERIC0_UPDATE &&
+ enc110->se_mask->AFMT_GENERIC2_UPDATE) {
REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
AFMT_GENERIC0_UPDATE, (packet_index == 0),
AFMT_GENERIC2_UPDATE, (packet_index == 2));
-
+ } else {
+ ASSERT(enc110->se_mask->AFMT_GENERIC0_UPDATE);
+ ASSERT(enc110->se_mask->AFMT_GENERIC2_UPDATE);
}
}
@@ -234,12 +241,15 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
}
/* set dynamic range and YCbCr range */
-
- REG_UPDATE_2(
- DP_PIXEL_FORMAT,
- DP_DYN_RANGE, 0,
- DP_YCBCR_RANGE, 0);
-
+ if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) {
+ REG_UPDATE_2(
+ DP_PIXEL_FORMAT,
+ DP_DYN_RANGE, 0,
+ DP_YCBCR_RANGE, 0);
+ } else {
+ ASSERT(enc110->se_mask->DP_DYN_RANGE);
+ ASSERT(enc110->se_mask->DP_YCBCR_RANGE);
+ }
}
@@ -294,13 +304,12 @@ static void dce110_stream_encoder_hdmi_set_stream_attribute(
dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
- /* setup HDMI engine */
- REG_UPDATE_5(HDMI_CONTROL,
- HDMI_PACKET_GEN_VERSION, 1,
- HDMI_KEEPOUT_MODE, 1,
- HDMI_DEEP_COLOR_ENABLE, 0,
- HDMI_DATA_SCRAMBLE_EN, 0,
- HDMI_CLOCK_CHANNEL_RATE, 0);
+ if (enc110->regs->DIG_FE_CNTL) {
+ REG_UPDATE_3(HDMI_CONTROL,
+ HDMI_PACKET_GEN_VERSION, 1,
+ HDMI_KEEPOUT_MODE, 1,
+ HDMI_DEEP_COLOR_ENABLE, 0);
+ }
switch (crtc_timing->display_color_depth) {
case COLOR_DEPTH_888:
@@ -325,28 +334,6 @@ static void dce110_stream_encoder_hdmi_set_stream_attribute(
break;
}
- if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
- /* enable HDMI data scrambler
- * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
- * Clock channel frequency is 1/4 of character rate.
- */
- REG_UPDATE_2(HDMI_CONTROL,
- HDMI_DATA_SCRAMBLE_EN, 1,
- HDMI_CLOCK_CHANNEL_RATE, 1);
- } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
-
- /* TODO: New feature for DCE11, still need to implement */
-
- /* enable HDMI data scrambler
- * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
- * Clock channel frequency is the same
- * as character rate
- */
- REG_UPDATE_2(HDMI_CONTROL,
- HDMI_DATA_SCRAMBLE_EN, 1,
- HDMI_CLOCK_CHANNEL_RATE, 0);
- }
-
REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
HDMI_GC_CONT, 1,
HDMI_GC_SEND, 1,
@@ -396,9 +383,6 @@ static void dce110_stream_encoder_set_mst_bandwidth(
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
struct dc_context *ctx = enc110->base.ctx;
- uint32_t addr;
- uint32_t field;
- uint32_t value;
uint32_t retries = 0;
uint32_t x = dal_fixed31_32_floor(
avg_time_slots_per_mtp);
@@ -418,26 +402,9 @@ static void dce110_stream_encoder_set_mst_bandwidth(
/* wait for update to be completed on the link */
/* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
/* is reset to 0 (not pending) */
- {
- addr = REG(DP_MSE_RATE_UPDATE);
-
- do {
- value = dm_read_reg(ctx, addr);
-
- field = get_reg_field_value(
- value,
- DP_MSE_RATE_UPDATE,
- DP_MSE_RATE_UPDATE_PENDING);
-
- if (!(field &
- DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK))
- break;
-
- udelay(10);
-
- ++retries;
- } while (retries < DP_MST_UPDATE_MAX_RETRY);
- }
+ REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
+ enc110->se_mask->DP_MSE_RATE_UPDATE_PENDING,
+ 10, DP_MST_UPDATE_MAX_RETRY);
}
static void dce110_stream_encoder_update_hdmi_info_packets(
@@ -446,33 +413,40 @@ static void dce110_stream_encoder_update_hdmi_info_packets(
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- if (info_frame->avi.valid) {
- const uint32_t *content =
- (const uint32_t *) &info_frame->avi.sb[0];
+ if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
+ enc110->se_mask->HDMI_AVI_INFO_SEND) {
+ if (info_frame->avi.valid) {
+ const uint32_t *content =
+ (const uint32_t *) &info_frame->avi.sb[0];
- REG_WRITE(AFMT_AVI_INFO0, content[0]);
+ REG_WRITE(AFMT_AVI_INFO0, content[0]);
- REG_WRITE(AFMT_AVI_INFO1, content[1]);
+ REG_WRITE(AFMT_AVI_INFO1, content[1]);
- REG_WRITE(AFMT_AVI_INFO2, content[2]);
+ REG_WRITE(AFMT_AVI_INFO2, content[2]);
- REG_WRITE(AFMT_AVI_INFO3, content[3]);
+ REG_WRITE(AFMT_AVI_INFO3, content[3]);
- REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
- info_frame->avi.hb1);
+ REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
+ info_frame->avi.hb1);
- REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
- HDMI_AVI_INFO_SEND, 1,
- HDMI_AVI_INFO_CONT, 1);
+ REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
+ HDMI_AVI_INFO_SEND, 1,
+ HDMI_AVI_INFO_CONT, 1);
- REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
- VBI_LINE_0 + 2);
+ REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
+ VBI_LINE_0 + 2);
+ } else {
+ REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
+ HDMI_AVI_INFO_SEND, 0,
+ HDMI_AVI_INFO_CONT, 0);
+ }
} else {
- REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
- HDMI_AVI_INFO_SEND, 0,
- HDMI_AVI_INFO_CONT, 0);
+ ASSERT(enc110->se_mask->HDMI_AVI_INFO_SEND);
+ ASSERT(enc110->se_mask->HDMI_AVI_INFO_CONT);
+ ASSERT(enc110->se_mask->HDMI_AVI_INFO_LINE);
}
dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
@@ -504,9 +478,16 @@ static void dce110_stream_encoder_stop_hdmi_info_packets(
HDMI_GENERIC3_SEND, 0);
/* stop AVI packet on HDMI */
- REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
- HDMI_AVI_INFO_SEND, 0,
- HDMI_AVI_INFO_CONT, 0);
+ if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
+ enc110->se_mask->HDMI_AVI_INFO_SEND) {
+
+ REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
+ HDMI_AVI_INFO_SEND, 0,
+ HDMI_AVI_INFO_CONT, 0);
+ } else {
+ ASSERT(enc110->se_mask->HDMI_AVI_INFO_SEND);
+ ASSERT(enc110->se_mask->HDMI_AVI_INFO_CONT);
+ }
}
static void dce110_stream_encoder_update_dp_info_packets(
@@ -545,15 +526,25 @@ static void dce110_stream_encoder_stop_dp_info_packets(
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t value = REG_READ(DP_SEC_CNTL);
- REG_SET_7(DP_SEC_CNTL, 0,
- DP_SEC_GSP0_ENABLE, 0,
- DP_SEC_GSP1_ENABLE, 0,
- DP_SEC_GSP2_ENABLE, 0,
- DP_SEC_GSP3_ENABLE, 0,
- DP_SEC_AVI_ENABLE, 0,
- DP_SEC_MPG_ENABLE, 0,
- DP_SEC_STREAM_ENABLE, 0);
-
+ if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
+ REG_SET_7(DP_SEC_CNTL, 0,
+ DP_SEC_GSP0_ENABLE, 0,
+ DP_SEC_GSP1_ENABLE, 0,
+ DP_SEC_GSP2_ENABLE, 0,
+ DP_SEC_GSP3_ENABLE, 0,
+ DP_SEC_AVI_ENABLE, 0,
+ DP_SEC_MPG_ENABLE, 0,
+ DP_SEC_STREAM_ENABLE, 0);
+ } else {
+ ASSERT(enc110->se_mask->DP_SEC_AVI_ENABLE);
+ REG_SET_6(DP_SEC_CNTL, 0,
+ DP_SEC_GSP0_ENABLE, 0,
+ DP_SEC_GSP1_ENABLE, 0,
+ DP_SEC_GSP2_ENABLE, 0,
+ DP_SEC_GSP3_ENABLE, 0,
+ DP_SEC_MPG_ENABLE, 0,
+ DP_SEC_STREAM_ENABLE, 0);
+ }
/* this register shared with audio info frame.
* therefore we need to keep master enabled
* if at least one of the fields is not 0 */
@@ -1252,7 +1243,9 @@ bool dce110_stream_encoder_construct(
struct dc_context *ctx,
struct dc_bios *bp,
enum engine_id eng_id,
- const struct dce110_stream_enc_registers *regs)
+ const struct dce110_stream_enc_registers *regs,
+ const struct dce_stream_encoder_shift *se_shift,
+ const struct dce_stream_encoder_mask *se_mask)
{
if (!enc110)
return false;
@@ -1264,6 +1257,8 @@ bool dce110_stream_encoder_construct(
enc110->base.id = eng_id;
enc110->base.bp = bp;
enc110->regs = regs;
+ enc110->se_shift = se_shift;
+ enc110->se_mask = se_mask;
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
index 7c29c84bbcff..c6bb95888cc0 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
@@ -31,13 +31,20 @@
#define DCE110STRENC_FROM_STRENC(stream_encoder)\
container_of(stream_encoder, struct dce110_stream_encoder, base)
+#ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
+ #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L
+ #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L
+ #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004
+ #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008
+#endif
+
#define SE_COMMON_REG_LIST_DCE_BASE(id) \
- SE_COMMON_REG_LIST_BASE(id),\
- SRI(AFMT_AVI_INFO0, DIG, id), \
- SRI(AFMT_AVI_INFO1, DIG, id), \
- SRI(AFMT_AVI_INFO2, DIG, id), \
- SRI(AFMT_AVI_INFO3, DIG, id)
+ SE_COMMON_REG_LIST_BASE(id),\
+ SRI(AFMT_AVI_INFO0, DIG, id), \
+ SRI(AFMT_AVI_INFO1, DIG, id), \
+ SRI(AFMT_AVI_INFO2, DIG, id), \
+ SRI(AFMT_AVI_INFO3, DIG, id)
#define SE_COMMON_REG_LIST_BASE(id) \
SRI(AFMT_GENERIC_0, DIG, id), \
@@ -90,6 +97,313 @@
SE_COMMON_REG_LIST_DCE_BASE(id), \
SRI(AFMT_CNTL, DIG, id)
+
+#define SE_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
+ SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
+ SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
+ SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
+ SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
+ SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
+ SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
+ SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
+ SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
+ SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
+ SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
+ SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
+ SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
+ SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
+ SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC2_CONT, mask_sh),\
+ SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC2_SEND, mask_sh),\
+ SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC2_LINE, mask_sh),\
+ SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC3_CONT, mask_sh),\
+ SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC3_SEND, mask_sh),\
+ SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC3_LINE, mask_sh),\
+ SE_SF(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
+ SE_SF(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
+ SE_SF(DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
+ SE_SF(DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
+ SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
+ SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
+ SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
+ SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
+ SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
+ SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
+ SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
+ SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
+ SE_SF(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
+ SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
+ SE_SF(HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
+ SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
+ SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
+ SE_SF(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
+ SE_SF(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
+ SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
+ SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
+ SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
+ SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
+ SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
+ SE_SF(DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
+ SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
+ SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
+ SE_SF(DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
+ SE_SF(DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
+ SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
+ SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
+ SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
+ SE_SF(DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
+ SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
+ SE_SF(DP_VID_N, DP_VID_N, mask_sh),\
+ SE_SF(DP_VID_M, DP_VID_M, mask_sh),\
+ SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
+ SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
+ SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
+ SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
+ SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
+ SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
+ SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
+ SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
+ SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
+ SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
+ SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
+ SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
+ SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
+ SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
+ SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
+ SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
+ SE_SF(HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
+ SE_SF(AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
+ SE_SF(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
+ SE_SF(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
+ SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
+ SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
+ SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
+ SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
+ SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
+ SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
+ SE_SF(DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
+ SE_SF(DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
+ SE_SF(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
+ SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
+ SE_SF(DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
+ SE_SF(DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
+ SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh)
+
+#define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\
+ SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
+
+#define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\
+ SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
+ SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
+ SE_SF(TMDS_CNTL, TMDS_COLOR_FORMAT, mask_sh)
+
+#define SE_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
+ SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
+ SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
+ SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
+ SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
+ SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh)
+
+#define SE_COMMON_MASK_SH_LIST_DCE112(mask_sh)\
+ SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
+ SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
+ SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
+ SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
+ SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
+ SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
+
+struct dce_stream_encoder_shift {
+ uint8_t AFMT_GENERIC_INDEX;
+ uint8_t AFMT_GENERIC0_UPDATE;
+ uint8_t AFMT_GENERIC2_UPDATE;
+ uint8_t AFMT_GENERIC_HB0;
+ uint8_t AFMT_GENERIC_HB1;
+ uint8_t AFMT_GENERIC_HB2;
+ uint8_t AFMT_GENERIC_HB3;
+ uint8_t HDMI_GENERIC0_CONT;
+ uint8_t HDMI_GENERIC0_SEND;
+ uint8_t HDMI_GENERIC0_LINE;
+ uint8_t HDMI_GENERIC1_CONT;
+ uint8_t HDMI_GENERIC1_SEND;
+ uint8_t HDMI_GENERIC1_LINE;
+ uint8_t HDMI_GENERIC2_CONT;
+ uint8_t HDMI_GENERIC2_SEND;
+ uint8_t HDMI_GENERIC2_LINE;
+ uint8_t HDMI_GENERIC3_CONT;
+ uint8_t HDMI_GENERIC3_SEND;
+ uint8_t HDMI_GENERIC3_LINE;
+ uint8_t DP_PIXEL_ENCODING;
+ uint8_t DP_COMPONENT_DEPTH;
+ uint8_t DP_DYN_RANGE;
+ uint8_t DP_YCBCR_RANGE;
+ uint8_t HDMI_PACKET_GEN_VERSION;
+ uint8_t HDMI_KEEPOUT_MODE;
+ uint8_t HDMI_DEEP_COLOR_ENABLE;
+ uint8_t HDMI_CLOCK_CHANNEL_RATE;
+ uint8_t HDMI_DEEP_COLOR_DEPTH;
+ uint8_t HDMI_GC_CONT;
+ uint8_t HDMI_GC_SEND;
+ uint8_t HDMI_NULL_SEND;
+ uint8_t HDMI_AUDIO_INFO_SEND;
+ uint8_t AFMT_AUDIO_INFO_UPDATE;
+ uint8_t HDMI_AUDIO_INFO_LINE;
+ uint8_t HDMI_GC_AVMUTE;
+ uint8_t DP_MSE_RATE_X;
+ uint8_t DP_MSE_RATE_Y;
+ uint8_t DP_MSE_RATE_UPDATE_PENDING;
+ uint8_t AFMT_AVI_INFO_VERSION;
+ uint8_t HDMI_AVI_INFO_SEND;
+ uint8_t HDMI_AVI_INFO_CONT;
+ uint8_t HDMI_AVI_INFO_LINE;
+ uint8_t DP_SEC_GSP0_ENABLE;
+ uint8_t DP_SEC_STREAM_ENABLE;
+ uint8_t DP_SEC_GSP1_ENABLE;
+ uint8_t DP_SEC_GSP2_ENABLE;
+ uint8_t DP_SEC_GSP3_ENABLE;
+ uint8_t DP_SEC_AVI_ENABLE;
+ uint8_t DP_SEC_MPG_ENABLE;
+ uint8_t DP_VID_STREAM_DIS_DEFER;
+ uint8_t DP_VID_STREAM_ENABLE;
+ uint8_t DP_VID_STREAM_STATUS;
+ uint8_t DP_STEER_FIFO_RESET;
+ uint8_t DP_VID_M_N_GEN_EN;
+ uint8_t DP_VID_N;
+ uint8_t DP_VID_M;
+ uint8_t DIG_START;
+ uint8_t AFMT_AUDIO_SRC_SELECT;
+ uint8_t AFMT_AUDIO_CHANNEL_ENABLE;
+ uint8_t HDMI_AUDIO_PACKETS_PER_LINE;
+ uint8_t HDMI_AUDIO_DELAY_EN;
+ uint8_t AFMT_60958_CS_UPDATE;
+ uint8_t AFMT_AUDIO_LAYOUT_OVRD;
+ uint8_t AFMT_60958_OSF_OVRD;
+ uint8_t HDMI_ACR_AUTO_SEND;
+ uint8_t HDMI_ACR_SOURCE;
+ uint8_t HDMI_ACR_AUDIO_PRIORITY;
+ uint8_t HDMI_ACR_CTS_32;
+ uint8_t HDMI_ACR_N_32;
+ uint8_t HDMI_ACR_CTS_44;
+ uint8_t HDMI_ACR_N_44;
+ uint8_t HDMI_ACR_CTS_48;
+ uint8_t HDMI_ACR_N_48;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_L;
+ uint8_t AFMT_60958_CS_CLOCK_ACCURACY;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_R;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_2;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_3;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_4;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_5;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_6;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_7;
+ uint8_t DP_SEC_AUD_N;
+ uint8_t DP_SEC_TIMESTAMP_MODE;
+ uint8_t DP_SEC_ASP_ENABLE;
+ uint8_t DP_SEC_ATP_ENABLE;
+ uint8_t DP_SEC_AIP_ENABLE;
+ uint8_t DP_SEC_ACM_ENABLE;
+ uint8_t AFMT_AUDIO_SAMPLE_SEND;
+ uint8_t AFMT_AUDIO_CLOCK_EN;
+ uint8_t TMDS_PIXEL_ENCODING;
+ uint8_t TMDS_COLOR_FORMAT;
+};
+
+struct dce_stream_encoder_mask {
+ uint32_t AFMT_GENERIC_INDEX;
+ uint32_t AFMT_GENERIC0_UPDATE;
+ uint32_t AFMT_GENERIC2_UPDATE;
+ uint32_t AFMT_GENERIC_HB0;
+ uint32_t AFMT_GENERIC_HB1;
+ uint32_t AFMT_GENERIC_HB2;
+ uint32_t AFMT_GENERIC_HB3;
+ uint32_t HDMI_GENERIC0_CONT;
+ uint32_t HDMI_GENERIC0_SEND;
+ uint32_t HDMI_GENERIC0_LINE;
+ uint32_t HDMI_GENERIC1_CONT;
+ uint32_t HDMI_GENERIC1_SEND;
+ uint32_t HDMI_GENERIC1_LINE;
+ uint32_t HDMI_GENERIC2_CONT;
+ uint32_t HDMI_GENERIC2_SEND;
+ uint32_t HDMI_GENERIC2_LINE;
+ uint32_t HDMI_GENERIC3_CONT;
+ uint32_t HDMI_GENERIC3_SEND;
+ uint32_t HDMI_GENERIC3_LINE;
+ uint32_t DP_PIXEL_ENCODING;
+ uint32_t DP_COMPONENT_DEPTH;
+ uint32_t DP_DYN_RANGE;
+ uint32_t DP_YCBCR_RANGE;
+ uint32_t HDMI_PACKET_GEN_VERSION;
+ uint32_t HDMI_KEEPOUT_MODE;
+ uint32_t HDMI_DEEP_COLOR_ENABLE;
+ uint32_t HDMI_CLOCK_CHANNEL_RATE;
+ uint32_t HDMI_DEEP_COLOR_DEPTH;
+ uint32_t HDMI_GC_CONT;
+ uint32_t HDMI_GC_SEND;
+ uint32_t HDMI_NULL_SEND;
+ uint32_t HDMI_AUDIO_INFO_SEND;
+ uint32_t AFMT_AUDIO_INFO_UPDATE;
+ uint32_t HDMI_AUDIO_INFO_LINE;
+ uint32_t HDMI_GC_AVMUTE;
+ uint32_t DP_MSE_RATE_X;
+ uint32_t DP_MSE_RATE_Y;
+ uint32_t DP_MSE_RATE_UPDATE_PENDING;
+ uint32_t AFMT_AVI_INFO_VERSION;
+ uint32_t HDMI_AVI_INFO_SEND;
+ uint32_t HDMI_AVI_INFO_CONT;
+ uint32_t HDMI_AVI_INFO_LINE;
+ uint32_t DP_SEC_GSP0_ENABLE;
+ uint32_t DP_SEC_STREAM_ENABLE;
+ uint32_t DP_SEC_GSP1_ENABLE;
+ uint32_t DP_SEC_GSP2_ENABLE;
+ uint32_t DP_SEC_GSP3_ENABLE;
+ uint32_t DP_SEC_AVI_ENABLE;
+ uint32_t DP_SEC_MPG_ENABLE;
+ uint32_t DP_VID_STREAM_DIS_DEFER;
+ uint32_t DP_VID_STREAM_ENABLE;
+ uint32_t DP_VID_STREAM_STATUS;
+ uint32_t DP_STEER_FIFO_RESET;
+ uint32_t DP_VID_M_N_GEN_EN;
+ uint32_t DP_VID_N;
+ uint32_t DP_VID_M;
+ uint32_t DIG_START;
+ uint32_t AFMT_AUDIO_SRC_SELECT;
+ uint32_t AFMT_AUDIO_CHANNEL_ENABLE;
+ uint32_t HDMI_AUDIO_PACKETS_PER_LINE;
+ uint32_t HDMI_AUDIO_DELAY_EN;
+ uint32_t AFMT_60958_CS_UPDATE;
+ uint32_t AFMT_AUDIO_LAYOUT_OVRD;
+ uint32_t AFMT_60958_OSF_OVRD;
+ uint32_t HDMI_ACR_AUTO_SEND;
+ uint32_t HDMI_ACR_SOURCE;
+ uint32_t HDMI_ACR_AUDIO_PRIORITY;
+ uint32_t HDMI_ACR_CTS_32;
+ uint32_t HDMI_ACR_N_32;
+ uint32_t HDMI_ACR_CTS_44;
+ uint32_t HDMI_ACR_N_44;
+ uint32_t HDMI_ACR_CTS_48;
+ uint32_t HDMI_ACR_N_48;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_L;
+ uint32_t AFMT_60958_CS_CLOCK_ACCURACY;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_R;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_2;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_3;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_4;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_5;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_6;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_7;
+ uint32_t DP_SEC_AUD_N;
+ uint32_t DP_SEC_TIMESTAMP_MODE;
+ uint32_t DP_SEC_ASP_ENABLE;
+ uint32_t DP_SEC_ATP_ENABLE;
+ uint32_t DP_SEC_AIP_ENABLE;
+ uint32_t DP_SEC_ACM_ENABLE;
+ uint32_t AFMT_AUDIO_SAMPLE_SEND;
+ uint32_t AFMT_AUDIO_CLOCK_EN;
+ uint32_t TMDS_PIXEL_ENCODING;
+ uint32_t TMDS_COLOR_FORMAT;
+};
+
struct dce110_stream_enc_registers {
uint32_t AFMT_CNTL;
uint32_t AFMT_AVI_INFO0;
@@ -146,6 +460,8 @@ struct dce110_stream_enc_registers {
struct dce110_stream_encoder {
struct stream_encoder base;
const struct dce110_stream_enc_registers *regs;
+ const struct dce_stream_encoder_shift *se_shift;
+ const struct dce_stream_encoder_mask *se_mask;
};
bool dce110_stream_encoder_construct(
@@ -153,7 +469,9 @@ bool dce110_stream_encoder_construct(
struct dc_context *ctx,
struct dc_bios *bp,
enum engine_id eng_id,
- const struct dce110_stream_enc_registers *regs);
+ const struct dce110_stream_enc_registers *regs,
+ const struct dce_stream_encoder_shift *se_shift,
+ const struct dce_stream_encoder_mask *se_mask);
void dce110_se_audio_mute_control(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 5c97be9925f9..0c1a9b8a9b5a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -291,7 +291,6 @@ static const struct dce110_link_enc_registers link_enc_regs[] = {
[id] = {\
SE_COMMON_REG_LIST_DCE_BASE(id),\
.AFMT_CNTL = 0,\
- .TMDS_CNTL = 0,\
}
static const struct dce110_stream_enc_registers stream_enc_regs[] = {
@@ -304,6 +303,14 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = {
stream_enc_regs(6)
};
+static const struct dce_stream_encoder_shift se_shift = {
+ SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
+};
+
+static const struct dce_stream_encoder_mask se_mask = {
+ SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
+};
+
#define audio_regs(id)\
[id] = {\
AUD_COMMON_REG_LIST(id)\
@@ -431,7 +438,8 @@ static struct stream_encoder *dce100_stream_encoder_create(
return NULL;
if (dce110_stream_encoder_construct(
- enc110, ctx, ctx->dc_bios, eng_id, &stream_enc_regs[eng_id]))
+ enc110, ctx, ctx->dc_bios, eng_id,
+ &stream_enc_regs[eng_id], &se_shift, &se_mask))
return &enc110->base;
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index ef0af3a72ccd..0ed9b831811d 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -258,6 +258,14 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = {
stream_enc_regs(2)
};
+static const struct dce_stream_encoder_shift se_shift = {
+ SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce_stream_encoder_mask se_mask = {
+ SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
+};
+
#define audio_regs(id)\
[id] = {\
AUD_COMMON_REG_LIST(id)\
@@ -406,7 +414,8 @@ static struct stream_encoder *dce110_stream_encoder_create(
return NULL;
if (dce110_stream_encoder_construct(
- enc110, ctx, ctx->dc_bios, eng_id, &stream_enc_regs[eng_id]))
+ enc110, ctx, ctx->dc_bios, eng_id,
+ &stream_enc_regs[eng_id], &se_shift, &se_mask))
return &enc110->base;
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 6e6bd9c9568d..c1456483cbdb 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -297,6 +297,14 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = {
stream_enc_regs(5)
};
+static const struct dce_stream_encoder_shift se_shift = {
+ SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
+};
+
+static const struct dce_stream_encoder_mask se_mask = {
+ SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
+};
+
#define audio_regs(id)\
[id] = {\
AUD_COMMON_REG_LIST(id)\
@@ -455,7 +463,8 @@ static struct stream_encoder *dce112_stream_encoder_create(
return NULL;
if (dce110_stream_encoder_construct(
- enc110, ctx, ctx->dc_bios, eng_id, &stream_enc_regs[eng_id]))
+ enc110, ctx, ctx->dc_bios, eng_id,
+ &stream_enc_regs[eng_id], &se_shift, &se_mask))
return &enc110->base;
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index d470f5cd0942..d10d3a80ae3a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -312,6 +312,14 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = {
stream_enc_regs(5)
};
+static const struct dce_stream_encoder_shift se_shift = {
+ SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
+};
+
+static const struct dce_stream_encoder_mask se_mask = {
+ SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
+};
+
#define audio_regs(id)\
[id] = {\
AUD_COMMON_REG_LIST(id)\
@@ -421,7 +429,8 @@ static struct stream_encoder *dce80_stream_encoder_create(
return NULL;
if (dce110_stream_encoder_construct(
- enc110, ctx, ctx->dc_bios, eng_id, &stream_enc_regs[eng_id]))
+ enc110, ctx, ctx->dc_bios, eng_id,
+ &stream_enc_regs[eng_id], &se_shift, &se_mask))
return &enc110->base;
BREAK_TO_DEBUGGER();
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 36/76] drm/amd/dal: Fixed wrong return value check condition.
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (34 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 35/76] drm/amd/dal: Pass in shift and mask for stream encoder Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 37/76] drm/amd/dal: Make set_overscan_blank_color optional Harry Wentland
` (40 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
index fef7bc4c33cb..bc444438ec95 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
@@ -1065,7 +1065,7 @@ bool dce110_link_encoder_construct(
struct bp_encoder_cap_info bp_cap_info = {0};
const struct dc_vbios_funcs *bp_funcs = enc110->base.ctx->dc_bios->funcs;
- if (BP_RESULT_OK != bp_funcs->get_encoder_cap_info(
+ if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info(
enc110->base.ctx->dc_bios, enc110->base.id,
&bp_cap_info))
enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 37/76] drm/amd/dal: Make set_overscan_blank_color optional
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (35 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 36/76] drm/amd/dal: Fixed wrong return value check condition Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 38/76] drm/amd/dal: Hard-coded LB_MEMORY_SIZE Harry Wentland
` (39 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 4181a2207dc4..486fdfa98608 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -756,9 +756,10 @@ static void program_scaler(const struct core_dc *dc,
pipe_ctx->scl_data.lb_bpp,
&pipe_ctx->stream->bit_depth_params);
- pipe_ctx->tg->funcs->set_overscan_blank_color(
- pipe_ctx->tg,
- &color);
+ if (pipe_ctx->tg->funcs->set_overscan_blank_color)
+ pipe_ctx->tg->funcs->set_overscan_blank_color(
+ pipe_ctx->tg,
+ &color);
pipe_ctx->xfm->funcs->transform_set_scaler(pipe_ctx->xfm,
&pipe_ctx->scl_data);
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 38/76] drm/amd/dal: Hard-coded LB_MEMORY_SIZE
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (36 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 37/76] drm/amd/dal: Make set_overscan_blank_color optional Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:00 ` [PATCH 39/76] drm/amd/dal: Rotation and mirror support Harry Wentland
` (38 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wesley Chalmers
From: Wesley Chalmers <Wesley.Chalmers@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 4 +++-
drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c | 2 ++
drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c | 6 +++---
drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c | 2 +-
drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 4 +++-
drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c | 2 ++
drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c | 2 +-
drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h | 1 +
8 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 0c1a9b8a9b5a..908bb297bd0f 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -491,8 +491,10 @@ static struct transform *dce100_transform_create(
if (!transform)
return NULL;
- if (dce110_transform_construct(transform, ctx, inst, offsets))
+ if (dce110_transform_construct(transform, ctx, inst, offsets)) {
+ transform->base.lb_memory_size = 0x6B0; /*1712*/
return &transform->base;
+ }
BREAK_TO_DEBUGGER();
dm_free(transform);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
index 3426210b7482..a8973795eeeb 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
@@ -116,6 +116,8 @@ bool dce110_transform_construct(
xfm110->base.lb_bits_per_entry = LB_BITS_PER_ENTRY;
xfm110->base.lb_total_entries_num = LB_TOTAL_NUMBER_OF_ENTRIES;
+ xfm110->base.lb_memory_size = 0x6B0; /*1712*/
+
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
index 01168b46df84..48a10128a9c2 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
@@ -26,8 +26,8 @@
#include "dm_services.h"
/* include DCE11 register header files */
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
+#include "dce/dce_11_2_d.h"
+#include "dce/dce_11_2_sh_mask.h"
#include "dce110_transform.h"
#include "dce110_transform_v.h"
@@ -786,7 +786,7 @@ bool dce110_transform_power_up_line_buffer(struct transform *xfm)
/*Use all three pieces of memory always*/
set_reg_field_value(value, 0, LB_MEMORY_CTRL, LB_MEMORY_CONFIG);
/*hard coded number DCE11 1712(0x6B0) Partitions: 720/960/1712*/
- set_reg_field_value(value, LB_TOTAL_NUMBER_OF_ENTRIES, LB_MEMORY_CTRL,
+ set_reg_field_value(value, xfm110->base.lb_memory_size, LB_MEMORY_CTRL,
LB_MEMORY_SIZE);
dm_write_reg(xfm110->base.ctx, LB_REG(mmLB_MEMORY_CTRL), value);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
index bcab405a1a33..b17929dc51ea 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_v.c
@@ -800,7 +800,7 @@ static bool dce110_transform_v_power_up_line_buffer(struct transform *xfm)
/*Use all three pieces of memory always*/
set_reg_field_value(value, 0, LBV_MEMORY_CTRL, LB_MEMORY_CONFIG);
/*hard coded number DCE11 1712(0x6B0) Partitions: 720/960/1712*/
- set_reg_field_value(value, LB_TOTAL_NUMBER_OF_ENTRIES, LBV_MEMORY_CTRL,
+ set_reg_field_value(value, xfm110->base.lb_memory_size, LBV_MEMORY_CTRL,
LB_MEMORY_SIZE);
dm_write_reg(xfm110->base.ctx, mmLBV_MEMORY_CTRL, value);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index c1456483cbdb..7cd772dbd7ce 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -516,8 +516,10 @@ static struct transform *dce112_transform_create(
if (!transform)
return NULL;
- if (dce110_transform_construct(transform, ctx, inst, offsets))
+ if (dce110_transform_construct(transform, ctx, inst, offsets)) {
+ transform->base.lb_memory_size = 0x1404; /*5124*/
return &transform->base;
+ }
BREAK_TO_DEBUGGER();
dm_free(transform);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
index a37ecb842f74..48cbcbb28c77 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform.c
@@ -105,6 +105,8 @@ bool dce80_transform_construct(
xfm80->base.lb_bits_per_entry = LB_BITS_PER_ENTRY;
xfm80->base.lb_total_entries_num = LB_TOTAL_NUMBER_OF_ENTRIES;
+ xfm80->base.lb_memory_size = 0x6B0; /*1712*/
+
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
index 264d260320a6..cd310a99144c 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_transform_bit_depth.c
@@ -732,7 +732,7 @@ bool dce80_transform_power_up_line_buffer(struct transform *xfm)
/*Use all three pieces of memory always*/
set_reg_field_value(value, 0, LB_MEMORY_CTRL, LB_MEMORY_CONFIG);
/*hard coded number DCE8 1712(0x6B0) Partitions: 720/960/1712*/
- set_reg_field_value(value, LB_TOTAL_NUMBER_OF_ENTRIES, LB_MEMORY_CTRL,
+ set_reg_field_value(value, xfm80->base.lb_memory_size, LB_MEMORY_CTRL,
LB_MEMORY_SIZE);
dm_write_reg(xfm80->base.ctx, LB_REG(mmLB_MEMORY_CTRL), value);
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
index 8053455ffdbf..31547406aa31 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/transform.h
@@ -40,6 +40,7 @@ struct transform {
int lb_total_entries_num;
int lb_bits_per_entry;
+ unsigned int lb_memory_size;
};
enum lb_pixel_depth {
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 39/76] drm/amd/dal: Rotation and mirror support
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (37 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 38/76] drm/amd/dal: Hard-coded LB_MEMORY_SIZE Harry Wentland
@ 2016-11-21 23:00 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 40/76] drm/amd/dal: remove unnessary adapter service functions Harry Wentland
` (37 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:00 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Vitaly Prosyak
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Add hardware programming for horizontal mirror.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 3 +++
drivers/gpu/drm/amd/dal/dc/dc.h | 1 +
drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 4 +++-
drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 3 ++-
drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 3 ++-
drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c | 3 ++-
drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h | 3 ++-
7 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index 766cdb1d4286..3b29ac471056 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -1354,6 +1354,7 @@ bool dc_commit_surfaces_to_target(
plane_info[i].format = new_surfaces[i]->format;
plane_info[i].plane_size = new_surfaces[i]->plane_size;
plane_info[i].rotation = new_surfaces[i]->rotation;
+ plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
plane_info[i].visible = new_surfaces[i]->visible;
@@ -1456,6 +1457,8 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda
updates[i].plane_info->plane_size;
surface->public.rotation =
updates[i].plane_info->rotation;
+ surface->public.horizontal_mirror =
+ updates[i].plane_info->horizontal_mirror;
surface->public.stereo_format =
updates[i].plane_info->stereo_format;
surface->public.tiling_info =
diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
index 0451b610b3e2..ba8190f8d168 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
@@ -238,6 +238,7 @@ struct dc_plane_info {
union dc_tiling_info tiling_info;
enum surface_pixel_format format;
enum dc_rotation_angle rotation;
+ bool horizontal_mirror;
enum plane_stereo_format stereo_format;
enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/
bool visible;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 486fdfa98608..a6679a95694e 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -1677,7 +1677,8 @@ static void set_plane_config(
&surface->public.tiling_info,
&surface->public.plane_size,
surface->public.rotation,
- NULL);
+ NULL,
+ false);
if (dc->public.config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(
@@ -2019,6 +2020,7 @@ static void dce110_program_front_end_for_pipe(
&surface->public.tiling_info,
&surface->public.plane_size,
surface->public.rotation,
+ false,
false);
if (dc->public.config.gpu_vm_support)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
index 3183728ed417..3eb0e73d2eb6 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
@@ -525,7 +525,8 @@ bool dce110_mem_input_program_surface_config(
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
- struct dc_plane_dcc_param *dcc)
+ struct dc_plane_dcc_param *dcc,
+ bool horizotal_mirror)
{
struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
index c9e3f5c1fa22..7a521c56e8d9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
@@ -128,7 +128,8 @@ bool dce110_mem_input_program_surface_config(
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
- struct dc_plane_dcc_param *dcc);
+ struct dc_plane_dcc_param *dcc,
+ bool horizontal_mirror);
/*
* dce110_mem_input_program_pte_vm
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
index 5376fed66c29..0903d3b4913d 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
@@ -666,7 +666,8 @@ bool dce110_mem_input_v_program_surface_config(
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
- struct dc_plane_dcc_param *dcc)
+ struct dc_plane_dcc_param *dcc,
+ bool horizotal_mirror)
{
struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
index 9ad3b4218cb0..c743ae13cdf5 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
@@ -80,7 +80,8 @@ struct mem_input_funcs {
union dc_tiling_info *tiling_info,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
- struct dc_plane_dcc_param *dcc);
+ struct dc_plane_dcc_param *dcc,
+ bool horizontal_mirror);
bool (*mem_input_is_flip_pending)(struct mem_input *mem_input);
};
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 40/76] drm/amd/dal: remove unnessary adapter service functions
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (38 preceding siblings ...)
2016-11-21 23:00 ` [PATCH 39/76] drm/amd/dal: Rotation and mirror support Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 41/76] drm/amd/dal: remove dal_override_parameters Harry Wentland
` (36 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- call bios directly
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 168 +--------------------
.../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c | 5 +-
.../gpu/drm/amd/dal/dc/dce112/dce112_compressor.c | 5 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_compressor.c | 5 +-
.../amd/dal/dc/gpu/dce110/display_clock_dce110.c | 13 +-
.../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c | 9 +-
.../amd/dal/include/adapter_service_interface.h | 41 -----
7 files changed, 21 insertions(+), 225 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index 435b222c48a4..245438229623 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -608,7 +608,6 @@ static bool adapter_service_construct(
struct as_init_data *init_data)
{
struct dc_bios *dcb;
- enum dce_version dce_version;
uint32_t i;
if (!init_data)
@@ -631,7 +630,7 @@ static bool adapter_service_construct(
as->default_values[id] = feature_entry_table[i].default_value;
}
- if (dal_adapter_service_get_dce_version(as) == DCE_VERSION_11_0) {
+ if (as->ctx->dce_version == DCE_VERSION_11_0) {
uint32_t i;
for (i = 0; i < ARRAY_SIZE(feature_entry_table); i++) {
@@ -652,7 +651,6 @@ static bool adapter_service_construct(
}
as->dce_environment = init_data->dce_environment;
- dce_version = dal_adapter_service_get_dce_version(as);
dcb = as->ctx->dc_bios;
@@ -731,87 +729,6 @@ void dal_adapter_service_destroy(
}
/*
- * dal_adapter_service_get_dce_version
- *
- * Get the DCE version of current ASIC
- */
-enum dce_version dal_adapter_service_get_dce_version(
- const struct adapter_service *as)
-{
- uint32_t version = as->asic_cap->data[ASIC_DATA_DCE_VERSION];
-
- switch (version) {
- case 0x80:
- /* CI Bonaire */
- return DCE_VERSION_8_0;
- case 0x100:
- return DCE_VERSION_10_0;
- case 0x110:
- return DCE_VERSION_11_0;
- case 0x112:
- return DCE_VERSION_11_2;
- default:
- ASSERT_CRITICAL(false);
- return DCE_VERSION_UNKNOWN;
- }
-}
-
-/**
- * Get the source objects of an object
- *
- * \param [in] id The graphics object id
- * \param [in] index Enumerating index which starts at 0
- *
- * \return If enumerating successfully, return the VALID source object id,
- * otherwise, returns "zeroed out" object id.
- * Client should call dal_graphics_object_id_is_valid() to check
- * weather the id is valid.
- */
-struct graphics_object_id dal_adapter_service_get_src_obj(
- struct adapter_service *as,
- struct graphics_object_id id,
- uint32_t index)
-{
- struct graphics_object_id src_object_id;
- struct dc_bios *dcb = as->ctx->dc_bios;
-
- if (BP_RESULT_OK != dcb->funcs->get_src_obj(dcb, id, index,
- &src_object_id)) {
- src_object_id =
- dal_graphics_object_id_init(
- 0,
- ENUM_ID_UNKNOWN,
- OBJECT_TYPE_UNKNOWN);
- }
-
- return src_object_id;
-}
-
-bool dal_adapter_service_get_device_tag(
- struct adapter_service *as,
- struct graphics_object_id connector_object_id,
- uint32_t device_tag_index,
- struct connector_device_tag_info *info)
-{
- struct dc_bios *dcb = as->ctx->dc_bios;
-
- if (BP_RESULT_OK == dcb->funcs->get_device_tag(dcb,
- connector_object_id, device_tag_index, info))
- return true;
- else
- return false;
-}
-
-/* Check if DeviceId is supported by ATOM_OBJECT_HEADER support info */
-bool dal_adapter_service_is_device_id_supported(struct adapter_service *as,
- struct device_id id)
-{
- struct dc_bios *dcb = as->ctx->dc_bios;
-
- return dcb->funcs->is_device_id_supported(dcb, id);
-}
-
-/*
* dal_adapter_service_is_feature_supported
*
* Return if a given feature is supported by the ASIC. The feature has to be
@@ -828,39 +745,6 @@ bool dal_adapter_service_is_feature_supported(struct adapter_service *as,
}
/*
- * dal_adapter_service_get_ss_info_num
- *
- * Get number of spread spectrum entries from BIOS
- */
-uint32_t dal_adapter_service_get_ss_info_num(
- struct adapter_service *as,
- enum as_signal_type signal)
-{
- struct dc_bios *dcb = as->ctx->dc_bios;
-
- return dcb->funcs->get_ss_entry_number(dcb, signal);
-}
-
-/*
- * dal_adapter_service_get_ss_info
- *
- * Get spread spectrum info from BIOS
- */
-bool dal_adapter_service_get_ss_info(
- struct adapter_service *as,
- enum as_signal_type signal,
- uint32_t idx,
- struct spread_spectrum_info *info)
-{
- struct dc_bios *dcb = as->ctx->dc_bios;
-
- enum bp_result bp_result = dcb->funcs->get_spread_spectrum_info(dcb,
- signal, idx, info);
-
- return BP_RESULT_OK == bp_result;
-}
-
-/*
* dal_adapter_service_is_dfs_bypass_enabled
*
* Check if DFS bypass is enabled
@@ -952,22 +836,6 @@ bool dal_adapter_service_get_feature_value(struct adapter_service *as,
return true;
}
-bool dal_adapter_service_get_embedded_panel_info(
- struct adapter_service *as,
- struct embedded_panel_info *info)
-{
- enum bp_result result;
- struct dc_bios *dcb = as->ctx->dc_bios;
-
- if (info == NULL)
- /*TODO: add DALASSERT_MSG here*/
- return false;
-
- result = dcb->funcs->get_embedded_panel_info(dcb, info);
-
- return result == BP_RESULT_OK;
-}
-
/*
* dal_adapter_service_should_optimize
*
@@ -1018,37 +886,3 @@ bool dal_adapter_service_should_optimize(
return (supported_optimization & feature) != 0;
}
-bool dal_adapter_service_get_encoder_cap_info(
- struct adapter_service *as,
- struct graphics_object_id id,
- struct graphics_object_encoder_cap_info *info)
-{
- struct bp_encoder_cap_info bp_cap_info = {0};
- enum bp_result result;
- struct dc_bios *dcb = as->ctx->dc_bios;
-
- if (NULL == info) {
- ASSERT_CRITICAL(false);
- return false;
- }
-
- /*
- * Retrieve Encoder Capability Information from VBIOS and store the
- * call result (success or fail)
- * Info from VBIOS about HBR2 has two fields:
- *
- * - dpHbr2Cap: indicates supported/not supported by HW Encoder
- * - dpHbr2En : indicates DP spec compliant/not compliant
- */
- result = dcb->funcs->get_encoder_cap_info(dcb, id, &bp_cap_info);
-
- /* Set dp_hbr2_validated flag (it's equal to Enable) */
- info->dp_hbr2_validated = bp_cap_info.DP_HBR2_EN;
-
- if (result == BP_RESULT_OK) {
- info->dp_hbr2_cap = bp_cap_info.DP_HBR2_CAP;
- return true;
- }
-
- return false;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
index 7612efb27939..62bf70363b3c 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
@@ -795,6 +795,7 @@ void dce110_compressor_set_fbc_invalidation_triggers(
bool dce110_compressor_construct(struct dce110_compressor *compressor,
struct dc_context *ctx, struct adapter_service *as)
{
+ struct dc_bios *bp = ctx->dc_bios;
struct embedded_panel_info panel_info;
compressor->base.options.bits.FBC_SUPPORT = true;
@@ -833,8 +834,8 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor,
compressor->base.attached_inst = 0;
compressor->base.is_enabled = false;
- if (dal_adapter_service_get_embedded_panel_info(as,
- &panel_info)) {
+ if (BP_RESULT_OK ==
+ bp->funcs->get_embedded_panel_info(bp, &panel_info)) {
compressor->base.embedded_panel_h_size =
panel_info.lcd_timing.horizontal_addressable;
compressor->base.embedded_panel_v_size =
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
index 1b0792e0219a..aa06777306f8 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
@@ -795,6 +795,7 @@ void dce112_compressor_set_fbc_invalidation_triggers(
bool dce112_compressor_construct(struct dce112_compressor *compressor,
struct dc_context *ctx, struct adapter_service *as)
{
+ struct dc_bios *bp = ctx->dc_bios;
struct embedded_panel_info panel_info;
compressor->base.options.bits.FBC_SUPPORT = true;
@@ -833,8 +834,8 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor,
compressor->base.attached_inst = 0;
compressor->base.is_enabled = false;
- if (dal_adapter_service_get_embedded_panel_info(as,
- &panel_info)) {
+ if (BP_RESULT_OK ==
+ bp->funcs->get_embedded_panel_info(bp, &panel_info)) {
compressor->base.embedded_panel_h_size =
panel_info.lcd_timing.horizontal_addressable;
compressor->base.embedded_panel_v_size =
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
index 667be43aaa07..8cab5e60bc9b 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
@@ -776,6 +776,7 @@ void dce80_compressor_set_fbc_invalidation_triggers(
bool dce80_compressor_construct(struct dce80_compressor *compressor,
struct dc_context *ctx, struct adapter_service *as)
{
+ struct dc_bios *bp = ctx->dc_bios;
struct embedded_panel_info panel_info;
compressor->base.options.bits.FBC_SUPPORT = true;
@@ -814,8 +815,8 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor,
compressor->base.attached_inst = 0;
compressor->base.is_enabled = false;
- if (dal_adapter_service_get_embedded_panel_info(as,
- &panel_info)) {
+ if (BP_RESULT_OK ==
+ bp->funcs->get_embedded_panel_info(bp, &panel_info)) {
compressor->base.embedded_panel_h_size =
panel_info.lcd_timing.horizontal_addressable;
compressor->base.embedded_panel_v_size =
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
index 9aa9b8fc927f..ec0f6ae61542 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
@@ -926,6 +926,7 @@ static bool dal_display_clock_dce110_construct(
struct adapter_service *as)
{
struct display_clock *dc_base = &dc110->disp_clk_base;
+ struct dc_bios *bp = dc110->disp_clk_base.ctx->dc_bios;
if (NULL == as)
return false;
@@ -973,19 +974,16 @@ static bool dal_display_clock_dce110_construct(
{
uint32_t ss_info_num =
- dal_adapter_service_get_ss_info_num(
- as,
+ bp->funcs->get_ss_entry_number(bp,
AS_SIGNAL_TYPE_GPU_PLL);
if (ss_info_num) {
struct spread_spectrum_info info;
- bool result;
+ enum bp_result result;
memset(&info, 0, sizeof(info));
- result =
- dal_adapter_service_get_ss_info(
- as,
+ result = bp->funcs->get_spread_spectrum_info(bp,
AS_SIGNAL_TYPE_GPU_PLL,
0,
&info);
@@ -995,7 +993,8 @@ static bool dal_display_clock_dce110_construct(
* SSInfo.spreadSpectrumPercentage !=0 would be sign
* that SS is enabled
*/
- if (result && info.spread_spectrum_percentage != 0) {
+ if (result == BP_RESULT_OK &&
+ info.spread_spectrum_percentage != 0) {
dc110->ss_on_gpu_pll = true;
dc110->gpu_pll_ss_divider =
info.spread_percentage_divider;
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
index 0741139db8b5..68134a0e70b4 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
@@ -719,24 +719,25 @@ static void display_clock_ss_construct(
struct display_clock_dce80 *disp_clk,
struct adapter_service *as)
{
- uint32_t ss_entry_num = dal_adapter_service_get_ss_info_num(as,
+ struct dc_bios *bp = disp_clk->disp_clk.ctx->dc_bios;
+ uint32_t ss_entry_num = bp->funcs->get_ss_entry_number(bp,
AS_SIGNAL_TYPE_GPU_PLL);
/*Read SS Info from VBIOS SS Info table for DP Reference Clock spread.*/
if (ss_entry_num > 0) {/* Should be only one entry */
struct spread_spectrum_info ss_info;
- bool res;
+ enum bp_result res;
memset(&ss_info, 0, sizeof(struct spread_spectrum_info));
- res = dal_adapter_service_get_ss_info(as,
+ res = bp->funcs->get_spread_spectrum_info(bp,
AS_SIGNAL_TYPE_GPU_PLL, 0, &ss_info);
/* Based on VBIOS, VBIOS will keep entry for GPU PLL SS even if
* SS not enabled and in that case
* SSInfo.spreadSpectrumPercentage !=0 would be
* sign that SS is enabled*/
- if (res && ss_info.spread_spectrum_percentage != 0) {
+ if (res == BP_RESULT_OK && ss_info.spread_spectrum_percentage != 0) {
disp_clk->ss_on_gpu_pll = true;
disp_clk->gpu_pll_ss_divider =
ss_info.spread_percentage_divider;
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index 39adbbf25638..35ca9ca96467 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -330,22 +330,6 @@ struct adapter_service *dal_adapter_service_create(
void dal_adapter_service_destroy(
struct adapter_service **as);
-/* Get the DCE version of current ASIC */
-enum dce_version dal_adapter_service_get_dce_version(
- const struct adapter_service *as);
-
-/* Get number of spread spectrum entries from BIOS */
-uint32_t dal_adapter_service_get_ss_info_num(
- struct adapter_service *as,
- enum as_signal_type signal);
-
-/* Get spread spectrum info from BIOS */
-bool dal_adapter_service_get_ss_info(
- struct adapter_service *as,
- enum as_signal_type signal,
- uint32_t idx,
- struct spread_spectrum_info *info);
-
/* Check if DFS bypass is enabled */
bool dal_adapter_service_is_dfs_bypass_enabled(struct adapter_service *as);
@@ -373,33 +357,8 @@ bool dal_adapter_service_get_i2c_info(
struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags(
struct adapter_service *as);
-bool dal_adapter_service_get_embedded_panel_info(
- struct adapter_service *as,
- struct embedded_panel_info *info);
-
-
-bool dal_adapter_service_get_device_tag(
- struct adapter_service *as,
- struct graphics_object_id connector_object_id,
- uint32_t device_tag_index,
- struct connector_device_tag_info *info);
-
-bool dal_adapter_service_is_device_id_supported(
- struct adapter_service *as,
- struct device_id id);
-
-struct graphics_object_id dal_adapter_service_get_src_obj(
- struct adapter_service *as,
- struct graphics_object_id id,
- uint32_t index);
-
/* Reports whether driver settings allow requested optimization */
bool dal_adapter_service_should_optimize(
struct adapter_service *as, enum optimization_feature feature);
-bool dal_adapter_service_get_encoder_cap_info(
- struct adapter_service *as,
- struct graphics_object_id id,
- struct graphics_object_encoder_cap_info *info);
-
#endif /* __DAL_ADAPTER_SERVICE_INTERFACE_H__ */
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 41/76] drm/amd/dal: remove dal_override_parameters
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (39 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 40/76] drm/amd/dal: remove unnessary adapter service functions Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 42/76] drm/amd/dal: remove unnessary adapter service functions Harry Wentland
` (35 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- overrride param added in 65c31cba
- looks like was quick workaround for amdsoc to support persistence issue
- simplify by removing indirections
- DAL_PARAM_ENABLE_GPU_SCALING enabled on all platforms and not used. remove
- DAL_PARAM_DISABLE_CLOCK_SHARING still needed. replace with disable_disp_pll_sharing in dc_config.
* note: behavior change: fix DP + HDMI timing sync in case of disable_disp_pll_sharing = 1
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 17 ----
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 110 ++-------------------
drivers/gpu/drm/amd/dal/dc/core/dc.c | 3 +-
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 18 ++--
drivers/gpu/drm/amd/dal/dc/dc.h | 2 +-
drivers/gpu/drm/amd/dal/dc/dc_types.h | 44 ---------
.../amd/dal/include/adapter_service_interface.h | 3 -
7 files changed, 20 insertions(+), 177 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
index d67e77ada6c0..f667620e30e9 100644
--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
@@ -54,15 +54,6 @@
#include "modules/inc/mod_freesync.h"
-/* Define variables here
- * These values will be passed to DAL for feature enable purpose
- * Disable ALL for HDMI light up
- * TODO: follow up if need this mechanism*/
-struct dal_override_parameters display_param = {
- .bool_param_enable_mask = 0,
- .bool_param_values = 0,
-};
-
/* Debug facilities */
#define AMDGPU_DM_NOT_IMPL(fmt, ...) \
DRM_INFO("DM_NOT_IMPL: " fmt, ##__VA_ARGS__)
@@ -280,8 +271,6 @@ int amdgpu_dm_init(struct amdgpu_device *adev)
goto error;
}
- init_data.display_param = display_param;
-
init_data.asic_id.chip_family = adev->family;
init_data.asic_id.pci_revision_id = adev->rev_id;
@@ -310,12 +299,6 @@ int amdgpu_dm_init(struct amdgpu_device *adev)
adev->dm.dal = NULL;
- /* enable gpu scaling in DAL */
- init_data.display_param.bool_param_enable_mask |=
- 1 << DAL_PARAM_ENABLE_GPU_SCALING;
- init_data.display_param.bool_param_values |=
- 1 << DAL_PARAM_ENABLE_GPU_SCALING;
-
init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
/* Display Core create. */
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index 245438229623..21fd3249b0c1 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -136,7 +136,6 @@ static const struct feature_source_entry feature_entry_table[] = {
{FEATURE_MAX_BACKLIGHT_LEVEL, 255, false},
{FEATURE_LOAD_DMCU_FIRMWARE, true, true},
{FEATURE_DISABLE_AZ_CLOCK_GATING, false, true},
- {FEATURE_ENABLE_GPU_SCALING, false, true},
{FEATURE_DONGLE_SINK_COUNT_CHECK, true, true},
{FEATURE_INSTANT_UP_SCALE_DOWN_SCALE, false, true},
{FEATURE_TILED_DISPLAY, false, true},
@@ -161,7 +160,6 @@ static const struct feature_source_entry feature_entry_table[] = {
{FEATURE_DISABLE_FBC_COMP_CLK_GATE, false, true},
{FEATURE_PIXEL_PERFECT_OUTPUT, false, true},
{FEATURE_8BPP_SUPPORTED, false, true},
- {FEATURE_DISABLE_CLOCK_SHARING, false, true}
};
enum {
@@ -335,90 +333,6 @@ static void initialize_backlight_caps(
}
as->backlight_caps_initialized = true;
}
-
-static void log_overriden_features(
- struct adapter_service *as,
- const char *feature_name,
- enum adapter_feature_id id,
- bool bool_feature,
- uint32_t value)
-{
- if (bool_feature)
- dm_logger_write(as->ctx->logger, LOG_FEATURE_OVERRIDE,
- "Overridden %s is %s now\n",
- feature_name,
- (value == 0) ? "disabled" : "enabled");
- else
- dm_logger_write(as->ctx->logger, LOG_FEATURE_OVERRIDE,
- "Overridden %s new value: %d\n",
- feature_name,
- value);
-}
-
-/*************************************
- * Local static functions definition *
- *************************************/
-
-#define check_bool_feature(feature) \
-case FEATURE_ ## feature: \
- if (param->bool_param_enable_mask & \
- (1 << DAL_PARAM_ ## feature)) { \
- *data = param->bool_param_values & \
- (1 << DAL_PARAM_ ## feature); \
- ret = true; \
- feature_name = "FEATURE_" #feature; \
- } \
- break
-
-/*
- * override_default_parameters
- *
- * Override features (from runtime parameter)
- * corresponding to Adapter Service Feature ID
- */
-static bool override_default_parameters(
- struct adapter_service *as,
- const struct dal_override_parameters *param,
- const uint32_t idx,
- uint32_t *data)
-{
- bool ret = false;
- bool bool_feature = true;
- char *feature_name;
-
- if (idx >= get_feature_entries_num()) {
- ASSERT_CRITICAL(false);
- return false;
- }
-
- switch (feature_entry_table[idx].feature_id) {
- check_bool_feature(MAXIMIZE_STUTTER_MARKS);
- check_bool_feature(MAXIMIZE_URGENCY_WATERMARKS);
- check_bool_feature(USE_MAX_DISPLAY_CLK);
- check_bool_feature(ENABLE_DFS_BYPASS);
- check_bool_feature(POWER_GATING_PIPE_IN_TILE);
- check_bool_feature(POWER_GATING_LB_PORTION);
- check_bool_feature(PSR_ENABLE);
- check_bool_feature(VARI_BRIGHT_ENABLE);
- check_bool_feature(USE_PPLIB);
- check_bool_feature(DISABLE_LPT_SUPPORT);
- check_bool_feature(DUMMY_FBC_BACKEND);
- check_bool_feature(ENABLE_GPU_SCALING);
- check_bool_feature(DISABLE_CLOCK_SHARING);
- default:
- return false;
- }
- if (ret)
- log_overriden_features(
- as,
- feature_name,
- feature_entry_table[idx].feature_id,
- bool_feature,
- *data);
-
- return ret;
-}
-
/*
* get_feature_value_from_data_sources
*
@@ -536,8 +450,7 @@ static void set_bool_value(
* Generate the internal feature set from multiple data sources
*/
static bool generate_feature_set(
- struct adapter_service *as,
- const struct dal_override_parameters *param)
+ struct adapter_service *as)
{
uint32_t i = 0;
uint32_t value = 0;
@@ -561,17 +474,14 @@ static bool generate_feature_set(
set_idx = (uint32_t)((entry->feature_id - 1) / 32);
internal_idx = (uint32_t)((entry->feature_id - 1) % 32);
- /* TODO: wireless, runtime parameter, vbios */
- if (!override_default_parameters(as, param, i, &value)) {
- if (!get_feature_value_from_data_sources(
- as, i, &value)) {
- /*
- * Can't find feature values from
- * above data sources
- * Assign default value
- */
- value = as->default_values[entry->feature_id];
- }
+ if (!get_feature_value_from_data_sources(
+ as, i, &value)) {
+ /*
+ * Can't find feature values from
+ * above data sources
+ * Assign default value
+ */
+ value = as->default_values[entry->feature_id];
}
if (entry->is_boolean_type)
@@ -645,7 +555,7 @@ static bool adapter_service_construct(
}
/* Generate feature set table */
- if (!generate_feature_set(as, init_data->display_param)) {
+ if (!generate_feature_set(as)) {
ASSERT_CRITICAL(false);
goto failed_to_generate_features;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index 3b29ac471056..cfc8e8f95d5b 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -185,7 +185,6 @@ static struct adapter_service *create_as(
init_data.hw_init_data.vram_width = init->asic_id.vram_width;
init_data.hw_init_data.vram_type = init->asic_id.vram_type;
- init_data.display_param = &init->display_param;
init_data.vbios_override = init->vbios_override;
init_data.dce_environment = init->dce_environment;
@@ -689,7 +688,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
core_dc->public.caps.max_links = core_dc->link_count;
core_dc->public.caps.max_audios = core_dc->res_pool->audio_count;
- core_dc->public.config.gpu_vm_support = init_params->flags.gpu_vm_support;
+ core_dc->public.config = init_params->flags;
dm_logger_write(core_dc->ctx->logger, LOG_DC,
"Display Core initialized\n");
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index 4c93d539ef8a..a4061c68596a 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -301,15 +301,11 @@ struct clock_source *resource_find_used_clk_src_for_sharing(
struct resource_context *res_ctx,
struct pipe_ctx *pipe_ctx)
{
- if (!dal_adapter_service_is_feature_supported(
- res_ctx->pool->adapter_srv,
- FEATURE_DISABLE_CLOCK_SHARING)) {
- int i;
-
- for (i = 0; i < MAX_PIPES; i++) {
- if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
- return res_ctx->pipe_ctx[i].clock_source;
- }
+ int i;
+
+ for (i = 0; i < MAX_PIPES; i++) {
+ if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
+ return res_ctx->pipe_ctx[i].clock_source;
}
return NULL;
@@ -1869,7 +1865,9 @@ enum dc_status resource_map_clock_resources(
pipe_ctx->clock_source =
context->res_ctx.pool->dp_clock_source;
else {
- pipe_ctx->clock_source =
+ pipe_ctx->clock_source = NULL;
+
+ if (!dc->public.config.disable_disp_pll_sharing)
resource_find_used_clk_src_for_sharing(
&context->res_ctx,
pipe_ctx);
diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
index ba8190f8d168..044fea7ce32a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
@@ -132,6 +132,7 @@ struct dc_link_funcs {
/* Structure to hold configuration flags set by dm at dc creation. */
struct dc_config {
bool gpu_vm_support;
+ bool disable_disp_pll_sharing;
};
struct dc_debug {
@@ -151,7 +152,6 @@ struct dc {
struct dc_init_data {
struct hw_asic_id asic_id;
- struct dal_override_parameters display_param;
void *driver; /* ctx */
struct cgs_device *cgs_device;
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
index 15f45180a0cf..30e12e5cbe1b 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
@@ -121,50 +121,6 @@ struct hw_asic_id {
void *atombios_base_address;
};
-/* array index for integer override parameters*/
-enum int_param_array_index {
- DAL_PARAM_MAX_COFUNC_NON_DP_DISPLAYS = 0,
- DAL_PARAM_DRR_SUPPORT,
- DAL_INT_PARAM_MAX
-};
-
-struct dal_override_parameters {
- uint32_t bool_param_enable_mask;
- uint32_t bool_param_values;
-};
-
-/*
- * shift values for bool override parameter mask
- * bmask is for this struct,if we touch this feature
- * bval indicates every bit fields for this struct too,1 is enable this feature
- * amdgpu.disp_bval=1594, amdgpu.disp_bmask=1594 ,
- * finally will show log like this:
- * Overridden FEATURE_LIGHT_SLEEP is enabled now
- * Overridden FEATURE_USE_MAX_DISPLAY_CLK is enabled now
- * Overridden FEATURE_ENABLE_DFS_BYPASS is enabled now
- * Overridden FEATURE_POWER_GATING_PIPE_IN_TILE is enabled now
- * Overridden FEATURE_USE_PPLIB is enabled now
- * Overridden FEATURE_DISABLE_LPT_SUPPORT is enabled now
- * Overridden FEATURE_DUMMY_FBC_BACKEND is enabled now
- * */
-enum bool_param_shift {
- DAL_PARAM_MAXIMIZE_STUTTER_MARKS = 0,
- DAL_PARAM_LIGHT_SLEEP,
- DAL_PARAM_MAXIMIZE_URGENCY_WATERMARKS,
- DAL_PARAM_USE_MAX_DISPLAY_CLK,
- DAL_PARAM_ENABLE_DFS_BYPASS,
- DAL_PARAM_POWER_GATING_PIPE_IN_TILE,
- DAL_PARAM_POWER_GATING_LB_PORTION,
- DAL_PARAM_PSR_ENABLE,
- DAL_PARAM_VARI_BRIGHT_ENABLE,
- DAL_PARAM_USE_PPLIB,
- DAL_PARAM_DISABLE_LPT_SUPPORT,
- DAL_PARAM_DUMMY_FBC_BACKEND,
- DAL_PARAM_ENABLE_GPU_SCALING,
- DAL_PARAM_DISABLE_CLOCK_SHARING,
- DAL_BOOL_PARAM_MAX
-};
-
#define MAX_EDID_BUFFER_SIZE 512
#define EDID_BLOCK_SIZE 128
#define MAX_SURFACE_NUM 2
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index 35ca9ca96467..bb4964743a4d 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -115,7 +115,6 @@ enum adapter_feature_id {
FEATURE_ABM_2_0,
FEATURE_SUPPORT_MIRABILIS,
FEATURE_LOAD_DMCU_FIRMWARE, /* 20th */
- FEATURE_ENABLE_GPU_SCALING,
FEATURE_DONGLE_SINK_COUNT_CHECK,
FEATURE_INSTANT_UP_SCALE_DOWN_SCALE,
FEATURE_TILED_DISPLAY,
@@ -126,7 +125,6 @@ enum adapter_feature_id {
FEATURE_SUPPORT_SMOOTH_BRIGHTNESS,
FEATURE_ALLOW_DIRECT_MEMORY_ACCESS_TRIG, /* 30th */
FEATURE_POWER_GATING_LB_PORTION,
- FEATURE_DISABLE_CLOCK_SHARING, /* 32nd. Set Done. */
FEATURE_SET_02_END = FEATURE_SET_02_START + 31,
/* UInt set, 1 entry: DCP Bit Depth Reduction Mode */
@@ -317,7 +315,6 @@ enum as_drr_support {
struct as_init_data {
struct hw_asic_id hw_init_data;
struct dc_context *ctx;
- const struct dal_override_parameters *display_param;
struct dc_bios *vbios_override;
enum dce_environment dce_environment;
};
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 42/76] drm/amd/dal: remove unnessary adapter service functions
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (40 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 41/76] drm/amd/dal: remove dal_override_parameters Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 43/76] " Harry Wentland
` (34 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- remove ASIC_DATA_VRAM_BITWIDTH. use asic_id directly
- remove FEATURE_NO_HPD_LOW_POLLING_VCC_OFF. = 1 on all supported asic
- remove FEATURE_DUMMY_FBC_BACKEND. = 0 on all asic
- remove FEATURE_DISABLE_LPT_SUPPORT. = 0 on all asic
- remove FEATURE_DISABLE_FBC_COMP_CLK_GATE. = 0 on all asic
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 20 ----------
.../amd/dal/dc/asic_capability/asic_capability.c | 2 -
.../dc/asic_capability/carrizo_asic_capability.c | 1 -
.../dc/asic_capability/hawaii_asic_capability.c | 1 -
.../dc/asic_capability/polaris10_asic_capability.c | 1 -
.../dal/dc/asic_capability/tonga_asic_capability.c | 1 -
drivers/gpu/drm/amd/dal/dc/core/dc.c | 3 +-
drivers/gpu/drm/amd/dal/dc/dc_types.h | 45 +++++++++++-----------
drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c | 3 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c | 15 ++------
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 2 +-
.../gpu/drm/amd/dal/dc/dce112/dce112_compressor.c | 15 ++------
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 2 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_compressor.c | 15 ++------
drivers/gpu/drm/amd/dal/dc/inc/core_dc.h | 1 -
.../amd/dal/include/adapter_service_interface.h | 16 +-------
.../drm/amd/dal/include/asic_capability_types.h | 2 -
17 files changed, 40 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index 21fd3249b0c1..e6a5bd08d997 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -94,13 +94,11 @@ static const struct feature_source_entry feature_entry_table[] = {
{FEATURE_DCP_BIT_DEPTH_REDUCTION_MODE, 0, false},
{FEATURE_DCP_DITHER_MODE, 0, false},
{FEATURE_DCP_PROGRAMMING_WA, 0, false},
- {FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, false, true},
{FEATURE_ENABLE_DFS_BYPASS, false, true},
{FEATURE_WIRELESS_FULL_TIMING_ADJUSTMENT, false, true},
{FEATURE_WIRELESS_LIMIT_720P, false, true},
{FEATURE_MODIFY_TIMINGS_FOR_WIRELESS, false, true},
{FEATURE_DETECT_REQUIRE_HPD_HIGH, false, true},
- {FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, false, true},
{FEATURE_LB_HIGH_RESOLUTION, false, true},
{FEATURE_MAX_CONTROLLER_NUM, 0, false},
{FEATURE_DRR_SUPPORT, AS_DRR_SUPPORT_ENABLED, false},
@@ -154,10 +152,7 @@ static const struct feature_source_entry feature_entry_table[] = {
{FEATURE_ALLOW_DIRECT_MEMORY_ACCESS_TRIG, false, true},
{FEATURE_FORCE_STATIC_SCREEN_EVENT_TRIGGERS, 0, false},
{FEATURE_USE_PPLIB, true, true},
- {FEATURE_DISABLE_LPT_SUPPORT, false, true},
- {FEATURE_DUMMY_FBC_BACKEND, false, true},
{FEATURE_DPMS_AUDIO_ENDPOINT_CONTROL, true, true},
- {FEATURE_DISABLE_FBC_COMP_CLK_GATE, false, true},
{FEATURE_PIXEL_PERFECT_OUTPUT, false, true},
{FEATURE_8BPP_SUPPORTED, false, true},
};
@@ -367,10 +362,6 @@ static bool get_feature_value_from_data_sources(
*data = as->asic_cap->caps.HPD_CHECK_FOR_EDID;
break;
- case FEATURE_NO_HPD_LOW_POLLING_VCC_OFF:
- *data = as->asic_cap->caps.NO_VCC_OFF_HPD_POLLING;
- break;
-
case FEATURE_STUTTER_MODE:
*data = as->asic_cap->data[ASIC_DATA_STUTTERMODE];
break;
@@ -674,17 +665,6 @@ bool dal_adapter_service_is_dfs_bypass_enabled(
return false;
}
-/*
- * dal_adapter_service_get_asic_vram_bit_width
- *
- * Get the video RAM bit width set on the ASIC
- */
-uint32_t dal_adapter_service_get_asic_vram_bit_width(
- struct adapter_service *as)
-{
- return as->asic_cap->data[ASIC_DATA_VRAM_BITWIDTH];
-}
-
struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags(
struct adapter_service *as)
{
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
index 543fee50c21a..5d50455ca0d8 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
@@ -54,7 +54,6 @@ static bool construct(
memset(cap->data, 0, sizeof(cap->data));
/* ASIC data */
- cap->data[ASIC_DATA_VRAM_BITWIDTH] = init->vram_width;
cap->runtime_flags = init->runtime_flags;
cap->data[ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE] = 10;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 4;
@@ -71,7 +70,6 @@ static bool construct(
cap->caps.WIRELESS_COMPRESSED_AUDIO = false;
cap->caps.VCE_SUPPORTED = false;
cap->caps.HPD_CHECK_FOR_EDID = false;
- cap->caps.NO_VCC_OFF_HPD_POLLING = false;
cap->caps.NEED_MC_TUNING = false;
cap->caps.SUPPORT_8BPP = true;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
index 982d1cd5bad9..90050e8856dd 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
@@ -63,7 +63,6 @@ void carrizo_asic_capability_create(struct asic_capability *cap,
cap->caps.DP_MST_SUPPORTED = true;
cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
cap->caps.MIRABILIS_SUPPORTED = true;
- cap->caps.NO_VCC_OFF_HPD_POLLING = true;
cap->caps.VCE_SUPPORTED = true;
cap->caps.HPD_CHECK_FOR_EDID = true;
cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
index 628f985acf23..f5a3cda8c5b3 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
@@ -111,7 +111,6 @@ void dal_hawaii_asic_capability_create(struct asic_capability *cap,
cap->caps.HEADLESS_NO_OPM_SUPPORTED = true;
cap->caps.HPD_CHECK_FOR_EDID = true;
- cap->caps.NO_VCC_OFF_HPD_POLLING = true;
/* true will hang the system! */
cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = false;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
index 1b1524b2e6e4..89bb01f436b9 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
@@ -66,7 +66,6 @@ void polaris10_asic_capability_create(struct asic_capability *cap,
cap->caps.DP_MST_SUPPORTED = true;
cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
cap->caps.MIRABILIS_SUPPORTED = true;
- cap->caps.NO_VCC_OFF_HPD_POLLING = true;
cap->caps.VCE_SUPPORTED = true;
cap->caps.HPD_CHECK_FOR_EDID = true;
cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
index 58d4913e3aea..aa2333f9dc07 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
@@ -64,7 +64,6 @@ void tonga_asic_capability_create(struct asic_capability *cap,
cap->caps.DP_MST_SUPPORTED = true;
cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
cap->caps.MIRABILIS_SUPPORTED = true;
- cap->caps.NO_VCC_OFF_HPD_POLLING = true;
cap->caps.VCE_SUPPORTED = true;
cap->caps.HPD_CHECK_FOR_EDID = true;
cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index cfc8e8f95d5b..994b91967ad8 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -535,8 +535,7 @@ static bool construct(struct core_dc *dc,
dc_ctx->cgs_device = init_params->cgs_device;
dc_ctx->driver_context = init_params->driver;
dc_ctx->dc = &dc->public;
-
- dc->asic_id = init_params->asic_id;
+ dc_ctx->asic_id = init_params->asic_id;
/* Create logger */
logger = dal_logger_create(dc_ctx);
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
index 30e12e5cbe1b..933fa668da1b 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
@@ -62,28 +62,6 @@ enum dce_environment {
(IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
/********************************/
-
-struct dc_context {
- struct dc *dc;
-
- void *driver_context; /* e.g. amdgpu_device */
-
- struct dal_logger *logger;
- void *cgs_device;
-
- enum dce_environment dce_environment;
-
- /* todo: below should probably move to dc. to facilitate removal
- * of AS we will store these here
- */
- enum dce_version dce_version;
- struct dc_bios *dc_bios;
- bool created_bios;
- struct gpio_service *gpio_service;
- struct i2caux *i2caux;
- struct adapter_service *adapter_srv;
-};
-
/*
* ASIC Runtime Flags
*/
@@ -121,6 +99,29 @@ struct hw_asic_id {
void *atombios_base_address;
};
+struct dc_context {
+ struct dc *dc;
+
+ void *driver_context; /* e.g. amdgpu_device */
+
+ struct dal_logger *logger;
+ void *cgs_device;
+
+ enum dce_environment dce_environment;
+ struct hw_asic_id asic_id;
+
+ /* todo: below should probably move to dc. to facilitate removal
+ * of AS we will store these here
+ */
+ enum dce_version dce_version;
+ struct dc_bios *dc_bios;
+ bool created_bios;
+ struct gpio_service *gpio_service;
+ struct i2caux *i2caux;
+ struct adapter_service *adapter_srv;
+};
+
+
#define MAX_EDID_BUFFER_SIZE 512
#define EDID_BLOCK_SIZE 128
#define MAX_SURFACE_NUM 2
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
index bc444438ec95..1002187b0063 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
@@ -610,8 +610,7 @@ static void link_encoder_edp_wait_for_hpd_ready(
return;
}
- if (!power_up && dal_adapter_service_is_feature_supported(as,
- FEATURE_NO_HPD_LOW_POLLING_VCC_OFF))
+ if (!power_up)
/* from KV, we will not HPD low after turning off VCC -
* instead, we will check the SW timer in power_up(). */
return;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
index 62bf70363b3c..186ce3a9fe94 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
@@ -799,29 +799,22 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor,
struct embedded_panel_info panel_info;
compressor->base.options.bits.FBC_SUPPORT = true;
- if (!(dal_adapter_service_is_feature_supported(as,
- FEATURE_DISABLE_LPT_SUPPORT)))
- compressor->base.options.bits.LPT_SUPPORT = true;
+ compressor->base.options.bits.LPT_SUPPORT = true;
/* For DCE 11 always use one DRAM channel for LPT */
compressor->base.lpt_channels_num = 1;
-
- if (dal_adapter_service_is_feature_supported(as, FEATURE_DUMMY_FBC_BACKEND))
- compressor->base.options.bits.DUMMY_BACKEND = true;
+ compressor->base.options.bits.DUMMY_BACKEND = false;
/* Check if this system has more than 1 DRAM channel; if only 1 then LPT
* should not be supported */
if (compressor->base.memory_bus_width == 64)
compressor->base.options.bits.LPT_SUPPORT = false;
- if (dal_adapter_service_is_feature_supported(as,
- FEATURE_DISABLE_FBC_COMP_CLK_GATE))
- compressor->base.options.bits.CLK_GATING_DISABLED = true;
+ compressor->base.options.bits.CLK_GATING_DISABLED = false;
compressor->base.ctx = ctx;
compressor->base.embedded_panel_h_size = 0;
compressor->base.embedded_panel_v_size = 0;
- compressor->base.memory_bus_width =
- dal_adapter_service_get_asic_vram_bit_width(as);
+ compressor->base.memory_bus_width = ctx->asic_id.vram_width;
compressor->base.allocated_size = 0;
compressor->base.preferred_requested_size = 0;
compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 0ed9b831811d..a924ed0faea6 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -1191,7 +1191,7 @@ static bool construct(
ctx->dc_bios->regs = &bios_regs;
pool->base.adapter_srv = as;
- pool->base.res_cap = dce110_resource_cap(&dc->asic_id);
+ pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
pool->base.funcs = &dce110_res_pool_funcs;
/*************************************************
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
index aa06777306f8..e34779b4b1de 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
@@ -799,29 +799,22 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor,
struct embedded_panel_info panel_info;
compressor->base.options.bits.FBC_SUPPORT = true;
- if (!(dal_adapter_service_is_feature_supported(as,
- FEATURE_DISABLE_LPT_SUPPORT)))
- compressor->base.options.bits.LPT_SUPPORT = true;
+ compressor->base.options.bits.LPT_SUPPORT = true;
/* For DCE 11 always use one DRAM channel for LPT */
compressor->base.lpt_channels_num = 1;
-
- if (dal_adapter_service_is_feature_supported(as, FEATURE_DUMMY_FBC_BACKEND))
- compressor->base.options.bits.DUMMY_BACKEND = true;
+ compressor->base.options.bits.DUMMY_BACKEND = false;
/* Check if this system has more than 1 DRAM channel; if only 1 then LPT
* should not be supported */
if (compressor->base.memory_bus_width == 64)
compressor->base.options.bits.LPT_SUPPORT = false;
- if (dal_adapter_service_is_feature_supported(as,
- FEATURE_DISABLE_FBC_COMP_CLK_GATE))
- compressor->base.options.bits.CLK_GATING_DISABLED = true;
+ compressor->base.options.bits.CLK_GATING_DISABLED = false;
compressor->base.ctx = ctx;
compressor->base.embedded_panel_h_size = 0;
compressor->base.embedded_panel_v_size = 0;
- compressor->base.memory_bus_width =
- dal_adapter_service_get_asic_vram_bit_width(as);
+ compressor->base.memory_bus_width = ctx->asic_id.vram_width;
compressor->base.allocated_size = 0;
compressor->base.preferred_requested_size = 0;
compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 7cd772dbd7ce..0ab589f1c1a7 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -1202,7 +1202,7 @@ static bool construct(
ctx->dc_bios->regs = &bios_regs;
pool->base.adapter_srv = adapter_serv;
- pool->base.res_cap = dce112_resource_cap(&dc->asic_id);
+ pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
pool->base.funcs = &dce112_res_pool_funcs;
/*************************************************
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
index 8cab5e60bc9b..bcd44ebafc36 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
@@ -780,29 +780,22 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor,
struct embedded_panel_info panel_info;
compressor->base.options.bits.FBC_SUPPORT = true;
- if (!(dal_adapter_service_is_feature_supported(as,
- FEATURE_DISABLE_LPT_SUPPORT)))
- compressor->base.options.bits.LPT_SUPPORT = true;
+ compressor->base.options.bits.LPT_SUPPORT = true;
/* For DCE 11 always use one DRAM channel for LPT */
compressor->base.lpt_channels_num = 1;
-
- if (dal_adapter_service_is_feature_supported(as, FEATURE_DUMMY_FBC_BACKEND))
- compressor->base.options.bits.DUMMY_BACKEND = true;
+ compressor->base.options.bits.DUMMY_BACKEND = false;
/* Check if this system has more than 1 DRAM channel; if only 1 then LPT
* should not be supported */
if (compressor->base.memory_bus_width == 64)
compressor->base.options.bits.LPT_SUPPORT = false;
- if (dal_adapter_service_is_feature_supported(as,
- FEATURE_DISABLE_FBC_COMP_CLK_GATE))
- compressor->base.options.bits.CLK_GATING_DISABLED = true;
+ compressor->base.options.bits.CLK_GATING_DISABLED = false;
compressor->base.ctx = ctx;
compressor->base.embedded_panel_h_size = 0;
compressor->base.embedded_panel_v_size = 0;
- compressor->base.memory_bus_width =
- dal_adapter_service_get_asic_vram_bit_width(as);
+ compressor->base.memory_bus_width = ctx->asic_id.vram_width;
compressor->base.allocated_size = 0;
compressor->base.preferred_requested_size = 0;
compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
index 668e6c826090..826ae7a8998f 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
@@ -17,7 +17,6 @@
struct core_dc {
struct dc public;
struct dc_context *ctx;
- struct hw_asic_id asic_id;
uint8_t link_count;
struct core_link *links[MAX_PIPES * 2];
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index bb4964743a4d..eee36b421950 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -80,7 +80,6 @@ enum adapter_feature_id {
FEATURE_ALLOW_EDP_RESOURCE_SHARING,
FEATURE_SUPPORT_DP_YUV,
FEATURE_SUPPORT_DP_Y_ONLY,
- FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, /* 20th */
FEATURE_ENABLE_DFS_BYPASS,
FEATURE_LB_HIGH_RESOLUTION,
FEATURE_DP_DISPLAY_FORCE_SS_ENABLE,
@@ -166,9 +165,6 @@ enum adapter_feature_id {
FEATURE_POWER_GATING_PIPE_IN_TILE = FEATURE_SET_12_END + 1,
FEATURE_SET_13_START = FEATURE_POWER_GATING_PIPE_IN_TILE,
FEATURE_USE_PPLIB,
- FEATURE_DISABLE_LPT_SUPPORT,
- FEATURE_DUMMY_FBC_BACKEND,
- FEATURE_DISABLE_FBC_COMP_CLK_GATE,
FEATURE_DPMS_AUDIO_ENDPOINT_CONTROL,
FEATURE_PIXEL_PERFECT_OUTPUT,
FEATURE_8BPP_SUPPORTED,
@@ -315,6 +311,7 @@ enum as_drr_support {
struct as_init_data {
struct hw_asic_id hw_init_data;
struct dc_context *ctx;
+ const struct dal_override_parameters *display_param;
struct dc_bios *vbios_override;
enum dce_environment dce_environment;
};
@@ -330,11 +327,6 @@ void dal_adapter_service_destroy(
/* Check if DFS bypass is enabled */
bool dal_adapter_service_is_dfs_bypass_enabled(struct adapter_service *as);
-
-/* Get the video RAM bit width set on the ASIC */
-uint32_t dal_adapter_service_get_asic_vram_bit_width(
- struct adapter_service *as);
-
/* Return if a given feature is supported by the ASIC */
bool dal_adapter_service_is_feature_supported(struct adapter_service *as,
enum adapter_feature_id feature_id);
@@ -345,12 +337,6 @@ bool dal_adapter_service_get_feature_value(struct adapter_service *as,
void *data,
uint32_t size);
-/* Get I2C information from BIOS */
-bool dal_adapter_service_get_i2c_info(
- struct adapter_service *as,
- struct graphics_object_id id,
- struct graphics_object_i2c_info *i2c_info);
-
struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags(
struct adapter_service *as);
diff --git a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
index 8c6c40247e02..b0915e7f7048 100644
--- a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
+++ b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
@@ -48,7 +48,6 @@ struct asic_caps {
bool WIRELESS_COMPRESSED_AUDIO:1;
bool VCE_SUPPORTED:1;
bool HPD_CHECK_FOR_EDID:1;
- bool NO_VCC_OFF_HPD_POLLING:1;
bool NEED_MC_TUNING:1;
bool SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT:1;
bool DFSBYPASS_DYNAMIC_SUPPORT:1;
@@ -86,7 +85,6 @@ enum asic_data {
ASIC_DATA_FIRST = 0,
ASIC_DATA_DCE_VERSION = ASIC_DATA_FIRST,
ASIC_DATA_DCE_VERSION_MINOR,
- ASIC_DATA_VRAM_BITWIDTH,
ASIC_DATA_LINEBUFFER_SIZE,
ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY,
ASIC_DATA_MC_LATENCY,
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 43/76] drm/amd/dal: remove unnessary adapter service functions
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (41 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 42/76] drm/amd/dal: remove unnessary adapter service functions Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 44/76] drm/amd/dal: Fix null pointer missed in earlier refactor Harry Wentland
` (33 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- remove FEATURE_USE_MAX_DISPLAY_CLK. move to dc_debug option
- DFS bypass query bios directly. add debug option
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 38 ----------------------
drivers/gpu/drm/amd/dal/dc/core/dc.c | 4 +++
drivers/gpu/drm/amd/dal/dc/dc.h | 2 ++
.../amd/dal/dc/gpu/dce110/display_clock_dce110.c | 14 +++++---
.../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c | 15 +++++----
.../amd/dal/include/adapter_service_interface.h | 9 -----
6 files changed, 23 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index e6a5bd08d997..6034c7416ac0 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -86,7 +86,6 @@ static const struct feature_source_entry feature_entry_table[] = {
{FEATURE_MAXIMIZE_URGENCY_WATERMARKS, false, true},
{FEATURE_MAXIMIZE_STUTTER_MARKS, false, true},
{FEATURE_MAXIMIZE_NBP_MARKS, false, true},
- {FEATURE_USE_MAX_DISPLAY_CLK, false, true},
{FEATURE_ALLOW_EDP_RESOURCE_SHARING, false, true},
{FEATURE_SUPPORT_DP_YUV, false, true},
{FEATURE_SUPPORT_DP_Y_ONLY, false, true},
@@ -94,7 +93,6 @@ static const struct feature_source_entry feature_entry_table[] = {
{FEATURE_DCP_BIT_DEPTH_REDUCTION_MODE, 0, false},
{FEATURE_DCP_DITHER_MODE, 0, false},
{FEATURE_DCP_PROGRAMMING_WA, 0, false},
- {FEATURE_ENABLE_DFS_BYPASS, false, true},
{FEATURE_WIRELESS_FULL_TIMING_ADJUSTMENT, false, true},
{FEATURE_WIRELESS_LIMIT_720P, false, true},
{FEATURE_MODIFY_TIMINGS_FOR_WIRELESS, false, true},
@@ -629,42 +627,6 @@ void dal_adapter_service_destroy(
*as = NULL;
}
-/*
- * dal_adapter_service_is_feature_supported
- *
- * Return if a given feature is supported by the ASIC. The feature has to be
- * a boolean type.
- */
-bool dal_adapter_service_is_feature_supported(struct adapter_service *as,
- enum adapter_feature_id feature_id)
-{
- bool data = 0;
-
- dal_adapter_service_get_feature_value(as, feature_id, &data, sizeof(bool));
-
- return data;
-}
-
-/*
- * dal_adapter_service_is_dfs_bypass_enabled
- *
- * Check if DFS bypass is enabled
- */
-bool dal_adapter_service_is_dfs_bypass_enabled(
- struct adapter_service *as)
-{
- struct dc_bios *bp = as->ctx->dc_bios;
-
- if (bp->integrated_info == NULL)
- return false;
- if ((bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) &&
- dal_adapter_service_is_feature_supported(as,
- FEATURE_ENABLE_DFS_BYPASS))
- return true;
- else
- return false;
-}
-
struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags(
struct adapter_service *as)
{
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index 994b91967ad8..e3ec5c5163b8 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -692,6 +692,10 @@ struct dc *dc_create(const struct dc_init_data *init_params)
dm_logger_write(core_dc->ctx->logger, LOG_DC,
"Display Core initialized\n");
+
+ /* TODO: missing feature to be enabled */
+ core_dc->public.debug.disalbe_dfs_bypass = true;
+
return &core_dc->public;
construct_fail:
diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
index 044fea7ce32a..22ed46d3844c 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
@@ -139,6 +139,8 @@ struct dc_debug {
bool surface_visual_confirm;
bool disable_stutter;
bool disable_dcc;
+ bool disalbe_dfs_bypass;
+ bool max_disp_clk;
};
struct dc {
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
index ec0f6ae61542..af04348d2a7a 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
@@ -36,6 +36,7 @@
#include "../divider_range.h"
#include "display_clock_dce110.h"
+#include "dc.h"
#define FROM_DISPLAY_CLOCK(base) \
container_of(base, struct display_clock_dce110, disp_clk_base)
@@ -670,6 +671,7 @@ static bool display_clock_integrated_info_construct(
struct display_clock_dce110 *disp_clk,
struct adapter_service *as)
{
+ struct dc_debug *debug = &disp_clk->disp_clk_base.ctx->dc->debug;
struct dc_bios *bp = disp_clk->disp_clk_base.ctx->dc_bios;
struct integrated_info info;
struct firmware_info fw_info;
@@ -730,11 +732,13 @@ static bool display_clock_integrated_info_construct(
info.disp_clk_voltage[i].max_supported_clk;
}
}
- disp_clk->dfs_bypass_enabled =
- dal_adapter_service_is_dfs_bypass_enabled(as);
- disp_clk->use_max_disp_clk =
- dal_adapter_service_is_feature_supported(as,
- FEATURE_USE_MAX_DISPLAY_CLK);
+
+ disp_clk->dfs_bypass_enabled = false;
+ if (!debug->disalbe_dfs_bypass)
+ if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
+ disp_clk->dfs_bypass_enabled = true;
+
+ disp_clk->use_max_disp_clk = debug->max_disp_clk;
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
index 68134a0e70b4..3f93a0a3875a 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
@@ -35,6 +35,7 @@
#include "../divider_range.h"
#include "display_clock_dce80.h"
+#include "dc.h"
#define DCE80_DFS_BYPASS_THRESHOLD_KHZ 100000
@@ -754,6 +755,7 @@ static bool display_clock_integrated_info_construct(
struct display_clock_dce80 *disp_clk,
struct adapter_service *as)
{
+ struct dc_debug *debug = &disp_clk->disp_clk.ctx->dc->debug;
struct dc_bios *bp = disp_clk->disp_clk.ctx->dc_bios;
struct integrated_info info = { { { 0 } } };
struct firmware_info fw_info = { { 0 } };
@@ -809,14 +811,13 @@ static bool display_clock_integrated_info_construct(
}
}
- disp_clk->dfs_bypass_enabled =
- dal_adapter_service_is_dfs_bypass_enabled(as) &&
- dal_adapter_service_is_feature_supported(as,
- FEATURE_ENABLE_DFS_BYPASS);
+ disp_clk->dfs_bypass_enabled = false;
+ if (!debug->disalbe_dfs_bypass)
+ if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
+ disp_clk->dfs_bypass_enabled = true;
+
+ disp_clk->use_max_disp_clk = debug->max_disp_clk;
- disp_clk->use_max_disp_clk =
- dal_adapter_service_is_feature_supported(as,
- FEATURE_USE_MAX_DISPLAY_CLK);
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index eee36b421950..4cc9c6272a06 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -76,11 +76,9 @@ enum adapter_feature_id {
FEATURE_MAXIMIZE_URGENCY_WATERMARKS,
FEATURE_MAXIMIZE_STUTTER_MARKS,
FEATURE_MAXIMIZE_NBP_MARKS,
- FEATURE_USE_MAX_DISPLAY_CLK,
FEATURE_ALLOW_EDP_RESOURCE_SHARING,
FEATURE_SUPPORT_DP_YUV,
FEATURE_SUPPORT_DP_Y_ONLY,
- FEATURE_ENABLE_DFS_BYPASS,
FEATURE_LB_HIGH_RESOLUTION,
FEATURE_DP_DISPLAY_FORCE_SS_ENABLE,
FEATURE_REPORT_CE_MODE_ONLY,
@@ -324,13 +322,6 @@ struct adapter_service *dal_adapter_service_create(
void dal_adapter_service_destroy(
struct adapter_service **as);
-/* Check if DFS bypass is enabled */
-bool dal_adapter_service_is_dfs_bypass_enabled(struct adapter_service *as);
-
-/* Return if a given feature is supported by the ASIC */
-bool dal_adapter_service_is_feature_supported(struct adapter_service *as,
- enum adapter_feature_id feature_id);
-
/* Get the cached value of a given feature */
bool dal_adapter_service_get_feature_value(struct adapter_service *as,
const enum adapter_feature_id feature_id,
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 44/76] drm/amd/dal: Fix null pointer missed in earlier refactor
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (42 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 43/76] " Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 45/76] drm/amd/dal: fix typo disalbe_dfs_bypass Harry Wentland
` (32 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
index af04348d2a7a..9a0938d5453a 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
@@ -930,7 +930,7 @@ static bool dal_display_clock_dce110_construct(
struct adapter_service *as)
{
struct display_clock *dc_base = &dc110->disp_clk_base;
- struct dc_bios *bp = dc110->disp_clk_base.ctx->dc_bios;
+ struct dc_bios *bp = ctx->dc_bios;
if (NULL == as)
return false;
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 45/76] drm/amd/dal: fix typo disalbe_dfs_bypass
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (43 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 44/76] drm/amd/dal: Fix null pointer missed in earlier refactor Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 46/76] drm/amd/dal: Remove unused function from dc Harry Wentland
` (31 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 2 +-
drivers/gpu/drm/amd/dal/dc/dc.h | 2 +-
drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c | 2 +-
drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index e3ec5c5163b8..76e6e5d3f98e 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -694,7 +694,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
/* TODO: missing feature to be enabled */
- core_dc->public.debug.disalbe_dfs_bypass = true;
+ core_dc->public.debug.disable_dfs_bypass = true;
return &core_dc->public;
diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
index 22ed46d3844c..d73ae63b4ec9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
@@ -139,7 +139,7 @@ struct dc_debug {
bool surface_visual_confirm;
bool disable_stutter;
bool disable_dcc;
- bool disalbe_dfs_bypass;
+ bool disable_dfs_bypass;
bool max_disp_clk;
};
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
index 9a0938d5453a..c993c541dc7e 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
@@ -734,7 +734,7 @@ static bool display_clock_integrated_info_construct(
}
disp_clk->dfs_bypass_enabled = false;
- if (!debug->disalbe_dfs_bypass)
+ if (!debug->disable_dfs_bypass)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
disp_clk->dfs_bypass_enabled = true;
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
index 3f93a0a3875a..8fd78b8c93ae 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
@@ -812,7 +812,7 @@ static bool display_clock_integrated_info_construct(
}
disp_clk->dfs_bypass_enabled = false;
- if (!debug->disalbe_dfs_bypass)
+ if (!debug->disable_dfs_bypass)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
disp_clk->dfs_bypass_enabled = true;
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 46/76] drm/amd/dal: Remove unused function from dc
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (44 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 45/76] drm/amd/dal: fix typo disalbe_dfs_bypass Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 47/76] drm/amd/dal: remove dal_adapter_service_should_optimize Harry Wentland
` (30 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ding Wang
From: Ding Wang <Ding.Wang@amd.com>
Signed-off-by: Ding Wang <Ding.Wang@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 8 --------
drivers/gpu/drm/amd/dal/dc/dm_services.h | 3 ---
2 files changed, 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index 76e6e5d3f98e..d7721c218017 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -902,12 +902,6 @@ static bool targets_changed(
return false;
}
-void pplib_apply_safe_state(
- const struct core_dc *dc)
-{
- dm_pp_apply_safe_state(dc->ctx);
-}
-
static void fill_display_configs(
const struct validate_context *context,
struct dm_pp_display_configuration *pp_display_cfg)
@@ -1110,8 +1104,6 @@ bool dc_commit_targets(
goto fail;
}
- pplib_apply_safe_state(core_dc);
-
if (!dcb->funcs->is_accelerated_mode(dcb)) {
core_dc->hwss.enable_accelerated_mode(core_dc);
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
index 04349c723e2e..016df3468a12 100644
--- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
@@ -215,9 +215,6 @@ bool dm_pp_notify_wm_clock_changes(
const struct dc_context *ctx,
struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
-bool dm_pp_apply_safe_state(
- const struct dc_context *ctx);
-
/* DAL calls this function to notify PP about completion of Mode Set.
* For PP it means that current DCE clocks are those which were returned
* by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 47/76] drm/amd/dal: remove dal_adapter_service_should_optimize
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (45 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 46/76] drm/amd/dal: Remove unused function from dc Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 48/76] drm/amd/dal: remove dal_adapter_service_get_feature_value Harry Wentland
` (29 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- remove runtime_flags. only flag used is SKIP_POWER_DOWN_ON_RESUME and = 1 for all platform
- remove optimization_feature. optimization are default behavior
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 5 --
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 56 ----------------------
.../amd/dal/dc/asic_capability/asic_capability.c | 1 -
drivers/gpu/drm/amd/dal/dc/core/dc.c | 1 -
drivers/gpu/drm/amd/dal/dc/dc_types.h | 26 ----------
drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c | 6 +--
.../amd/dal/include/adapter_service_interface.h | 3 --
.../amd/dal/include/asic_capability_interface.h | 1 -
.../drm/amd/dal/include/grph_object_ctrl_defs.h | 30 ------------
9 files changed, 2 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
index f667620e30e9..9a65b978d07a 100644
--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
@@ -280,11 +280,6 @@ int amdgpu_dm_init(struct amdgpu_device *adev)
/* TODO: initialize init_data.asic_id.vram_type here!!!! */
init_data.asic_id.atombios_base_address =
adev->mode_info.atom_context->bios;
- init_data.asic_id.runtime_flags.flags.bits.SKIP_POWER_DOWN_ON_RESUME = 1;
-
- if ((adev->asic_type == CHIP_CARRIZO) ||
- (adev->asic_type == CHIP_STONEY))
- init_data.asic_id.runtime_flags.flags.bits.GNB_WAKEUP_SUPPORTED = 1;
init_data.driver = adev;
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index 6034c7416ac0..a6e0763c21e5 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -627,12 +627,6 @@ void dal_adapter_service_destroy(
*as = NULL;
}
-struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags(
- struct adapter_service *as)
-{
- return as->asic_cap->runtime_flags;
-}
-
/*
* dal_adapter_service_get_feature_value
*
@@ -688,53 +682,3 @@ bool dal_adapter_service_get_feature_value(struct adapter_service *as,
return true;
}
-/*
- * dal_adapter_service_should_optimize
- *
- * @brief Reports whether driver settings allow requested optimization
- *
- * @param
- * as: adapter service handler
- * feature: for which optimization is validated
- *
- * @return
- * true if requested feature can be optimized
- */
-bool dal_adapter_service_should_optimize(
- struct adapter_service *as, enum optimization_feature feature)
-{
- uint32_t supported_optimization = 0;
- struct dal_asic_runtime_flags flags;
- struct dc_bios *bp = as->ctx->dc_bios;
-
- if (!dal_adapter_service_get_feature_value(as, FEATURE_OPTIMIZATION,
- &supported_optimization, sizeof(uint32_t)))
- return false;
-
- /* Retrieve ASIC runtime flags */
- flags = dal_adapter_service_get_asic_runtime_flags(as);
-
- /* Check runtime flags against different optimization features */
- switch (feature) {
- case OF_SKIP_HW_PROGRAMMING_ON_ENABLED_EMBEDDED_DISPLAY:
- if (!flags.flags.bits.OPTIMIZED_DISPLAY_PROGRAMMING_ON_BOOT)
- return false;
- break;
-
- case OF_SKIP_RESET_OF_ALL_HW_ON_S3RESUME:
- if (bp->integrated_info == NULL ||
- !flags.flags.bits.SKIP_POWER_DOWN_ON_RESUME)
- return false;
- break;
- case OF_SKIP_POWER_DOWN_INACTIVE_ENCODER:
- if (!dal_adapter_service_get_asic_runtime_flags(as).flags.bits.
- SKIP_POWER_DOWN_ON_RESUME)
- return false;
- break;
- default:
- break;
- }
-
- return (supported_optimization & feature) != 0;
-}
-
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
index 5d50455ca0d8..89dd74675ba9 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
@@ -54,7 +54,6 @@ static bool construct(
memset(cap->data, 0, sizeof(cap->data));
/* ASIC data */
- cap->runtime_flags = init->runtime_flags;
cap->data[ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE] = 10;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 4;
cap->data[ASIC_DATA_DOWNSCALE_LIMIT] = 200;
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index d7721c218017..4e1a9383ebcb 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -181,7 +181,6 @@ static struct adapter_service *create_as(
init_data.hw_init_data.fake_paths_num = init->asic_id.fake_paths_num;
init_data.hw_init_data.feature_flags = init->asic_id.feature_flags;
init_data.hw_init_data.hw_internal_rev = init->asic_id.hw_internal_rev;
- init_data.hw_init_data.runtime_flags = init->asic_id.runtime_flags;
init_data.hw_init_data.vram_width = init->asic_id.vram_width;
init_data.hw_init_data.vram_type = init->asic_id.vram_type;
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
index 933fa668da1b..fb8d094429bc 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
@@ -61,31 +61,6 @@ enum dce_environment {
#define IS_DIAG_DC(dce_environment) \
(IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
-/********************************/
-/*
- * ASIC Runtime Flags
- */
-struct dal_asic_runtime_flags {
- union {
- uint32_t raw;
- struct {
- uint32_t EMULATE_REPLUG_ON_CAP_CHANGE:1;
- uint32_t SUPPORT_XRBIAS:1;
- uint32_t SKIP_POWER_DOWN_ON_RESUME:1;
- uint32_t FULL_DETECT_ON_RESUME:1;
- uint32_t GSL_FRAMELOCK:1;
- uint32_t NO_LOW_BPP_MODES:1;
- uint32_t BLOCK_ON_INITIAL_DETECTION:1;
- uint32_t OPTIMIZED_DISPLAY_PROGRAMMING_ON_BOOT:1;
- uint32_t DRIVER_CONTROLLED_BRIGHTNESS:1;
- uint32_t MODIFIABLE_FRAME_DURATION:1;
- uint32_t MIRACAST_SUPPORTED:1;
- uint32_t CONNECTED_STANDBY_SUPPORTED:1;
- uint32_t GNB_WAKEUP_SUPPORTED:1;
- } bits;
- } flags;
-};
-
struct hw_asic_id {
uint32_t chip_id;
uint32_t chip_family;
@@ -94,7 +69,6 @@ struct hw_asic_id {
uint32_t vram_type;
uint32_t vram_width;
uint32_t feature_flags;
- struct dal_asic_runtime_flags runtime_flags;
uint32_t fake_paths_num;
void *atombios_base_address;
};
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
index 1002187b0063..88a775b7c1fb 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
@@ -1359,10 +1359,8 @@ void dce110_link_encoder_disable_output(
struct bp_transmitter_control cntl = { 0 };
enum bp_result result;
- if (!is_dig_enabled(enc110) && enc110->base.adapter_service &&
- dal_adapter_service_should_optimize(
- enc110->base.adapter_service,
- OF_SKIP_POWER_DOWN_INACTIVE_ENCODER)) {
+ if (!is_dig_enabled(enc110)) {
+ /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
return;
}
/* Power-down RX and disable GPU PHY should be paired.
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index 4cc9c6272a06..a88c94d0ef45 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -328,9 +328,6 @@ bool dal_adapter_service_get_feature_value(struct adapter_service *as,
void *data,
uint32_t size);
-struct dal_asic_runtime_flags dal_adapter_service_get_asic_runtime_flags(
- struct adapter_service *as);
-
/* Reports whether driver settings allow requested optimization */
bool dal_adapter_service_should_optimize(
struct adapter_service *as, enum optimization_feature feature);
diff --git a/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h b/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h
index b5335d188c3a..57cc72fdc560 100644
--- a/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/asic_capability_interface.h
@@ -38,7 +38,6 @@ struct asic_capability {
struct asic_caps caps;
struct asic_stereo_3d_caps stereo_3d_caps;
struct asic_bugs bugs;
- struct dal_asic_runtime_flags runtime_flags;
uint32_t data[ASIC_DATA_MAX_NUMBER];
};
diff --git a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
index 10909c33d66e..9c0bf6521dd9 100644
--- a/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
+++ b/drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h
@@ -381,36 +381,6 @@ struct bios_event_info {
bool backlight_changed;
};
-/* Bitvector and bitfields of possible optimizations
- #IMPORTANT# Keep bitfields match bitvector! */
-enum optimization_feature {
- /* Don't do HW programming on panels that were enabled by VBIOS */
- OF_SKIP_HW_PROGRAMMING_ON_ENABLED_EMBEDDED_DISPLAY = 0x1,
- OF_SKIP_RESET_OF_ALL_HW_ON_S3RESUME = 0x2,
- OF_SKIP_HW_RESET_OF_EMBEDDED_DISPLAY_ON_S3RESUME = 0x4,
- OF_SKIP_POWER_UP_VBIOS_ENABLED_ENCODER = 0x8,
- /* Do not turn off VCC while powering down on boot or resume */
- OF_KEEP_VCC_DURING_POWER_DOWN_ON_BOOT_OR_RESUME = 0x10,
- /* Do not turn off VCC while performing SetMode */
- OF_KEEP_VCC_DURING_SET_MODE = 0x20,
- OF_DO_NOT_WAIT_FOR_HPD_LOW = 0x40,
- OF_SKIP_POWER_DOWN_INACTIVE_ENCODER = 0x80
-};
-
-/* Bitvector and bitfields of performance measurements
- #IMPORTANT# Keep bitfields match bitvector! */
-
-enum {
- PERF_MEASURE_POWERCODE_OFFSET = 0x0,
- PERF_MEASURE_POWER_CODE_MASK = 0xFF,
- PERF_MEASURE_POWER_STATE_OFFSET = 8,
- PERF_MEASURE_POWER_STATE_MASK = 0x000FF00,
- PERF_MEASURE_PREV_POWER_STATE_OFFSET = 16,
- PERF_MEASURE_PREV_POWER_STATE_MASK = 0x00FF0000,
- PERF_MEASURE_DISPLAY_INDEX_OFFSET = 24,
- PERF_MEASURE_DISPLAY_INDEX_MASK = 0xFF000000
-};
-
enum {
HDMI_PIXEL_CLOCK_IN_KHZ_297 = 297000,
TMDS_PIXEL_CLOCK_IN_KHZ_165 = 165000
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 48/76] drm/amd/dal: remove dal_adapter_service_get_feature_value
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (46 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 47/76] drm/amd/dal: remove dal_adapter_service_should_optimize Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 49/76] drm/amd/dal: remove adapter_service from Harry Wentland
` (28 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION always = 0.
-- this is a debug option when dmif first got introduced. no need to keep it. always allocate DMIF
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 59 ----------------------
.../dc/asic_capability/carrizo_asic_capability.c | 1 -
.../dc/asic_capability/hawaii_asic_capability.c | 3 --
.../dc/asic_capability/polaris10_asic_capability.c | 1 -
.../dal/dc/asic_capability/tonga_asic_capability.c | 1 -
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 26 ++++------
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 23 ---------
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c | 5 --
drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c | 14 ++---
drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h | 7 +++
.../amd/dal/include/adapter_service_interface.h | 17 +------
.../drm/amd/dal/include/asic_capability_types.h | 1 -
12 files changed, 21 insertions(+), 137 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index a6e0763c21e5..41d9a6125e14 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -100,7 +100,6 @@ static const struct feature_source_entry feature_entry_table[] = {
{FEATURE_LB_HIGH_RESOLUTION, false, true},
{FEATURE_MAX_CONTROLLER_NUM, 0, false},
{FEATURE_DRR_SUPPORT, AS_DRR_SUPPORT_ENABLED, false},
- {FEATURE_STUTTER_MODE, 15, false},
{FEATURE_DP_DISPLAY_FORCE_SS_ENABLE, false, true},
{FEATURE_REPORT_CE_MODE_ONLY, false, true},
{FEATURE_ALLOW_OPTIMIZED_MODE_AS_DEFAULT, false, true},
@@ -360,10 +359,6 @@ static bool get_feature_value_from_data_sources(
*data = as->asic_cap->caps.HPD_CHECK_FOR_EDID;
break;
- case FEATURE_STUTTER_MODE:
- *data = as->asic_cap->data[ASIC_DATA_STUTTERMODE];
- break;
-
case FEATURE_8BPP_SUPPORTED:
*data = as->asic_cap->caps.SUPPORT_8BPP;
break;
@@ -627,58 +622,4 @@ void dal_adapter_service_destroy(
*as = NULL;
}
-/*
- * dal_adapter_service_get_feature_value
- *
- * Get the cached value of a given feature. This value can be a boolean, int,
- * or characters.
- */
-bool dal_adapter_service_get_feature_value(struct adapter_service *as,
- const enum adapter_feature_id feature_id,
- void *data,
- uint32_t size)
-{
- uint32_t entry_idx = 0;
- uint32_t set_idx = 0;
- uint32_t set_internal_idx = 0;
-
- if (feature_id >= FEATURE_MAXIMUM || feature_id <= FEATURE_UNKNOWN) {
- ASSERT_CRITICAL(false);
- return false;
- }
-
- if (data == NULL) {
- ASSERT_CRITICAL(false);
- return false;
- }
-
- entry_idx = lookup_feature_entry(as, feature_id);
- set_idx = (uint32_t)((feature_id - 1)/32);
- set_internal_idx = (uint32_t)((feature_id - 1) % 32);
-
- if (entry_idx >= get_feature_entries_num()) {
- /* Cannot find this entry */
- ASSERT_CRITICAL(false);
- return false;
- }
-
- if (feature_entry_table[entry_idx].is_boolean_type) {
- if (size != sizeof(bool)) {
- ASSERT_CRITICAL(false);
- return false;
- }
-
- *(bool *)data = get_bool_value(as->adapter_feature_set[set_idx],
- set_internal_idx);
- } else {
- if (size != sizeof(uint32_t)) {
- ASSERT_CRITICAL(false);
- return false;
- }
-
- *(uint32_t *)data = as->adapter_feature_set[set_idx];
- }
-
- return true;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
index 90050e8856dd..7243e51e909f 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
@@ -53,7 +53,6 @@ void carrizo_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 45;
cap->data[ASIC_DATA_MC_LATENCY] = 5000;
- cap->data[ASIC_DATA_STUTTERMODE] = 0x200A;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
cap->data[ASIC_DATA_DOWNSCALE_LIMIT] = 150;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
index f5a3cda8c5b3..e0c9ef4557e7 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
@@ -63,9 +63,6 @@ void dal_hawaii_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
cap->data[ASIC_DATA_MC_LATENCY] = 5000; /* units of ns */
-
- /* StutterModeEnhanced; Quad DMIF Buffer */
- cap->data[ASIC_DATA_STUTTERMODE] = 0x2002;
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
index 89bb01f436b9..7716d6587793 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
@@ -54,7 +54,6 @@ void polaris10_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
cap->data[ASIC_DATA_MC_LATENCY] = 3000;
- cap->data[ASIC_DATA_STUTTERMODE] = 0x200A;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
index aa2333f9dc07..6c819ab8fd6e 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
@@ -50,7 +50,6 @@ void tonga_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
cap->data[ASIC_DATA_MC_LATENCY] = 5000;
- cap->data[ASIC_DATA_STUTTERMODE] = 0x2002;
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
index 3eb0e73d2eb6..a78ad8ddcaf8 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
@@ -836,10 +836,6 @@ void dce110_allocate_mem_input(
uint32_t field;
uint32_t pix_dur;
- if (bm110->supported_stutter_mode
- & STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION)
- goto register_underflow_int;
-
/*Allocate DMIF buffer*/
value = dm_read_reg(mi->ctx, addr);
field = get_reg_field_value(
@@ -950,14 +946,10 @@ void dce110_free_mem_input(
struct dce110_mem_input *bm_dce110 = TO_DCE110_MEM_INPUT(mi);
uint32_t value;
- if (!(bm_dce110->supported_stutter_mode &
- STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION)) {
-
- /* De-allocate DMIF buffer first */
- if (mmPIPE0_DMIF_BUFFER_CONTROL + bm_dce110->offsets.pipe != 0)
- deallocate_dmif_buffer_helper(
- mi->ctx, bm_dce110->offsets.pipe);
- }
+ /* De-allocate DMIF buffer first */
+ if (mmPIPE0_DMIF_BUFFER_CONTROL + bm_dce110->offsets.pipe != 0)
+ deallocate_dmif_buffer_helper(
+ mi->ctx, bm_dce110->offsets.pipe);
/* TODO: unregister underflow interrupt
unregisterInterrupt();
@@ -1005,6 +997,11 @@ bool dce110_mem_input_construct(
uint32_t inst,
const struct dce110_mem_input_reg_offsets *offsets)
{
+ /* supported stutter method
+ * STUTTER_MODE_ENHANCED
+ * STUTTER_MODE_QUAD_DMIF_BUFFER
+ * STUTTER_MODE_WATERMARK_NBP_STATE
+ */
mem_input110->base.funcs = &dce110_mem_input_funcs;
mem_input110->base.ctx = ctx;
@@ -1012,10 +1009,5 @@ bool dce110_mem_input_construct(
mem_input110->offsets = *offsets;
- mem_input110->supported_stutter_mode = 0;
- dal_adapter_service_get_feature_value(as, FEATURE_STUTTER_MODE,
- &(mem_input110->supported_stutter_mode),
- sizeof(mem_input110->supported_stutter_mode));
-
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
index 7a521c56e8d9..8edd25ab19a6 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
@@ -36,32 +36,9 @@ struct dce110_mem_input_reg_offsets {
uint32_t pipe;
};
-enum stutter_mode_type {
-/* TODO: Clean up these enums, right now only one is being used
- * STUTTER_MODE_LEGACY = 0X00000001,
- * STUTTER_MODE_ENHANCED = 0X00000002,
- * STUTTER_MODE_FID_NBP_STATE = 0X00000004,
- * STUTTER_MODE_WATERMARK_NBP_STATE = 0X00000008,
- * STUTTER_MODE_SINGLE_DISPLAY_MODEL = 0X00000010,
- * STUTTER_MODE_MIXED_DISPLAY_MODEL = 0X00000020,
- * STUTTER_MODE_DUAL_DMIF_BUFFER = 0X00000040,
- */
- STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION = 0X00000080,
-/*
- * STUTTER_MODE_NO_ADVANCED_REQUEST = 0X00000100,
- * STUTTER_MODE_NO_LB_RESET = 0X00000200,
- * STUTTER_MODE_DISABLED = 0X00000400,
- * STUTTER_MODE_AGGRESSIVE_MARKS = 0X00000800,
- * STUTTER_MODE_URGENCY = 0X00001000,
- * STUTTER_MODE_QUAD_DMIF_BUFFER = 0X00002000,
- * STUTTER_MODE_NOT_USED = 0X00008000
- */
-};
-
struct dce110_mem_input {
struct mem_input base;
struct dce110_mem_input_reg_offsets offsets;
- uint32_t supported_stutter_mode;
};
bool dce110_mem_input_construct(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
index 0903d3b4913d..78c63680cc0b 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
@@ -1071,11 +1071,6 @@ bool dce110_mem_input_v_construct(
mem_input110->offsets = dce110_mi_v_reg_offsets[0];
- mem_input110->supported_stutter_mode = 0;
- dal_adapter_service_get_feature_value(as, FEATURE_STUTTER_MODE,
- &(mem_input110->supported_stutter_mode),
- sizeof(mem_input110->supported_stutter_mode));
-
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
index 5e08a2dfb039..be822d1b5989 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
@@ -108,10 +108,6 @@ static void allocate_mem_input(
uint32_t value;
uint32_t field;
- if (bm80->supported_stutter_mode
- & STUTTER_MODE_NO_DMIF_BUFFER_ALLOCATION)
- goto register_underflow_int;
-
/*Allocate DMIF buffer*/
value = dm_read_reg(mi->ctx, addr);
field = get_reg_field_value(
@@ -194,7 +190,10 @@ bool dce80_mem_input_construct(
uint32_t inst,
const struct dce110_mem_input_reg_offsets *offsets)
{
-
+ /* supported stutter method
+ * STUTTER_MODE_ENHANCED
+ * STUTTER_MODE_QUAD_DMIF_BUFFER
+ */
mem_input80->base.funcs = &dce80_mem_input_funcs;
mem_input80->base.ctx = ctx;
@@ -202,11 +201,6 @@ bool dce80_mem_input_construct(
mem_input80->offsets = *offsets;
- mem_input80->supported_stutter_mode = 0;
- dal_adapter_service_get_feature_value(as, FEATURE_STUTTER_MODE,
- &(mem_input80->supported_stutter_mode),
- sizeof(mem_input80->supported_stutter_mode));
-
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
index c743ae13cdf5..c4a78eefd362 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
@@ -29,12 +29,19 @@
#include "include/grph_object_id.h"
#include "inc/bandwidth_calcs.h"
+struct stutter_modes {
+ bool enhanced;
+ bool quad_dmif_buffer;
+ bool watermark_nb_pstate;
+};
+
struct mem_input {
struct mem_input_funcs *funcs;
struct dc_context *ctx;
struct dc_plane_address request_address;
struct dc_plane_address current_address;
uint32_t inst;
+ struct stutter_modes stutter_mode;
};
struct mem_input_funcs {
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index a88c94d0ef45..48484b0de5bb 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -149,13 +149,8 @@ enum adapter_feature_id {
FEATURE_SET_10_START = FEATURE_DRR_SUPPORT,
FEATURE_SET_10_END = FEATURE_SET_10_START + 31,
- /* UInt set, 1 entry: Stutter mode support */
- FEATURE_STUTTER_MODE = FEATURE_SET_10_END + 1,
- FEATURE_SET_11_START = FEATURE_STUTTER_MODE,
- FEATURE_SET_11_END = FEATURE_SET_11_START + 31,
-
/* UInt set, 1 entry: Measure PSR setup time */
- FEATURE_PSR_SETUP_TIME_TEST = FEATURE_SET_11_END + 1,
+ FEATURE_PSR_SETUP_TIME_TEST = FEATURE_SET_10_END + 1,
FEATURE_SET_12_START = FEATURE_PSR_SETUP_TIME_TEST,
FEATURE_SET_12_END = FEATURE_SET_12_START + 31,
@@ -322,14 +317,4 @@ struct adapter_service *dal_adapter_service_create(
void dal_adapter_service_destroy(
struct adapter_service **as);
-/* Get the cached value of a given feature */
-bool dal_adapter_service_get_feature_value(struct adapter_service *as,
- const enum adapter_feature_id feature_id,
- void *data,
- uint32_t size);
-
-/* Reports whether driver settings allow requested optimization */
-bool dal_adapter_service_should_optimize(
- struct adapter_service *as, enum optimization_feature feature);
-
#endif /* __DAL_ADAPTER_SERVICE_INTERFACE_H__ */
diff --git a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
index b0915e7f7048..c44dae043599 100644
--- a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
+++ b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
@@ -90,7 +90,6 @@ enum asic_data {
ASIC_DATA_MC_LATENCY,
ASIC_DATA_MC_LATENCY_SLOW,
ASIC_DATA_MEMORYTYPE_MULTIPLIER,
- ASIC_DATA_STUTTERMODE,
ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR,
ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE,
ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY,
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 49/76] drm/amd/dal: remove adapter_service from
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (47 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 48/76] drm/amd/dal: remove dal_adapter_service_get_feature_value Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 50/76] drm/amd/dal: remove adapter_service dependency Harry Wentland
` (27 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- bios, clock source. compressor, mem_input, timing_generator, link_encoder
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 2 +-
drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 22 +++++++++-------------
drivers/gpu/drm/amd/dal/dc/core/dc.c | 1 -
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 1 -
drivers/gpu/drm/amd/dal/dc/dc_bios_types.h | 3 +--
drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c | 4 ----
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 9 ++++-----
.../drm/amd/dal/dc/dce110/dce110_clock_source.c | 1 -
.../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c | 8 +++-----
.../gpu/drm/amd/dal/dc/dce110/dce110_compressor.h | 5 ++---
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 2 --
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 1 -
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c | 3 +--
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h | 3 +--
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 13 ++++++-------
.../amd/dal/dc/dce110/dce110_timing_generator.c | 4 ----
.../amd/dal/dc/dce110/dce110_timing_generator.h | 1 -
.../amd/dal/dc/dce110/dce110_timing_generator_v.c | 4 ----
.../amd/dal/dc/dce110/dce110_timing_generator_v.h | 1 -
.../gpu/drm/amd/dal/dc/dce112/dce112_compressor.c | 7 +++----
.../gpu/drm/amd/dal/dc/dce112/dce112_compressor.h | 5 ++---
.../gpu/drm/amd/dal/dc/dce112/dce112_mem_input.c | 3 +--
.../gpu/drm/amd/dal/dc/dce112/dce112_mem_input.h | 1 -
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 6 +++---
.../gpu/drm/amd/dal/dc/dce80/dce80_compressor.c | 9 +++------
.../gpu/drm/amd/dal/dc/dce80/dce80_compressor.h | 5 ++---
drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c | 1 -
drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h | 1 -
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 9 ++++-----
.../drm/amd/dal/dc/dce80/dce80_timing_generator.c | 5 -----
.../drm/amd/dal/dc/dce80/dce80_timing_generator.h | 1 -
.../amd/dal/dc/gpu/dce110/display_clock_dce110.c | 16 +++++-----------
.../amd/dal/dc/gpu/dce112/display_clock_dce112.c | 3 +--
.../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c | 21 +++++++--------------
.../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.h | 3 +--
drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c | 2 --
drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h | 1 -
drivers/gpu/drm/amd/dal/dc/inc/compressor.h | 1 +
drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h | 1 -
.../drm/amd/dal/dc/virtual/virtual_link_encoder.c | 2 --
.../drm/amd/dal/include/bios_parser_interface.h | 1 -
.../drm/amd/dal/include/display_clock_interface.h | 9 +++------
42 files changed, 64 insertions(+), 137 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index 41d9a6125e14..b91301561b7f 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -548,7 +548,7 @@ static bool adapter_service_construct(
dcb = as->ctx->dc_bios;
- dcb->funcs->post_init(dcb, as);
+ dcb->funcs->post_init(dcb);
/* Generate backlight translation table and initializes
other brightness properties */
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
index 586df420f87b..1d3ee3f10f3e 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
@@ -2923,7 +2923,7 @@ static uint32_t get_support_mask_for_device_id(struct device_id device_id)
*/
static bool i2c_read(
- struct adapter_service *as,
+ struct bios_parser *bp,
struct graphics_object_i2c_info *i2c_info,
uint8_t *buffer,
uint32_t length)
@@ -2936,7 +2936,7 @@ static bool i2c_read(
i2c_info->i2c_hw_assist,
i2c_info->i2c_line };
- ddc = dal_gpio_create_ddc(as->ctx->gpio_service,
+ ddc = dal_gpio_create_ddc(bp->base.ctx->gpio_service,
i2c_info->gpio_info.clk_a_register_index,
(1 << i2c_info->gpio_info.clk_a_shift), &hw_info);
@@ -2986,7 +2986,6 @@ static bool i2c_read(
*/
static enum bp_result get_ext_display_connection_info(
struct bios_parser *bp,
- struct adapter_service *as,
ATOM_OBJECT *opm_object,
ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO *ext_display_connection_info_tbl)
{
@@ -3013,7 +3012,7 @@ static enum bp_result get_ext_display_connection_info(
BP_RESULT_OK)
return BP_RESULT_BADBIOSTABLE;
- if (i2c_read(as,
+ if (i2c_read(bp,
&i2c_info,
(uint8_t *)ext_display_connection_info_tbl,
sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO))) {
@@ -3333,8 +3332,7 @@ static ATOM_CONNECTOR_HPDPIN_LUT_RECORD *get_ext_connector_hpd_pin_lut_record(
*
*/
static enum bp_result patch_bios_image_from_ext_display_connection_info(
- struct bios_parser *bp,
- struct adapter_service *as)
+ struct bios_parser *bp)
{
ATOM_OBJECT_TABLE *connector_tbl;
uint32_t connector_tbl_offset;
@@ -3374,7 +3372,7 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
connector_tbl = GET_IMAGE(ATOM_OBJECT_TABLE, connector_tbl_offset);
/* Read Connector info table from EEPROM through i2c */
- if (get_ext_display_connection_info(bp, as,
+ if (get_ext_display_connection_info(bp,
opm_object,
&ext_display_connection_info_tbl) != BP_RESULT_OK) {
@@ -3570,8 +3568,7 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
*
*/
-static void process_ext_display_connection_info(struct bios_parser *bp,
- struct adapter_service *as)
+static void process_ext_display_connection_info(struct bios_parser *bp)
{
ATOM_OBJECT_TABLE *connector_tbl;
uint32_t connector_tbl_offset;
@@ -3626,7 +3623,7 @@ static void process_ext_display_connection_info(struct bios_parser *bp,
/* Step 2: (only if MXM connector found) Patch BIOS image with
* info from external module */
if (mxm_connector_found &&
- patch_bios_image_from_ext_display_connection_info(bp, as) !=
+ patch_bios_image_from_ext_display_connection_info(bp) !=
BP_RESULT_OK) {
/* Patching the bios image has failed. We will copy
* again original image provided and afterwards
@@ -3660,12 +3657,11 @@ static void process_ext_display_connection_info(struct bios_parser *bp,
}
}
-static void bios_parser_post_init(struct dc_bios *dcb,
- struct adapter_service *as)
+static void bios_parser_post_init(struct dc_bios *dcb)
{
struct bios_parser *bp = BP_FROM_DCB(dcb);
- process_ext_display_connection_info(bp, as);
+ process_ext_display_connection_info(bp);
}
static bool bios_parser_is_accelerated_mode(
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index 4e1a9383ebcb..c5f98525a630 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -139,7 +139,6 @@ static bool create_links(
link->link_id.enum_id = ENUM_ID_1;
link->link_enc = dm_alloc(sizeof(*link->link_enc));
- enc_init.adapter_service = as;
enc_init.ctx = dc->ctx;
enc_init.channel = CHANNEL_ID_UNKNOWN;
enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index 1eb1089a8288..e59e439a35e7 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -1032,7 +1032,6 @@ static bool construct(
dal_ddc_get_line(
dal_ddc_service_get_ddc_pin(link->ddc));
- enc_init_data.adapter_service = as;
enc_init_data.ctx = dc_ctx;
bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
enc_init_data.connector = link->link_id;
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
index 4771e415e33e..790c5bd51cb9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_bios_types.h
@@ -199,8 +199,7 @@ struct dc_vbios_funcs {
enum controller_id controller_id,
enum bp_pipe_control_action action);
- void (*post_init)(struct dc_bios *bios,
- struct adapter_service *as);
+ void (*post_init)(struct dc_bios *bios);
void (*bios_parser_destroy)(struct dc_bios **dcb);
};
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
index 88a775b7c1fb..b924b3d5bc22 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
@@ -596,7 +596,6 @@ static void link_encoder_edp_wait_for_hpd_ready(
bool power_up)
{
struct dc_context *ctx = enc110->base.ctx;
- struct adapter_service *as = enc110->base.adapter_service;
struct graphics_object_id connector = enc110->base.connector;
struct gpio *hpd;
bool edp_hpd_high = false;
@@ -971,7 +970,6 @@ bool dce110_link_encoder_construct(
const struct dce110_link_enc_hpd_registers *hpd_regs)
{
struct graphics_object_encoder_cap_info enc_cap_info = {0};
- struct adapter_service *as = init_data->adapter_service;
enc110->base.funcs = &dce110_lnk_enc_funcs;
enc110->base.ctx = init_data->ctx;
@@ -981,8 +979,6 @@ bool dce110_link_encoder_construct(
enc110->base.connector = init_data->connector;
enc110->base.input_signals = SIGNAL_TYPE_ALL;
- enc110->base.adapter_service = as;
-
enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
enc110->base.features.flags.raw = 0;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 908bb297bd0f..feb922836e82 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -418,7 +418,7 @@ static struct timing_generator *dce100_timing_generator_create(
if (!tg110)
return NULL;
- if (dce110_timing_generator_construct(tg110, as, ctx, instance,
+ if (dce110_timing_generator_construct(tg110, ctx, instance,
offsets))
return &tg110->base;
@@ -455,7 +455,6 @@ static const struct resource_create_funcs res_create_funcs = {
static struct mem_input *dce100_mem_input_create(
struct dc_context *ctx,
- struct adapter_service *as,
uint32_t inst,
const struct dce110_mem_input_reg_offsets *offset)
{
@@ -466,7 +465,7 @@ static struct mem_input *dce100_mem_input_create(
return NULL;
if (dce110_mem_input_construct(mem_input110,
- ctx, as, inst, offset))
+ ctx, inst, offset))
return &mem_input110->base;
BREAK_TO_DEBUGGER();
@@ -918,7 +917,7 @@ static bool construct(
}
}
- pool->base.display_clock = dal_display_clock_dce110_create(ctx, as);
+ pool->base.display_clock = dal_display_clock_dce110_create(ctx);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
@@ -973,7 +972,7 @@ static bool construct(
goto res_create_fail;
}
- pool->base.mis[i] = dce100_mem_input_create(ctx, as, i,
+ pool->base.mis[i] = dce100_mem_input_create(ctx, i,
&dce100_mi_reg_offsets[i]);
if (pool->base.mis[i] == NULL) {
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
index 0e81aec6ef78..08d3bdacacc3 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
@@ -36,7 +36,6 @@
#include "include/logger_interface.h"
#include "dce110_clock_source.h"
-#include "adapter_service_interface.h"
#define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
#define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
index 186ce3a9fe94..518150a414e2 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
@@ -31,7 +31,6 @@
#include "gmc/gmc_8_2_d.h"
#include "include/logger_interface.h"
-#include "include/adapter_service_interface.h"
#include "dce110_compressor.h"
@@ -793,7 +792,7 @@ void dce110_compressor_set_fbc_invalidation_triggers(
}
bool dce110_compressor_construct(struct dce110_compressor *compressor,
- struct dc_context *ctx, struct adapter_service *as)
+ struct dc_context *ctx)
{
struct dc_bios *bp = ctx->dc_bios;
struct embedded_panel_info panel_info;
@@ -837,8 +836,7 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor,
return true;
}
-struct compressor *dce110_compressor_create(struct dc_context *ctx,
- struct adapter_service *as)
+struct compressor *dce110_compressor_create(struct dc_context *ctx)
{
struct dce110_compressor *cp110 =
dm_alloc(sizeof(struct dce110_compressor));
@@ -846,7 +844,7 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx,
if (!cp110)
return NULL;
- if (dce110_compressor_construct(cp110, ctx, as))
+ if (dce110_compressor_construct(cp110, ctx))
return &cp110->base;
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h
index 86c30d43e9fb..22af5be51581 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h
@@ -40,11 +40,10 @@ struct dce110_compressor {
struct dce110_compressor_reg_offsets offsets;
};
-struct compressor *dce110_compressor_create(struct dc_context *ctx,
- struct adapter_service *as);
+struct compressor *dce110_compressor_create(struct dc_context *ctx);
bool dce110_compressor_construct(struct dce110_compressor *cp110,
- struct dc_context *ctx, struct adapter_service *as);
+ struct dc_context *ctx);
void dce110_compressor_destroy(struct compressor **cp);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
index a78ad8ddcaf8..0b778c984e9a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
@@ -31,7 +31,6 @@
#include "gmc/gmc_8_2_sh_mask.h"
#include "include/logger_interface.h"
-#include "adapter_service_interface.h"
#include "dce110_mem_input.h"
@@ -993,7 +992,6 @@ static struct mem_input_funcs dce110_mem_input_funcs = {
bool dce110_mem_input_construct(
struct dce110_mem_input *mem_input110,
struct dc_context *ctx,
- struct adapter_service *as,
uint32_t inst,
const struct dce110_mem_input_reg_offsets *offsets)
{
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
index 8edd25ab19a6..83b2df93ce49 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
@@ -44,7 +44,6 @@ struct dce110_mem_input {
bool dce110_mem_input_construct(
struct dce110_mem_input *mem_input110,
struct dc_context *ctx,
- struct adapter_service *as,
uint32_t inst,
const struct dce110_mem_input_reg_offsets *offsets);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
index 78c63680cc0b..acf200ba16b1 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
@@ -1061,8 +1061,7 @@ static struct mem_input_funcs dce110_mem_input_v_funcs = {
bool dce110_mem_input_v_construct(
struct dce110_mem_input *mem_input110,
- struct dc_context *ctx,
- struct adapter_service *as)
+ struct dc_context *ctx)
{
mem_input110->base.funcs = &dce110_mem_input_v_funcs;
mem_input110->base.ctx = ctx;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h
index 07b663624d91..5b1796ccefc0 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.h
@@ -30,8 +30,7 @@
bool dce110_mem_input_v_construct(
struct dce110_mem_input *mem_input110,
- struct dc_context *ctx,
- struct adapter_service *as);
+ struct dc_context *ctx);
/*
* This function will program nbp stutter and urgency watermarks to minimum
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index a924ed0faea6..28d389c0ead5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -395,7 +395,7 @@ static struct timing_generator *dce110_timing_generator_create(
if (!tg110)
return NULL;
- if (dce110_timing_generator_construct(tg110, as, ctx, instance, offsets))
+ if (dce110_timing_generator_construct(tg110, ctx, instance, offsets))
return &tg110->base;
BREAK_TO_DEBUGGER();
@@ -432,7 +432,6 @@ static const struct resource_create_funcs res_create_funcs = {
static struct mem_input *dce110_mem_input_create(
struct dc_context *ctx,
- struct adapter_service *as,
uint32_t inst,
const struct dce110_mem_input_reg_offsets *offset)
{
@@ -443,7 +442,7 @@ static struct mem_input *dce110_mem_input_create(
return NULL;
if (dce110_mem_input_construct(mem_input110,
- ctx, as, inst, offset))
+ ctx, inst, offset))
return &mem_input110->base;
BREAK_TO_DEBUGGER();
@@ -1049,8 +1048,8 @@ static void underlay_create(struct dc_context *ctx, struct resource_pool *pool)
struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv));
dce110_opp_v_construct(dce110_oppv, ctx);
- dce110_timing_generator_v_construct(dce110_tgv, pool->adapter_srv, ctx);
- dce110_mem_input_v_construct(dce110_miv, ctx, pool->adapter_srv);
+ dce110_timing_generator_v_construct(dce110_tgv, ctx);
+ dce110_mem_input_v_construct(dce110_miv, ctx);
dce110_transform_v_construct(dce110_xfmv, ctx);
pool->opps[pool->pipe_count] = &dce110_oppv->base;
@@ -1239,7 +1238,7 @@ static bool construct(
}
}
- pool->base.display_clock = dal_display_clock_dce110_create(ctx, as);
+ pool->base.display_clock = dal_display_clock_dce110_create(ctx);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
@@ -1282,7 +1281,7 @@ static bool construct(
goto res_create_fail;
}
- pool->base.mis[i] = dce110_mem_input_create(ctx, as, i,
+ pool->base.mis[i] = dce110_mem_input_create(ctx, i,
&dce110_mi_reg_offsets[i]);
if (pool->base.mis[i] == NULL) {
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
index 120f4bd619b5..3d736c15ca25 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
@@ -1926,7 +1926,6 @@ static const struct timing_generator_funcs dce110_tg_funcs = {
bool dce110_timing_generator_construct(
struct dce110_timing_generator *tg110,
- struct adapter_service *as,
struct dc_context *ctx,
uint32_t instance,
const struct dce110_timing_generator_offsets *offsets)
@@ -1934,9 +1933,6 @@ bool dce110_timing_generator_construct(
if (!tg110)
return false;
- if (!as)
- return false;
-
tg110->controller_id = CONTROLLER_ID_D0 + instance;
tg110->base.inst = instance;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
index 86ba37308a39..39906502ad5c 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
@@ -119,7 +119,6 @@ struct dce110_timing_generator {
bool dce110_timing_generator_construct(
struct dce110_timing_generator *tg,
- struct adapter_service *as,
struct dc_context *ctx,
uint32_t instance,
const struct dce110_timing_generator_offsets *offsets);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
index aadeeb33c53f..56cf3fe3ad28 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.c
@@ -721,15 +721,11 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = {
bool dce110_timing_generator_v_construct(
struct dce110_timing_generator *tg110,
- struct adapter_service *as,
struct dc_context *ctx)
{
if (!tg110)
return false;
- if (!as)
- return false;
-
tg110->controller_id = CONTROLLER_ID_UNDERLAY0;
tg110->base.funcs = &dce110_tg_v_funcs;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.h
index fe3fb811d80b..7e49ca8e26ad 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator_v.h
@@ -28,7 +28,6 @@
bool dce110_timing_generator_v_construct(
struct dce110_timing_generator *tg110,
- struct adapter_service *as,
struct dc_context *ctx);
#endif /* __DC_TIMING_GENERATOR_V_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
index e34779b4b1de..70c4ea2ad294 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.c
@@ -793,7 +793,7 @@ void dce112_compressor_set_fbc_invalidation_triggers(
}
bool dce112_compressor_construct(struct dce112_compressor *compressor,
- struct dc_context *ctx, struct adapter_service *as)
+ struct dc_context *ctx)
{
struct dc_bios *bp = ctx->dc_bios;
struct embedded_panel_info panel_info;
@@ -837,8 +837,7 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor,
return true;
}
-struct compressor *dce112_compressor_create(struct dc_context *ctx,
- struct adapter_service *as)
+struct compressor *dce112_compressor_create(struct dc_context *ctx)
{
struct dce112_compressor *cp110 =
dm_alloc(sizeof(struct dce112_compressor));
@@ -846,7 +845,7 @@ struct compressor *dce112_compressor_create(struct dc_context *ctx,
if (!cp110)
return NULL;
- if (dce112_compressor_construct(cp110, ctx, as))
+ if (dce112_compressor_construct(cp110, ctx))
return &cp110->base;
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.h
index 6a0efe80e3c6..106506387270 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_compressor.h
@@ -40,11 +40,10 @@ struct dce112_compressor {
struct dce112_compressor_reg_offsets offsets;
};
-struct compressor *dce112_compressor_create(struct dc_context *ctx,
- struct adapter_service *as);
+struct compressor *dce112_compressor_create(struct dc_context *ctx);
bool dce112_compressor_construct(struct dce112_compressor *cp110,
- struct dc_context *ctx, struct adapter_service *as);
+ struct dc_context *ctx);
void dce112_compressor_destroy(struct compressor **cp);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.c
index dcbe9b4c8f0d..24b1b91abd71 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.c
@@ -423,11 +423,10 @@ static void dce112_mem_input_program_display_marks(
bool dce112_mem_input_construct(
struct dce110_mem_input *mem_input110,
struct dc_context *ctx,
- struct adapter_service *as,
uint32_t inst,
const struct dce110_mem_input_reg_offsets *offsets)
{
- if (!dce110_mem_input_construct(mem_input110, ctx, as, inst, offsets))
+ if (!dce110_mem_input_construct(mem_input110, ctx, inst, offsets))
return false;
mem_input110->base.funcs->mem_input_program_display_marks =
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.h
index 00b127ac18a7..de2aaf0f9a8e 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_mem_input.h
@@ -31,7 +31,6 @@
bool dce112_mem_input_construct(
struct dce110_mem_input *mem_input110,
struct dc_context *ctx,
- struct adapter_service *as,
uint32_t inst,
const struct dce110_mem_input_reg_offsets *offsets);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 0ab589f1c1a7..92fcd4eeb5bf 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -444,7 +444,7 @@ static struct timing_generator *dce112_timing_generator_create(
if (!tg110)
return NULL;
- if (dce110_timing_generator_construct(tg110, as, ctx, instance, offsets))
+ if (dce110_timing_generator_construct(tg110, ctx, instance, offsets))
return &tg110->base;
BREAK_TO_DEBUGGER();
@@ -491,7 +491,7 @@ static struct mem_input *dce112_mem_input_create(
return NULL;
if (dce112_mem_input_construct(mem_input110,
- ctx, as, inst, offset))
+ ctx, inst, offset))
return &mem_input110->base;
BREAK_TO_DEBUGGER();
@@ -1263,7 +1263,7 @@ static bool construct(
}
pool->base.display_clock = dal_display_clock_dce112_create(
- ctx, adapter_serv);
+ ctx);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
index bcd44ebafc36..eeedb7c4fe53 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.c
@@ -31,8 +31,6 @@
#include "gmc/gmc_7_1_d.h"
#include "include/logger_interface.h"
-#include "include/adapter_service_interface.h"
-
#include "dce80_compressor.h"
#define DCP_REG(reg)\
@@ -774,7 +772,7 @@ void dce80_compressor_set_fbc_invalidation_triggers(
}
bool dce80_compressor_construct(struct dce80_compressor *compressor,
- struct dc_context *ctx, struct adapter_service *as)
+ struct dc_context *ctx)
{
struct dc_bios *bp = ctx->dc_bios;
struct embedded_panel_info panel_info;
@@ -818,8 +816,7 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor,
return true;
}
-struct compressor *dce80_compressor_create(struct dc_context *ctx,
- struct adapter_service *as)
+struct compressor *dce80_compressor_create(struct dc_context *ctx)
{
struct dce80_compressor *cp80 =
dm_alloc(sizeof(struct dce80_compressor));
@@ -827,7 +824,7 @@ struct compressor *dce80_compressor_create(struct dc_context *ctx,
if (!cp80)
return NULL;
- if (dce80_compressor_construct(cp80, ctx, as))
+ if (dce80_compressor_construct(cp80, ctx))
return &cp80->base;
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.h
index f5f357c43fda..01290969ff92 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_compressor.h
@@ -40,11 +40,10 @@ struct dce80_compressor {
struct dce80_compressor_reg_offsets offsets;
};
-struct compressor *dce80_compressor_create(struct dc_context *ctx,
- struct adapter_service *as);
+struct compressor *dce80_compressor_create(struct dc_context *ctx);
bool dce80_compressor_construct(struct dce80_compressor *cp80,
- struct dc_context *ctx, struct adapter_service *as);
+ struct dc_context *ctx);
void dce80_compressor_destroy(struct compressor **cp);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
index be822d1b5989..5d84a9bc5f9f 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
@@ -186,7 +186,6 @@ static struct mem_input_funcs dce80_mem_input_funcs = {
bool dce80_mem_input_construct(
struct dce110_mem_input *mem_input80,
struct dc_context *ctx,
- struct adapter_service *as,
uint32_t inst,
const struct dce110_mem_input_reg_offsets *offsets)
{
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h
index 6d589f52d473..357b9e2e9f1e 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.h
@@ -30,7 +30,6 @@
bool dce80_mem_input_construct(
struct dce110_mem_input *mem_input80,
struct dc_context *ctx,
- struct adapter_service *as,
uint32_t inst,
const struct dce110_mem_input_reg_offsets *offsets);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index d10d3a80ae3a..42b5ccdb3508 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -410,7 +410,7 @@ static struct timing_generator *dce80_timing_generator_create(
if (!tg110)
return NULL;
- if (dce80_timing_generator_construct(tg110, as, ctx, instance, offsets))
+ if (dce80_timing_generator_construct(tg110, ctx, instance, offsets))
return &tg110->base;
BREAK_TO_DEBUGGER();
@@ -446,7 +446,6 @@ static const struct resource_create_funcs res_create_funcs = {
static struct mem_input *dce80_mem_input_create(
struct dc_context *ctx,
- struct adapter_service *as,
uint32_t inst,
const struct dce110_mem_input_reg_offsets *offsets)
{
@@ -457,7 +456,7 @@ static struct mem_input *dce80_mem_input_create(
return NULL;
if (dce80_mem_input_construct(mem_input80,
- ctx, as, inst, offsets))
+ ctx, inst, offsets))
return &mem_input80->base;
BREAK_TO_DEBUGGER();
@@ -922,7 +921,7 @@ static bool construct(
}
}
- pool->base.display_clock = dal_display_clock_dce80_create(ctx, as);
+ pool->base.display_clock = dal_display_clock_dce80_create(ctx);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
@@ -963,7 +962,7 @@ static bool construct(
goto res_create_fail;
}
- pool->base.mis[i] = dce80_mem_input_create(ctx, as, i,
+ pool->base.mis[i] = dce80_mem_input_create(ctx, i,
&dce80_mi_reg_offsets[i]);
if (pool->base.mis[i] == NULL) {
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c
index 206c4ec584b8..e8fae0a7eeb4 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.c
@@ -32,7 +32,6 @@
#include "dc_types.h"
#include "include/grph_object_id.h"
-#include "include/adapter_service_interface.h"
#include "include/logger_interface.h"
#include "../dce110/dce110_timing_generator.h"
#include "dce80_timing_generator.h"
@@ -152,7 +151,6 @@ static const struct timing_generator_funcs dce80_tg_funcs = {
bool dce80_timing_generator_construct(
struct dce110_timing_generator *tg110,
- struct adapter_service *as,
struct dc_context *ctx,
uint32_t instance,
const struct dce110_timing_generator_offsets *offsets)
@@ -160,9 +158,6 @@ bool dce80_timing_generator_construct(
if (!tg110)
return false;
- if (!as)
- return false;
-
tg110->controller_id = CONTROLLER_ID_D0 + instance;
tg110->base.inst = instance;
tg110->offsets = *offsets;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h
index 86de41a3b31d..6e4722a970d7 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_timing_generator.h
@@ -32,7 +32,6 @@
/* DCE8.0 implementation inherits from DCE11.0 */
bool dce80_timing_generator_construct(
struct dce110_timing_generator *tg,
- struct adapter_service *as,
struct dc_context *ctx,
uint32_t instance,
const struct dce110_timing_generator_offsets *offsets);
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
index c993c541dc7e..5ea7ea1e7814 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
@@ -668,8 +668,7 @@ static uint32_t calculate_min_clock(
}
static bool display_clock_integrated_info_construct(
- struct display_clock_dce110 *disp_clk,
- struct adapter_service *as)
+ struct display_clock_dce110 *disp_clk)
{
struct dc_debug *debug = &disp_clk->disp_clk_base.ctx->dc->debug;
struct dc_bios *bp = disp_clk->disp_clk_base.ctx->dc_bios;
@@ -926,15 +925,11 @@ static const struct display_clock_funcs funcs = {
static bool dal_display_clock_dce110_construct(
struct display_clock_dce110 *dc110,
- struct dc_context *ctx,
- struct adapter_service *as)
+ struct dc_context *ctx)
{
struct display_clock *dc_base = &dc110->disp_clk_base;
struct dc_bios *bp = ctx->dc_bios;
- if (NULL == as)
- return false;
-
if (!dal_display_clock_construct_base(dc_base, ctx))
return false;
@@ -942,7 +937,7 @@ static bool dal_display_clock_dce110_construct(
dc110->dfs_bypass_disp_clk = 0;
- if (!display_clock_integrated_info_construct(dc110, as))
+ if (!display_clock_integrated_info_construct(dc110))
dm_logger_write(dc_base->ctx->logger, LOG_WARNING,
"Cannot obtain VBIOS integrated info\n");
@@ -1023,8 +1018,7 @@ static bool dal_display_clock_dce110_construct(
*****************************************************************************/
struct display_clock *dal_display_clock_dce110_create(
- struct dc_context *ctx,
- struct adapter_service *as)
+ struct dc_context *ctx)
{
struct display_clock_dce110 *dc110;
@@ -1033,7 +1027,7 @@ struct display_clock *dal_display_clock_dce110_create(
if (dc110 == NULL)
return NULL;
- if (dal_display_clock_dce110_construct(dc110, ctx, as))
+ if (dal_display_clock_dce110_construct(dc110, ctx))
return &dc110->disp_clk_base;
dm_free(dc110);
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
index f94da476c9a5..600a09cd6021 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/display_clock_dce112.c
@@ -948,8 +948,7 @@ bool dal_display_clock_dce112_construct(
*****************************************************************************/
struct display_clock *dal_display_clock_dce112_create(
- struct dc_context *ctx,
- struct adapter_service *as)
+ struct dc_context *ctx)
{
struct display_clock_dce112 *dc112;
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
index 8fd78b8c93ae..fbac724a2407 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
@@ -717,8 +717,7 @@ static void store_max_clocks_state(
}
static void display_clock_ss_construct(
- struct display_clock_dce80 *disp_clk,
- struct adapter_service *as)
+ struct display_clock_dce80 *disp_clk)
{
struct dc_bios *bp = disp_clk->disp_clk.ctx->dc_bios;
uint32_t ss_entry_num = bp->funcs->get_ss_entry_number(bp,
@@ -752,8 +751,7 @@ static void display_clock_ss_construct(
}
static bool display_clock_integrated_info_construct(
- struct display_clock_dce80 *disp_clk,
- struct adapter_service *as)
+ struct display_clock_dce80 *disp_clk)
{
struct dc_debug *debug = &disp_clk->disp_clk.ctx->dc->debug;
struct dc_bios *bp = disp_clk->disp_clk.ctx->dc_bios;
@@ -856,14 +854,10 @@ static const struct display_clock_funcs funcs = {
static bool display_clock_construct(
struct dc_context *ctx,
- struct display_clock_dce80 *disp_clk,
- struct adapter_service *as)
+ struct display_clock_dce80 *disp_clk)
{
struct display_clock *dc_base = &disp_clk->disp_clk;
- if (NULL == as)
- return false;
-
if (!dal_display_clock_construct_base(dc_base, ctx))
return false;
@@ -894,9 +888,9 @@ static bool display_clock_construct(
* state dependent clocks.*/
disp_clk->cur_min_clks_state = CLOCKS_STATE_INVALID;
- display_clock_ss_construct(disp_clk, as);
+ display_clock_ss_construct(disp_clk);
- if (!display_clock_integrated_info_construct(disp_clk, as)) {
+ if (!display_clock_integrated_info_construct(disp_clk)) {
dm_logger_write(dc_base->ctx->logger, LOG_WARNING,
"Cannot obtain VBIOS integrated info");
}
@@ -923,8 +917,7 @@ static bool display_clock_construct(
}
struct display_clock *dal_display_clock_dce80_create(
- struct dc_context *ctx,
- struct adapter_service *as)
+ struct dc_context *ctx)
{
struct display_clock_dce80 *disp_clk;
@@ -933,7 +926,7 @@ struct display_clock *dal_display_clock_dce80_create(
if (disp_clk == NULL)
return NULL;
- if (display_clock_construct(ctx, disp_clk, as))
+ if (display_clock_construct(ctx, disp_clk))
return &disp_clk->disp_clk;
dm_free(disp_clk);
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.h
index 2d687049e456..944dd0380413 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.h
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.h
@@ -52,7 +52,6 @@ struct display_clock_dce80 {
};
struct display_clock *dal_display_clock_dce80_create(
- struct dc_context *ctx,
- struct adapter_service *as);
+ struct dc_context *ctx);
#endif /* __DAL_DISPLAY_CLOCK_DCE80_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
index 08586fb3d18a..4929cd2aa3da 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
@@ -26,8 +26,6 @@
#include "dm_services.h"
#include "display_clock.h"
-#include "adapter_service_interface.h"
-
void dal_display_clock_base_set_dp_ref_clock_source(
struct display_clock *disp_clk,
enum clock_source_id clk_src)
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h
index 18b79fd3fcb8..663580d18a09 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h
@@ -63,7 +63,6 @@ struct display_clock {
const struct display_clock_funcs *funcs;
uint32_t min_display_clk_threshold_khz;
enum clock_source_id id;
- struct adapter_service *as;
enum clocks_state cur_min_clks_state;
};
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/compressor.h b/drivers/gpu/drm/amd/dal/dc/inc/compressor.h
index a2e44b55c637..af292596b101 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/compressor.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/compressor.h
@@ -27,6 +27,7 @@
#define __DAL_COMPRESSOR_H__
#include "include/grph_object_id.h"
+#include "bios_parser_interface.h"
enum fbc_compress_ratio {
FBC_COMPRESS_RATIO_INVALID = 0,
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
index 9667f00e9447..edef4a41fe4f 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
@@ -22,7 +22,6 @@ struct core_stream;
struct pipe_ctx;
struct encoder_init_data {
- struct adapter_service *adapter_service;
enum channel_id channel;
struct graphics_object_id connector;
enum hpd_source_id hpd_source;
diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
index 164f9eac1fd2..bb4433ff3b6e 100644
--- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
@@ -136,8 +136,6 @@ bool virtual_link_encoder_construct(
enc->hpd_source = init_data->hpd_source;
enc->connector = init_data->connector;
- enc->adapter_service = init_data->adapter_service;
-
enc->transmitter = init_data->transmitter;
enc->features.max_pixel_clock = VIRTUAL_MAX_PIXEL_CLK_IN_KHZ;
diff --git a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
index 7c0e1bf26485..d51101c5c6b0 100644
--- a/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/bios_parser_interface.h
@@ -28,7 +28,6 @@
#include "dc_bios_types.h"
-struct adapter_service;
struct bios_parser;
struct bp_init_data {
diff --git a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
index 3d394bea324b..4556f4c8e388 100644
--- a/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/display_clock_interface.h
@@ -118,16 +118,13 @@ struct display_clock_state {
struct display_clock;
struct display_clock *dal_display_clock_dce112_create(
- struct dc_context *ctx,
- struct adapter_service *as);
+ struct dc_context *ctx);
struct display_clock *dal_display_clock_dce110_create(
- struct dc_context *ctx,
- struct adapter_service *as);
+ struct dc_context *ctx);
struct display_clock *dal_display_clock_dce80_create(
- struct dc_context *ctx,
- struct adapter_service *as);
+ struct dc_context *ctx);
void dal_display_clock_destroy(struct display_clock **to_destroy);
bool dal_display_clock_validate(
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 50/76] drm/amd/dal: remove adapter_service dependency
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (48 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 49/76] drm/amd/dal: remove adapter_service from Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 51/76] drm/amd/dal: remove SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT Harry Wentland
` (26 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 6 +-----
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 14 +++++---------
drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 1 -
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 10 +++++-----
drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h | 1 -
drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 7 +------
drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h | 2 --
drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h | 1 -
drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c | 1 -
drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 9 ++-------
drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h | 2 --
drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 9 +--------
drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h | 2 --
drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c | 1 -
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 8 ++------
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h | 2 --
drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c | 1 +
drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 3 ---
drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h | 2 --
drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h | 2 --
drivers/gpu/drm/amd/dal/dc/inc/resource.h | 2 +-
drivers/gpu/drm/amd/dal/include/i2caux_interface.h | 1 -
drivers/gpu/drm/amd/dal/include/link_service_types.h | 1 -
23 files changed, 19 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index c5f98525a630..a3c9cb3e1249 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -72,7 +72,6 @@ static void destroy_links(struct core_dc *dc)
static bool create_links(
struct core_dc *dc,
- struct adapter_service *as,
uint32_t num_virtual_links)
{
int i;
@@ -106,7 +105,6 @@ static bool create_links(
struct core_link *link;
link_init_params.ctx = dc->ctx;
- link_init_params.adapter_srv = as;
link_init_params.connector_index = i;
link_init_params.link_index = dc->link_count;
link_init_params.dc = dc;
@@ -130,7 +128,6 @@ static bool create_links(
goto failed_alloc;
}
- link->adapter_srv = as;
link->ctx = dc->ctx;
link->dc = dc;
link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
@@ -604,7 +601,6 @@ static bool construct(struct core_dc *dc,
}
dc->res_pool = dc_create_resource_pool(
- as,
dc,
init_params->num_virtual_links,
dc_version,
@@ -612,7 +608,7 @@ static bool construct(struct core_dc *dc,
if (!dc->res_pool)
goto create_resource_fail;
- if (!create_links(dc, as, init_params->num_virtual_links))
+ if (!create_links(dc, init_params->num_virtual_links))
goto create_links_fail;
allocate_dc_stream_funcs(dc);
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index e59e439a35e7..af5fb0fc4c3e 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -787,8 +787,7 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot)
}
static enum hpd_source_id get_hpd_line(
- struct core_link *link,
- struct adapter_service *as)
+ struct core_link *link)
{
struct gpio *hpd;
enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
@@ -826,7 +825,7 @@ static enum hpd_source_id get_hpd_line(
return hpd_id;
}
-static enum channel_id get_ddc_line(struct core_link *link, struct adapter_service *as)
+static enum channel_id get_ddc_line(struct core_link *link)
{
struct ddc *ddc;
enum channel_id channel = CHANNEL_ID_UNKNOWN;
@@ -938,7 +937,6 @@ static bool construct(
const struct link_init_data *init_params)
{
uint8_t i;
- struct adapter_service *as = init_params->adapter_srv;
struct gpio *hpd_gpio = NULL;
struct ddc_service_init_data ddc_service_init_data = { 0 };
struct dc_context *dc_ctx = init_params->ctx;
@@ -953,7 +951,6 @@ static bool construct(
link->link_status.dpcd_caps = &link->dpcd_caps;
link->dc = init_params->dc;
- link->adapter_srv = as;
link->ctx = dc_ctx;
link->public.link_index = init_params->link_index;
@@ -1017,7 +1014,6 @@ static bool construct(
init_params->connector_index,
link->public.connector_signal);
- ddc_service_init_data.as = as;
ddc_service_init_data.ctx = link->ctx;
ddc_service_init_data.id = link->link_id;
ddc_service_init_data.link = link;
@@ -1035,8 +1031,8 @@ static bool construct(
enc_init_data.ctx = dc_ctx;
bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
enc_init_data.connector = link->link_id;
- enc_init_data.channel = get_ddc_line(link, as);
- enc_init_data.hpd_source = get_hpd_line(link, as);
+ enc_init_data.channel = get_ddc_line(link);
+ enc_init_data.hpd_source = get_hpd_line(link);
enc_init_data.transmitter =
translate_encoder_to_transmitter(enc_init_data.encoder);
link->link_enc = link->dc->res_pool->funcs->link_enc_create(
@@ -1562,7 +1558,7 @@ bool dc_link_setup_psr(const struct dc_link *dc_link,
dc_link->psr_caps.psr_frame_capture_indication_req;
psr_context.skipPsrWaitForPllLock =
- link->link_enc->adapter_service->
+ ctx->adapter_srv->
asic_cap->caps.SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT;
psr_context.numberOfControllers =
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
index c945d4b27def..6be8e08e3d99 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
@@ -287,7 +287,6 @@ static bool construct(
ddc_service->link = init_data->link;
ddc_service->ctx = init_data->ctx;
- ddc_service->as = init_data->as;
if (BP_RESULT_OK != dcb->funcs->get_i2c_info(dcb, init_data->id, &i2c_info)) {
ddc_service->ddc_pin = NULL;
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index a4061c68596a..4e76d5dbbac0 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -72,7 +72,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
return dc_version;
}
-struct resource_pool *dc_create_resource_pool(struct adapter_service *adapter_serv,
+struct resource_pool *dc_create_resource_pool(
struct core_dc *dc,
int num_virtual_links,
enum dce_version dc_version,
@@ -82,16 +82,16 @@ struct resource_pool *dc_create_resource_pool(struct adapter_service *adapter_se
switch (dc_version) {
case DCE_VERSION_8_0:
return dce80_create_resource_pool(
- adapter_serv, num_virtual_links, dc);
+ num_virtual_links, dc);
case DCE_VERSION_10_0:
return dce100_create_resource_pool(
- adapter_serv, num_virtual_links, dc);
+ num_virtual_links, dc);
case DCE_VERSION_11_0:
return dce110_create_resource_pool(
- adapter_serv, num_virtual_links, dc, asic_id);
+ num_virtual_links, dc, asic_id);
case DCE_VERSION_11_2:
return dce112_create_resource_pool(
- adapter_serv, num_virtual_links, dc);
+ num_virtual_links, dc);
default:
break;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h
index 91fa86ec44e3..b143fe88f49f 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_ddc_types.h
@@ -104,7 +104,6 @@ struct ddc_service {
union ddc_wa wa;
enum ddc_transaction_type transaction_type;
enum display_dongle_type dongle_type;
- struct adapter_service *as;
struct dc_context *ctx;
struct core_link *link;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index feb922836e82..9062ca209fd9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -407,7 +407,6 @@ static struct audio *create_audio(
}
static struct timing_generator *dce100_timing_generator_create(
- struct adapter_service *as,
struct dc_context *ctx,
uint32_t instance,
const struct dce110_timing_generator_offsets *offsets)
@@ -859,7 +858,6 @@ static const struct resource_funcs dce100_res_pool_funcs = {
};
static bool construct(
- struct adapter_service *as,
uint8_t num_virtual_links,
struct core_dc *dc,
struct dce110_resource_pool *pool)
@@ -872,7 +870,6 @@ static bool construct(
ctx->dc_bios->regs = &bios_regs;
- pool->base.adapter_srv = as;
pool->base.res_cap = &res_cap;
pool->base.funcs = &dce100_res_pool_funcs;
pool->base.underlay_pipe_index = -1;
@@ -962,7 +959,6 @@ static bool construct(
for (i = 0; i < pool->base.pipe_count; i++) {
pool->base.timing_generators[i] =
dce100_timing_generator_create(
- as,
ctx,
i,
&dce100_tg_offsets[i]);
@@ -1028,7 +1024,6 @@ res_create_fail:
}
struct resource_pool *dce100_create_resource_pool(
- struct adapter_service *as,
uint8_t num_virtual_links,
struct core_dc *dc)
{
@@ -1038,7 +1033,7 @@ struct resource_pool *dce100_create_resource_pool(
if (!pool)
return NULL;
- if (construct(as, num_virtual_links, dc, pool))
+ if (construct(num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
index 24af9bf4a6ae..bfd7518c94c9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
@@ -8,13 +8,11 @@
#ifndef DCE100_RESOURCE_H_
#define DCE100_RESOURCE_H_
-struct adapter_service;
struct core_dc;
struct resource_pool;
struct dc_validation_set;
struct resource_pool *dce100_create_resource_pool(
- struct adapter_service *as,
uint8_t num_virtual_links,
struct core_dc *dc);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
index 4405bdbb3bb8..a6b4d0d2429f 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
@@ -27,7 +27,6 @@
#define __DC_HWSS_DCE110_H__
#include "core_types.h"
-#include "adapter_service_interface.h"
#define GAMMA_HW_POINTS_NUM 256
struct core_dc;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
index acf200ba16b1..f0310bab4030 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input_v.c
@@ -31,7 +31,6 @@
#include "gmc/gmc_8_2_sh_mask.h"
#include "include/logger_interface.h"
-#include "adapter_service_interface.h"
#include "inc/bandwidth_calcs.h"
#include "dce110_mem_input.h"
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 28d389c0ead5..8a840d3b86d7 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -47,7 +47,6 @@
#include "dce110/dce110_opp_v.h"
#include "dce110/dce110_clock_source.h"
#include "dce110/dce110_hw_sequencer.h"
-#include "adapter_service_interface.h"
#include "reg_helper.h"
@@ -384,7 +383,6 @@ static struct audio *create_audio(
}
static struct timing_generator *dce110_timing_generator_create(
- struct adapter_service *as,
struct dc_context *ctx,
uint32_t instance,
const struct dce110_timing_generator_offsets *offsets)
@@ -1174,7 +1172,6 @@ const struct resource_caps *dce110_resource_cap(
}
static bool construct(
- struct adapter_service *as,
uint8_t num_virtual_links,
struct core_dc *dc,
struct dce110_resource_pool *pool,
@@ -1189,7 +1186,6 @@ static bool construct(
ctx->dc_bios->regs = &bios_regs;
- pool->base.adapter_srv = as;
pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
pool->base.funcs = &dce110_res_pool_funcs;
@@ -1274,7 +1270,7 @@ static bool construct(
for (i = 0; i < pool->base.pipe_count; i++) {
pool->base.timing_generators[i] = dce110_timing_generator_create(
- as, ctx, i, &dce110_tg_offsets[i]);
+ ctx, i, &dce110_tg_offsets[i]);
if (pool->base.timing_generators[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error("DC: failed to create tg!\n");
@@ -1341,7 +1337,6 @@ res_create_fail:
}
struct resource_pool *dce110_create_resource_pool(
- struct adapter_service *as,
uint8_t num_virtual_links,
struct core_dc *dc,
struct hw_asic_id asic_id)
@@ -1352,7 +1347,7 @@ struct resource_pool *dce110_create_resource_pool(
if (!pool)
return NULL;
- if (construct(as, num_virtual_links, dc, pool, asic_id))
+ if (construct(num_virtual_links, dc, pool, asic_id))
return &pool->base;
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
index 95c5873e9e88..535623aa0052 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
@@ -28,7 +28,6 @@
#include "core_types.h"
-struct adapter_service;
struct core_dc;
struct resource_pool;
@@ -49,7 +48,6 @@ void dce110_resource_build_bit_depth_reduction_params(
struct bit_depth_reduction_params *fmt_bit_depth);
struct resource_pool *dce110_create_resource_pool(
- struct adapter_service *as,
uint8_t num_virtual_links,
struct core_dc *dc,
struct hw_asic_id asic_id);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 92fcd4eeb5bf..578d8fd89d39 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -433,7 +433,6 @@ static struct audio *create_audio(
static struct timing_generator *dce112_timing_generator_create(
- struct adapter_service *as,
struct dc_context *ctx,
uint32_t instance,
const struct dce110_timing_generator_offsets *offsets)
@@ -480,7 +479,6 @@ static const struct resource_create_funcs res_create_funcs = {
static struct mem_input *dce112_mem_input_create(
struct dc_context *ctx,
- struct adapter_service *as,
uint32_t inst,
const struct dce110_mem_input_reg_offsets *offset)
{
@@ -1190,7 +1188,6 @@ const struct resource_caps *dce112_resource_cap(
}
static bool construct(
- struct adapter_service *adapter_serv,
uint8_t num_virtual_links,
struct core_dc *dc,
struct dce110_resource_pool *pool)
@@ -1201,7 +1198,6 @@ static bool construct(
ctx->dc_bios->regs = &bios_regs;
- pool->base.adapter_srv = adapter_serv;
pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
pool->base.funcs = &dce112_res_pool_funcs;
@@ -1302,7 +1298,6 @@ static bool construct(
for (i = 0; i < pool->base.pipe_count; i++) {
pool->base.timing_generators[i] =
dce112_timing_generator_create(
- adapter_serv,
ctx,
i,
&dce112_tg_offsets[i]);
@@ -1314,7 +1309,6 @@ static bool construct(
pool->base.mis[i] = dce112_mem_input_create(
ctx,
- adapter_serv,
i,
&dce112_mi_reg_offsets[i]);
if (pool->base.mis[i] == NULL) {
@@ -1381,7 +1375,6 @@ res_create_fail:
}
struct resource_pool *dce112_create_resource_pool(
- struct adapter_service *as,
uint8_t num_virtual_links,
struct core_dc *dc)
{
@@ -1391,7 +1384,7 @@ struct resource_pool *dce112_create_resource_pool(
if (!pool)
return NULL;
- if (construct(as, num_virtual_links, dc, pool))
+ if (construct(num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h
index 324b3d73fe70..9d2427752389 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h
@@ -28,12 +28,10 @@
#include "core_types.h"
-struct adapter_service;
struct core_dc;
struct resource_pool;
struct resource_pool *dce112_create_resource_pool(
- struct adapter_service *as,
uint8_t num_virtual_links,
struct core_dc *dc);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
index 5d84a9bc5f9f..078a608dc737 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
@@ -31,7 +31,6 @@
#include "gmc/gmc_7_1_sh_mask.h"
#include "include/logger_interface.h"
-#include "adapter_service_interface.h"
#include "inc/bandwidth_calcs.h"
#include "../dce110/dce110_mem_input.h"
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index 42b5ccdb3508..7bf277e7bada 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -399,7 +399,6 @@ static struct audio *create_audio(
}
static struct timing_generator *dce80_timing_generator_create(
- struct adapter_service *as,
struct dc_context *ctx,
uint32_t instance,
const struct dce110_timing_generator_offsets *offsets)
@@ -851,7 +850,6 @@ static enum clocks_state dce80_resource_convert_clock_state_pp_to_dc(
}
static bool construct(
- struct adapter_service *as,
uint8_t num_virtual_links,
struct core_dc *dc,
struct dce110_resource_pool *pool)
@@ -864,7 +862,6 @@ static bool construct(
ctx->dc_bios->regs = &bios_regs;
- pool->base.adapter_srv = as;
pool->base.res_cap = &res_cap;
pool->base.funcs = &dce80_res_pool_funcs;
@@ -955,7 +952,7 @@ static bool construct(
for (i = 0; i < pool->base.pipe_count; i++) {
pool->base.timing_generators[i] = dce80_timing_generator_create(
- as, ctx, i, &dce80_tg_offsets[i]);
+ ctx, i, &dce80_tg_offsets[i]);
if (pool->base.timing_generators[i] == NULL) {
BREAK_TO_DEBUGGER();
dm_error("DC: failed to create tg!\n");
@@ -1012,7 +1009,6 @@ res_create_fail:
}
struct resource_pool *dce80_create_resource_pool(
- struct adapter_service *as,
uint8_t num_virtual_links,
struct core_dc *dc)
{
@@ -1022,7 +1018,7 @@ struct resource_pool *dce80_create_resource_pool(
if (!pool)
return NULL;
- if (construct(as, num_virtual_links, dc, pool))
+ if (construct(num_virtual_links, dc, pool))
return &pool->base;
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h
index 46b0f1d7a62f..2a0cdccddeaf 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.h
@@ -28,12 +28,10 @@
#include "core_types.h"
-struct adapter_service;
struct core_dc;
struct resource_pool;
struct resource_pool *dce80_create_resource_pool(
- struct adapter_service *as,
uint8_t num_virtual_links,
struct core_dc *dc);
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
index 63ffd7cb418d..5391655af23a 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c
@@ -29,6 +29,7 @@
* Pre-requisites: headers required by header of this unit
*/
#include "include/i2caux_interface.h"
+#include "dc_bios_types.h"
/*
* Header of this unit
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
index 4ed88728a54d..3fca7ec3cec8 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
@@ -127,7 +127,6 @@ struct link_init_data {
uint32_t connector_index; /* this will be mapped to the HPD pins */
uint32_t link_index; /* this is mapped to DAL display_index
TODO: remove it when DC is complete. */
- struct adapter_service *adapter_srv;
};
/* DP MST stream allocation (payload bandwidth number) */
@@ -155,7 +154,6 @@ struct core_link {
struct dc_context *ctx; /* TODO: AUTO remove 'dal' when DC is complete*/
- struct adapter_service *adapter_srv;
struct link_encoder *link_enc;
struct ddc_service *ddc;
struct graphics_object_id link_id;
@@ -264,7 +262,6 @@ struct resource_pool {
struct audio_support audio_support;
struct display_clock *display_clock;
- struct adapter_service *adapter_srv;
struct irq_service *irqs;
const struct resource_funcs *funcs;
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h
index e5daeb945bac..830fc3d039c9 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h
@@ -32,7 +32,6 @@
#define EDID_SEGMENT_SIZE 256
struct ddc_service;
-struct adapter_service;
struct graphics_object_id;
enum ddc_result;
struct av_sync_data;
@@ -66,7 +65,6 @@ void dal_ddc_aux_payloads_add(
bool write);
struct ddc_service_init_data {
- struct adapter_service *as;
struct graphics_object_id id;
struct dc_context *ctx;
struct core_link *link;
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
index edef4a41fe4f..77f8aa410898 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/link_encoder.h
@@ -13,7 +13,6 @@
#include "dc_types.h"
struct dc_context;
-struct adapter_service;
struct encoder_set_dp_phy_pattern_param;
struct link_mst_stream_allocation_table;
struct dc_link_settings;
@@ -201,7 +200,6 @@ struct psr_dmcu_context {
struct link_encoder {
const struct link_encoder_funcs *funcs;
- struct adapter_service *adapter_service;
int32_t aux_channel_offset;
struct dc_context *ctx;
struct graphics_object_id id;
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
index 4e64e45e897b..9606cb28cd62 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
@@ -69,7 +69,7 @@ bool resource_construct(
struct resource_pool *pool,
const struct resource_create_funcs *create_funcs);
-struct resource_pool *dc_create_resource_pool(struct adapter_service *adapter_serv,
+struct resource_pool *dc_create_resource_pool(
struct core_dc *dc,
int num_virtual_links,
enum dce_version dc_version,
diff --git a/drivers/gpu/drm/amd/dal/include/i2caux_interface.h b/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
index a78576a38b36..d2ec04d1c592 100644
--- a/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/i2caux_interface.h
@@ -26,7 +26,6 @@
#ifndef __DAL_I2CAUX_INTERFACE_H__
#define __DAL_I2CAUX_INTERFACE_H__
-#include "adapter_service_interface.h"
#include "gpio_service_interface.h"
diff --git a/drivers/gpu/drm/amd/dal/include/link_service_types.h b/drivers/gpu/drm/amd/dal/include/link_service_types.h
index 96e6b38aa9f9..06e68426d430 100644
--- a/drivers/gpu/drm/amd/dal/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/dal/include/link_service_types.h
@@ -162,7 +162,6 @@ struct link_service_init_data {
struct link_service_init_options init_options;
uint32_t connector_enum_id;
struct graphics_object_id connector_id;
- struct adapter_service *adapter_service;
struct dc_context *ctx;
struct topology_mgr *tm;
};
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 51/76] drm/amd/dal: remove SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (49 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 50/76] drm/amd/dal: remove adapter_service dependency Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 52/76] drm/amd/dal: remove adapter_service and asic_capability Harry Wentland
` (25 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- always 0 except KV, which is not supported
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index af5fb0fc4c3e..c0b5c2c5b8e0 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -1557,9 +1557,7 @@ bool dc_link_setup_psr(const struct dc_link *dc_link,
psr_context.psrFrameCaptureIndicationReq =
dc_link->psr_caps.psr_frame_capture_indication_req;
- psr_context.skipPsrWaitForPllLock =
- ctx->adapter_srv->
- asic_cap->caps.SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT;
+ psr_context.skipPsrWaitForPllLock = 0; /* only = 1 in KV */
psr_context.numberOfControllers =
link->dc->res_pool->res_cap->num_timing_generator;
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 52/76] drm/amd/dal: remove adapter_service and asic_capability
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (50 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 51/76] drm/amd/dal: remove SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 53/76] drm/amd/dal: Update stream_encoder programming sequence Harry Wentland
` (24 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
Yay!!!!
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/Makefile | 2 +-
drivers/gpu/drm/amd/dal/dc/adapter/Makefile | 10 -
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 625 ---------------------
.../gpu/drm/amd/dal/dc/adapter/adapter_service.h | 34 --
.../gpu/drm/amd/dal/dc/asic_capability/Makefile | 50 --
.../amd/dal/dc/asic_capability/asic_capability.c | 181 ------
.../dc/asic_capability/carrizo_asic_capability.c | 133 -----
.../dc/asic_capability/carrizo_asic_capability.h | 36 --
.../dc/asic_capability/hawaii_asic_capability.c | 132 -----
.../dc/asic_capability/hawaii_asic_capability.h | 37 --
.../dc/asic_capability/polaris10_asic_capability.c | 125 -----
.../dc/asic_capability/polaris10_asic_capability.h | 36 --
.../dal/dc/asic_capability/tonga_asic_capability.c | 132 -----
.../dal/dc/asic_capability/tonga_asic_capability.h | 18 -
drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 2 -
drivers/gpu/drm/amd/dal/dc/core/dc.c | 48 --
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 5 -
drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 3 -
drivers/gpu/drm/amd/dal/dc/dc_types.h | 1 -
drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c | 3 -
20 files changed, 1 insertion(+), 1612 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/Makefile
delete mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
index f1a60322dce6..834bb1814be5 100644
--- a/drivers/gpu/drm/amd/dal/dc/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
@@ -2,7 +2,7 @@
# Makefile for Display Core (dc) component.
#
-DC_LIBS = adapter asic_capability basics bios calcs dce \
+DC_LIBS = basics bios calcs dce \
gpio gpu i2caux irq virtual
DC_LIBS += dce112
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
deleted file mode 100644
index 3297656bf948..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Makefile for the 'adapter' sub-component of DAL.
-# It provides the control and status of HW adapter.
-
-ADAPTER = adapter_service.o
-
-AMD_DAL_ADAPTER = $(addprefix $(AMDDALPATH)/dc/adapter/,$(ADAPTER))
-
-AMD_DAL_FILES += $(AMD_DAL_ADAPTER)
-
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
deleted file mode 100644
index b91301561b7f..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ /dev/null
@@ -1,625 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "dc_bios_types.h"
-
-#include "include/adapter_service_interface.h"
-#include "include/i2caux_interface.h"
-#include "include/asic_capability_types.h"
-#include "include/gpio_service_interface.h"
-#include "include/asic_capability_interface.h"
-#include "include/logger_interface.h"
-
-#include "adapter_service.h"
-
-#include "atom.h"
-
-#define ABSOLUTE_BACKLIGHT_MAX 255
-#define DEFAULT_MIN_BACKLIGHT 12
-#define DEFAULT_MAX_BACKLIGHT 255
-#define BACKLIGHT_CURVE_COEFFB 100
-#define BACKLIGHT_CURVE_COEFFA_FACTOR 10000
-#define BACKLIGHT_CURVE_COEFFB_FACTOR 100
-
-/*
- * Adapter service feature entry table.
- *
- * This is an array of features that is used to generate feature set. Each
- * entry consists three element:
- *
- * Feature name, default value, and if this feature is a boolean type. A
- * feature can only be a boolean or int type.
- *
- * Example 1: a boolean type feature
- * FEATURE_ENABLE_HW_EDID_POLLING, false, true
- *
- * First element is feature name: EATURE_ENABLE_HW_EDID_POLLING, it has a
- * default value 0, and it is a boolean feature.
- *
- * Example 2: an int type feature
- * FEATURE_DCP_PROGRAMMING_WA, 0x1FF7, false
- *
- * In this case, the default value is 0x1FF7 and not a boolean type, which
- * makes it an int type.
- */
-/* Type of feature with its runtime parameter and default value */
-struct feature_source_entry {
- enum adapter_feature_id feature_id;
- uint32_t default_value;
- bool is_boolean_type;
-};
-
-static const struct feature_source_entry feature_entry_table[] = {
- /* Feature name | default value | is boolean type */
- {FEATURE_ENABLE_HW_EDID_POLLING, false, true},
- {FEATURE_DP_SINK_DETECT_POLL_DATA_PIN, false, true},
- {FEATURE_UNDERFLOW_INTERRUPT, false, true},
- {FEATURE_ALLOW_WATERMARK_ADJUSTMENT, false, true},
- {FEATURE_DCP_DITHER_FRAME_RANDOM_ENABLE, false, true},
- {FEATURE_DCP_DITHER_RGB_RANDOM_ENABLE, false, true},
- {FEATURE_DCP_DITHER_HIGH_PASS_RANDOM_ENABLE, false, true},
- {FEATURE_LINE_BUFFER_ENHANCED_PIXEL_DEPTH, false, true},
- {FEATURE_MAXIMIZE_URGENCY_WATERMARKS, false, true},
- {FEATURE_MAXIMIZE_STUTTER_MARKS, false, true},
- {FEATURE_MAXIMIZE_NBP_MARKS, false, true},
- {FEATURE_ALLOW_EDP_RESOURCE_SHARING, false, true},
- {FEATURE_SUPPORT_DP_YUV, false, true},
- {FEATURE_SUPPORT_DP_Y_ONLY, false, true},
- {FEATURE_MODIFY_TIMINGS_FOR_WIRELESS, false, true},
- {FEATURE_DCP_BIT_DEPTH_REDUCTION_MODE, 0, false},
- {FEATURE_DCP_DITHER_MODE, 0, false},
- {FEATURE_DCP_PROGRAMMING_WA, 0, false},
- {FEATURE_WIRELESS_FULL_TIMING_ADJUSTMENT, false, true},
- {FEATURE_WIRELESS_LIMIT_720P, false, true},
- {FEATURE_MODIFY_TIMINGS_FOR_WIRELESS, false, true},
- {FEATURE_DETECT_REQUIRE_HPD_HIGH, false, true},
- {FEATURE_LB_HIGH_RESOLUTION, false, true},
- {FEATURE_MAX_CONTROLLER_NUM, 0, false},
- {FEATURE_DRR_SUPPORT, AS_DRR_SUPPORT_ENABLED, false},
- {FEATURE_DP_DISPLAY_FORCE_SS_ENABLE, false, true},
- {FEATURE_REPORT_CE_MODE_ONLY, false, true},
- {FEATURE_ALLOW_OPTIMIZED_MODE_AS_DEFAULT, false, true},
- {FEATURE_FORCE_TIMING_RESYNC, false, true},
- {FEATURE_TMDS_DISABLE_DITHERING, false, true},
- {FEATURE_HDMI_DISABLE_DITHERING, false, true},
- {FEATURE_DP_DISABLE_DITHERING, false, true},
- {FEATURE_EMBEDDED_DISABLE_DITHERING, true, true},
- {FEATURE_ALLOW_SELF_REFRESH, false, true},
- {FEATURE_ALLOW_DYNAMIC_PIXEL_ENCODING_CHANGE, false, true},
- {FEATURE_ALLOW_HSYNC_VSYNC_ADJUSTMENT, false, true},
- {FEATURE_FORCE_PSR, false, true},
- {FEATURE_PSR_SETUP_TIME_TEST, 0, false},
- {FEATURE_POWER_GATING_PIPE_IN_TILE, true, true},
- {FEATURE_POWER_GATING_LB_PORTION, true, true},
- {FEATURE_PREFER_3D_TIMING, false, true},
- {FEATURE_VARI_BRIGHT_ENABLE, true, true},
- {FEATURE_PSR_ENABLE, false, true},
- {FEATURE_WIRELESS_ENABLE_COMPRESSED_AUDIO, false, true},
- {FEATURE_WIRELESS_INCLUDE_UNVERIFIED_TIMINGS, true, true},
- {FEATURE_DP_FRAME_PACK_STEREO3D, false, true},
- {FEATURE_DISPLAY_PREFERRED_VIEW, 0, false},
- {FEATURE_ALLOW_HDMI_WITHOUT_AUDIO, false, true},
- {FEATURE_ABM_2_0, false, true},
- {FEATURE_SUPPORT_MIRABILIS, false, true},
- {FEATURE_OPTIMIZATION, 0xFFFF, false},
- {FEATURE_PERF_MEASURE, 0, false},
- {FEATURE_MIN_BACKLIGHT_LEVEL, 0, false},
- {FEATURE_MAX_BACKLIGHT_LEVEL, 255, false},
- {FEATURE_LOAD_DMCU_FIRMWARE, true, true},
- {FEATURE_DISABLE_AZ_CLOCK_GATING, false, true},
- {FEATURE_DONGLE_SINK_COUNT_CHECK, true, true},
- {FEATURE_INSTANT_UP_SCALE_DOWN_SCALE, false, true},
- {FEATURE_TILED_DISPLAY, false, true},
- {FEATURE_PREFERRED_ABM_CONFIG_SET, 0, false},
- {FEATURE_CHANGE_SW_I2C_SPEED, 50, false},
- {FEATURE_CHANGE_HW_I2C_SPEED, 50, false},
- {FEATURE_CHANGE_I2C_SPEED_CONTROL, false, true},
- {FEATURE_DEFAULT_PSR_LEVEL, 0, false},
- {FEATURE_MAX_CLOCK_SOURCE_NUM, 0, false},
- {FEATURE_REPORT_SINGLE_SELECTED_TIMING, false, true},
- {FEATURE_ALLOW_HDMI_HIGH_CLK_DP_DONGLE, true, true},
- {FEATURE_SUPPORT_EXTERNAL_PANEL_DRR, false, true},
- {FEATURE_LVDS_SAFE_PIXEL_CLOCK_RANGE, 0, false},
- {FEATURE_ABM_CONFIG, 0, false},
- {FEATURE_WIRELESS_ENABLE, false, true},
- {FEATURE_ALLOW_DIRECT_MEMORY_ACCESS_TRIG, false, true},
- {FEATURE_FORCE_STATIC_SCREEN_EVENT_TRIGGERS, 0, false},
- {FEATURE_USE_PPLIB, true, true},
- {FEATURE_DPMS_AUDIO_ENDPOINT_CONTROL, true, true},
- {FEATURE_PIXEL_PERFECT_OUTPUT, false, true},
- {FEATURE_8BPP_SUPPORTED, false, true},
-};
-
-enum {
- LEGACY_MAX_NUM_OF_CONTROLLERS = 2,
- DEFAULT_NUM_COFUNC_NON_DP_DISPLAYS = 2
-};
-
-/*
- * get_feature_entries_num
- *
- * Get number of feature entries
- */
-static inline uint32_t get_feature_entries_num(void)
-{
- return ARRAY_SIZE(feature_entry_table);
-}
-
-static void get_platform_info_methods(
- struct adapter_service *as)
-{
- struct platform_info_params params;
- uint32_t mask = 0;
-
- params.data = &mask;
- params.method = PM_GET_AVAILABLE_METHODS;
-
- if (dm_get_platform_info(as->ctx, ¶ms))
- as->platform_methods_mask = mask;
-
-}
-
-static void initialize_backlight_caps(
- struct adapter_service *as)
-{
- struct firmware_info fw_info;
- struct embedded_panel_info panel_info;
- struct platform_info_ext_brightness_caps caps;
- struct platform_info_params params;
- bool custom_curve_present = false;
- bool custom_min_max_present = false;
- struct dc_bios *dcb = as->ctx->dc_bios;
-
- if (!(PM_GET_EXTENDED_BRIGHNESS_CAPS & as->platform_methods_mask)) {
- dm_logger_write(as->ctx->logger, LOG_BACKLIGHT,
- "This method is not supported\n");
- return;
- }
-
- if (dcb->funcs->get_firmware_info(dcb, &fw_info) != BP_RESULT_OK ||
- dcb->funcs->get_embedded_panel_info(dcb, &panel_info) != BP_RESULT_OK)
- return;
-
- params.data = ∩︀
- params.method = PM_GET_EXTENDED_BRIGHNESS_CAPS;
-
- if (dm_get_platform_info(as->ctx, ¶ms)) {
- as->ac_level_percentage = caps.basic_caps.ac_level_percentage;
- as->dc_level_percentage = caps.basic_caps.dc_level_percentage;
- custom_curve_present = (caps.data_points_num > 0);
- custom_min_max_present = true;
- } else
- return;
- /* Choose minimum backlight level base on priority:
- * extended caps,VBIOS,default */
- if (custom_min_max_present)
- as->backlight_8bit_lut[0] = caps.min_input_signal;
-
- else if (fw_info.min_allowed_bl_level > 0)
- as->backlight_8bit_lut[0] = fw_info.min_allowed_bl_level;
-
- else
- as->backlight_8bit_lut[0] = DEFAULT_MIN_BACKLIGHT;
-
- /* Choose maximum backlight level base on priority:
- * extended caps,default */
- if (custom_min_max_present)
- as->backlight_8bit_lut[100] = caps.max_input_signal;
-
- else
- as->backlight_8bit_lut[100] = DEFAULT_MAX_BACKLIGHT;
-
- if (as->backlight_8bit_lut[100] > ABSOLUTE_BACKLIGHT_MAX)
- as->backlight_8bit_lut[100] = ABSOLUTE_BACKLIGHT_MAX;
-
- if (as->backlight_8bit_lut[0] > as->backlight_8bit_lut[100])
- as->backlight_8bit_lut[0] = as->backlight_8bit_lut[100];
-
- if (custom_curve_present) {
- uint16_t index = 1;
- uint16_t i;
- uint16_t num_of_data_points = (caps.data_points_num <= 99 ?
- caps.data_points_num : 99);
- /* Filling translation table from data points -
- * between every two provided data points we
- * lineary interpolate missing values
- */
- for (i = 0 ; i < num_of_data_points; i++) {
- uint16_t luminance = caps.data_points[i].luminance;
- uint16_t signal_level =
- caps.data_points[i].signal_level;
-
- if (signal_level < as->backlight_8bit_lut[0])
- signal_level = as->backlight_8bit_lut[0];
-
- if (signal_level > as->backlight_8bit_lut[100])
- signal_level = as->backlight_8bit_lut[100];
-
- /* Lineary interpolate missing values */
- if (index < luminance) {
- uint16_t base_value =
- as->backlight_8bit_lut[index-1];
- uint16_t delta_signal =
- signal_level - base_value;
- uint16_t delta_luma = luminance - index + 1;
- uint16_t step = delta_signal;
-
- for (; index < luminance ; index++) {
- as->backlight_8bit_lut[index] =
- base_value +
- (step / delta_luma);
- step += delta_signal;
- }
- }
- /* Now [index == luminance], so we can add
- * data point to the translation table */
- as->backlight_8bit_lut[index++] = signal_level;
- }
- /* Complete the final segment of interpolation -
- * between last datapoint and maximum value */
- if (index < 100) {
- uint16_t base_value = as->backlight_8bit_lut[index-1];
- uint16_t delta_signal =
- as->backlight_8bit_lut[100]-base_value;
- uint16_t delta_luma = 100 - index + 1;
- uint16_t step = delta_signal;
-
- for (; index < 100 ; index++) {
- as->backlight_8bit_lut[index] = base_value +
- (step / delta_luma);
- step += delta_signal;
- }
- }
- }
- /* build backlight translation table based on default curve */
- else {
- /* Default backlight curve can be defined by
- * polinomial F(x) = A(x*x) + Bx + C.
- * Backlight curve should always satisfy
- * F(0) = min, F(100) = max, so polinomial coefficients are:
- * A is 0.0255 - B/100 - min/10000 -
- * (255-max)/10000 = (max - min)/10000 - B/100
- * B is adjustable factor to modify the curve.
- * Bigger B results in less concave curve.
- * B range is [0..(max-min)/100]
- * C is backlight minimum
- */
- uint16_t delta = as->backlight_8bit_lut[100] -
- as->backlight_8bit_lut[0];
- uint16_t coeffc = as->backlight_8bit_lut[0];
- uint16_t coeffb = (BACKLIGHT_CURVE_COEFFB < delta ?
- BACKLIGHT_CURVE_COEFFB : delta);
- uint16_t coeffa = delta - coeffb;
- uint16_t i;
- uint32_t temp;
-
- for (i = 1; i < 100 ; i++) {
- temp = (coeffa * i * i) / BACKLIGHT_CURVE_COEFFA_FACTOR;
- as->backlight_8bit_lut[i] = temp + (coeffb * i) /
- BACKLIGHT_CURVE_COEFFB_FACTOR + coeffc;
- }
- }
- as->backlight_caps_initialized = true;
-}
-/*
- * get_feature_value_from_data_sources
- *
- * For a given feature, determine its value from ASIC cap and wireless
- * data source.
- * idx : index of feature_entry_table for the feature id.
- */
-static bool get_feature_value_from_data_sources(
- const struct adapter_service *as,
- const uint32_t idx,
- uint32_t *data)
-{
- if (idx >= get_feature_entries_num()) {
- ASSERT_CRITICAL(false);
- return false;
- }
-
- switch (feature_entry_table[idx].feature_id) {
- case FEATURE_WIRELESS_LIMIT_720P:
- *data = as->asic_cap->caps.WIRELESS_LIMIT_TO_720P;
- break;
-
- case FEATURE_WIRELESS_FULL_TIMING_ADJUSTMENT:
- *data = as->asic_cap->caps.WIRELESS_FULL_TIMING_ADJUSTMENT;
- break;
-
- case FEATURE_MODIFY_TIMINGS_FOR_WIRELESS:
- *data = as->asic_cap->caps.WIRELESS_TIMING_ADJUSTMENT;
- break;
-
- case FEATURE_DETECT_REQUIRE_HPD_HIGH:
- *data = as->asic_cap->caps.HPD_CHECK_FOR_EDID;
- break;
-
- case FEATURE_8BPP_SUPPORTED:
- *data = as->asic_cap->caps.SUPPORT_8BPP;
- break;
-
- default:
- return false;
- }
-
- return true;
-}
-
-/* get_bool_value
- *
- * Get the boolean value of a given feature
- */
-static bool get_bool_value(
- const uint32_t set,
- const uint32_t idx)
-{
- if (idx >= 32) {
- ASSERT_CRITICAL(false);
- return false;
- }
-
- return ((set & (1 << idx)) != 0);
-}
-
-/*
- * lookup_feature_entry
- *
- * Find the entry index of a given feature in feature table
- */
-static uint32_t lookup_feature_entry(struct adapter_service *as,
- enum adapter_feature_id feature_id)
-{
- uint32_t entries_num = get_feature_entries_num();
- uint32_t i = 0;
-
- while (i != entries_num) {
- if (feature_entry_table[i].feature_id == feature_id)
- break;
-
- ++i;
- }
-
- return i;
-}
-
-/*
- * set_bool_value
- *
- * Set the boolean value of a given feature
- */
-static void set_bool_value(
- uint32_t *set,
- const uint32_t idx,
- bool value)
-{
- if (idx >= 32) {
- ASSERT_CRITICAL(false);
- return;
- }
-
- if (value)
- *set |= (1 << idx);
- else
- *set &= ~(1 << idx);
-}
-
-/*
- * generate_feature_set
- *
- * Generate the internal feature set from multiple data sources
- */
-static bool generate_feature_set(
- struct adapter_service *as)
-{
- uint32_t i = 0;
- uint32_t value = 0;
- uint32_t set_idx = 0;
- uint32_t internal_idx = 0;
- uint32_t entry_num = 0;
- const struct feature_source_entry *entry = NULL;
-
- memset(as->adapter_feature_set, 0, sizeof(as->adapter_feature_set));
- entry_num = get_feature_entries_num();
-
- while (i != entry_num) {
- entry = &feature_entry_table[i];
-
- if (entry->feature_id <= FEATURE_UNKNOWN ||
- entry->feature_id >= FEATURE_MAXIMUM) {
- ASSERT_CRITICAL(false);
- return false;
- }
-
- set_idx = (uint32_t)((entry->feature_id - 1) / 32);
- internal_idx = (uint32_t)((entry->feature_id - 1) % 32);
-
- if (!get_feature_value_from_data_sources(
- as, i, &value)) {
- /*
- * Can't find feature values from
- * above data sources
- * Assign default value
- */
- value = as->default_values[entry->feature_id];
- }
-
- if (entry->is_boolean_type)
- set_bool_value(&as->adapter_feature_set[set_idx],
- internal_idx,
- value != 0);
- else
- as->adapter_feature_set[set_idx] = value;
-
- i++;
- }
-
- return true;
-}
-
-/*
- * adapter_service_destruct
- *
- * Release memory of objects in adapter service
- */
-static void adapter_service_destruct(
- struct adapter_service *as)
-{
- dal_asic_capability_destroy(&as->asic_cap);
-}
-
-/*
- * adapter_service_construct
- *
- * Construct the derived type of adapter service
- */
-static bool adapter_service_construct(
- struct adapter_service *as,
- struct as_init_data *init_data)
-{
- struct dc_bios *dcb;
- uint32_t i;
-
- if (!init_data)
- return false;
-
- /* Create ASIC capability */
- as->ctx = init_data->ctx;
- as->asic_cap = dal_asic_capability_create(
- &init_data->hw_init_data, as->ctx);
-
- if (!as->asic_cap) {
- ASSERT_CRITICAL(false);
- return false;
- }
-
- for (i = 0; i < ARRAY_SIZE(feature_entry_table); i++) {
- enum adapter_feature_id id =
- feature_entry_table[i].feature_id;
-
- as->default_values[id] = feature_entry_table[i].default_value;
- }
-
- if (as->ctx->dce_version == DCE_VERSION_11_0) {
- uint32_t i;
-
- for (i = 0; i < ARRAY_SIZE(feature_entry_table); i++) {
- enum adapter_feature_id id =
- feature_entry_table[i].feature_id;
-
- if (id == FEATURE_MAXIMIZE_URGENCY_WATERMARKS ||
- id == FEATURE_MAXIMIZE_STUTTER_MARKS ||
- id == FEATURE_MAXIMIZE_NBP_MARKS)
- as->default_values[id] = true;
- }
- }
-
- /* Generate feature set table */
- if (!generate_feature_set(as)) {
- ASSERT_CRITICAL(false);
- goto failed_to_generate_features;
- }
-
- as->dce_environment = init_data->dce_environment;
-
- dcb = as->ctx->dc_bios;
-
- dcb->funcs->post_init(dcb);
-
- /* Generate backlight translation table and initializes
- other brightness properties */
- as->backlight_caps_initialized = false;
-
- get_platform_info_methods(as);
-
- initialize_backlight_caps(as);
-
- return true;
-
-failed_to_generate_features:
- dal_asic_capability_destroy(&as->asic_cap);
-
- return false;
-}
-
-/*
- * Global function definition
- */
-
-/*
- * dal_adapter_service_create
- *
- * Create adapter service
- */
-struct adapter_service *dal_adapter_service_create(
- struct as_init_data *init_data)
-{
- struct adapter_service *as;
-
- as = dm_alloc(sizeof(struct adapter_service));
-
- if (!as) {
- ASSERT_CRITICAL(false);
- return NULL;
- }
-
- if (adapter_service_construct(as, init_data))
- return as;
-
- ASSERT_CRITICAL(false);
-
- dm_free(as);
-
- return NULL;
-}
-
-/*
- * dal_adapter_service_destroy
- *
- * Destroy adapter service and objects it contains
- */
-void dal_adapter_service_destroy(
- struct adapter_service **as)
-{
- if (!as) {
- ASSERT_CRITICAL(false);
- return;
- }
-
- if (!*as) {
- ASSERT_CRITICAL(false);
- return;
- }
-
- adapter_service_destruct(*as);
-
- dm_free(*as);
-
- *as = NULL;
-}
-
-
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
deleted file mode 100644
index 823322bfc3a2..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_ADAPTER_SERVICE_H__
-#define __DAL_ADAPTER_SERVICE_H__
-
-/* Include */
-#include "dc_bios_types.h"
-#include "include/adapter_service_interface.h"
-
-
-#endif /* __DAL_ADAPTER_SERVICE_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
deleted file mode 100644
index 01ba25d1c2fa..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# Makefile for the 'asic_capability' sub-component of DAL.
-#
-
-ASIC_CAPABILITY = asic_capability.o
-
-AMD_DAL_ASIC_CAPABILITY = \
- $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY))
-
-AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY)
-
-###############################################################################
-# DCE 8x
-###############################################################################
-ASIC_CAPABILITY_DCE80 = hawaii_asic_capability.o
-
-AMD_DAL_ASIC_CAPABILITY_DCE80 = \
- $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE80))
-
-AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE80)
-
-
-###############################################################################
-# DCE 10x
-###############################################################################
-ASIC_CAPABILITY_DCE10 = tonga_asic_capability.o
-
-AMD_DAL_ASIC_CAPABILITY_DCE10 = \
- $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE10))
-
-AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE10)
-
-
-###############################################################################
-# DCE 11x
-###############################################################################
-ASIC_CAPABILITY_DCE11 = carrizo_asic_capability.o
-
-AMD_DAL_ASIC_CAPABILITY_DCE11 = \
- $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE11))
-
-AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE11)
-
-
-ASIC_CAPABILITY_DCE112 = polaris10_asic_capability.o
-
-AMD_DAL_ASIC_CAPABILITY_DCE112 = \
- $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE112))
-
-AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE112)
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
deleted file mode 100644
index 89dd74675ba9..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/logger_interface.h"
-
-#include "include/asic_capability_interface.h"
-#include "include/asic_capability_types.h"
-#include "include/dal_types.h"
-#include "include/dal_asic_id.h"
-
-#include "hawaii_asic_capability.h"
-
-#include "tonga_asic_capability.h"
-
-#include "carrizo_asic_capability.h"
-
-#include "polaris10_asic_capability.h"
-
-/*
- * Initializes asic_capability instance.
- */
-static bool construct(
- struct asic_capability *cap,
- struct hw_asic_id *init,
- struct dc_context *ctx)
-{
- bool asic_supported = false;
-
- cap->ctx = ctx;
- memset(cap->data, 0, sizeof(cap->data));
-
- /* ASIC data */
- cap->data[ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE] = 10;
- cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 4;
- cap->data[ASIC_DATA_DOWNSCALE_LIMIT] = 200;
-
- /* ASIC basic capability */
- cap->caps.UNDERSCAN_FOR_HDMI_ONLY = true;
- cap->caps.SUPPORT_CEA861E_FINAL = true;
- cap->caps.MIRABILIS_SUPPORTED = false;
- cap->caps.MIRABILIS_ENABLED_BY_DEFAULT = false;
- cap->caps.WIRELESS_LIMIT_TO_720P = false;
- cap->caps.WIRELESS_FULL_TIMING_ADJUSTMENT = false;
- cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
- cap->caps.WIRELESS_COMPRESSED_AUDIO = false;
- cap->caps.VCE_SUPPORTED = false;
- cap->caps.HPD_CHECK_FOR_EDID = false;
- cap->caps.NEED_MC_TUNING = false;
- cap->caps.SUPPORT_8BPP = true;
-
- /* ASIC stereo 3D capability */
- cap->stereo_3d_caps.SUPPORTED = true;
-
- switch (init->chip_family) {
- case FAMILY_CI:
- dal_hawaii_asic_capability_create(cap, init);
- asic_supported = true;
- break;
-
- case FAMILY_KV:
- break;
-
- case FAMILY_CZ:
- carrizo_asic_capability_create(cap, init);
- asic_supported = true;
- break;
-
- case FAMILY_VI:
- if (ASIC_REV_IS_TONGA_P(init->hw_internal_rev) ||
- ASIC_REV_IS_FIJI_P(init->hw_internal_rev)) {
- tonga_asic_capability_create(cap, init);
- asic_supported = true;
- break;
- }
- if (ASIC_REV_IS_POLARIS10_P(init->hw_internal_rev) ||
- ASIC_REV_IS_POLARIS11_M(init->hw_internal_rev)) {
- polaris10_asic_capability_create(cap, init);
- asic_supported = true;
- }
- break;
-
- default:
- /* unsupported "chip_family" */
- break;
- }
-
- if (false == asic_supported) {
- dm_logger_write(ctx->logger, LOG_ERROR,
- "%s: ASIC not supported!\n", __func__);
- }
-
- return asic_supported;
-}
-
-static void destruct(
- struct asic_capability *cap)
-{
- /* nothing to do (yet?) */
-}
-
-/*
- * dal_asic_capability_create
- *
- * Creates asic capability based on DCE version.
- */
-struct asic_capability *dal_asic_capability_create(
- struct hw_asic_id *init,
- struct dc_context *ctx)
-{
- struct asic_capability *cap;
-
- if (!init) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- cap = dm_alloc(sizeof(struct asic_capability));
-
- if (!cap) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- if (construct(cap, init, ctx))
- return cap;
-
- BREAK_TO_DEBUGGER();
-
- dm_free(cap);
-
- return NULL;
-}
-
-/*
- * dal_asic_capability_destroy
- *
- * Destroy allocated memory.
- */
-void dal_asic_capability_destroy(
- struct asic_capability **cap)
-{
- if (!cap) {
- BREAK_TO_DEBUGGER();
- return;
- }
-
- if (!*cap) {
- BREAK_TO_DEBUGGER();
- return;
- }
-
- destruct(*cap);
-
- dm_free(*cap);
-
- *cap = NULL;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
deleted file mode 100644
index 7243e51e909f..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/asic_capability_interface.h"
-#include "include/asic_capability_types.h"
-
-#include "carrizo_asic_capability.h"
-
-#include "atom.h"
-#include "dce/dce_11_0_d.h"
-#include "smu/smu_8_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
-#include "dal_asic_id.h"
-
-#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
-
-/*
- * carrizo_asic_capability_create
- *
- * Create and initiate Carrizo capability.
- */
-void carrizo_asic_capability_create(struct asic_capability *cap,
- struct hw_asic_id *init)
-{
- uint32_t e_fuse_setting;
- /* ASIC data */
- cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
- cap->data[ASIC_DATA_DCE_VERSION] = 0x110; /* DCE 11 */
- cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
- cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 45;
- cap->data[ASIC_DATA_MC_LATENCY] = 5000;
- cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
- cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
- cap->data[ASIC_DATA_DOWNSCALE_LIMIT] = 150;
-
- /* ASIC basic capability */
- cap->caps.IS_FUSION = true;
- cap->caps.DP_MST_SUPPORTED = true;
- cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
- cap->caps.MIRABILIS_SUPPORTED = true;
- cap->caps.VCE_SUPPORTED = true;
- cap->caps.HPD_CHECK_FOR_EDID = true;
- cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
- cap->caps.SUPPORT_8BPP = false;
-
- /* ASIC stereo 3d capability */
- cap->stereo_3d_caps.DISPLAY_BASED_ON_WS = true;
- cap->stereo_3d_caps.HDMI_FRAME_PACK = true;
- cap->stereo_3d_caps.INTERLACE_FRAME_PACK = true;
- cap->stereo_3d_caps.DISPLAYPORT_FRAME_PACK = true;
- cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
- cap->stereo_3d_caps.INTERLEAVE = true;
-
- e_fuse_setting = dm_read_index_reg(cap->ctx,CGS_IND_REG__SMC, ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
-
- /* Bits [28:27]*/
- switch ((e_fuse_setting >> 27) & 0x3) {
- case 0:
- /*both VCE engine are working*/
- cap->caps.VCE_SUPPORTED = true;
- cap->caps.WIRELESS_TIMING_ADJUSTMENT = false;
- /*TODO:
- cap->caps.wirelessLowVCEPerformance = false;
- m_AsicCaps.vceInstance0Enabled = true;
- m_AsicCaps.vceInstance1Enabled = true;*/
- cap->caps.NEED_MC_TUNING = true;
- break;
-
- case 1:
- cap->caps.VCE_SUPPORTED = true;
- cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
- /*TODO:
- m_AsicCaps.wirelessLowVCEPerformance = false;
- m_AsicCaps.vceInstance1Enabled = true;*/
- cap->caps.NEED_MC_TUNING = true;
- break;
-
- case 2:
- cap->caps.VCE_SUPPORTED = true;
- cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
- /*TODO:
- m_AsicCaps.wirelessLowVCEPerformance = false;
- m_AsicCaps.vceInstance0Enabled = true;*/
- cap->caps.NEED_MC_TUNING = true;
- break;
-
- case 3:
- /* VCE_DISABLE = 0x3 - both VCE
- * instances are in harvesting,
- * no VCE supported any more.
- */
- cap->caps.VCE_SUPPORTED = false;
- break;
-
- default:
- break;
- }
-
- if (ASIC_REV_IS_STONEY(init->hw_internal_rev))
- {
- /* Stoney is the same DCE11, but only two pipes, three digs.
- * and HW added 64bit back for non SG */
- /*3 DP MST per connector, limited by number of pipe and number
- * of Dig.*/
- cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 2;
-
- }
-
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
deleted file mode 100644
index d1e9b8337d5b..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_CARRIZO_ASIC_CAPABILITY_H__
-#define __DAL_CARRIZO_ASIC_CAPABILITY_H__
-
-/* Forward declaration */
-struct asic_capability;
-
-/* Create and initialize Carrizo data */
-void carrizo_asic_capability_create(struct asic_capability *cap,
- struct hw_asic_id *init);
-
-#endif /* __DAL_CARRIZO_ASIC_CAPABILITY_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
deleted file mode 100644
index e0c9ef4557e7..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-/*
- * Includes
- */
-
-#include "dm_services.h"
-
-#include "include/asic_capability_interface.h"
-#include "include/asic_capability_types.h"
-#include "include/dal_types.h"
-#include "include/dal_asic_id.h"
-#include "include/logger_interface.h"
-#include "hawaii_asic_capability.h"
-
-#include "atom.h"
-
-#include "dce/dce_8_0_d.h"
-#include "gmc/gmc_7_1_d.h"
-
-/*
- * Sea Islands (CI) ASIC capability.
- *
- * dal_hawaii_asic_capability_create
- *
- * Create and initiate hawaii capability.
- */
-void dal_hawaii_asic_capability_create(struct asic_capability *cap,
- struct hw_asic_id *init)
-{
- uint32_t mc_seq_misc0;
-
- /* ASIC data */
- cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
-
- cap->data[ASIC_DATA_DCE_VERSION] = 0x80; /* DCE 8.0 */
-
- /* Pixel RAM is 1712 entries of 144 bits each or
- * in other words 246528 bits. */
- cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
- cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
- cap->data[ASIC_DATA_MC_LATENCY] = 5000; /* units of ns */
- cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
- cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
-
- mc_seq_misc0 = dm_read_reg(cap->ctx, mmMC_SEQ_MISC0);
-
- switch (mc_seq_misc0 & MC_MISC0__MEMORY_TYPE_MASK) {
- case MC_MISC0__MEMORY_TYPE__GDDR1:
- case MC_MISC0__MEMORY_TYPE__DDR2:
- case MC_MISC0__MEMORY_TYPE__DDR3:
- case MC_MISC0__MEMORY_TYPE__GDDR3:
- case MC_MISC0__MEMORY_TYPE__GDDR4:
- cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
- break;
- case MC_MISC0__MEMORY_TYPE__GDDR5:
- cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
- break;
- default:
- dm_logger_write(cap->ctx->logger, LOG_ERROR,
- "%s:Unrecognized memory type!", __func__);
- cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
- break;
- }
-
- /* ASIC stereo 3D capability */
- cap->stereo_3d_caps.INTERLEAVE = true;
- cap->stereo_3d_caps.HDMI_FRAME_PACK = true;
- cap->stereo_3d_caps.INTERLACE_FRAME_PACK = true;
- cap->stereo_3d_caps.DISPLAYPORT_FRAME_PACK = true;
- cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
- cap->stereo_3d_caps.DISPLAY_BASED_ON_WS = true;
-
- /* ASIC basic capability */
- cap->caps.DP_MST_SUPPORTED = true;
- cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
-
- cap->caps.MIRABILIS_SUPPORTED = true;
- cap->caps.MIRABILIS_ENABLED_BY_DEFAULT = true;
-
- /* Remap device tag IDs when patching VBIOS. */
- cap->caps.DEVICE_TAG_REMAP_SUPPORTED = true;
-
- /* Report headless if no OPM attached (with MXM connectors present). */
- cap->caps.HEADLESS_NO_OPM_SUPPORTED = true;
-
- cap->caps.HPD_CHECK_FOR_EDID = true;
-
- /* true will hang the system! */
- cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = false;
-
- /* Do w/a on CI A0 by default */
- if (init->hw_internal_rev == CI_BONAIRE_M_A0)
- cap->bugs.LB_WA_IS_SUPPORTED = true;
-
- /* Apply MC Tuning for Hawaii */
- if (ASIC_REV_IS_HAWAII_P(init->hw_internal_rev))
- cap->caps.NEED_MC_TUNING = true;
-
- /* DCE6.0 and DCE8.0 has a HW issue when accessing registers
- * from ROM block. When there is a W access following R or W access
- * right after (no more than couple of cycles) the first W access
- * sometimes is not executed (in rate of about once per 100K tries).
- * It creates problems in different scenarios of FL setup. */
- cap->bugs.ROM_REGISTER_ACCESS = true;
-
- /* VCE is supported */
- cap->caps.VCE_SUPPORTED = true;
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.h b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.h
deleted file mode 100644
index 191d9b293e29..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_BONAIRE_CAPABILITY_H__
-#define __DAL_BONAIRE_CAPABILITY_H__
-
-/* Forward declaration */
-struct asic_capability;
-struct hw_asic_id;
-
-/* Create and initialise Bonaire data */
-void dal_hawaii_asic_capability_create(struct asic_capability *cap,
- struct hw_asic_id *init);
-
-#endif /* __DAL_BONAIRE_CAPABILITY_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
deleted file mode 100644
index 7716d6587793..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/asic_capability_interface.h"
-#include "include/asic_capability_types.h"
-
-#include "polaris10_asic_capability.h"
-
-#include "atom.h"
-#include "dce/dce_11_2_d.h"
-#include "dce/dce_11_2_sh_mask.h"
-#include "dal_asic_id.h"
-
-#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
-
-/*
- * carrizo_asic_capability_create
- *
- * Create and initiate Carrizo capability.
- */
-void polaris10_asic_capability_create(struct asic_capability *cap,
- struct hw_asic_id *init)
-{
- uint32_t e_fuse_setting;
- /* ASIC data */
-
- cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
- cap->data[ASIC_DATA_DCE_VERSION] = 0x112; /* DCE 11 */
- cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 5124 * 144;
- cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
-
- cap->data[ASIC_DATA_MC_LATENCY] = 3000;
- cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
-
- cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
-
- cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
-
- /* ASIC basic capability */
- cap->caps.IS_FUSION = true;
- cap->caps.DP_MST_SUPPORTED = true;
- cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
- cap->caps.MIRABILIS_SUPPORTED = true;
- cap->caps.VCE_SUPPORTED = true;
- cap->caps.HPD_CHECK_FOR_EDID = true;
- cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
- cap->caps.SUPPORT_8BPP = false;
-
- /* ASIC stereo 3d capability */
- cap->stereo_3d_caps.DISPLAY_BASED_ON_WS = true;
- cap->stereo_3d_caps.HDMI_FRAME_PACK = true;
- cap->stereo_3d_caps.INTERLACE_FRAME_PACK = true;
- cap->stereo_3d_caps.DISPLAYPORT_FRAME_PACK = true;
- cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
- cap->stereo_3d_caps.INTERLEAVE = true;
-
- e_fuse_setting = dm_read_index_reg(cap->ctx,CGS_IND_REG__SMC, ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
-
- /* Bits [28:27]*/
- switch ((e_fuse_setting >> 27) & 0x3) {
- case 0:
- /*both VCE engine are working*/
- cap->caps.VCE_SUPPORTED = true;
- cap->caps.WIRELESS_TIMING_ADJUSTMENT = false;
- /*TODO:
- cap->caps.wirelessLowVCEPerformance = false;
- m_AsicCaps.vceInstance0Enabled = true;
- m_AsicCaps.vceInstance1Enabled = true;*/
- cap->caps.NEED_MC_TUNING = true;
- break;
-
- case 1:
- cap->caps.VCE_SUPPORTED = true;
- cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
- /*TODO:
- m_AsicCaps.wirelessLowVCEPerformance = false;
- m_AsicCaps.vceInstance1Enabled = true;*/
- cap->caps.NEED_MC_TUNING = true;
- break;
-
- case 2:
- cap->caps.VCE_SUPPORTED = true;
- cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
- /*TODO:
- m_AsicCaps.wirelessLowVCEPerformance = false;
- m_AsicCaps.vceInstance0Enabled = true;*/
- cap->caps.NEED_MC_TUNING = true;
- break;
-
- case 3:
- /* VCE_DISABLE = 0x3 - both VCE
- * instances are in harvesting,
- * no VCE supported any more.
- */
- cap->caps.VCE_SUPPORTED = false;
- break;
-
- default:
- break;
- }
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.h b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.h
deleted file mode 100644
index c8aebe1541c4..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_POLARIS10_ASIC_CAPABILITY_H__
-#define __DAL_POLARIS10_ASIC_CAPABILITY_H__
-
-/* Forward declaration */
-struct asic_capability;
-
-/* Create and initialize Polaris10 data */
-void polaris10_asic_capability_create(struct asic_capability *cap,
- struct hw_asic_id *init);
-
-#endif /* __DAL_POLARIS10_ASIC_CAPABILITY_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
deleted file mode 100644
index 6c819ab8fd6e..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/asic_capability_interface.h"
-#include "include/asic_capability_types.h"
-
-#include "tonga_asic_capability.h"
-
-#include "atom.h"
-#include "dce/dce_10_0_d.h"
-#include "dce/dce_10_0_sh_mask.h"
-#include "dal_asic_id.h"
-
-#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
-
-/*
- * carrizo_asic_capability_create
- *
- * Create and initiate Carrizo capability.
- */
-void tonga_asic_capability_create(struct asic_capability *cap,
- struct hw_asic_id *init)
-{
- uint32_t e_fuse_setting;
- /* ASIC data */
- cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
- cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
- cap->data[ASIC_DATA_MC_LATENCY] = 5000;
- cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
- cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
- cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
-
- cap->data[ASIC_DATA_DCE_VERSION] = 0x100; /* DCE 11 */
-
- cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
-
- /* ASIC basic capability */
- cap->caps.IS_FUSION = true;
- cap->caps.DP_MST_SUPPORTED = true;
- cap->caps.PANEL_SELF_REFRESH_SUPPORTED = true;
- cap->caps.MIRABILIS_SUPPORTED = true;
- cap->caps.VCE_SUPPORTED = true;
- cap->caps.HPD_CHECK_FOR_EDID = true;
- cap->caps.DFSBYPASS_DYNAMIC_SUPPORT = true;
- cap->caps.SUPPORT_8BPP = false;
-
- /* ASIC stereo 3d capability */
- cap->stereo_3d_caps.DISPLAY_BASED_ON_WS = true;
- cap->stereo_3d_caps.HDMI_FRAME_PACK = true;
- cap->stereo_3d_caps.INTERLACE_FRAME_PACK = true;
- cap->stereo_3d_caps.DISPLAYPORT_FRAME_PACK = true;
- cap->stereo_3d_caps.DISPLAYPORT_FRAME_ALT = true;
- cap->stereo_3d_caps.INTERLEAVE = true;
-
- e_fuse_setting = dm_read_index_reg(cap->ctx, CGS_IND_REG__SMC,
- ixVCE_HARVEST_FUSE_MACRO__ADDRESS);
-
- /* Bits [28:27]*/
- switch ((e_fuse_setting >> 27) & 0x3) {
- case 0:
- /* both VCE engine are working*/
- cap->caps.VCE_SUPPORTED = true;
- cap->caps.WIRELESS_TIMING_ADJUSTMENT = false;
- /*
- * TODO:
- * cap->caps.wirelessLowVCEPerformance = false;
- * m_AsicCaps.vceInstance0Enabled = true;
- * m_AsicCaps.vceInstance1Enabled = true;
- */
- cap->caps.NEED_MC_TUNING = true;
- break;
-
- case 1:
- cap->caps.VCE_SUPPORTED = true;
- cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
- /*
- * TODO:
- * m_AsicCaps.wirelessLowVCEPerformance = false;
- * m_AsicCaps.vceInstance1Enabled = true;
- */
- cap->caps.NEED_MC_TUNING = true;
- break;
-
- case 2:
- cap->caps.VCE_SUPPORTED = true;
- cap->caps.WIRELESS_TIMING_ADJUSTMENT = true;
- /*
- * TODO:
- * m_AsicCaps.wirelessLowVCEPerformance = false;
- * m_AsicCaps.vceInstance0Enabled = true;
- */
- cap->caps.NEED_MC_TUNING = true;
- break;
-
- case 3:
- /*
- * VCE_DISABLE = 0x3 - both VCE
- * instances are in harvesting,
- * no VCE supported any more.
- */
- cap->caps.VCE_SUPPORTED = false;
- break;
-
- default:
- break;
- }
-
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
deleted file mode 100644
index ca6d68368386..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * tonga_asic_capability.h
- *
- * Created on: 2016-01-18
- * Author: qyang
- */
-
-#ifndef TONGA_ASIC_CAPABILITY_H_
-#define TONGA_ASIC_CAPABILITY_H_
-
-/* Forward declaration */
-struct asic_capability;
-
-/* Create and initialize Carrizo data */
-void tonga_asic_capability_create(struct asic_capability *cap,
- struct hw_asic_id *init);
-
-#endif /* TONGA_ASIC_CAPABILITY_H_ */
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
index 1d3ee3f10f3e..7fdce9b62f1d 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
@@ -42,8 +42,6 @@
#include "bios_parser_types_internal.h"
#include "bios_parser_interface.h"
-/* TODO remove - only needed for gpio_service */
-#include "adapter/adapter_service.h"
/* TODO remove - only needed for default i2c speed */
#include "dc.h"
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index a3c9cb3e1249..e58b27fc3322 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -157,37 +157,6 @@ failed_alloc:
return false;
}
-
-
-static struct adapter_service *create_as(
- const struct dc_init_data *init,
- struct dc_context *dc_ctx)
-{
- struct adapter_service *as = NULL;
- struct as_init_data init_data;
-
- memset(&init_data, 0, sizeof(init_data));
-
- init_data.ctx = dc_ctx;
-
- /* HW init data */
- init_data.hw_init_data.chip_id = init->asic_id.chip_id;
- init_data.hw_init_data.chip_family = init->asic_id.chip_family;
- init_data.hw_init_data.pci_revision_id = init->asic_id.pci_revision_id;
- init_data.hw_init_data.fake_paths_num = init->asic_id.fake_paths_num;
- init_data.hw_init_data.feature_flags = init->asic_id.feature_flags;
- init_data.hw_init_data.hw_internal_rev = init->asic_id.hw_internal_rev;
- init_data.hw_init_data.vram_width = init->asic_id.vram_width;
- init_data.hw_init_data.vram_type = init->asic_id.vram_type;
-
- init_data.vbios_override = init->vbios_override;
- init_data.dce_environment = init->dce_environment;
-
- as = dal_adapter_service_create(&init_data);
-
- return as;
-}
-
static bool stream_adjust_vmin_vmax(struct dc *dc,
const struct dc_stream **stream, int num_streams,
int vmin, int vmax)
@@ -488,9 +457,6 @@ static void destruct(struct core_dc *dc)
if (dc->ctx->gpio_service)
dal_gpio_service_destroy(&dc->ctx->gpio_service);
- if (dc->ctx->adapter_srv)
- dal_adapter_service_destroy(&dc->ctx->adapter_srv);
-
if (dc->ctx->i2caux)
dal_i2caux_destroy(&dc->ctx->i2caux);
@@ -510,7 +476,6 @@ static bool construct(struct core_dc *dc,
const struct dc_init_data *init_params)
{
struct dal_logger *logger;
- struct adapter_service *as = NULL;
struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
@@ -577,18 +542,6 @@ static bool construct(struct core_dc *dc,
goto failed_to_create_i2caux;
}
- /* TODO: Refactor DCE code to remove AS and asic caps */
- if (dc_version < DCE_VERSION_MAX) {
- /* Create adapter service */
- as = create_as(init_params, dc_ctx);
-
- if (!as) {
- dm_error("%s: create_as() failed!\n", __func__);
- goto as_fail;
- }
- dc_ctx->adapter_srv = as;
- }
-
/* Create GPIO service */
dc_ctx->gpio_service = dal_gpio_service_create(
dc_version,
@@ -619,7 +572,6 @@ static bool construct(struct core_dc *dc,
create_links_fail:
create_resource_fail:
gpio_fail:
-as_fail:
failed_to_create_i2caux:
bios_fail:
logger_fail:
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index c0b5c2c5b8e0..620ef03651f1 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -39,13 +39,8 @@
#include "hw_sequencer.h"
#include "resource.h"
#include "fixed31_32.h"
-#include "adapter/adapter_service.h"
#include "include/asic_capability_interface.h"
-
-/* TODO remove - only needed for gpio_service */
-#include "adapter/adapter_service.h"
-
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_enum.h"
#include "dce/dce_11_0_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
index 6be8e08e3d99..7f6d5ec27058 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
@@ -35,9 +35,6 @@
#include "core_types.h"
#include "dc_link_ddc.h"
-/* TODO remove - only needed for gpio_service */
-#include "adapter/adapter_service.h"
-
#define AUX_POWER_UP_WA_DELAY 500
#define I2C_OVER_AUX_DEFER_WA_DELAY 70
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_types.h b/drivers/gpu/drm/amd/dal/dc/dc_types.h
index fb8d094429bc..ae9fcca121e6 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc_types.h
@@ -92,7 +92,6 @@ struct dc_context {
bool created_bios;
struct gpio_service *gpio_service;
struct i2caux *i2caux;
- struct adapter_service *adapter_srv;
};
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
index b924b3d5bc22..3b3c01a647bc 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
@@ -35,9 +35,6 @@
#include "gpio_service_interface.h"
-/* TODO remove - only needed for gpio_service */
-#include "adapter/adapter_service.h"
-
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
#include "dce/dce_11_0_enum.h"
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 53/76] drm/amd/dal: Update stream_encoder programming sequence
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (51 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 52/76] drm/amd/dal: remove adapter_service and asic_capability Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 54/76] drm/amd/dal: Disable bit depth reduction in set link test pattern Harry Wentland
` (23 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zeyu Fan
From: Zeyu Fan <Zeyu.Fan@amd.com>
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c | 152 +++++++++++----------
.../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h | 102 +++++++++++---
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 3 +-
drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h | 3 +-
drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h | 83 +++++++----
.../amd/dal/dc/virtual/virtual_stream_encoder.c | 3 +-
6 files changed, 223 insertions(+), 123 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
index e0654793e6b7..98925f9278db 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
@@ -71,6 +71,31 @@ static void dce110_update_generic_info_packet(
const struct encoder_info_packet *info_packet)
{
uint32_t regval;
+ /* TODOFPGA Figure out a proper number for max_retries polling for lock
+ * use 50 for now.
+ */
+ uint32_t max_retries = 50;
+
+ if (REG(AFMT_VBI_PACKET_CONTROL1)) {
+ if (packet_index >= 8)
+ ASSERT(0);
+
+ /* poll dig_update_lock is not locked -> asic internal signal
+ * assume otg master lock will unlock it
+ */
+ REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
+ 1, 10, max_retries);
+
+ /* check if HW reading GSP memory */
+ REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
+ 1, 10, max_retries);
+
+ /* HW does is not reading GSP memory not reading too long ->
+ * something wrong. clear GPS memory access and notify?
+ * hw SW is writing to GSP memory
+ */
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
+ }
/* choose which generic packet to use */
{
regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
@@ -105,15 +130,11 @@ static void dce110_update_generic_info_packet(
REG_WRITE(AFMT_GENERIC_7, 0);
}
- /* force double-buffered packet update */
- if (enc110->se_mask->AFMT_GENERIC0_UPDATE &&
- enc110->se_mask->AFMT_GENERIC2_UPDATE) {
+ if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
+ /* force double-buffered packet update */
REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
AFMT_GENERIC0_UPDATE, (packet_index == 0),
AFMT_GENERIC2_UPDATE, (packet_index == 2));
- } else {
- ASSERT(enc110->se_mask->AFMT_GENERIC0_UPDATE);
- ASSERT(enc110->se_mask->AFMT_GENERIC2_UPDATE);
}
}
@@ -160,15 +181,15 @@ static void dce110_update_hdmi_info_packet(
break;
case 2:
REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
- HDMI_GENERIC2_CONT, cont,
- HDMI_GENERIC2_SEND, send,
- HDMI_GENERIC2_LINE, line);
+ HDMI_GENERIC0_CONT, cont,
+ HDMI_GENERIC0_SEND, send,
+ HDMI_GENERIC0_LINE, line);
break;
case 3:
REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
- HDMI_GENERIC3_CONT, cont,
- HDMI_GENERIC3_SEND, send,
- HDMI_GENERIC3_LINE, line);
+ HDMI_GENERIC1_CONT, cont,
+ HDMI_GENERIC1_SEND, send,
+ HDMI_GENERIC1_LINE, line);
break;
default:
/* invalid HW packet index */
@@ -183,10 +204,20 @@ static void dce110_update_hdmi_info_packet(
/* setup stream encoder in dp mode */
static void dce110_stream_encoder_dp_set_stream_attribute(
struct stream_encoder *enc,
- struct dc_crtc_timing *crtc_timing)
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space)
{
+ uint32_t h_active_start;
+ uint32_t v_active_start;
+ uint32_t misc0;
+ uint32_t misc1;
+ uint32_t h_blank;
+ uint32_t h_back_porch;
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
+ /* for bring up, disable dp double TODO */
+ REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
+
/* set pixel encoding */
switch (crtc_timing->pixel_encoding) {
case PIXEL_ENCODING_YCBCR422:
@@ -219,39 +250,46 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
}
+ misc1 = REG_READ(DP_MSA_MISC);
/* set color depth */
switch (crtc_timing->display_color_depth) {
+ case COLOR_DEPTH_666:
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
+ 0);
+ misc0 = 0;
+ break;
case COLOR_DEPTH_888:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_8BPC);
+ misc0 = 1;
break;
case COLOR_DEPTH_101010:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_10BPC);
+
+ misc0 = 2;
break;
case COLOR_DEPTH_121212:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_12BPC);
+ misc0 = 3;
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_6BPC);
+ misc0 = 0;
break;
}
/* set dynamic range and YCbCr range */
- if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) {
+ if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
REG_UPDATE_2(
- DP_PIXEL_FORMAT,
- DP_DYN_RANGE, 0,
- DP_YCBCR_RANGE, 0);
- } else {
- ASSERT(enc110->se_mask->DP_DYN_RANGE);
- ASSERT(enc110->se_mask->DP_YCBCR_RANGE);
- }
-}
+ DP_PIXEL_FORMAT,
+ DP_DYN_RANGE, 0,
+ DP_YCBCR_RANGE, 0);
+}
static void dce110_stream_encoder_set_stream_attribute_helper(
struct dce110_stream_encoder *enc110,
@@ -403,7 +441,7 @@ static void dce110_stream_encoder_set_mst_bandwidth(
/* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
/* is reset to 0 (not pending) */
REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
- enc110->se_mask->DP_MSE_RATE_UPDATE_PENDING,
+ 1,
10, DP_MST_UPDATE_MAX_RETRY);
}
@@ -443,15 +481,15 @@ static void dce110_stream_encoder_update_hdmi_info_packets(
HDMI_AVI_INFO_SEND, 0,
HDMI_AVI_INFO_CONT, 0);
}
- } else {
- ASSERT(enc110->se_mask->HDMI_AVI_INFO_SEND);
- ASSERT(enc110->se_mask->HDMI_AVI_INFO_CONT);
- ASSERT(enc110->se_mask->HDMI_AVI_INFO_LINE);
}
- dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
- dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
- dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
+ if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
+ enc110->se_mask->HDMI_AVI_INFO_SEND) {
+ dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
+ dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
+ dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
+ }
+
}
static void dce110_stream_encoder_stop_hdmi_info_packets(
@@ -470,24 +508,13 @@ static void dce110_stream_encoder_stop_hdmi_info_packets(
/* stop generic packets 2 & 3 on HDMI */
REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
- HDMI_GENERIC2_CONT, 0,
- HDMI_GENERIC2_LINE, 0,
- HDMI_GENERIC2_SEND, 0,
- HDMI_GENERIC3_CONT, 0,
- HDMI_GENERIC3_LINE, 0,
- HDMI_GENERIC3_SEND, 0);
-
- /* stop AVI packet on HDMI */
- if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
- enc110->se_mask->HDMI_AVI_INFO_SEND) {
+ HDMI_GENERIC0_CONT, 0,
+ HDMI_GENERIC0_LINE, 0,
+ HDMI_GENERIC0_SEND, 0,
+ HDMI_GENERIC1_CONT, 0,
+ HDMI_GENERIC1_LINE, 0,
+ HDMI_GENERIC1_SEND, 0);
- REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
- HDMI_AVI_INFO_SEND, 0,
- HDMI_AVI_INFO_CONT, 0);
- } else {
- ASSERT(enc110->se_mask->HDMI_AVI_INFO_SEND);
- ASSERT(enc110->se_mask->HDMI_AVI_INFO_CONT);
- }
}
static void dce110_stream_encoder_update_dp_info_packets(
@@ -500,14 +527,14 @@ static void dce110_stream_encoder_update_dp_info_packets(
if (info_frame->vsc.valid)
dce110_update_generic_info_packet(
enc110,
- 0,
+ 0, /* packetIndex */
&info_frame->vsc);
/* enable/disable transmission of packet(s).
* If enabled, packet transmission begins on the next frame
*/
+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
- REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
/* This bit is the master enable bit.
* When enabling secondary stream engine,
* this master bit must also be set.
@@ -535,16 +562,8 @@ static void dce110_stream_encoder_stop_dp_info_packets(
DP_SEC_AVI_ENABLE, 0,
DP_SEC_MPG_ENABLE, 0,
DP_SEC_STREAM_ENABLE, 0);
- } else {
- ASSERT(enc110->se_mask->DP_SEC_AVI_ENABLE);
- REG_SET_6(DP_SEC_CNTL, 0,
- DP_SEC_GSP0_ENABLE, 0,
- DP_SEC_GSP1_ENABLE, 0,
- DP_SEC_GSP2_ENABLE, 0,
- DP_SEC_GSP3_ENABLE, 0,
- DP_SEC_MPG_ENABLE, 0,
- DP_SEC_STREAM_ENABLE, 0);
}
+
/* this register shared with audio info frame.
* therefore we need to keep master enabled
* if at least one of the fields is not 0 */
@@ -558,7 +577,6 @@ static void dce110_stream_encoder_dp_blank(
struct stream_encoder *enc)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- uint32_t value;
uint32_t retries = 0;
uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
@@ -586,19 +604,9 @@ static void dce110_stream_encoder_dp_blank(
* Poll for DP_VID_STREAM_STATUS == 0
*/
- do {
- value = REG_READ(DP_VID_STREAM_CNTL);
-
- if (!get_reg_field_value(
- value,
- DP_VID_STREAM_CNTL,
- DP_VID_STREAM_STATUS))
- break;
-
- udelay(10);
-
- ++retries;
- } while (retries < max_retries);
+ REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
+ 1,
+ 10, max_retries);
ASSERT(retries <= max_retries);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
index c6bb95888cc0..88ef2a1f2a43 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
@@ -97,7 +97,6 @@
SE_COMMON_REG_LIST_DCE_BASE(id), \
SRI(AFMT_CNTL, DIG, id)
-
#define SE_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -115,12 +114,6 @@
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
- SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC2_CONT, mask_sh),\
- SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC2_SEND, mask_sh),\
- SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC2_LINE, mask_sh),\
- SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC3_CONT, mask_sh),\
- SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC3_SEND, mask_sh),\
- SE_SF(HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC3_LINE, mask_sh),\
SE_SF(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
SE_SF(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
SE_SF(DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
@@ -222,18 +215,31 @@ struct dce_stream_encoder_shift {
uint8_t AFMT_GENERIC_HB1;
uint8_t AFMT_GENERIC_HB2;
uint8_t AFMT_GENERIC_HB3;
+ uint8_t AFMT_GENERIC_LOCK_STATUS;
+ uint8_t AFMT_GENERIC_CONFLICT;
+ uint8_t AFMT_GENERIC_CONFLICT_CLR;
+ uint8_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC0_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC1_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC2_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC3_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC4_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC5_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC6_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC7_FRAME_UPDATE;
uint8_t HDMI_GENERIC0_CONT;
uint8_t HDMI_GENERIC0_SEND;
uint8_t HDMI_GENERIC0_LINE;
uint8_t HDMI_GENERIC1_CONT;
uint8_t HDMI_GENERIC1_SEND;
uint8_t HDMI_GENERIC1_LINE;
- uint8_t HDMI_GENERIC2_CONT;
- uint8_t HDMI_GENERIC2_SEND;
- uint8_t HDMI_GENERIC2_LINE;
- uint8_t HDMI_GENERIC3_CONT;
- uint8_t HDMI_GENERIC3_SEND;
- uint8_t HDMI_GENERIC3_LINE;
uint8_t DP_PIXEL_ENCODING;
uint8_t DP_COMPONENT_DEPTH;
uint8_t DP_DYN_RANGE;
@@ -262,6 +268,10 @@ struct dce_stream_encoder_shift {
uint8_t DP_SEC_GSP1_ENABLE;
uint8_t DP_SEC_GSP2_ENABLE;
uint8_t DP_SEC_GSP3_ENABLE;
+ uint8_t DP_SEC_GSP4_ENABLE;
+ uint8_t DP_SEC_GSP5_ENABLE;
+ uint8_t DP_SEC_GSP6_ENABLE;
+ uint8_t DP_SEC_GSP7_ENABLE;
uint8_t DP_SEC_AVI_ENABLE;
uint8_t DP_SEC_MPG_ENABLE;
uint8_t DP_VID_STREAM_DIS_DEFER;
@@ -307,6 +317,19 @@ struct dce_stream_encoder_shift {
uint8_t AFMT_AUDIO_CLOCK_EN;
uint8_t TMDS_PIXEL_ENCODING;
uint8_t TMDS_COLOR_FORMAT;
+ uint8_t DP_DB_DISABLE;
+ uint8_t DP_MSA_MISC0;
+ uint8_t DP_MSA_HTOTAL;
+ uint8_t DP_MSA_VTOTAL;
+ uint8_t DP_MSA_HSTART;
+ uint8_t DP_MSA_VSTART;
+ uint8_t DP_MSA_HSYNCWIDTH;
+ uint8_t DP_MSA_HSYNCPOLARITY;
+ uint8_t DP_MSA_VSYNCWIDTH;
+ uint8_t DP_MSA_VSYNCPOLARITY;
+ uint8_t DP_MSA_HWIDTH;
+ uint8_t DP_MSA_VHEIGHT;
+ uint8_t HDMI_DB_DISABLE;
};
struct dce_stream_encoder_mask {
@@ -317,18 +340,31 @@ struct dce_stream_encoder_mask {
uint32_t AFMT_GENERIC_HB1;
uint32_t AFMT_GENERIC_HB2;
uint32_t AFMT_GENERIC_HB3;
+ uint32_t AFMT_GENERIC_LOCK_STATUS;
+ uint32_t AFMT_GENERIC_CONFLICT;
+ uint32_t AFMT_GENERIC_CONFLICT_CLR;
+ uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC0_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC1_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC2_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC3_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC4_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC5_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC6_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC7_FRAME_UPDATE;
uint32_t HDMI_GENERIC0_CONT;
uint32_t HDMI_GENERIC0_SEND;
uint32_t HDMI_GENERIC0_LINE;
uint32_t HDMI_GENERIC1_CONT;
uint32_t HDMI_GENERIC1_SEND;
uint32_t HDMI_GENERIC1_LINE;
- uint32_t HDMI_GENERIC2_CONT;
- uint32_t HDMI_GENERIC2_SEND;
- uint32_t HDMI_GENERIC2_LINE;
- uint32_t HDMI_GENERIC3_CONT;
- uint32_t HDMI_GENERIC3_SEND;
- uint32_t HDMI_GENERIC3_LINE;
uint32_t DP_PIXEL_ENCODING;
uint32_t DP_COMPONENT_DEPTH;
uint32_t DP_DYN_RANGE;
@@ -357,6 +393,10 @@ struct dce_stream_encoder_mask {
uint32_t DP_SEC_GSP1_ENABLE;
uint32_t DP_SEC_GSP2_ENABLE;
uint32_t DP_SEC_GSP3_ENABLE;
+ uint32_t DP_SEC_GSP4_ENABLE;
+ uint32_t DP_SEC_GSP5_ENABLE;
+ uint32_t DP_SEC_GSP6_ENABLE;
+ uint32_t DP_SEC_GSP7_ENABLE;
uint32_t DP_SEC_AVI_ENABLE;
uint32_t DP_SEC_MPG_ENABLE;
uint32_t DP_VID_STREAM_DIS_DEFER;
@@ -402,6 +442,19 @@ struct dce_stream_encoder_mask {
uint32_t AFMT_AUDIO_CLOCK_EN;
uint32_t TMDS_PIXEL_ENCODING;
uint32_t TMDS_COLOR_FORMAT;
+ uint32_t DP_DB_DISABLE;
+ uint32_t DP_MSA_MISC0;
+ uint32_t DP_MSA_HTOTAL;
+ uint32_t DP_MSA_VTOTAL;
+ uint32_t DP_MSA_HSTART;
+ uint32_t DP_MSA_VSTART;
+ uint32_t DP_MSA_HSYNCWIDTH;
+ uint32_t DP_MSA_HSYNCPOLARITY;
+ uint32_t DP_MSA_VSYNCWIDTH;
+ uint32_t DP_MSA_VSYNCPOLARITY;
+ uint32_t DP_MSA_HWIDTH;
+ uint32_t DP_MSA_VHEIGHT;
+ uint32_t HDMI_DB_DISABLE;
};
struct dce110_stream_enc_registers {
@@ -421,6 +474,7 @@ struct dce110_stream_enc_registers {
uint32_t AFMT_GENERIC_HDR;
uint32_t AFMT_INFOFRAME_CONTROL0;
uint32_t AFMT_VBI_PACKET_CONTROL;
+ uint32_t AFMT_VBI_PACKET_CONTROL1;
uint32_t AFMT_AUDIO_PACKET_CONTROL;
uint32_t AFMT_AUDIO_PACKET_CONTROL2;
uint32_t AFMT_AUDIO_SRC_CONTROL;
@@ -443,6 +497,8 @@ struct dce110_stream_enc_registers {
uint32_t HDMI_GC;
uint32_t HDMI_GENERIC_PACKET_CONTROL0;
uint32_t HDMI_GENERIC_PACKET_CONTROL1;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL2;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL3;
uint32_t HDMI_INFOFRAME_CONTROL0;
uint32_t HDMI_INFOFRAME_CONTROL1;
uint32_t HDMI_VBI_PACKET_CONTROL;
@@ -455,6 +511,14 @@ struct dce110_stream_enc_registers {
uint32_t HDMI_ACR_48_0;
uint32_t HDMI_ACR_48_1;
uint32_t TMDS_CNTL;
+ uint32_t DP_DB_CNTL;
+ uint32_t DP_MSA_MISC;
+ uint32_t DP_MSA_COLORIMETRY;
+ uint32_t DP_MSA_TIMING_PARAM1;
+ uint32_t DP_MSA_TIMING_PARAM2;
+ uint32_t DP_MSA_TIMING_PARAM3;
+ uint32_t DP_MSA_TIMING_PARAM4;
+ uint32_t HDMI_DB_CONTROL;
};
struct dce110_stream_encoder {
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index a6679a95694e..249438456f73 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -855,7 +855,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(
if (dc_is_dp_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_enc->funcs->dp_set_stream_attribute(
pipe_ctx->stream_enc,
- &stream->public.timing);
+ &stream->public.timing,
+ stream->public.output_color_space);
if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute(
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
index 83c246c558a5..9caf2b365420 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/stream_encoder.h
@@ -55,7 +55,8 @@ struct stream_encoder {
struct stream_encoder_funcs {
void (*dp_set_stream_attribute)(
struct stream_encoder *enc,
- struct dc_crtc_timing *crtc_timing);
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space);
void (*hdmi_set_stream_attribute)(
struct stream_encoder *enc,
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
index ef652abcd276..4c1286dc3bdb 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
@@ -69,38 +69,50 @@
#define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \
REG_SET_N(reg, 3, init_value, \
- FD(reg##__##f1), v1,\
- FD(reg##__##f2), v2,\
- FD(reg##__##f3), v3)
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2,\
+ FN(reg, f3), v3)
#define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \
REG_SET_N(reg, 4, init_value, \
- FD(reg##__##f1), v1,\
- FD(reg##__##f2), v2,\
- FD(reg##__##f3), v3,\
- FD(reg##__##f4), v4)
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2,\
+ FN(reg, f3), v3,\
+ FN(reg, f4), v4)
#define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
f5, v5, f6, v6) \
REG_SET_N(reg, 6, init_value, \
- FD(reg##__##f1), v1,\
- FD(reg##__##f2), v2,\
- FD(reg##__##f3), v3,\
- FD(reg##__##f4), v4,\
- FD(reg##__##f5), v5,\
- FD(reg##__##f6), v6)
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2,\
+ FN(reg, f3), v3,\
+ FN(reg, f4), v4,\
+ FN(reg, f5), v5,\
+ FN(reg, f6), v6)
#define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
f5, v5, f6, v6, f7, v7) \
REG_SET_N(reg, 7, init_value, \
- FD(reg##__##f1), v1,\
- FD(reg##__##f2), v2,\
- FD(reg##__##f3), v3,\
- FD(reg##__##f4), v4,\
- FD(reg##__##f5), v5,\
- FD(reg##__##f6), v6,\
- FD(reg##__##f7), v7)
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2,\
+ FN(reg, f3), v3,\
+ FN(reg, f4), v4,\
+ FN(reg, f5), v5,\
+ FN(reg, f6), v6,\
+ FN(reg, f7), v7)
+#define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \
+ REG_SET_N(reg, 10, init_value, \
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2, \
+ FN(reg, f3), v3, \
+ FN(reg, f4), v4, \
+ FN(reg, f5), v5, \
+ FN(reg, f6), v6, \
+ FN(reg, f7), v7, \
+ FN(reg, f8), v8, \
+ FN(reg, f9), v9, \
+ FN(reg, f10), v10)
/* macro to get register fields
* read given register and fill in field value in output parameter */
@@ -196,15 +208,28 @@
#define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \
REG_UPDATE_N(reg, 9, \
- FN(reg, f1), val1,\
- FN(reg, f2), val2, \
- FN(reg, f3), val3, \
- FN(reg, f4), val4, \
- FN(reg, f5), val5, \
- FN(reg, f6), val6, \
- FN(reg, f7), val7, \
- FN(reg, f8), val8, \
- FN(reg, f9), val9)
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2, \
+ FN(reg, f3), v3, \
+ FN(reg, f4), v4, \
+ FN(reg, f5), v5, \
+ FN(reg, f6), v6, \
+ FN(reg, f7), v7, \
+ FN(reg, f8), v8, \
+ FN(reg, f9), v9)
+
+#define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \
+ REG_UPDATE_N(reg, 10, \
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2, \
+ FN(reg, f3), v3, \
+ FN(reg, f4), v4, \
+ FN(reg, f5), v5, \
+ FN(reg, f6), v6, \
+ FN(reg, f7), v7, \
+ FN(reg, f8), v8, \
+ FN(reg, f9), v9, \
+ FN(reg, f10), v10)
/* macro to update a register field to specified values in given sequences.
* useful when toggling bits
diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
index 30d07efb4ee7..8de21d9a8079 100644
--- a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
@@ -28,7 +28,8 @@
static void virtual_stream_encoder_dp_set_stream_attribute(
struct stream_encoder *enc,
- struct dc_crtc_timing *crtc_timing) {}
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space) {}
static void virtual_stream_encoder_hdmi_set_stream_attribute(
struct stream_encoder *enc,
--
2.10.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 54/76] drm/amd/dal: Disable bit depth reduction in set link test pattern
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (52 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 53/76] drm/amd/dal: Update stream_encoder programming sequence Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 55/76] drm/amd/dal: Handle AUX error during RECIEVE state of transaction Harry Wentland
` (22 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wenjing Liu
From: Wenjing Liu <Wenjing.Liu@amd.com>
[Description]
Driver current only programs timing generator to set the link test pattern.
However for deep color, bit depth reduction is not disabled.
This causes DP compliance reads a wrong CRC
when evaluating the pattern.
Call the general dc_link_dp_set_test_pattern function.
This has already provide a correct sequence for
programming link test pattern
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 53 ++++++++++------------------
1 file changed, 18 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
index b7c4b5899dcd..dd06960e110c 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
@@ -1668,6 +1668,7 @@ static void dp_test_send_link_test_pattern(struct core_link *link)
{
union link_test_pattern dpcd_test_pattern;
union test_misc dpcd_test_params;
+ enum dp_test_pattern test_pattern;
memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
@@ -1684,52 +1685,30 @@ static void dp_test_send_link_test_pattern(struct core_link *link)
&dpcd_test_params.raw,
sizeof(dpcd_test_params));
- /* translate request */
- enum controller_dp_test_pattern test_pattern;
- enum dc_color_depth color_depth;
-
switch (dpcd_test_pattern.bits.PATTERN) {
case LINK_TEST_PATTERN_COLOR_RAMP:
- test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
+ test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
break;
case LINK_TEST_PATTERN_VERTICAL_BARS:
- test_pattern = CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
+ test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
break; /* black and white */
case LINK_TEST_PATTERN_COLOR_SQUARES:
test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
TEST_DYN_RANGE_VESA ?
- CONTROLLER_DP_TEST_PATTERN_COLORSQUARES :
- CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA);
+ DP_TEST_PATTERN_COLOR_SQUARES :
+ DP_TEST_PATTERN_COLOR_SQUARES_CEA);
break;
default:
- test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
- break;
- }
-
- switch (dpcd_test_params.bits.BPC) {
- case TEST_BIT_DEPTH_6:
- color_depth = COLOR_DEPTH_666;
- break;
- case TEST_BIT_DEPTH_8:
- color_depth = COLOR_DEPTH_888;
- break;
- case TEST_BIT_DEPTH_10:
- color_depth = COLOR_DEPTH_101010;
- break;
- case TEST_BIT_DEPTH_12:
- color_depth = COLOR_DEPTH_121212;
- break;
- case TEST_BIT_DEPTH_16:
- color_depth = COLOR_DEPTH_161616;
- break;
- default:
- color_depth = COLOR_DEPTH_UNDEFINED;
+ test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
break;
}
- link->dc->current_context->res_ctx.pipe_ctx->tg->funcs->
- set_test_pattern(link->dc->current_context->res_ctx.
- pipe_ctx->tg, test_pattern, color_depth);
+ dc_link_dp_set_test_pattern(
+ &link->public,
+ test_pattern,
+ NULL,
+ NULL,
+ 0);
}
static void handle_automated_test(struct core_link *link)
@@ -1784,6 +1763,7 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
{
struct core_link *link = DC_LINK_TO_LINK(dc_link);
union hpd_irq_data hpd_irq_dpcd_data = {{{{0}}}};
+ union device_service_irq device_service_clear = {0};
enum dc_status result = DDC_RESULT_UNKNOWN;
bool status = false;
/* For use cases related to down stream connection status change,
@@ -1809,12 +1789,15 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link)
}
if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
+ device_service_clear.bits.AUTOMATED_TEST = 1;
core_link_write_dpcd(
link,
DPCD_ADDRESS_DEVICE_SERVICE_IRQ_VECTOR,
- &hpd_irq_dpcd_data.bytes.device_service_irq.raw,
- sizeof(hpd_irq_dpcd_data.bytes.device_service_irq));
+ &device_service_clear.raw,
+ sizeof(device_service_clear.raw));
+ device_service_clear.raw = 0;
handle_automated_test(link);
+ return false;
}
if (!allow_hpd_rx_irq(link)) {
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 55/76] drm/amd/dal: Handle AUX error during RECIEVE state of transaction
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (53 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 54/76] drm/amd/dal: Disable bit depth reduction in set link test pattern Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 56/76] drm/amd/dal: Remove unnecessary increment in scaler ratio calculation Harry Wentland
` (21 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wenjing Liu
From: Wenjing Liu <Wenjing.Liu@amd.com>
[Description]
DP compliance intermittent failure for aux channel error retry.
During DP compliance test generates AUX channel error,
asic may intermittently set the AUX_SW_DONE bit to 1
but indicates channel error during RECIEVE state.
Driver fails to retry without checking the error bits
The fix will retry upon following errors:
During the RECIEVE state of a SW transaction,
some `H` symbol(s) were detected that were not part of a `STOP` pattern
During the RECIEVE state of a SW transaction,
some `L` symbol(s) were detected that were not part of a `STOP` pattern.
During the RECIEVE state of a SW transaction,
symbol(s) had both correlation counters below the threshold level
of detection set by
AUX_RX_CONTROL.AUX_RX_DETECTION_THRESHOLD.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
index c112bdd5e7ab..f49fd1ad3807 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c
@@ -362,7 +362,11 @@ static enum aux_channel_operation_result get_channel_status(
(value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK))
return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
- else if (value & AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK)
+ else if ((value & AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK) ||
+ (value & AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK) ||
+ (value &
+ AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK) ||
+ (value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK))
return AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
*returned_bytes = get_reg_field_value(value,
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 56/76] drm/amd/dal: Remove unnecessary increment in scaler ratio calculation
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (54 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 55/76] drm/amd/dal: Handle AUX error during RECIEVE state of transaction Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 57/76] drm/amd/dal: Add YCBCR420 to stream encoder Harry Wentland
` (20 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jordan Lazare
From: Jordan Lazare <Jordan.Lazare@amd.com>
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index 4e76d5dbbac0..0578052859e3 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -493,9 +493,6 @@ static void calculate_scaling_ratios(
pipe_ctx->scl_data.ratios.horz.value = div64_s64(
pipe_ctx->scl_data.ratios.horz.value * in_w, out_w);
- pipe_ctx->scl_data.ratios.horz.value++;
- pipe_ctx->scl_data.ratios.vert.value++;
-
pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz;
pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert;
--
2.10.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 57/76] drm/amd/dal: Add YCBCR420 to stream encoder
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (55 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 56/76] drm/amd/dal: Remove unnecessary increment in scaler ratio calculation Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 58/76] drm/amd/dal: Add surface log to dc Harry Wentland
` (19 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zeyu Fan
From: Zeyu Fan <Zeyu.Fan@amd.com>
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c | 37 +++++++++++++++++-----
.../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h | 4 +++
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 4 +--
3 files changed, 35 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
index 98925f9278db..89e09150234e 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
@@ -27,11 +27,29 @@
#include "dm_services.h"
#include "dc_bios_types.h"
#include "dce_stream_encoder.h"
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
-#include "dce/dce_11_0_enum.h"
#include "reg_helper.h"
+enum DP_PIXEL_ENCODING {
+DP_PIXEL_ENCODING_RGB444 = 0x00000000,
+DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
+DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
+DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
+DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
+DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
+DP_PIXEL_ENCODING_RESERVED = 0x00000006,
+};
+
+
+enum DP_COMPONENT_DEPTH {
+DP_COMPONENT_DEPTH_6BPC = 0x00000000,
+DP_COMPONENT_DEPTH_8BPC = 0x00000001,
+DP_COMPONENT_DEPTH_10BPC = 0x00000002,
+DP_COMPONENT_DEPTH_12BPC = 0x00000003,
+DP_COMPONENT_DEPTH_16BPC = 0x00000004,
+DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
+};
+
+
#define REG(reg)\
(enc110->regs->reg)
@@ -221,14 +239,12 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
/* set pixel encoding */
switch (crtc_timing->pixel_encoding) {
case PIXEL_ENCODING_YCBCR422:
-
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_YCBCR422);
-
break;
case PIXEL_ENCODING_YCBCR444:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
- PIXEL_ENCODING_YCBCR444);
+ DP_PIXEL_ENCODING_YCBCR444);
if (crtc_timing->flags.Y_ONLY)
if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
@@ -237,13 +253,18 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
* 8, 10, 12, 16 bits */
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_Y_ONLY);
-
-
/* Note: DP_MSA_MISC1 bit 7 is the indicator
* of Y-only mode.
* This bit is set in HW if register
* DP_PIXEL_ENCODING is programmed to 0x4 */
break;
+ case PIXEL_ENCODING_YCBCR420:
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
+ DP_PIXEL_ENCODING_YCBCR420);
+ if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
+ REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
+
+ break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_RGB444);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
index 88ef2a1f2a43..2778f89e5abf 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
@@ -330,6 +330,8 @@ struct dce_stream_encoder_shift {
uint8_t DP_MSA_HWIDTH;
uint8_t DP_MSA_VHEIGHT;
uint8_t HDMI_DB_DISABLE;
+ uint8_t DP_VID_N_MUL;
+ uint8_t DP_VID_M_DOUBLE_VALUE_EN;
};
struct dce_stream_encoder_mask {
@@ -455,6 +457,8 @@ struct dce_stream_encoder_mask {
uint32_t DP_MSA_HWIDTH;
uint32_t DP_MSA_VHEIGHT;
uint32_t HDMI_DB_DISABLE;
+ uint32_t DP_VID_N_MUL;
+ uint32_t DP_VID_M_DOUBLE_VALUE_EN;
};
struct dce110_stream_enc_registers {
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 578d8fd89d39..9f47bec557ea 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -298,11 +298,11 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = {
};
static const struct dce_stream_encoder_shift se_shift = {
- SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
+ SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
};
static const struct dce_stream_encoder_mask se_mask = {
- SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
+ SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
};
#define audio_regs(id)\
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 58/76] drm/amd/dal: Add surface log to dc
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (56 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 57/76] drm/amd/dal: Add YCBCR420 to stream encoder Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 59/76] drm/amd/dal: add stoney bounding box to bw_calcs Harry Wentland
` (18 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/Makefile | 2 +-
drivers/gpu/drm/amd/dal/dc/basics/logger.c | 6 +-
drivers/gpu/drm/amd/dal/dc/core/dc.c | 6 +
drivers/gpu/drm/amd/dal/dc/core/dc_debug.c | 270 +++++++++++++++++++++
drivers/gpu/drm/amd/dal/dc/dc.h | 3 +
drivers/gpu/drm/amd/dal/include/logger_interface.h | 18 ++
drivers/gpu/drm/amd/dal/include/logger_types.h | 1 +
7 files changed, 303 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_debug.c
diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile
index 834bb1814be5..f9c5db6f6cd1 100644
--- a/drivers/gpu/drm/amd/dal/dc/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/Makefile
@@ -15,7 +15,7 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/dc/,$(DC_LIBS))
include $(AMD_DC)
DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_target.o dc_sink.o dc_stream.o \
-dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o
+dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o
AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
diff --git a/drivers/gpu/drm/amd/dal/dc/basics/logger.c b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
index 3c16fe1d91ff..a5625a3badab 100644
--- a/drivers/gpu/drm/amd/dal/dc/basics/logger.c
+++ b/drivers/gpu/drm/amd/dal/dc/basics/logger.c
@@ -57,7 +57,8 @@ static const struct dc_log_type_info log_type_info_tbl[] = {
{LOG_EVENT_DETECTION, "Detect"},
{LOG_EVENT_LINK_TRAINING, "LKTN"},
{LOG_EVENT_LINK_LOSS, "LinkLoss"},
- {LOG_EVENT_UNDERFLOW, "Underflow"}
+ {LOG_EVENT_UNDERFLOW, "Underflow"},
+ {LOG_IF_TRACE, "InterfaceTrace"}
};
@@ -83,7 +84,8 @@ static const struct dc_log_type_info log_type_info_tbl[] = {
(1 << LOG_DETECTION_EDID_PARSER) | \
(1 << LOG_DETECTION_DP_CAPS) | \
(1 << LOG_BACKLIGHT)) | \
- (1 << LOG_I2C_AUX)/* | \
+ (1 << LOG_I2C_AUX) | \
+ (1 << LOG_IF_TRACE) /* | \
(1 << LOG_SURFACE) | \
(1 << LOG_SCALER) | \
(1 << LOG_DML) | \
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index e58b27fc3322..d928b3f93ab6 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -1119,6 +1119,8 @@ bool dc_pre_update_surfaces_to_target(
struct validate_context *temp_context;
bool ret = true;
+ pre_surface_trace(dc, new_surfaces, new_surface_count);
+
if (core_dc->current_context->target_count == 0)
return false;
@@ -1249,6 +1251,8 @@ bool dc_post_update_surfaces_to_target(struct dc *dc)
struct core_dc *core_dc = DC_TO_CORE(dc);
int i;
+ post_surface_trace(dc);
+
for (i = 0; i < core_dc->current_context->res_ctx.pool->pipe_count; i++)
if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == NULL)
core_dc->hwss.power_down_front_end(
@@ -1320,6 +1324,8 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda
int i, j;
bool is_new_pipe_surface[MAX_SURFACES];
+ update_surface_trace(dc, updates, surface_count);
+
for (j = 0; j < MAX_SURFACES; j++)
is_new_pipe_surface[j] = true;
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_debug.c b/drivers/gpu/drm/amd/dal/dc/core/dc_debug.c
new file mode 100644
index 000000000000..8ca0f1e0369a
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_debug.c
@@ -0,0 +1,270 @@
+/*
+ * dc_debug.c
+ *
+ * Created on: Nov 3, 2016
+ * Author: yonsun
+ */
+
+#include "dm_services.h"
+
+#include "dc.h"
+
+#include "core_status.h"
+#include "core_types.h"
+#include "hw_sequencer.h"
+
+#include "resource.h"
+
+#define SURFACE_TRACE(...) do {\
+ if (dc->debug.surface_trace) \
+ dm_logger_write(logger, \
+ LOG_IF_TRACE, \
+ ##__VA_ARGS__); \
+} while (0)
+
+void pre_surface_trace(
+ const struct dc *dc,
+ const struct dc_surface *const *surfaces,
+ int surface_count)
+{
+ int i;
+ struct core_dc *core_dc = DC_TO_CORE(dc);
+ struct dal_logger *logger = core_dc->ctx->logger;
+
+ for (i = 0; i < surface_count; i++) {
+ const struct dc_surface *surface = surfaces[i];
+
+ SURFACE_TRACE("Surface %d:\n", i);
+
+ SURFACE_TRACE(
+ "surface->visible = %d;\n"
+ "surface->flip_immediate = %d;\n"
+ "surface->address.type = %d;\n"
+ "surface->address.grph.addr.quad_part = 0x%X;\n"
+ "surface->address.grph.meta_addr.quad_part = 0x%X;\n"
+ "surface->scaling_quality.h_taps = %d;\n"
+ "surface->scaling_quality.v_taps = %d;\n"
+ "surface->scaling_quality.h_taps_c = %d;\n"
+ "surface->scaling_quality.v_taps_c = %d;\n",
+ surface->visible,
+ surface->flip_immediate,
+ surface->address.type,
+ surface->address.grph.addr.quad_part,
+ surface->address.grph.meta_addr.quad_part,
+ surface->scaling_quality.h_taps,
+ surface->scaling_quality.v_taps,
+ surface->scaling_quality.h_taps_c,
+ surface->scaling_quality.v_taps_c);
+
+ SURFACE_TRACE(
+ "surface->src_rect.x = %d;\n"
+ "surface->src_rect.y = %d;\n"
+ "surface->src_rect.width = %d;\n"
+ "surface->src_rect.height = %d;\n"
+ "surface->dst_rect.x = %d;\n"
+ "surface->dst_rect.y = %d;\n"
+ "surface->dst_rect.width = %d;\n"
+ "surface->dst_rect.height = %d;\n"
+ "surface->clip_rect.x = %d;\n"
+ "surface->clip_rect.y = %d;\n"
+ "surface->clip_rect.width = %d;\n"
+ "surface->clip_rect.height = %d;\n",
+ surface->src_rect.x,
+ surface->src_rect.y,
+ surface->src_rect.width,
+ surface->src_rect.height,
+ surface->dst_rect.x,
+ surface->dst_rect.y,
+ surface->dst_rect.width,
+ surface->dst_rect.height,
+ surface->clip_rect.x,
+ surface->clip_rect.y,
+ surface->clip_rect.width,
+ surface->clip_rect.height);
+
+ SURFACE_TRACE(
+ "surface->plane_size.grph.surface_size.x = %d;\n"
+ "surface->plane_size.grph.surface_size.y = %d;\n"
+ "surface->plane_size.grph.surface_size.width = %d;\n"
+ "surface->plane_size.grph.surface_size.height = %d;\n"
+ "surface->plane_size.grph.surface_pitch = %d;\n"
+ "surface->plane_size.grph.meta_pitch = %d;\n",
+ surface->plane_size.grph.surface_size.x,
+ surface->plane_size.grph.surface_size.y,
+ surface->plane_size.grph.surface_size.width,
+ surface->plane_size.grph.surface_size.height,
+ surface->plane_size.grph.surface_pitch,
+ surface->plane_size.grph.meta_pitch);
+
+
+ SURFACE_TRACE(
+ "surface->tiling_info.gfx8.num_banks = %d;\n"
+ "surface->tiling_info.gfx8.bank_width = %d;\n"
+ "surface->tiling_info.gfx8.bank_width_c = %d;\n"
+ "surface->tiling_info.gfx8.bank_height = %d;\n"
+ "surface->tiling_info.gfx8.bank_height_c = %d;\n"
+ "surface->tiling_info.gfx8.tile_aspect = %d;\n"
+ "surface->tiling_info.gfx8.tile_aspect_c = %d;\n"
+ "surface->tiling_info.gfx8.tile_split = %d;\n"
+ "surface->tiling_info.gfx8.tile_split_c = %d;\n"
+ "surface->tiling_info.gfx8.tile_mode = %d;\n"
+ "surface->tiling_info.gfx8.tile_mode_c = %d;\n",
+ surface->tiling_info.gfx8.num_banks,
+ surface->tiling_info.gfx8.bank_width,
+ surface->tiling_info.gfx8.bank_width_c,
+ surface->tiling_info.gfx8.bank_height,
+ surface->tiling_info.gfx8.bank_height_c,
+ surface->tiling_info.gfx8.tile_aspect,
+ surface->tiling_info.gfx8.tile_aspect_c,
+ surface->tiling_info.gfx8.tile_split,
+ surface->tiling_info.gfx8.tile_split_c,
+ surface->tiling_info.gfx8.tile_mode,
+ surface->tiling_info.gfx8.tile_mode_c);
+
+ SURFACE_TRACE(
+ "surface->tiling_info.gfx8.pipe_config = %d;\n"
+ "surface->tiling_info.gfx8.array_mode = %d;\n"
+ "surface->color_space = %d;\n"
+ "surface->dcc.enable = %d;\n"
+ "surface->format = %d;\n"
+ "surface->rotation = %d;\n"
+ "surface->stereo_format = %d;\n",
+ surface->tiling_info.gfx8.pipe_config,
+ surface->tiling_info.gfx8.array_mode,
+ surface->color_space,
+ surface->dcc.enable,
+ surface->format,
+ surface->rotation,
+ surface->stereo_format);
+ SURFACE_TRACE("\n");
+ }
+ SURFACE_TRACE("\n");
+}
+
+void update_surface_trace(
+ const struct dc *dc,
+ const struct dc_surface_update *updates,
+ int surface_count)
+{
+ int i;
+ struct core_dc *core_dc = DC_TO_CORE(dc);
+ struct dal_logger *logger = core_dc->ctx->logger;
+
+ for (i = 0; i < surface_count; i++) {
+ const struct dc_surface_update *update = &updates[i];
+
+ SURFACE_TRACE("Update %d\n", i);
+ if (update->flip_addr) {
+ SURFACE_TRACE("flip_addr->address.type = %d;\n"
+ "flip_addr->address.grph.addr.quad_part = 0x%X;\n"
+ "flip_addr->address.grph.meta_addr.quad_part = 0x%X;\n"
+ "flip_addr->flip_immediate = %d;\n",
+ update->flip_addr->address.type,
+ update->flip_addr->address.grph.addr.quad_part,
+ update->flip_addr->address.grph.meta_addr.quad_part,
+ update->flip_addr->flip_immediate);
+ }
+
+ if (update->plane_info) {
+ SURFACE_TRACE(
+ "plane_info->color_space = %d;\n"
+ "plane_info->format = %d;\n"
+ "plane_info->plane_size.grph.meta_pitch = %d;\n"
+ "plane_info->plane_size.grph.surface_pitch = %d;\n"
+ "plane_info->plane_size.grph.surface_size.height = %d;\n"
+ "plane_info->plane_size.grph.surface_size.width = %d;\n"
+ "plane_info->plane_size.grph.surface_size.x = %d;\n"
+ "plane_info->plane_size.grph.surface_size.y = %d;\n"
+ "plane_info->rotation = %d;\n",
+ update->plane_info->color_space,
+ update->plane_info->format,
+ update->plane_info->plane_size.grph.meta_pitch,
+ update->plane_info->plane_size.grph.surface_pitch,
+ update->plane_info->plane_size.grph.surface_size.height,
+ update->plane_info->plane_size.grph.surface_size.width,
+ update->plane_info->plane_size.grph.surface_size.x,
+ update->plane_info->plane_size.grph.surface_size.y,
+ update->plane_info->rotation,
+ update->plane_info->stereo_format);
+
+ SURFACE_TRACE(
+ "plane_info->tiling_info.gfx8.num_banks = %d;\n"
+ "plane_info->tiling_info.gfx8.bank_width = %d;\n"
+ "plane_info->tiling_info.gfx8.bank_width_c = %d;\n"
+ "plane_info->tiling_info.gfx8.bank_height = %d;\n"
+ "plane_info->tiling_info.gfx8.bank_height_c = %d;\n"
+ "plane_info->tiling_info.gfx8.tile_aspect = %d;\n"
+ "plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n"
+ "plane_info->tiling_info.gfx8.tile_split = %d;\n"
+ "plane_info->tiling_info.gfx8.tile_split_c = %d;\n"
+ "plane_info->tiling_info.gfx8.tile_mode = %d;\n"
+ "plane_info->tiling_info.gfx8.tile_mode_c = %d;\n",
+ update->plane_info->tiling_info.gfx8.num_banks,
+ update->plane_info->tiling_info.gfx8.bank_width,
+ update->plane_info->tiling_info.gfx8.bank_width_c,
+ update->plane_info->tiling_info.gfx8.bank_height,
+ update->plane_info->tiling_info.gfx8.bank_height_c,
+ update->plane_info->tiling_info.gfx8.tile_aspect,
+ update->plane_info->tiling_info.gfx8.tile_aspect_c,
+ update->plane_info->tiling_info.gfx8.tile_split,
+ update->plane_info->tiling_info.gfx8.tile_split_c,
+ update->plane_info->tiling_info.gfx8.tile_mode,
+ update->plane_info->tiling_info.gfx8.tile_mode_c);
+
+ SURFACE_TRACE(
+ "plane_info->tiling_info.gfx8.pipe_config = %d;\n"
+ "plane_info->tiling_info.gfx8.array_mode = %d;\n"
+ "plane_info->visible = %d;\n",
+ update->plane_info->tiling_info.gfx8.pipe_config,
+ update->plane_info->tiling_info.gfx8.array_mode,
+ update->plane_info->visible);
+ }
+
+ if (update->scaling_info) {
+ SURFACE_TRACE(
+ "scaling_info->src_rect.x = %d;\n"
+ "scaling_info->src_rect.y = %d;\n"
+ "scaling_info->src_rect.width = %d;\n"
+ "scaling_info->src_rect.height = %d;\n"
+ "scaling_info->dst_rect.x = %d;\n"
+ "scaling_info->dst_rect.y = %d;\n"
+ "scaling_info->dst_rect.width = %d;\n"
+ "scaling_info->dst_rect.height = %d;\n"
+ "scaling_info->clip_rect.x = %d;\n"
+ "scaling_info->clip_rect.y = %d;\n"
+ "scaling_info->clip_rect.width = %d;\n"
+ "scaling_info->clip_rect.height = %d;\n"
+ "scaling_info->scaling_quality.h_taps = %d;\n"
+ "scaling_info->scaling_quality.v_taps = %d;\n"
+ "scaling_info->scaling_quality.h_taps_c = %d;\n"
+ "scaling_info->scaling_quality.v_taps_c = %d;\n",
+ update->scaling_info->src_rect.x,
+ update->scaling_info->src_rect.y,
+ update->scaling_info->src_rect.width,
+ update->scaling_info->src_rect.height,
+ update->scaling_info->dst_rect.x,
+ update->scaling_info->dst_rect.y,
+ update->scaling_info->dst_rect.width,
+ update->scaling_info->dst_rect.height,
+ update->scaling_info->clip_rect.x,
+ update->scaling_info->clip_rect.y,
+ update->scaling_info->clip_rect.width,
+ update->scaling_info->clip_rect.height,
+ update->scaling_info->scaling_quality.h_taps,
+ update->scaling_info->scaling_quality.v_taps,
+ update->scaling_info->scaling_quality.h_taps_c,
+ update->scaling_info->scaling_quality.v_taps_c);
+ }
+ SURFACE_TRACE("\n");
+ }
+ SURFACE_TRACE("\n");
+}
+
+void post_surface_trace(const struct dc *dc)
+{
+ struct core_dc *core_dc = DC_TO_CORE(dc);
+ struct dal_logger *logger = core_dc->ctx->logger;
+
+ SURFACE_TRACE("post surface process.\n");
+
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
index d73ae63b4ec9..26624e2661fa 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
@@ -141,6 +141,9 @@ struct dc_debug {
bool disable_dcc;
bool disable_dfs_bypass;
bool max_disp_clk;
+ bool target_trace;
+ bool surface_trace;
+ bool validation_trace;
};
struct dc {
diff --git a/drivers/gpu/drm/amd/dal/include/logger_interface.h b/drivers/gpu/drm/amd/dal/include/logger_interface.h
index 859215630914..b58d30de8293 100644
--- a/drivers/gpu/drm/amd/dal/include/logger_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/logger_interface.h
@@ -30,6 +30,7 @@
struct dc_context;
struct dc_link;
+struct dc_surface_update;
/*
*
@@ -67,6 +68,23 @@ void dc_conn_log(struct dc_context *ctx,
const char *msg,
...);
+void logger_write(struct dal_logger *logger,
+ enum dc_log_type log_type,
+ const char *msg,
+ void *paralist);
+
+void pre_surface_trace(
+ const struct dc *dc,
+ const struct dc_surface *const *surfaces,
+ int surface_count);
+
+void update_surface_trace(
+ const struct dc *dc,
+ const struct dc_surface_update *updates,
+ int surface_count);
+
+void post_surface_trace(const struct dc *dc);
+
/* Any function which is empty or have incomplete implementation should be
* marked by this macro.
diff --git a/drivers/gpu/drm/amd/dal/include/logger_types.h b/drivers/gpu/drm/amd/dal/include/logger_types.h
index 1ea60bb9e716..babd6523b105 100644
--- a/drivers/gpu/drm/amd/dal/include/logger_types.h
+++ b/drivers/gpu/drm/amd/dal/include/logger_types.h
@@ -61,6 +61,7 @@ enum dc_log_type {
LOG_EVENT_LINK_TRAINING,
LOG_EVENT_LINK_LOSS,
LOG_EVENT_UNDERFLOW,
+ LOG_IF_TRACE,
LOG_SECTION_TOTAL_COUNT
};
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 59/76] drm/amd/dal: add stoney bounding box to bw_calcs
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (57 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 58/76] drm/amd/dal: Add surface log to dc Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 60/76] drm/amd/dal: Implement DCHUB interface Harry Wentland
` (17 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 110 +++++++++++++++++++++
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 5 +-
drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h | 1 +
3 files changed, 115 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
index 8e669971b321..5247543dc6c1 100644
--- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
@@ -2294,6 +2294,116 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
break;
+ case BW_CALCS_VERSION_STONEY:
+ vbios.memory_type = bw_def_gddr5;
+ vbios.dram_channel_width_in_bits = 64;
+ vbios.number_of_dram_channels = 1;
+ vbios.number_of_dram_banks = 8;
+ vbios.high_yclk = bw_int_to_fixed(1866);
+ vbios.mid_yclk = bw_int_to_fixed(1866);
+ vbios.low_yclk = bw_int_to_fixed(1333);
+ vbios.low_sclk = bw_int_to_fixed(200);
+ vbios.mid1_sclk = bw_int_to_fixed(600);
+ vbios.mid2_sclk = bw_int_to_fixed(600);
+ vbios.mid3_sclk = bw_int_to_fixed(600);
+ vbios.mid4_sclk = bw_int_to_fixed(600);
+ vbios.mid5_sclk = bw_int_to_fixed(600);
+ vbios.mid6_sclk = bw_int_to_fixed(600);
+ vbios.high_sclk = bw_int_to_fixed(800);
+ vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
+ vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
+ vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
+ vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
+ vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
+ vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
+ vbios.data_return_bus_width = bw_int_to_fixed(32);
+ vbios.trc = bw_int_to_fixed(50);
+ vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
+ vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(158, 10);
+ vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
+ vbios.nbp_state_change_latency = bw_frc_to_fixed(208, 10);
+ vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
+ vbios.scatter_gather_enable = true;
+ vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
+ vbios.cursor_width = 32;
+ vbios.average_compression_rate = 4;
+ vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
+ vbios.blackout_duration = bw_int_to_fixed(18); /* us */
+ vbios.maximum_blackout_recovery_time = bw_int_to_fixed(20);
+
+ dceip.large_cursor = false;
+ dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
+ dceip.dmif_pipe_en_fbc_chunk_tracker = false;
+ dceip.cursor_max_outstanding_group_num = 1;
+ dceip.lines_interleaved_into_lb = 2;
+ dceip.chunk_width = 256;
+ dceip.number_of_graphics_pipes = 2;
+ dceip.number_of_underlay_pipes = 1;
+ dceip.low_power_tiling_mode = 0;
+ dceip.display_write_back_supported = false;
+ dceip.argb_compression_support = false;
+ dceip.underlay_vscaler_efficiency6_bit_per_component =
+ bw_frc_to_fixed(35556, 10000);
+ dceip.underlay_vscaler_efficiency8_bit_per_component =
+ bw_frc_to_fixed(34286, 10000);
+ dceip.underlay_vscaler_efficiency10_bit_per_component =
+ bw_frc_to_fixed(32, 10);
+ dceip.underlay_vscaler_efficiency12_bit_per_component =
+ bw_int_to_fixed(3);
+ dceip.graphics_vscaler_efficiency6_bit_per_component =
+ bw_frc_to_fixed(35, 10);
+ dceip.graphics_vscaler_efficiency8_bit_per_component =
+ bw_frc_to_fixed(34286, 10000);
+ dceip.graphics_vscaler_efficiency10_bit_per_component =
+ bw_frc_to_fixed(32, 10);
+ dceip.graphics_vscaler_efficiency12_bit_per_component =
+ bw_int_to_fixed(3);
+ dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
+ dceip.max_dmif_buffer_allocated = 2;
+ dceip.graphics_dmif_size = 12288;
+ dceip.underlay_luma_dmif_size = 19456;
+ dceip.underlay_chroma_dmif_size = 23552;
+ dceip.pre_downscaler_enabled = true;
+ dceip.underlay_downscale_prefetch_enabled = true;
+ dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
+ dceip.lb_size_per_component444 = bw_int_to_fixed(82176);
+ dceip.graphics_lb_nodownscaling_multi_line_prefetching = false;
+ dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
+ bw_int_to_fixed(0);
+ dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
+ 82176);
+ dceip.underlay420_chroma_lb_size_per_component =
+ bw_int_to_fixed(164352);
+ dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
+ 82176);
+ dceip.cursor_chunk_width = bw_int_to_fixed(64);
+ dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
+ dceip.underlay_maximum_width_efficient_for_tiling =
+ bw_int_to_fixed(1920);
+ dceip.underlay_maximum_height_efficient_for_tiling =
+ bw_int_to_fixed(1080);
+ dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
+ bw_frc_to_fixed(3, 10);
+ dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
+ bw_int_to_fixed(25);
+ dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
+ 2);
+ dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
+ bw_int_to_fixed(128);
+ dceip.limit_excessive_outstanding_dmif_requests = true;
+ dceip.linear_mode_line_request_alternation_slice =
+ bw_int_to_fixed(64);
+ dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
+ 32;
+ dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
+ dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
+ dceip.request_efficiency = bw_frc_to_fixed(8, 10);
+ dceip.dispclk_per_request = bw_int_to_fixed(2);
+ dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
+ dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
+ dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
+ dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
+ break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 8a840d3b86d7..cac8a19f28ed 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -1325,7 +1325,10 @@ static bool construct(
if (!dce110_hw_sequencer_construct(dc))
goto res_create_fail;
- bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_CARRIZO);
+ if (ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev))
+ bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_STONEY);
+ else
+ bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_CARRIZO);
bw_calcs_data_update_from_pplib(dc);
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
index 6fb38c718d2d..f9b871b6199b 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h
@@ -39,6 +39,7 @@ enum bw_calcs_version {
BW_CALCS_VERSION_CARRIZO,
BW_CALCS_VERSION_POLARIS10,
BW_CALCS_VERSION_POLARIS11,
+ BW_CALCS_VERSION_STONEY,
};
/*******************************************************************************
--
2.10.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 60/76] drm/amd/dal: Implement DCHUB interface
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (58 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 59/76] drm/amd/dal: add stoney bounding box to bw_calcs Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 61/76] drm/amd/dal: fix initial bw_calc parameters Harry Wentland
` (16 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zeyu Fan
From: Zeyu Fan <Zeyu.Fan@amd.com>
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 26 ++++++++++++++++++++++
drivers/gpu/drm/amd/dal/dc/dc.h | 19 ++++++++++++++++
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 3 ++-
drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c | 3 ++-
drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h | 3 +++
5 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index d928b3f93ab6..0c814cf886c3 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -1802,3 +1802,29 @@ const struct dc_stream_status *dc_stream_get_status(
return &stream->status;
}
+
+bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
+{
+ int i;
+ int status_check = false;
+ struct core_dc *core_dc = DC_TO_CORE(dc);
+ struct mem_input *mi;
+
+ for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
+ if (core_dc->res_pool->mis[i] != NULL) {
+ mi = core_dc->res_pool->mis[i];
+ break;
+ }
+ }
+
+
+ if (mi->funcs->mem_input_update_dchub)
+ mi->funcs->mem_input_update_dchub(mi, dh_data);
+ else
+ ASSERT(mi->funcs->mem_input_update_dchub);
+
+
+ return true;
+
+}
+
diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
index 26624e2661fa..4c969eb26e85 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
@@ -155,6 +155,21 @@ struct dc {
struct dc_debug debug;
};
+enum frame_buffer_mode {
+ FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
+ FRAME_BUFFER_MODE_ZFB_ONLY,
+ FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
+} ;
+
+struct dchub_init_data {
+ bool dchub_initialzied;
+ bool dchub_info_valid;
+ int64_t zfb_phys_addr_base;
+ int64_t zfb_mc_base_addr;
+ uint64_t zfb_size_in_byte;
+ enum frame_buffer_mode fb_mode;
+};
+
struct dc_init_data {
struct hw_asic_id asic_id;
void *driver; /* ctx */
@@ -172,8 +187,11 @@ struct dc_init_data {
};
struct dc *dc_create(const struct dc_init_data *init_params);
+
void dc_destroy(struct dc **dc);
+bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data);
+
/*******************************************************************************
* Surface Interfaces
******************************************************************************/
@@ -346,6 +364,7 @@ bool dc_post_update_surfaces_to_target(
void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *updates,
int surface_count, struct dc_target *dc_target);
+
/*******************************************************************************
* Target Interfaces
******************************************************************************/
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
index 0b778c984e9a..834a73222926 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
@@ -983,7 +983,8 @@ static struct mem_input_funcs dce110_mem_input_funcs = {
.mem_input_program_surface_config =
dce110_mem_input_program_surface_config,
.mem_input_is_flip_pending =
- dce110_mem_input_is_flip_pending
+ dce110_mem_input_is_flip_pending,
+ .mem_input_update_dchub = NULL
};
/*****************************************/
/* Constructor, Destructor */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
index 078a608dc737..7cc3ae89b7ee 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
@@ -175,7 +175,8 @@ static struct mem_input_funcs dce80_mem_input_funcs = {
.mem_input_program_surface_config =
dce110_mem_input_program_surface_config,
.mem_input_is_flip_pending =
- dce110_mem_input_is_flip_pending
+ dce110_mem_input_is_flip_pending,
+ .mem_input_update_dchub = NULL
};
/*****************************************/
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
index c4a78eefd362..a4e91cc719d6 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
@@ -91,6 +91,9 @@ struct mem_input_funcs {
bool horizontal_mirror);
bool (*mem_input_is_flip_pending)(struct mem_input *mem_input);
+
+ void (*mem_input_update_dchub)(struct mem_input *mem_input,
+ struct dchub_init_data *dh_data);
};
#endif
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 61/76] drm/amd/dal: fix initial bw_calc parameters
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (59 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 60/76] drm/amd/dal: Implement DCHUB interface Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 62/76] drm/amd/dal: Don't read I2C_DATA register when in write mode Harry Wentland
` (15 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
index 5247543dc6c1..0dbe47db3740 100644
--- a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
@@ -2121,7 +2121,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
dceip.number_of_underlay_pipes = 0;
dceip.low_power_tiling_mode = 0;
dceip.display_write_back_supported = false;
- dceip.argb_compression_support = false;
+ dceip.argb_compression_support = true;
dceip.underlay_vscaler_efficiency6_bit_per_component =
bw_frc_to_fixed(35556, 10000);
dceip.underlay_vscaler_efficiency8_bit_per_component =
@@ -2231,7 +2231,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
dceip.number_of_underlay_pipes = 0;
dceip.low_power_tiling_mode = 0;
dceip.display_write_back_supported = false;
- dceip.argb_compression_support = false;
+ dceip.argb_compression_support = true;
dceip.underlay_vscaler_efficiency6_bit_per_component =
bw_frc_to_fixed(35556, 10000);
dceip.underlay_vscaler_efficiency8_bit_per_component =
@@ -2321,7 +2321,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(158, 10);
vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
- vbios.nbp_state_change_latency = bw_frc_to_fixed(208, 10);
+ vbios.nbp_state_change_latency = bw_frc_to_fixed(2008, 100);
vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
vbios.scatter_gather_enable = true;
vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
@@ -2341,7 +2341,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
dceip.number_of_underlay_pipes = 1;
dceip.low_power_tiling_mode = 0;
dceip.display_write_back_supported = false;
- dceip.argb_compression_support = false;
+ dceip.argb_compression_support = true;
dceip.underlay_vscaler_efficiency6_bit_per_component =
bw_frc_to_fixed(35556, 10000);
dceip.underlay_vscaler_efficiency8_bit_per_component =
--
2.10.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 62/76] drm/amd/dal: Don't read I2C_DATA register when in write mode
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (60 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 61/76] drm/amd/dal: fix initial bw_calc parameters Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 63/76] drm/amd/dal: disable break_to_debugger for bandwidth failures in diags Harry Wentland
` (14 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c | 25 +++++++++++-----------
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
index 17758ab2e9fb..2b606a542cb8 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c
@@ -256,6 +256,7 @@ static bool process_transaction(
{
uint32_t length = request->length;
uint8_t *buffer = request->data;
+ uint32_t value = 0;
bool last_transaction = false;
@@ -291,26 +292,24 @@ static bool process_transaction(
* For an I2C send operation, the LSB must be programmed to 0;
* for I2C receive operation, the LSB must be programmed to 1. */
if (hw_engine->transaction_count == 0) {
- REG_SET_4(DC_I2C_DATA, 0,
- DC_I2C_DATA_RW, false,
- DC_I2C_DATA, request->address,
- DC_I2C_INDEX, 0,
- DC_I2C_INDEX_WRITE, 1);
+ value = REG_SET_4(DC_I2C_DATA, 0,
+ DC_I2C_DATA_RW, false,
+ DC_I2C_DATA, request->address,
+ DC_I2C_INDEX, 0,
+ DC_I2C_INDEX_WRITE, 1);
hw_engine->buffer_used_write = 0;
} else
- REG_SET_2(DC_I2C_DATA, 0,
- DC_I2C_DATA_RW, false,
- DC_I2C_DATA, request->address);
+ value = REG_SET_2(DC_I2C_DATA, 0,
+ DC_I2C_DATA_RW, false,
+ DC_I2C_DATA, request->address);
hw_engine->buffer_used_write++;
if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
while (length) {
-
- REG_UPDATE_2(DC_I2C_DATA,
- DC_I2C_INDEX_WRITE, 0,
- DC_I2C_DATA, *buffer++);
-
+ REG_SET_2(DC_I2C_DATA, value,
+ DC_I2C_INDEX_WRITE, 0,
+ DC_I2C_DATA, *buffer++);
hw_engine->buffer_used_write++;
--length;
}
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 63/76] drm/amd/dal: disable break_to_debugger for bandwidth failures in diags
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (61 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 62/76] drm/amd/dal: Don't read I2C_DATA register when in write mode Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 64/76] drm/amd/dal: PSR second monitor blackout fix Harry Wentland
` (13 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index 0c814cf886c3..c96e9edacaf1 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -1205,7 +1205,6 @@ bool dc_pre_update_surfaces_to_target(
context);
if (!temp_context) {
dm_error("%s:failed apply clk constraints\n", __func__);
- BREAK_TO_DEBUGGER();
ret = false;
goto unexpected_fail;
}
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 64/76] drm/amd/dal: PSR second monitor blackout fix
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (62 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 63/76] drm/amd/dal: disable break_to_debugger for bandwidth failures in diags Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 65/76] drm/amd/dal: Fixe linux compile error Harry Wentland
` (12 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Amy Zhang
From: Amy Zhang <Amy.Zhang@amd.com>
- Added check to make sure stream and link are corresponding to each other
- Initialized PSR caps
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 13 +++++++------
drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 6 ++++++
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index c96e9edacaf1..66686ee1c3e1 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -314,14 +314,15 @@ static bool setup_psr(struct dc *dc, const struct dc_stream *stream)
int i;
unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
- for (i = 0; i < core_dc->link_count; i++)
- dc_link_setup_psr(&core_dc->links[i]->public,
- stream);
+ for (i = 0; i < core_dc->link_count; i++) {
+ if (core_stream->sink->link == core_dc->links[i])
+ dc_link_setup_psr(&core_dc->links[i]->public,
+ stream);
+ }
for (i = 0; i < MAX_PIPES; i++) {
- if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == core_stream
- && i != underlay_idx) {
-
+ if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
+ == core_stream && i != underlay_idx) {
pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
core_dc->hwss.set_static_screen_control(&pipes, 1,
0x182);
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
index dd06960e110c..2b0b23ac6cac 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
@@ -2134,6 +2134,12 @@ static void retrieve_link_cap(struct core_link *link)
link->public.test_pattern_enabled = false;
link->public.compliance_test_state.raw = 0;
+ link->public.psr_caps.psr_exit_link_training_required = false;
+ link->public.psr_caps.psr_frame_capture_indication_req = false;
+ link->public.psr_caps.psr_rfb_setup_time = 0;
+ link->public.psr_caps.psr_sdp_transmit_line_num_deadline = 0;
+ link->public.psr_caps.psr_version = 0;
+
/* read sink count */
core_link_read_dpcd(link,
DPCD_ADDRESS_SINK_COUNT,
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 65/76] drm/amd/dal: Fixe linux compile error.
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (63 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 64/76] drm/amd/dal: PSR second monitor blackout fix Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 66/76] drm/amd/dal: consolidate DCE hw_sequencer Harry Wentland
` (11 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index 66686ee1c3e1..9c8550bc8c06 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -47,6 +47,7 @@
#include "dc_link_ddc.h"
#include "dm_helpers.h"
+#include "mem_input.h"
/*******************************************************************************
* Private structures
@@ -1806,7 +1807,6 @@ const struct dc_stream_status *dc_stream_get_status(
bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
{
int i;
- int status_check = false;
struct core_dc *core_dc = DC_TO_CORE(dc);
struct mem_input *mi;
@@ -1817,7 +1817,6 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
}
}
-
if (mi->funcs->mem_input_update_dchub)
mi->funcs->mem_input_update_dchub(mi, dh_data);
else
--
2.10.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 66/76] drm/amd/dal: consolidate DCE hw_sequencer
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (64 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 65/76] drm/amd/dal: Fixe linux compile error Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 67/76] " Harry Wentland
` (10 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- store register offset / shift / mask in dce_hwseq
- retire func_ptr enable_fe_clock and replace with direct call
- add debug assert guarding read/write to uninitialized offset
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 2 +
drivers/gpu/drm/amd/dal/dc/dce/Makefile | 2 +-
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c | 43 +++++++++++
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h | 78 +++++++++++++++++++
.../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c | 19 -----
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 33 +++++++-
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 33 +-------
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 33 +++++++-
.../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c | 30 +-------
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 33 +++++++-
.../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c | 20 +----
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 33 +++++++-
drivers/gpu/drm/amd/dal/dc/dm_services.h | 90 ++++++++++++----------
drivers/gpu/drm/amd/dal/dc/inc/core_dc.h | 1 +
drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 3 -
drivers/gpu/drm/amd/dal/dc/inc/resource.h | 7 +-
16 files changed, 313 insertions(+), 147 deletions(-)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index 0578052859e3..25b03cba906e 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -193,6 +193,8 @@ bool resource_construct(
pool->stream_enc_count++;
}
+ dc->hwseq = create_funcs->create_hwseq(ctx);
+
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/Makefile b/drivers/gpu/drm/amd/dal/dc/dce/Makefile
index 306070dd5455..738f33f64d64 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce/Makefile
@@ -5,7 +5,7 @@
# - register programming through common macros that look up register
# offset/shift/mask stored in dce_hw struct
-DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o
+DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
new file mode 100644
index 000000000000..2eab8fb3be7d
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dce_hwseq.h"
+#include "reg_helper.h"
+
+#define CTX \
+ hws->ctx
+#define REG(reg)\
+ hws->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+ hws->shifts->field_name, hws->masks->field_name
+
+void dce_enable_fe_clock(struct dce_hwseq *hws,
+ unsigned int fe_inst, bool enable)
+{
+ REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],
+ DCFE_CLOCK_ENABLE, enable);
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
new file mode 100644
index 000000000000..b12b2a3b1405
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DCE_HWSEQ_H__
+#define __DCE_HWSEQ_H__
+
+#include "hw_sequencer.h"
+
+#define HWSEQ_DCE8_REG_LIST_BASE() \
+ .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
+ .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
+ .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \
+ .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \
+ .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \
+ .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL, \
+
+#define HWSEQ_COMMON_REG_LIST_BASE() \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
+
+ /* set field name */
+#define SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define HWSEQ_DCE8_MASK_SH_LIST_BASE(mask_sh)\
+ .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
+
+#define HWSEQ_COMMON_MASK_SH_LIST_BASE(mask_sh)\
+ SF(DCFE_CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
+
+struct dce_hwseq_registers {
+ uint32_t DCFE_CLOCK_CONTROL[6];
+};
+
+struct dce_hwseq_shift {
+ uint8_t DCFE_CLOCK_ENABLE;
+};
+
+struct dce_hwseq_mask {
+ uint32_t DCFE_CLOCK_ENABLE;
+};
+
+struct dce_hwseq {
+ struct dc_context *ctx;
+ const struct dce_hwseq_registers *regs;
+ const struct dce_hwseq_shift *shifts;
+ const struct dce_hwseq_mask *masks;
+};
+
+void dce_enable_fe_clock(struct dce_hwseq *hwss,
+ unsigned int inst, bool enable);
+
+#endif /*__DCE_HWSEQ_H__*/
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
index 713291d7853f..b17cdf702fec 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
@@ -83,24 +83,6 @@ static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
* Private definitions
******************************************************************************/
/***************************PIPE_CONTROL***********************************/
-static void dce100_enable_fe_clock(
- struct dc_context *ctx, uint8_t controller_id, bool enable)
-{
- uint32_t value = 0;
- uint32_t addr;
-
- addr = HW_REG_CRTC(mmDCFE_CLOCK_CONTROL, controller_id);
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- enable,
- DCFE_CLOCK_CONTROL,
- DCFE_CLOCK_ENABLE);
-
- dm_write_reg(ctx, addr, value);
-}
static bool dce100_pipe_control_lock(
struct dc_context *ctx,
@@ -287,7 +269,6 @@ bool dce100_hw_sequencer_construct(struct core_dc *dc)
dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce100_power_up;
dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
- dc->hwss.enable_fe_clock = dce100_enable_fe_clock;
dc->hwss.pipe_control_lock = dce100_pipe_control_lock;
dc->hwss.set_blender_mode = dce100_set_blender_mode;
dc->hwss.set_displaymarks = set_displaymarks;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 9062ca209fd9..2451327de092 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -43,6 +43,7 @@
#include "dce110/dce110_opp.h"
#include "dce110/dce110_clock_source.h"
#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
#include "dce100/dce100_hw_sequencer.h"
#include "reg_helper.h"
@@ -446,10 +447,40 @@ static struct stream_encoder *dce100_stream_encoder_create(
return NULL;
}
+#define SRII(reg_name, block, id)\
+ .reg_name[id] = mm ## block ## id ## _ ## reg_name
+
+static const struct dce_hwseq_registers hwseq_reg = {
+ HWSEQ_COMMON_REG_LIST_BASE()
+};
+
+static const struct dce_hwseq_shift hwseq_shift = {
+ HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+ HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK)
+};
+
+static struct dce_hwseq *dce100_hwseq_create(
+ struct dc_context *ctx)
+{
+ struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq));
+
+ if (hws) {
+ hws->ctx = ctx;
+ hws->regs = &hwseq_reg;
+ hws->shifts = &hwseq_shift;
+ hws->masks = &hwseq_mask;
+ }
+ return hws;
+}
+
static const struct resource_create_funcs res_create_funcs = {
.read_dce_straps = read_dce_straps,
.create_audio = create_audio,
- .create_stream_encoder = dce100_stream_encoder_create
+ .create_stream_encoder = dce100_stream_encoder_create,
+ .create_hwseq = dce100_hwseq_create,
};
static struct mem_input *dce100_mem_input_create(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 249438456f73..c4a2bbf57dcd 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -46,13 +46,13 @@
#include "clock_source.h"
#include "gamma_calcs.h"
#include "audio.h"
+#include "dce/dce_hwseq.h"
/* include DCE11 register header files */
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
struct dce110_hw_seq_reg_offsets {
- uint32_t dcfe;
uint32_t blnd;
uint32_t crtc;
};
@@ -66,30 +66,23 @@ enum blender_mode {
static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
{
- .dcfe = (mmDCFE0_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
.blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .dcfe = (mmDCFE1_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
.blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .dcfe = (mmDCFE2_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
.blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .dcfe = (mmDCFEV_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
.blnd = (mmBLNDV_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
}
};
-#define HW_REG_DCFE(reg, id)\
- (reg + reg_offsets[id].dcfe)
-
#define HW_REG_BLND(reg, id)\
(reg + reg_offsets[id].blnd)
@@ -103,25 +96,6 @@ static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
* Private definitions
******************************************************************************/
/***************************PIPE_CONTROL***********************************/
-static void dce110_enable_fe_clock(
- struct dc_context *ctx, uint8_t controller_id, bool enable)
-{
- uint32_t value = 0;
- uint32_t addr;
-
- addr = HW_REG_DCFE(mmDCFE_CLOCK_CONTROL, controller_id);
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- enable,
- DCFE_CLOCK_CONTROL,
- DCFE_CLOCK_ENABLE);
-
- dm_write_reg(ctx, addr, value);
-}
-
static void dce110_init_pte(struct dc_context *ctx)
{
uint32_t addr;
@@ -1616,7 +1590,7 @@ static void set_plane_config(
memset(&tbl_entry, 0, sizeof(tbl_entry));
adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
- dc->hwss.enable_fe_clock(ctx, pipe_ctx->pipe_idx, true);
+ dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
set_default_colors(pipe_ctx);
if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
@@ -1958,7 +1932,7 @@ static void dce110_program_front_end_for_pipe(
memset(&adjust, 0, sizeof(adjust));
adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
- dc->hwss.enable_fe_clock(ctx, pipe_ctx->pipe_idx, true);
+ dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true);
set_default_colors(pipe_ctx);
if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
@@ -2160,7 +2134,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.crtc_switch_to_clk_src = dce110_crtc_switch_to_clk_src,
.enable_display_power_gating = dce110_enable_display_power_gating,
.power_down_front_end = dce110_power_down_fe,
- .enable_fe_clock = dce110_enable_fe_clock,
.pipe_control_lock = dce110_pipe_control_lock,
.set_blender_mode = dce110_set_blender_mode,
.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index cac8a19f28ed..e0e3178b9134 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -46,6 +46,7 @@
#include "dce110/dce110_opp.h"
#include "dce110/dce110_opp_v.h"
#include "dce110/dce110_clock_source.h"
+#include "dce/dce_hwseq.h"
#include "dce110/dce110_hw_sequencer.h"
#include "reg_helper.h"
@@ -421,10 +422,40 @@ static struct stream_encoder *dce110_stream_encoder_create(
return NULL;
}
+#define SRII(reg_name, block, id)\
+ .reg_name[id] = mm ## block ## id ## _ ## reg_name
+
+static const struct dce_hwseq_registers hwseq_reg = {
+ HWSEQ_COMMON_REG_LIST_BASE()
+};
+
+static const struct dce_hwseq_shift hwseq_shift = {
+ HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+ HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK)
+};
+
+static struct dce_hwseq *dce110_hwseq_create(
+ struct dc_context *ctx)
+{
+ struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq));
+
+ if (hws) {
+ hws->ctx = ctx;
+ hws->regs = &hwseq_reg;
+ hws->shifts = &hwseq_shift;
+ hws->masks = &hwseq_mask;
+ }
+ return hws;
+}
+
static const struct resource_create_funcs res_create_funcs = {
.read_dce_straps = read_dce_straps,
.create_audio = create_audio,
- .create_stream_encoder = dce110_stream_encoder_create
+ .create_stream_encoder = dce110_stream_encoder_create,
+ .create_hwseq = dce110_hwseq_create,
};
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
index f5611d14dbc9..f8c2cfb64b11 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
@@ -29,6 +29,7 @@
#include "core_types.h"
#include "dce112_hw_sequencer.h"
+#include "dce/dce_hwseq.h"
#include "dce110/dce110_hw_sequencer.h"
#include "gpu/dce112/dc_clock_gating_dce112.h"
@@ -37,7 +38,6 @@
#include "dce/dce_11_2_sh_mask.h"
struct dce112_hw_seq_reg_offsets {
- uint32_t dcfe;
uint32_t blnd;
uint32_t crtc;
};
@@ -51,40 +51,31 @@ enum blender_mode {
static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
{
- .dcfe = (mmDCFE0_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
.blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .dcfe = (mmDCFE1_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
.blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .dcfe = (mmDCFE2_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
.blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .dcfe = (mmDCFE3_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
.blnd = (mmBLND3_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .dcfe = (mmDCFE4_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
.blnd = (mmBLND4_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .dcfe = (mmDCFE5_DCFE_CLOCK_CONTROL - mmDCFE_CLOCK_CONTROL),
.blnd = (mmBLND5_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
}
};
-#define HW_REG_DCFE(reg, id)\
- (reg + reg_offsets[id].dcfe)
-
#define HW_REG_BLND(reg, id)\
(reg + reg_offsets[id].blnd)
@@ -95,24 +86,6 @@ static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
* Private definitions
******************************************************************************/
/***************************PIPE_CONTROL***********************************/
-static void dce112_enable_fe_clock(
- struct dc_context *ctx, uint8_t controller_id, bool enable)
-{
- uint32_t value = 0;
- uint32_t addr;
-
- addr = HW_REG_DCFE(mmDCFE_CLOCK_CONTROL, controller_id);
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- enable,
- DCFE_CLOCK_CONTROL,
- DCFE_CLOCK_ENABLE);
-
- dm_write_reg(ctx, addr, value);
-}
static bool dce112_pipe_control_lock(
struct dc_context *ctx,
@@ -350,7 +323,6 @@ bool dce112_hw_sequencer_construct(struct core_dc *dc)
dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce112_power_up;
dc->hwss.pipe_control_lock = dce112_pipe_control_lock;
dc->hwss.set_blender_mode = dce112_set_blender_mode;
- dc->hwss.enable_fe_clock = dce112_enable_fe_clock;
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 9f47bec557ea..01534872d3b8 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -44,6 +44,7 @@
#include "dce110/dce110_ipp.h"
#include "dce112/dce112_clock_source.h"
+#include "dce/dce_hwseq.h"
#include "dce112/dce112_hw_sequencer.h"
#include "reg_helper.h"
@@ -471,10 +472,40 @@ static struct stream_encoder *dce112_stream_encoder_create(
return NULL;
}
+#define SRII(reg_name, block, id)\
+ .reg_name[id] = mm ## block ## id ## _ ## reg_name
+
+static const struct dce_hwseq_registers hwseq_reg = {
+ HWSEQ_COMMON_REG_LIST_BASE()
+};
+
+static const struct dce_hwseq_shift hwseq_shift = {
+ HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+ HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK)
+};
+
+static struct dce_hwseq *dce112_hwseq_create(
+ struct dc_context *ctx)
+{
+ struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq));
+
+ if (hws) {
+ hws->ctx = ctx;
+ hws->regs = &hwseq_reg;
+ hws->shifts = &hwseq_shift;
+ hws->masks = &hwseq_mask;
+ }
+ return hws;
+}
+
static const struct resource_create_funcs res_create_funcs = {
.read_dce_straps = read_dce_straps,
.create_audio = create_audio,
- .create_stream_encoder = dce112_stream_encoder_create
+ .create_stream_encoder = dce112_stream_encoder_create,
+ .create_hwseq = dce112_hwseq_create,
};
static struct mem_input *dce112_mem_input_create(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
index 2841e3b7cb71..d52513ba46a8 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
@@ -29,6 +29,7 @@
#include "core_types.h"
#include "dce80_hw_sequencer.h"
+#include "dce/dce_hwseq.h"
#include "dce110/dce110_hw_sequencer.h"
#include "gpu/dce80/dc_clock_gating_dce80.h"
@@ -87,24 +88,6 @@ static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
******************************************************************************/
/***************************PIPE_CONTROL***********************************/
-static void dce80_enable_fe_clock(
- struct dc_context *ctx, uint8_t controller_id, bool enable)
-{
- uint32_t value = 0;
- uint32_t addr;
-
- addr = HW_REG_CRTC(mmCRTC_DCFE_CLOCK_CONTROL, controller_id);
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- enable,
- CRTC_DCFE_CLOCK_CONTROL,
- CRTC_DCFE_CLOCK_ENABLE);
-
- dm_write_reg(ctx, addr, value);
-}
static bool dce80_pipe_control_lock(
struct dc_context *ctx,
@@ -241,7 +224,6 @@ bool dce80_hw_sequencer_construct(struct core_dc *dc)
dce110_hw_sequencer_construct(dc);
dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce80_power_up;
- dc->hwss.enable_fe_clock = dce80_enable_fe_clock;
dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
dc->hwss.pipe_control_lock = dce80_pipe_control_lock;
dc->hwss.set_blender_mode = dce80_set_blender_mode;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index 7bf277e7bada..100c8c01aa21 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -46,6 +46,7 @@
#include "dce110/dce110_ipp.h"
#include "dce110/dce110_clock_source.h"
#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
#include "dce80/dce80_hw_sequencer.h"
#include "reg_helper.h"
@@ -437,10 +438,40 @@ static struct stream_encoder *dce80_stream_encoder_create(
return NULL;
}
+#define SRII(reg_name, block, id)\
+ .reg_name[id] = mm ## block ## id ## _ ## reg_name
+
+static const struct dce_hwseq_registers hwseq_reg = {
+ HWSEQ_DCE8_REG_LIST_BASE()
+};
+
+static const struct dce_hwseq_shift hwseq_shift = {
+ HWSEQ_DCE8_MASK_SH_LIST_BASE(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+ HWSEQ_DCE8_MASK_SH_LIST_BASE(_MASK)
+};
+
+static struct dce_hwseq *dce80_hwseq_create(
+ struct dc_context *ctx)
+{
+ struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq));
+
+ if (hws) {
+ hws->ctx = ctx;
+ hws->regs = &hwseq_reg;
+ hws->shifts = &hwseq_shift;
+ hws->masks = &hwseq_mask;
+ }
+ return hws;
+}
+
static const struct resource_create_funcs res_create_funcs = {
.read_dce_straps = read_dce_straps,
.create_audio = create_audio,
- .create_stream_encoder = dce80_stream_encoder_create
+ .create_stream_encoder = dce80_stream_encoder_create,
+ .create_hwseq = dce80_hwseq_create,
};
static struct mem_input *dce80_mem_input_create(
diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
index 016df3468a12..6385ed48ad36 100644
--- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
@@ -38,6 +38,44 @@
#undef DEPRECATED
+/*
+ *
+ * general debug capabilities
+ *
+ */
+#if defined(CONFIG_DEBUG_KERNEL) || defined(CONFIG_DEBUG_DRIVER)
+
+#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB)
+#define ASSERT_CRITICAL(expr) do { \
+ if (WARN_ON(!(expr))) { \
+ kgdb_breakpoint(); \
+ } \
+} while (0)
+#else
+#define ASSERT_CRITICAL(expr) do { \
+ if (WARN_ON(!(expr))) { \
+ ; \
+ } \
+} while (0)
+#endif
+
+#if defined(CONFIG_DEBUG_KERNEL_DAL)
+#define ASSERT(expr) ASSERT_CRITICAL(expr)
+
+#else
+#define ASSERT(expr) WARN_ON(!(expr))
+#endif
+
+#define BREAK_TO_DEBUGGER() ASSERT(0)
+
+#endif /* CONFIG_DEBUG_KERNEL || CONFIG_DEBUG_DRIVER */
+
+
+#define DC_ERR(err_msg) do { \
+ BREAK_TO_DEBUGGER(); \
+ dm_error(err_msg); \
+} while (0)
+
#define dm_alloc(size) kzalloc(size, GFP_KERNEL)
#define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
#define dm_free(ptr) kfree(ptr)
@@ -63,7 +101,14 @@ static inline uint32_t dm_read_reg_func(
uint32_t address,
const char *func_name)
{
- uint32_t value = cgs_read_register(ctx->cgs_device, address);
+ uint32_t value;
+
+ if (address == 0) {
+ DC_ERR("invalid register read. address = 0");
+ return 0;
+ }
+
+ value = cgs_read_register(ctx->cgs_device, address);
#if defined(__DAL_REGISTER_LOGGER__)
if (true == dal_reg_logger_should_dump_register()) {
@@ -89,6 +134,11 @@ static inline void dm_write_reg_func(
DRM_INFO("%s DC_WRITE_REG: 0x%x 0x%x\n", func_name, address, value);
}
#endif
+
+ if (address == 0) {
+ DC_ERR("invalid register write. address = 0");
+ return;
+ }
cgs_write_register(ctx->cgs_device, address, value);
}
@@ -370,42 +420,4 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
long dm_get_pid(void);
long dm_get_tgid(void);
-/*
- *
- * general debug capabilities
- *
- */
-#if defined(CONFIG_DEBUG_KERNEL) || defined(CONFIG_DEBUG_DRIVER)
-
-#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB)
-#define ASSERT_CRITICAL(expr) do { \
- if (WARN_ON(!(expr))) { \
- kgdb_breakpoint(); \
- } \
-} while (0)
-#else
-#define ASSERT_CRITICAL(expr) do { \
- if (WARN_ON(!(expr))) { \
- ; \
- } \
-} while (0)
-#endif
-
-#if defined(CONFIG_DEBUG_KERNEL_DAL)
-#define ASSERT(expr) ASSERT_CRITICAL(expr)
-
-#else
-#define ASSERT(expr) WARN_ON(!(expr))
-#endif
-
-#define BREAK_TO_DEBUGGER() ASSERT(0)
-
-#endif /* CONFIG_DEBUG_KERNEL || CONFIG_DEBUG_DRIVER */
-
-
-#define DC_ERR(err_msg) do { \
- BREAK_TO_DEBUGGER(); \
- dm_error(err_msg); \
-} while (0)
-
#endif /* __DM_SERVICES_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
index 826ae7a8998f..7d6dc8ea75ab 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
@@ -39,6 +39,7 @@ struct core_dc {
/* HW functions */
struct hw_sequencer_funcs hwss;
+ struct dce_hwseq *hwseq;
/* temp store of dm_pp_display_configuration
* to compare to see if display config changed
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index 6435247a41e8..7091dc731d09 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -121,9 +121,6 @@ struct hw_sequencer_funcs {
void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
struct dc_link_settings *link_settings);
- void (*enable_fe_clock)(
- struct dc_context *ctx, uint8_t controller_id, bool enable);
-
bool (*pipe_control_lock)(
struct dc_context *ctx,
uint8_t controller_idx,
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
index 9606cb28cd62..33fb7d98b294 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
@@ -52,15 +52,16 @@ struct resource_straps {
struct resource_create_funcs {
void (*read_dce_straps)(
- struct dc_context *ctx, struct resource_straps *straps);
+ struct dc_context *ctx, struct resource_straps *straps);
struct audio *(*create_audio)(
struct dc_context *ctx, unsigned int inst);
struct stream_encoder *(*create_stream_encoder)(
- enum engine_id eng_id,
- struct dc_context *ctx);
+ enum engine_id eng_id, struct dc_context *ctx);
+ struct dce_hwseq *(*create_hwseq)(
+ struct dc_context *ctx);
};
bool resource_construct(
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 67/76] drm/amd/dal: consolidate DCE hw_sequencer
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (65 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 66/76] drm/amd/dal: consolidate DCE hw_sequencer Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 68/76] drm/amd/dal: debug options Harry Wentland
` (9 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- move blnd programming to new method
- separate out DCE11 underlay support.
- fix stoney wrong offsets
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 6 +-
drivers/gpu/drm/amd/dal/dc/dc_helper.c | 16 +++
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c | 81 +++++++++++
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h | 98 ++++++++++++--
.../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c | 114 ----------------
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 150 +--------------------
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 35 ++++-
.../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c | 126 -----------------
.../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c | 94 +------------
drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 13 +-
drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h | 27 +++-
11 files changed, 252 insertions(+), 508 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index 9c8550bc8c06..7636fc6d7052 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -1446,7 +1446,7 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda
if (updates[i].flip_addr) {
core_dc->hwss.pipe_control_lock(
- core_dc->ctx,
+ core_dc->hwseq,
pipe_ctx->pipe_idx,
PIPE_LOCK_CONTROL_SURFACE,
true);
@@ -1460,7 +1460,7 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda
if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
core_dc->hwss.pipe_control_lock(
- core_dc->ctx,
+ core_dc->hwseq,
pipe_ctx->pipe_idx,
PIPE_LOCK_CONTROL_SURFACE |
PIPE_LOCK_CONTROL_GRAPHICS |
@@ -1486,7 +1486,7 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda
if (updates[j].surface == &pipe_ctx->surface->public) {
if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
core_dc->hwss.pipe_control_lock(
- core_dc->ctx,
+ core_dc->hwseq,
pipe_ctx->pipe_idx,
PIPE_LOCK_CONTROL_GRAPHICS |
PIPE_LOCK_CONTROL_SCL |
diff --git a/drivers/gpu/drm/amd/dal/dc/dc_helper.c b/drivers/gpu/drm/amd/dal/dc/dc_helper.c
index 6ac801422c63..b3f7d40673e8 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/dal/dc/dc_helper.c
@@ -61,6 +61,22 @@ uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
return reg_val;
}
+uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
+ uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
+ uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
+ uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
+ uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
+ uint8_t shift5, uint32_t mask5, uint32_t *field_value5)
+{
+ uint32_t reg_val = dm_read_reg(ctx, addr);
+ *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
+ *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
+ *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
+ *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
+ *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
+ return reg_val;
+}
+
/* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer
* compiler won't be able to check for size match and is prone to stack corruption type of bugs
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
index 2eab8fb3be7d..80f827ba63b4 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
@@ -25,6 +25,7 @@
#include "dce_hwseq.h"
#include "reg_helper.h"
+#include "hw_sequencer.h"
#define CTX \
hws->ctx
@@ -41,3 +42,83 @@ void dce_enable_fe_clock(struct dce_hwseq *hws,
REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],
DCFE_CLOCK_ENABLE, enable);
}
+
+void dce_pipe_control_lock(struct dce_hwseq *hws,
+ unsigned int blnd_inst,
+ enum pipe_lock_control control_mask,
+ bool lock)
+{
+ uint32_t lock_val = lock ? 1 : 0;
+ uint32_t dcp_grph, scl, dcp_grph_surf, blnd, update_lock_mode;
+
+ uint32_t val = REG_GET_5(BLND_V_UPDATE_LOCK[blnd_inst],
+ BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
+ BLND_SCL_V_UPDATE_LOCK, &scl,
+ BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, &dcp_grph_surf,
+ BLND_BLND_V_UPDATE_LOCK, &blnd,
+ BLND_V_UPDATE_LOCK_MODE, &update_lock_mode);
+
+ if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
+ dcp_grph = lock_val;
+
+ if (control_mask & PIPE_LOCK_CONTROL_SCL)
+ scl = lock_val;
+
+ if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
+ dcp_grph_surf = lock_val;
+
+ if (control_mask & PIPE_LOCK_CONTROL_BLENDER)
+ blnd = lock_val;
+
+ if (control_mask & PIPE_LOCK_CONTROL_MODE)
+ update_lock_mode = lock_val;
+
+ REG_SET_5(BLND_V_UPDATE_LOCK[blnd_inst], val,
+ BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
+ BLND_SCL_V_UPDATE_LOCK, &scl,
+ BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, &dcp_grph_surf,
+ BLND_BLND_V_UPDATE_LOCK, &blnd,
+ BLND_V_UPDATE_LOCK_MODE, &update_lock_mode);
+
+ if (hws->wa.blnd_crtc_trigger)
+ if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) {
+ uint32_t value = REG_READ(CRTC_H_BLANK_START_END[blnd_inst]);
+ REG_WRITE(CRTC_H_BLANK_START_END[blnd_inst], value);
+ }
+}
+
+void dce_set_blender_mode(struct dce_hwseq *hws,
+ unsigned int blnd_inst,
+ enum blnd_mode mode)
+{
+ uint32_t feedthrough = 1;
+ uint32_t blnd_mode = 0;
+ uint32_t multiplied_mode = 0;
+ uint32_t alpha_mode = 2;
+
+ switch (mode) {
+ case BLND_MODE_OTHER_PIPE:
+ feedthrough = 0;
+ blnd_mode = 1;
+ alpha_mode = 0;
+ break;
+ case BLND_MODE_BLENDING:
+ feedthrough = 0;
+ blnd_mode = 2;
+ alpha_mode = 0;
+ multiplied_mode = 1;
+ break;
+ case BLND_MODE_CURRENT_PIPE:
+ default:
+ if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
+ blnd_inst == 0)
+ feedthrough = 0;
+ break;
+ }
+
+ REG_UPDATE_4(BLND_CONTROL[blnd_inst],
+ BLND_FEEDTHROUGH_EN, feedthrough,
+ BLND_ALPHA_MODE, alpha_mode,
+ BLND_MODE, blnd_mode,
+ BLND_MULTIPLIED_MODE, multiplied_mode);
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
index b12b2a3b1405..11bff8750999 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
@@ -27,42 +27,102 @@
#include "hw_sequencer.h"
-#define HWSEQ_DCE8_REG_LIST_BASE() \
+#define HWSEQ_DCEF_REG_LIST_DCE8() \
.DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \
.DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \
- .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL, \
+ .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL
-#define HWSEQ_COMMON_REG_LIST_BASE() \
+#define HWSEQ_DCEF_REG_LIST() \
SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
- SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 5)
+
+#define HWSEQ_BLND_REG_LIST() \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 4), \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 5), \
+ SRII(BLND_CONTROL, BLND, 0), \
+ SRII(BLND_CONTROL, BLND, 1), \
+ SRII(BLND_CONTROL, BLND, 2), \
+ SRII(BLND_CONTROL, BLND, 3), \
+ SRII(BLND_CONTROL, BLND, 4), \
+ SRII(BLND_CONTROL, BLND, 5)
+
+#define HWSEQ_DCE8_REG_LIST_BASE() \
+ HWSEQ_DCEF_REG_LIST_DCE8(), \
+ HWSEQ_BLND_REG_LIST(), \
+#define HWSEQ_COMMON_REG_LIST_BASE() \
+ HWSEQ_DCEF_REG_LIST(), \
+ HWSEQ_BLND_REG_LIST()
+
+struct dce_hwseq_registers {
+ uint32_t DCFE_CLOCK_CONTROL[6];
+ uint32_t BLND_V_UPDATE_LOCK[6];
+ uint32_t BLND_CONTROL[6];
+ uint32_t BLNDV_CONTROL;
+ uint32_t CRTC_H_BLANK_START_END[6];
+};
/* set field name */
-#define SF(reg_name, field_name, post_fix)\
- .field_name = reg_name ## __ ## field_name ## post_fix
+#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
+ .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
+
+#define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
+ HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh)
+
+#define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
+ HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\
+ HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\
+ HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\
+ HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
+ HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
#define HWSEQ_DCE8_MASK_SH_LIST_BASE(mask_sh)\
.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
+ HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
+ HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh)
#define HWSEQ_COMMON_MASK_SH_LIST_BASE(mask_sh)\
- SF(DCFE_CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
+ HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
+ HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_)
-struct dce_hwseq_registers {
- uint32_t DCFE_CLOCK_CONTROL[6];
-};
+#define HWSEQ_REG_FIED_LIST(type) \
+ type DCFE_CLOCK_ENABLE; \
+ type BLND_DCP_GRPH_V_UPDATE_LOCK; \
+ type BLND_SCL_V_UPDATE_LOCK; \
+ type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
+ type BLND_BLND_V_UPDATE_LOCK; \
+ type BLND_V_UPDATE_LOCK_MODE; \
+ type BLND_FEEDTHROUGH_EN; \
+ type BLND_ALPHA_MODE; \
+ type BLND_MODE; \
+ type BLND_MULTIPLIED_MODE; \
struct dce_hwseq_shift {
- uint8_t DCFE_CLOCK_ENABLE;
+ HWSEQ_REG_FIED_LIST(uint8_t)
};
struct dce_hwseq_mask {
- uint32_t DCFE_CLOCK_ENABLE;
+ HWSEQ_REG_FIED_LIST(uint32_t)
+};
+
+struct dce_hwseq_wa {
+ bool blnd_crtc_trigger;
};
struct dce_hwseq {
@@ -70,9 +130,23 @@ struct dce_hwseq {
const struct dce_hwseq_registers *regs;
const struct dce_hwseq_shift *shifts;
const struct dce_hwseq_mask *masks;
+ struct dce_hwseq_wa wa;
};
void dce_enable_fe_clock(struct dce_hwseq *hwss,
unsigned int inst, bool enable);
+void dce_pipe_control_lock(struct dce_hwseq *hws,
+ unsigned int blnd_inst,
+ enum pipe_lock_control control_mask,
+ bool lock);
+
+enum blnd_mode {
+ BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
+ BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
+ BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
+ BLND_MODE_STEREO
+};
+void dce_set_blender_mode(struct dce_hwseq *hws,
+ unsigned int blnd_inst, enum blnd_mode mode);
#endif /*__DCE_HWSEQ_H__*/
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
index b17cdf702fec..a7fa7ede2ec2 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
@@ -39,43 +39,27 @@ struct dce100_hw_seq_reg_offsets {
uint32_t crtc;
};
-enum blender_mode {
- BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
- BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
- BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
- BLENDER_MODE_STEREO
-};
-
static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
{
- .blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND3_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND4_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND5_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
}
};
-#define HW_REG_BLND(reg, id)\
- (reg + reg_offsets[id].blnd)
-
#define HW_REG_CRTC(reg, id)\
(reg + reg_offsets[id].crtc)
@@ -84,102 +68,6 @@ static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
******************************************************************************/
/***************************PIPE_CONTROL***********************************/
-static bool dce100_pipe_control_lock(
- struct dc_context *ctx,
- uint8_t controller_idx,
- uint32_t control_mask,
- bool lock)
-{
- uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
- uint32_t value = dm_read_reg(ctx, addr);
-
- if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SCL)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_SCL_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_SURF_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_BLND_V_UPDATE_LOCK);
- }
-
- if (control_mask & PIPE_LOCK_CONTROL_MODE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_V_UPDATE_LOCK_MODE);
-
- dm_write_reg(ctx, addr, value);
-
-
- return true;
-}
-
-static void dce100_set_blender_mode(
- struct core_dc *dc,
- uint8_t controller_id,
- uint32_t mode)
-{
- uint32_t value;
- uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
- uint32_t blnd_mode;
- uint32_t feedthrough = 0;
-
- struct dc_context *ctx = dc->ctx;
-
- switch (mode) {
- case BLENDER_MODE_OTHER_PIPE:
- feedthrough = 0;
- blnd_mode = 1;
- break;
- case BLENDER_MODE_BLENDING:
- feedthrough = 0;
- blnd_mode = 2;
- break;
- case BLENDER_MODE_CURRENT_PIPE:
- default:
- feedthrough = 1;
- blnd_mode = 0;
- break;
- }
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- feedthrough,
- BLND_CONTROL,
- BLND_FEEDTHROUGH_EN);
-
- set_reg_field_value(
- value,
- blnd_mode,
- BLND_CONTROL,
- BLND_MODE);
-
- dm_write_reg(ctx, addr, value);
-}
-
static bool dce100_enable_display_power_gating(
struct core_dc *dc,
uint8_t controller_id,
@@ -269,8 +157,6 @@ bool dce100_hw_sequencer_construct(struct core_dc *dc)
dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce100_power_up;
dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
- dc->hwss.pipe_control_lock = dce100_pipe_control_lock;
- dc->hwss.set_blender_mode = dce100_set_blender_mode;
dc->hwss.set_displaymarks = set_displaymarks;
dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed;
dc->hwss.set_bandwidth = set_bandwidth;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index c4a2bbf57dcd..10b55e77ecc0 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -53,32 +53,20 @@
#include "dce/dce_11_0_sh_mask.h"
struct dce110_hw_seq_reg_offsets {
- uint32_t blnd;
uint32_t crtc;
};
-enum blender_mode {
- BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
- BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
- BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
- BLENDER_MODE_STEREO
-};
-
static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
{
- .blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLNDV_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
}
};
@@ -163,132 +151,6 @@ static void dce110_init_pte(struct dc_context *ctx)
}
}
-/* this is a workaround for hw bug - it is a trigger on r/w */
-static void trigger_write_crtc_h_blank_start_end(
- struct dc_context *ctx,
- uint8_t controller_id)
-{
- uint32_t value;
- uint32_t addr;
-
- addr = HW_REG_CRTC(mmCRTC_H_BLANK_START_END, controller_id);
- value = dm_read_reg(ctx, addr);
- dm_write_reg(ctx, addr, value);
-}
-
-static bool dce110_pipe_control_lock(
- struct dc_context *ctx,
- uint8_t controller_idx,
- uint32_t control_mask,
- bool lock)
-{
- uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
- uint32_t value = dm_read_reg(ctx, addr);
-
- if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SCL)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_SCL_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_SURF_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_BLND_V_UPDATE_LOCK);
- }
-
- if (control_mask & PIPE_LOCK_CONTROL_MODE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_V_UPDATE_LOCK_MODE);
-
- dm_write_reg(ctx, addr, value);
-
- if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER))
- trigger_write_crtc_h_blank_start_end(ctx, controller_idx);
-
- return true;
-}
-
-static void dce110_set_blender_mode(
- struct core_dc *dc,
- uint8_t controller_id,
- uint32_t mode)
-{
- uint32_t value;
- uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
- uint32_t alpha_mode = 2;
- uint32_t blnd_mode = 0;
- uint32_t feedthrough = 1;
- uint32_t multiplied_mode = 0;
-
- struct dc_context *ctx = dc->ctx;
- unsigned int underlay_idx = dc->current_context->res_ctx.pool->underlay_pipe_index;
-
- switch (mode) {
- case BLENDER_MODE_OTHER_PIPE:
- feedthrough = 0;
- alpha_mode = 0;
- blnd_mode = 1;
- break;
- case BLENDER_MODE_BLENDING:
- feedthrough = 0;
- alpha_mode = 0;
- blnd_mode = 2;
- multiplied_mode = 1;
- break;
- case BLENDER_MODE_CURRENT_PIPE:
- default:
- if (controller_id == underlay_idx || controller_id == 0)
- feedthrough = 0;
- break;
- }
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- feedthrough,
- BLND_CONTROL,
- BLND_FEEDTHROUGH_EN);
- set_reg_field_value(
- value,
- alpha_mode,
- BLND_CONTROL,
- BLND_ALPHA_MODE);
- set_reg_field_value(
- value,
- blnd_mode,
- BLND_CONTROL,
- BLND_MODE);
- set_reg_field_value(
- value,
- multiplied_mode,
- BLND_CONTROL,
- BLND_MULTIPLIED_MODE);
-
- dm_write_reg(ctx, addr, value);
-}
-
static void dce110_crtc_switch_to_clk_src(
struct clock_source *clk_src, uint8_t crtc_inst)
{
@@ -1557,18 +1419,17 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx)
static void program_blender(const struct core_dc *dc,
struct pipe_ctx *pipe_ctx)
{
- enum blender_mode blender_mode = BLENDER_MODE_CURRENT_PIPE;
+ enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
if (pipe_ctx->bottom_pipe) {
if (pipe_ctx->bottom_pipe->surface->public.visible) {
if (pipe_ctx->surface->public.visible)
- blender_mode = BLENDER_MODE_BLENDING;
+ blender_mode = BLND_MODE_BLENDING;
else
- blender_mode = BLENDER_MODE_OTHER_PIPE;
+ blender_mode = BLND_MODE_OTHER_PIPE;
}
}
- dc->hwss.set_blender_mode(
- (struct core_dc *)dc, pipe_ctx->pipe_idx, blender_mode);
+ dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
}
/**
@@ -2134,8 +1995,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.crtc_switch_to_clk_src = dce110_crtc_switch_to_clk_src,
.enable_display_power_gating = dce110_enable_display_power_gating,
.power_down_front_end = dce110_power_down_fe,
- .pipe_control_lock = dce110_pipe_control_lock,
- .set_blender_mode = dce110_set_blender_mode,
+ .pipe_control_lock = dce_pipe_control_lock,
.clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,
.set_display_clock = dce110_set_display_clock,
.set_displaymarks = dce110_set_displaymarks,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index e0e3178b9134..e19a69419c5c 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -425,16 +425,39 @@ static struct stream_encoder *dce110_stream_encoder_create(
#define SRII(reg_name, block, id)\
.reg_name[id] = mm ## block ## id ## _ ## reg_name
-static const struct dce_hwseq_registers hwseq_reg = {
- HWSEQ_COMMON_REG_LIST_BASE()
+#define HWSEQ_DCE11_REG_LIST_BASE() \
+ HWSEQ_DCEF_REG_LIST(),\
+ SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
+ SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
+ SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
+ SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
+ SRII(BLND_CONTROL, BLND, 0),\
+ SRII(BLND_CONTROL, BLND, 1),\
+ .BLNDV_CONTROL = mmBLNDV_CONTROL
+
+static const struct dce_hwseq_registers hwseq_stoney_reg = {
+ HWSEQ_DCE11_REG_LIST_BASE(),
+ .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END,
+ .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK,
+ .BLND_CONTROL[2] = mmBLNDV_CONTROL,
+};
+
+static const struct dce_hwseq_registers hwseq_cz_reg = {
+ HWSEQ_DCE11_REG_LIST_BASE(),
+ SRII(CRTC_H_BLANK_START_END, CRTC, 2),
+ SRII(BLND_V_UPDATE_LOCK, BLND, 2),
+ SRII(BLND_CONTROL, BLND, 2),
+ .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END,
+ .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK,
+ .BLND_CONTROL[3] = mmBLNDV_CONTROL,
};
static const struct dce_hwseq_shift hwseq_shift = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT)
+ HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT),
};
static const struct dce_hwseq_mask hwseq_mask = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK)
+ HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK),
};
static struct dce_hwseq *dce110_hwseq_create(
@@ -444,9 +467,11 @@ static struct dce_hwseq *dce110_hwseq_create(
if (hws) {
hws->ctx = ctx;
- hws->regs = &hwseq_reg;
+ hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
+ &hwseq_stoney_reg : &hwseq_cz_reg;
hws->shifts = &hwseq_shift;
hws->masks = &hwseq_mask;
+ hws->wa.blnd_crtc_trigger = true;
}
return hws;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
index f8c2cfb64b11..4021b0b1e3a9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
@@ -29,7 +29,6 @@
#include "core_types.h"
#include "dce112_hw_sequencer.h"
-#include "dce/dce_hwseq.h"
#include "dce110/dce110_hw_sequencer.h"
#include "gpu/dce112/dc_clock_gating_dce112.h"
@@ -38,47 +37,30 @@
#include "dce/dce_11_2_sh_mask.h"
struct dce112_hw_seq_reg_offsets {
- uint32_t blnd;
uint32_t crtc;
};
-enum blender_mode {
- BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
- BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
- BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
- BLENDER_MODE_STEREO
-};
static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
{
- .blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND3_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND4_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND5_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
}
};
-
-#define HW_REG_BLND(reg, id)\
- (reg + reg_offsets[id].blnd)
-
#define HW_REG_CRTC(reg, id)\
(reg + reg_offsets[id].crtc)
@@ -87,112 +69,6 @@ static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
******************************************************************************/
/***************************PIPE_CONTROL***********************************/
-static bool dce112_pipe_control_lock(
- struct dc_context *ctx,
- uint8_t controller_idx,
- uint32_t control_mask,
- bool lock)
-{
- uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
- uint32_t value = dm_read_reg(ctx, addr);
-
- if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SCL)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_SCL_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_SURF_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_BLENDER) {
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_BLND_V_UPDATE_LOCK);
- }
-
- if (control_mask & PIPE_LOCK_CONTROL_MODE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_V_UPDATE_LOCK_MODE);
-
- dm_write_reg(ctx, addr, value);
-
- return true;
-}
-
-static void dce112_set_blender_mode(
- struct core_dc *dc,
- uint8_t controller_id,
- uint32_t mode)
-{
- uint32_t value;
- uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
- uint32_t alpha_mode = 2;
- uint32_t blnd_mode = 0;
- uint32_t feedthrough = 1;
- uint32_t multiplied_mode = 0;
- struct dc_context *ctx = dc->ctx;
-
- switch (mode) {
- case BLENDER_MODE_OTHER_PIPE:
- feedthrough = 0;
- alpha_mode = 0;
- blnd_mode = 1;
- break;
- case BLENDER_MODE_BLENDING:
- feedthrough = 0;
- alpha_mode = 0;
- blnd_mode = 2;
- multiplied_mode = 1;
- break;
- case BLENDER_MODE_CURRENT_PIPE:
- default:
- break;
- }
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- feedthrough,
- BLND_CONTROL,
- BLND_FEEDTHROUGH_EN);
- set_reg_field_value(
- value,
- alpha_mode,
- BLND_CONTROL,
- BLND_ALPHA_MODE);
- set_reg_field_value(
- value,
- blnd_mode,
- BLND_CONTROL,
- BLND_MODE);
- set_reg_field_value(
- value,
- multiplied_mode,
- BLND_CONTROL,
- BLND_MULTIPLIED_MODE);
-
- dm_write_reg(ctx, addr, value);
-}
-
static void dce112_crtc_switch_to_clk_src(
struct clock_source *clk_src, uint8_t crtc_inst)
{
@@ -321,8 +197,6 @@ bool dce112_hw_sequencer_construct(struct core_dc *dc)
dc->hwss.crtc_switch_to_clk_src = dce112_crtc_switch_to_clk_src;
dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce112_power_up;
- dc->hwss.pipe_control_lock = dce112_pipe_control_lock;
- dc->hwss.set_blender_mode = dce112_set_blender_mode;
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
index d52513ba46a8..a69e609b9e75 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
@@ -39,47 +39,30 @@
#include "dce/dce_8_0_sh_mask.h"
struct dce80_hw_seq_reg_offsets {
- uint32_t blnd;
uint32_t crtc;
};
-enum blender_mode {
- BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
- BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
- BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
- BLENDER_MODE_STEREO
-};
-
static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
{
- .blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND3_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND4_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
},
{
- .blnd = (mmBLND5_BLND_CONTROL - mmBLND_CONTROL),
.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
}
};
-#define HW_REG_BLND(reg, id)\
- (reg + reg_offsets[id].blnd)
-
#define HW_REG_CRTC(reg, id)\
(reg + reg_offsets[id].crtc)
@@ -89,80 +72,6 @@ static const struct dce80_hw_seq_reg_offsets reg_offsets[] = {
/***************************PIPE_CONTROL***********************************/
-static bool dce80_pipe_control_lock(
- struct dc_context *ctx,
- uint8_t controller_idx,
- uint32_t control_mask,
- bool lock)
-{
- uint32_t addr = HW_REG_BLND(mmBLND_V_UPDATE_LOCK, controller_idx);
- uint32_t value = dm_read_reg(ctx, addr);
-
- if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SCL)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_SCL_V_UPDATE_LOCK);
-
- if (control_mask & PIPE_LOCK_CONTROL_SURFACE)
- set_reg_field_value(
- value,
- lock,
- BLND_V_UPDATE_LOCK,
- BLND_DCP_GRPH_SURF_V_UPDATE_LOCK);
-
- dm_write_reg(ctx, addr, value);
-
- return true;
-}
-
-static void dce80_set_blender_mode(
- struct core_dc *dc,
- uint8_t controller_id,
- uint32_t mode)
-{
- uint32_t value;
- uint32_t addr = HW_REG_BLND(mmBLND_CONTROL, controller_id);
- uint32_t blnd_mode;
- uint32_t feedthrough = 0;
-
- struct dc_context *ctx = dc->ctx;
-
- switch (mode) {
- case BLENDER_MODE_OTHER_PIPE:
- feedthrough = 0;
- blnd_mode = 1;
- break;
- case BLENDER_MODE_BLENDING:
- feedthrough = 0;
- blnd_mode = 2;
- break;
- case BLENDER_MODE_CURRENT_PIPE:
- default:
- feedthrough = 1;
- blnd_mode = 0;
- break;
- }
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- blnd_mode,
- BLND_CONTROL,
- BLND_MODE);
-
- dm_write_reg(ctx, addr, value);
-}
-
static bool dce80_enable_display_power_gating(
struct core_dc *dc,
uint8_t controller_id,
@@ -225,8 +134,7 @@ bool dce80_hw_sequencer_construct(struct core_dc *dc)
dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce80_power_up;
dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
- dc->hwss.pipe_control_lock = dce80_pipe_control_lock;
- dc->hwss.set_blender_mode = dce80_set_blender_mode;
+ dc->hwss.pipe_control_lock = dce_pipe_control_lock;
dc->hwss.set_displaymarks = set_displaymarks;
dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed;
dc->hwss.set_bandwidth = set_bandwidth;
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index 7091dc731d09..dcaac8a336d1 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -121,17 +121,12 @@ struct hw_sequencer_funcs {
void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
struct dc_link_settings *link_settings);
- bool (*pipe_control_lock)(
- struct dc_context *ctx,
- uint8_t controller_idx,
- uint32_t control_mask,
+ void (*pipe_control_lock)(
+ struct dce_hwseq *hwseq,
+ unsigned int blnd_inst,
+ enum pipe_lock_control control_mask,
bool lock);
- void (*set_blender_mode)(
- struct core_dc *dc,
- uint8_t controller_id,
- uint32_t mode);
-
void (*set_displaymarks)(
const struct core_dc *dc,
struct validate_context *context);
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
index 4c1286dc3bdb..f0cf64b1d54e 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
@@ -80,6 +80,15 @@
FN(reg, f3), v3,\
FN(reg, f4), v4)
+#define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
+ f5, v5) \
+ REG_SET_N(reg, 6, init_value, \
+ FN(reg, f1), v1,\
+ FN(reg, f2), v2,\
+ FN(reg, f3), v3,\
+ FN(reg, f4), v4,\
+ FN(reg, f5), v5)
+
#define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \
f5, v5, f6, v6) \
REG_SET_N(reg, 6, init_value, \
@@ -101,7 +110,8 @@
FN(reg, f6), v6,\
FN(reg, f7), v7)
-#define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \
+#define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
+ v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \
REG_SET_N(reg, 10, init_value, \
FN(reg, f1), v1,\
FN(reg, f2), v2, \
@@ -131,6 +141,14 @@
FN(reg_name, f2), v2, \
FN(reg_name, f3), v3)
+#define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
+ generic_reg_get5(CTX, REG(reg_name), \
+ FN(reg_name, f1), v1, \
+ FN(reg_name, f2), v2, \
+ FN(reg_name, f3), v3, \
+ FN(reg_name, f4), v4, \
+ FN(reg_name, f5), v5)
+
/* macro to poll and wait for a register field to read back given value */
#define REG_WAIT(reg_name, field, val, delay, max_try) \
@@ -260,4 +278,11 @@ uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
uint8_t shift3, uint32_t mask3, uint32_t *field_value3);
+uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
+ uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
+ uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
+ uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
+ uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
+ uint8_t shift5, uint32_t mask5, uint32_t *field_value5);
+
#endif /* DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_REG_HELPER_H_ */
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 68/76] drm/amd/dal: debug options
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (66 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 67/76] " Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 69/76] drm/amd/dal: remove dc_clock_gating in gpu Harry Wentland
` (8 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- disable_clock_gate
- disable_power_gate
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dc.h | 8 +++++---
drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c | 5 +++++
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dc.h b/drivers/gpu/drm/amd/dal/dc/dc.h
index 4c969eb26e85..6bb3aeb53261 100644
--- a/drivers/gpu/drm/amd/dal/dc/dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/dc.h
@@ -137,13 +137,15 @@ struct dc_config {
struct dc_debug {
bool surface_visual_confirm;
- bool disable_stutter;
- bool disable_dcc;
- bool disable_dfs_bypass;
bool max_disp_clk;
bool target_trace;
bool surface_trace;
bool validation_trace;
+ bool disable_stutter;
+ bool disable_dcc;
+ bool disable_dfs_bypass;
+ bool disable_power_gate;
+ bool disable_clock_gate;
};
struct dc {
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
index 7671e49ffa49..19543db48f99 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
@@ -102,4 +102,9 @@ void dal_dc_clock_gating_dce110_power_up(
force_hw_base_light_sleep(ctx);
underlay_clock_enable(ctx);
}
+
+#if 0
+ if (ctx->dc->debug.disable_clock_gate)
+ return; /* clock gating not implemented so nothing to disable */
+#endif
}
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 69/76] drm/amd/dal: remove dc_clock_gating in gpu
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (67 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 68/76] drm/amd/dal: debug options Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 70/76] drm/amd/dal: dce_crtc_switch_to_clk_src Harry Wentland
` (7 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- also fix force_hw_base_light_sleep. wrong DCE version is hooked up
- fix previous commit underlay isn't powered up when FE is powered up
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c | 39 ++++++++
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h | 72 +++++++++++---
.../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c | 26 -----
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 4 +-
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 5 +-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 24 ++---
.../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c | 2 -
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 4 +-
.../gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c | 3 -
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 6 +-
drivers/gpu/drm/amd/dal/dc/gpu/Makefile | 6 +-
.../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c | 110 ---------------------
.../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h | 33 -------
.../amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c | 89 -----------------
.../amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h | 33 -------
.../amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c | 52 ----------
.../amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h | 31 ------
drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 3 -
18 files changed, 119 insertions(+), 423 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c
delete mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
index 80f827ba63b4..3a453bf395bb 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
@@ -122,3 +122,42 @@ void dce_set_blender_mode(struct dce_hwseq *hws,
BLND_MODE, blnd_mode,
BLND_MULTIPLIED_MODE, multiplied_mode);
}
+
+
+static void dce_disable_sram_shut_down(struct dce_hwseq *hws)
+{
+ if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
+ REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,
+ DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
+}
+
+static void dce_underlay_clock_enable(struct dce_hwseq *hws)
+{
+ /* todo: why do we need this at boot? is dce_enable_fe_clock enough? */
+ if (REG(DCFEV_CLOCK_CONTROL))
+ REG_UPDATE(DCFEV_CLOCK_CONTROL,
+ DCFEV_CLOCK_ENABLE, 1);
+}
+
+static void enable_hw_base_light_sleep(void)
+{
+ /* TODO: implement */
+}
+
+static void disable_sw_manual_control_light_sleep(void)
+{
+ /* TODO: implement */
+}
+
+void dce_clock_gating_power_up(
+ struct dce_hwseq *hws,
+ bool enable)
+{
+ if (enable) {
+ enable_hw_base_light_sleep();
+ disable_sw_manual_control_light_sleep();
+ } else {
+ dce_disable_sram_shut_down(hws);
+ dce_underlay_clock_enable(hws);
+ }
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
index 11bff8750999..5ec78dcad9b5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
@@ -41,7 +41,8 @@
SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
- SRII(DCFE_CLOCK_CONTROL, DCFE, 5)
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
+ SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
#define HWSEQ_BLND_REG_LIST() \
SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
@@ -57,9 +58,40 @@
SRII(BLND_CONTROL, BLND, 4), \
SRII(BLND_CONTROL, BLND, 5)
-#define HWSEQ_DCE8_REG_LIST_BASE() \
+#define HWSEQ_DCE11_REG_LIST_BASE() \
+ SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+ SR(DCFEV_CLOCK_CONTROL), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
+ SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
+ SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
+ SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
+ SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
+ SRII(BLND_CONTROL, BLND, 0),\
+ SRII(BLND_CONTROL, BLND, 1),\
+ SR(BLNDV_CONTROL)
+
+#define HWSEQ_DCE8_REG_LIST() \
HWSEQ_DCEF_REG_LIST_DCE8(), \
- HWSEQ_BLND_REG_LIST(), \
+ HWSEQ_BLND_REG_LIST()
+
+#define HWSEQ_ST_REG_LIST() \
+ HWSEQ_DCE11_REG_LIST_BASE(), \
+ .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \
+ .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \
+ .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \
+ .BLND_CONTROL[2] = mmBLNDV_CONTROL,
+
+#define HWSEQ_CZ_REG_LIST() \
+ HWSEQ_DCE11_REG_LIST_BASE(), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
+ SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
+ SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
+ SRII(BLND_CONTROL, BLND, 2), \
+ .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \
+ .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \
+ .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
+ .BLND_CONTROL[3] = mmBLNDV_CONTROL
#define HWSEQ_COMMON_REG_LIST_BASE() \
HWSEQ_DCEF_REG_LIST(), \
@@ -67,6 +99,8 @@
struct dce_hwseq_registers {
uint32_t DCFE_CLOCK_CONTROL[6];
+ uint32_t DCFEV_CLOCK_CONTROL;
+ uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
uint32_t BLND_V_UPDATE_LOCK[6];
uint32_t BLND_CONTROL[6];
uint32_t BLNDV_CONTROL;
@@ -77,7 +111,8 @@ struct dce_hwseq_registers {
.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
#define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
- HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh)
+ HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
+ SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
#define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
@@ -90,19 +125,28 @@ struct dce_hwseq_registers {
HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
-#define HWSEQ_DCE8_MASK_SH_LIST_BASE(mask_sh)\
+#define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh)
-#define HWSEQ_COMMON_MASK_SH_LIST_BASE(mask_sh)\
+#define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_)
+#define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
+ HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
+ SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh)
+
+#define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
+ HWSEQ_DCE10_MASK_SH_LIST(mask_sh)
+
#define HWSEQ_REG_FIED_LIST(type) \
type DCFE_CLOCK_ENABLE; \
+ type DCFEV_CLOCK_ENABLE; \
+ type DC_MEM_GLOBAL_PWR_REQ_DIS; \
type BLND_DCP_GRPH_V_UPDATE_LOCK; \
type BLND_SCL_V_UPDATE_LOCK; \
type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
@@ -133,6 +177,12 @@ struct dce_hwseq {
struct dce_hwseq_wa wa;
};
+enum blnd_mode {
+ BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
+ BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
+ BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
+};
+
void dce_enable_fe_clock(struct dce_hwseq *hwss,
unsigned int inst, bool enable);
@@ -141,12 +191,10 @@ void dce_pipe_control_lock(struct dce_hwseq *hws,
enum pipe_lock_control control_mask,
bool lock);
-enum blnd_mode {
- BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
- BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
- BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
- BLND_MODE_STEREO
-};
void dce_set_blender_mode(struct dce_hwseq *hws,
unsigned int blnd_inst, enum blnd_mode mode);
+
+void dce_clock_gating_power_up(struct dce_hwseq *hws,
+ bool enable);
+
#endif /*__DCE_HWSEQ_H__*/
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
index a7fa7ede2ec2..e2fe024e1182 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
@@ -122,30 +122,6 @@ static void set_bandwidth(struct core_dc *dc)
/* Do nothing until we have proper bandwitdth calcs */
}
-static void enable_hw_base_light_sleep(void)
-{
- /* TODO: implement */
-}
-
-static void disable_sw_manual_control_light_sleep(void)
-{
- /* TODO: implement */
-}
-
-static void enable_sw_manual_control_light_sleep(void)
-{
- /* TODO: implement */
-}
-
-static void dal_dc_clock_gating_dce100_power_up(struct dc_context *ctx, bool enable)
-{
- if (enable) {
- enable_hw_base_light_sleep();
- disable_sw_manual_control_light_sleep();
- } else {
- enable_sw_manual_control_light_sleep();
- }
-}
/**************************************************************************/
@@ -154,8 +130,6 @@ bool dce100_hw_sequencer_construct(struct core_dc *dc)
dce110_hw_sequencer_construct(dc);
/* TODO: dce80 is empty implementation at the moment*/
- dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce100_power_up;
-
dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
dc->hwss.set_displaymarks = set_displaymarks;
dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 2451327de092..4b8c1e79caaa 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -455,11 +455,11 @@ static const struct dce_hwseq_registers hwseq_reg = {
};
static const struct dce_hwseq_shift hwseq_shift = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT)
+ HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
};
static const struct dce_hwseq_mask hwseq_mask = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK)
+ HWSEQ_DCE10_MASK_SH_LIST(_MASK)
};
static struct dce_hwseq *dce100_hwseq_create(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 10b55e77ecc0..7ebe090c75f2 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -33,8 +33,6 @@
#include "dce110_hw_sequencer.h"
#include "dce110_timing_generator.h"
-#include "gpu/dce110/dc_clock_gating_dce110.h"
-
#include "bios/bios_parser_helper.h"
#include "timing_generator.h"
#include "mem_input.h"
@@ -1677,7 +1675,7 @@ static void init_hw(struct core_dc *dc)
true);
}
- dc->hwss.clock_gating_power_up(dc->ctx, false);
+ dce_clock_gating_power_up(dc->hwseq, false);;
/***************************************/
for (i = 0; i < dc->link_count; i++) {
@@ -1996,7 +1994,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.enable_display_power_gating = dce110_enable_display_power_gating,
.power_down_front_end = dce110_power_down_fe,
.pipe_control_lock = dce_pipe_control_lock,
- .clock_gating_power_up = dal_dc_clock_gating_dce110_power_up,
.set_display_clock = dce110_set_display_clock,
.set_displaymarks = dce110_set_displaymarks,
.increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index e19a69419c5c..3572301e09c0 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -426,38 +426,32 @@ static struct stream_encoder *dce110_stream_encoder_create(
.reg_name[id] = mm ## block ## id ## _ ## reg_name
#define HWSEQ_DCE11_REG_LIST_BASE() \
- HWSEQ_DCEF_REG_LIST(),\
+ SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+ SR(DCFEV_CLOCK_CONTROL), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
+ SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
SRII(BLND_CONTROL, BLND, 0),\
SRII(BLND_CONTROL, BLND, 1),\
- .BLNDV_CONTROL = mmBLNDV_CONTROL
+ SR(BLNDV_CONTROL)
static const struct dce_hwseq_registers hwseq_stoney_reg = {
- HWSEQ_DCE11_REG_LIST_BASE(),
- .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END,
- .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK,
- .BLND_CONTROL[2] = mmBLNDV_CONTROL,
+ HWSEQ_ST_REG_LIST()
};
static const struct dce_hwseq_registers hwseq_cz_reg = {
- HWSEQ_DCE11_REG_LIST_BASE(),
- SRII(CRTC_H_BLANK_START_END, CRTC, 2),
- SRII(BLND_V_UPDATE_LOCK, BLND, 2),
- SRII(BLND_CONTROL, BLND, 2),
- .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END,
- .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK,
- .BLND_CONTROL[3] = mmBLNDV_CONTROL,
+ HWSEQ_CZ_REG_LIST()
};
static const struct dce_hwseq_shift hwseq_shift = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT),
+ HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
};
static const struct dce_hwseq_mask hwseq_mask = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK),
+ HWSEQ_DCE11_MASK_SH_LIST(_MASK),
};
static struct dce_hwseq *dce110_hwseq_create(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
index 4021b0b1e3a9..1b5182a0c79e 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
@@ -30,7 +30,6 @@
#include "dce112_hw_sequencer.h"
#include "dce110/dce110_hw_sequencer.h"
-#include "gpu/dce112/dc_clock_gating_dce112.h"
/* include DCE11.2 register header files */
#include "dce/dce_11_2_d.h"
@@ -196,7 +195,6 @@ bool dce112_hw_sequencer_construct(struct core_dc *dc)
dce110_hw_sequencer_construct(dc);
dc->hwss.crtc_switch_to_clk_src = dce112_crtc_switch_to_clk_src;
dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
- dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce112_power_up;
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 01534872d3b8..514669153910 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -480,11 +480,11 @@ static const struct dce_hwseq_registers hwseq_reg = {
};
static const struct dce_hwseq_shift hwseq_shift = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(__SHIFT)
+ HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
};
static const struct dce_hwseq_mask hwseq_mask = {
- HWSEQ_COMMON_MASK_SH_LIST_BASE(_MASK)
+ HWSEQ_DCE112_MASK_SH_LIST(_MASK)
};
static struct dce_hwseq *dce112_hwseq_create(
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
index a69e609b9e75..c7a2b768bcd1 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_hw_sequencer.c
@@ -32,8 +32,6 @@
#include "dce/dce_hwseq.h"
#include "dce110/dce110_hw_sequencer.h"
-#include "gpu/dce80/dc_clock_gating_dce80.h"
-
/* include DCE8 register header files */
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"
@@ -132,7 +130,6 @@ bool dce80_hw_sequencer_construct(struct core_dc *dc)
{
dce110_hw_sequencer_construct(dc);
- dc->hwss.clock_gating_power_up = dal_dc_clock_gating_dce80_power_up;
dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
dc->hwss.pipe_control_lock = dce_pipe_control_lock;
dc->hwss.set_displaymarks = set_displaymarks;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index 100c8c01aa21..1279136d1764 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -442,15 +442,15 @@ static struct stream_encoder *dce80_stream_encoder_create(
.reg_name[id] = mm ## block ## id ## _ ## reg_name
static const struct dce_hwseq_registers hwseq_reg = {
- HWSEQ_DCE8_REG_LIST_BASE()
+ HWSEQ_DCE8_REG_LIST()
};
static const struct dce_hwseq_shift hwseq_shift = {
- HWSEQ_DCE8_MASK_SH_LIST_BASE(__SHIFT)
+ HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
};
static const struct dce_hwseq_mask hwseq_mask = {
- HWSEQ_DCE8_MASK_SH_LIST_BASE(_MASK)
+ HWSEQ_DCE8_MASK_SH_LIST(_MASK)
};
static struct dce_hwseq *dce80_hwseq_create(
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
index 06f405a6cf45..ec2ef4994ade 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
@@ -12,7 +12,7 @@ AMD_DAL_FILES += $(AMD_DAL_GPU)
###############################################################################
# DCE 80 family
###############################################################################
-GPU_DCE80 = display_clock_dce80.o dc_clock_gating_dce80.o
+GPU_DCE80 = display_clock_dce80.o
AMD_DAL_GPU_DCE80 = $(addprefix $(AMDDALPATH)/dc/gpu/dce80/,$(GPU_DCE80))
@@ -22,13 +22,13 @@ AMD_DAL_FILES += $(AMD_DAL_GPU_DCE80)
###############################################################################
# DCE 110 family
###############################################################################
-GPU_DCE110 = display_clock_dce110.o dc_clock_gating_dce110.o
+GPU_DCE110 = display_clock_dce110.o
AMD_DAL_GPU_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpu/dce110/,$(GPU_DCE110))
AMD_DAL_FILES += $(AMD_DAL_GPU_DCE110)
-GPU_DCE112 = display_clock_dce112.o dc_clock_gating_dce112.o
+GPU_DCE112 = display_clock_dce112.o
AMD_DAL_GPU_DCE112 = $(addprefix $(AMDDALPATH)/dc/gpu/dce112/,$(GPU_DCE112))
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
deleted file mode 100644
index 19543db48f99..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/logger_interface.h"
-
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
-#include "dc_clock_gating_dce110.h"
-
-/******************************************************************************
- * Macro definitions
- *****************************************************************************/
-
-#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL( \
- "%s:%s()\n", __FILE__, __func__)
-
-/******************************************************************************
- * static functions
- *****************************************************************************/
-static void force_hw_base_light_sleep(struct dc_context *ctx)
-{
- uint32_t addr = 0;
- uint32_t value = 0;
-
- addr = mmDC_MEM_GLOBAL_PWR_REQ_CNTL;
- /* Read the mmDC_MEM_GLOBAL_PWR_REQ_CNTL to get the currently
- * programmed DC_MEM_GLOBAL_PWR_REQ_DIS*/
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- 1,
- DC_MEM_GLOBAL_PWR_REQ_CNTL,
- DC_MEM_GLOBAL_PWR_REQ_DIS);
-
- dm_write_reg(ctx, addr, value);
-
-}
-
-static void underlay_clock_enable(struct dc_context *ctx)
-{
- uint32_t value = 0;
-
- value = dm_read_reg(ctx, mmDCFEV_CLOCK_CONTROL);
-
- set_reg_field_value(
- value,
- 1,
- DCFEV_CLOCK_CONTROL,
- DCFEV_CLOCK_ENABLE);
-
- dm_write_reg(ctx, mmDCFEV_CLOCK_CONTROL, value);
-}
-
-static void enable_hw_base_light_sleep(struct dc_context *ctx)
-{
- NOT_IMPLEMENTED();
-}
-
-static void disable_sw_manual_control_light_sleep(
- struct dc_context *ctx)
-{
- NOT_IMPLEMENTED();
-}
-
-/******************************************************************************
- * public functions
- *****************************************************************************/
-
-void dal_dc_clock_gating_dce110_power_up(
- struct dc_context *ctx,
- bool enable)
-{
- if (enable) {
- enable_hw_base_light_sleep(ctx);
- disable_sw_manual_control_light_sleep(ctx);
- } else {
- force_hw_base_light_sleep(ctx);
- underlay_clock_enable(ctx);
- }
-
-#if 0
- if (ctx->dc->debug.disable_clock_gate)
- return; /* clock gating not implemented so nothing to disable */
-#endif
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
deleted file mode 100644
index 1bfd75a1fb51..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_DC_CLOCK_GATING_DCE110_H__
-#define __DAL_DC_CLOCK_GATING_DCE110_H__
-
-void dal_dc_clock_gating_dce110_power_up(
- struct dc_context *ctx,
- bool enable);
-
-#endif /* __DAL_DC_CLOCK_GATING_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
deleted file mode 100644
index cef5008cd08d..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/logger_interface.h"
-
-#include "dce/dce_11_2_d.h"
-#include "dce/dce_11_2_sh_mask.h"
-#include "dc_clock_gating_dce112.h"
-
-/******************************************************************************
- * Macro definitions
- *****************************************************************************/
-
-#define NOT_IMPLEMENTED() DAL_LOGGER_NOT_IMPL(\
- "%s:%s()\n", __FILE__, __func__)
-
-/******************************************************************************
- * static functions
- *****************************************************************************/
-static void force_hw_base_light_sleep(struct dc_context *ctx)
-{
- uint32_t addr = 0;
- uint32_t value = 0;
-
- addr = mmDC_MEM_GLOBAL_PWR_REQ_CNTL;
- /* Read the mmDC_MEM_GLOBAL_PWR_REQ_CNTL to get the currently
- * programmed DC_MEM_GLOBAL_PWR_REQ_DIS*/
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- 1,
- DC_MEM_GLOBAL_PWR_REQ_CNTL,
- DC_MEM_GLOBAL_PWR_REQ_DIS);
-
- dm_write_reg(ctx, addr, value);
-
-}
-
-static void enable_hw_base_light_sleep(struct dc_context *ctx)
-{
- NOT_IMPLEMENTED();
-}
-
-static void disable_sw_manual_control_light_sleep(
- struct dc_context *ctx)
-{
- NOT_IMPLEMENTED();
-}
-
-/******************************************************************************
- * public functions
- *****************************************************************************/
-
-void dal_dc_clock_gating_dce112_power_up(
- struct dc_context *ctx,
- bool enable)
-{
- if (enable) {
- enable_hw_base_light_sleep(ctx);
- disable_sw_manual_control_light_sleep(ctx);
- } else {
- force_hw_base_light_sleep(ctx);
- }
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h
deleted file mode 100644
index 118da647de18..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce112/dc_clock_gating_dce112.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_DC_CLOCK_GATING_DCE112_H__
-#define __DAL_DC_CLOCK_GATING_DCE112_H__
-
-void dal_dc_clock_gating_dce112_power_up(
- struct dc_context *ctx,
- bool enable);
-
-#endif /* __DAL_DC_CLOCK_GATING_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c
deleted file mode 100644
index 5f575770f42e..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "dc_clock_gating_dce80.h"
-
-static void enable_hw_base_light_sleep(void)
-{
- /* TODO: implement */
-}
-
-static void disable_sw_manual_control_light_sleep(void)
-{
- /* TODO: implement */
-}
-
-static void enable_sw_manual_control_light_sleep(void)
-{
- /* TODO: implement */
-}
-
-void dal_dc_clock_gating_dce80_power_up(struct dc_context *ctx, bool enable)
-{
- if (enable) {
- enable_hw_base_light_sleep();
- disable_sw_manual_control_light_sleep();
- } else {
- enable_sw_manual_control_light_sleep();
- }
-}
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h
deleted file mode 100644
index f4111c5a5e63..000000000000
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/dc_clock_gating_dce80.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_DC_CLOCK_GATING_DCE80_H__
-#define __DAL_DC_CLOCK_GATING_DCE80_H__
-
-void dal_dc_clock_gating_dce80_power_up(struct dc_context *ctx, bool enable);
-
-#endif /* __DAL_DC_CLOCK_GATING_DCE80_H__ */
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index dcaac8a336d1..e568ed891a06 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -98,9 +98,6 @@ struct hw_sequencer_funcs {
void (*crtc_switch_to_clk_src)(struct clock_source *, uint8_t);
- /* power management */
- void (*clock_gating_power_up)(struct dc_context *ctx, bool enable);
-
void (*enable_display_pipe_clock_gating)(
struct dc_context *ctx,
bool clock_gating);
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 70/76] drm/amd/dal: dce_crtc_switch_to_clk_src
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (68 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 69/76] drm/amd/dal: remove dc_clock_gating in gpu Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 71/76] drm/amd/dal: include dm_services.h in reg_helper.h Harry Wentland
` (6 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- fix crtc_switch_to_clk_src
- fix programming phypll ids into ppll
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c | 36 +++++++++++-
drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h | 68 +++++++++++++++++++---
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 2 +-
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 35 +----------
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 13 -----
.../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c | 35 -----------
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 2 +-
drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 2 -
8 files changed, 98 insertions(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
index 3a453bf395bb..014043c13d7a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
@@ -149,8 +149,7 @@ static void disable_sw_manual_control_light_sleep(void)
/* TODO: implement */
}
-void dce_clock_gating_power_up(
- struct dce_hwseq *hws,
+void dce_clock_gating_power_up(struct dce_hwseq *hws,
bool enable)
{
if (enable) {
@@ -161,3 +160,36 @@ void dce_clock_gating_power_up(
dce_underlay_clock_enable(hws);
}
}
+
+void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
+ struct clock_source *clk_src,
+ unsigned int tg_inst)
+{
+ if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO) {
+ REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
+ DP_DTO0_ENABLE, 1);
+
+ } else if (clk_src->id >= CLOCK_SOURCE_COMBO_PHY_PLL0) {
+ uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0;
+
+ REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
+ PHYPLL_PIXEL_RATE_SOURCE, rate_source,
+ PIXEL_RATE_PLL_SOURCE, 0);
+
+ REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
+ DP_DTO0_ENABLE, 0);
+
+ } else if (clk_src->id <= CLOCK_SOURCE_ID_PLL2) {
+ uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0;
+
+ REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
+ PIXEL_RATE_SOURCE, rate_source,
+ DP_DTO0_ENABLE, 0);
+
+ if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
+ REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
+ PIXEL_RATE_PLL_SOURCE, 1);
+ } else {
+ DC_ERR("unknown clock source");
+ }
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
index 5ec78dcad9b5..4af8d560a7ee 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
@@ -58,6 +58,22 @@
SRII(BLND_CONTROL, BLND, 4), \
SRII(BLND_CONTROL, BLND, 5)
+#define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
+ SRII(PIXEL_RATE_CNTL, blk, 0), \
+ SRII(PIXEL_RATE_CNTL, blk, 1), \
+ SRII(PIXEL_RATE_CNTL, blk, 2), \
+ SRII(PIXEL_RATE_CNTL, blk, 3), \
+ SRII(PIXEL_RATE_CNTL, blk, 4), \
+ SRII(PIXEL_RATE_CNTL, blk, 5)
+
+#define HWSEQ_PHYPLL_REG_LIST(blk) \
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
+ SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
+
#define HWSEQ_DCE11_REG_LIST_BASE() \
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
SR(DCFEV_CLOCK_CONTROL), \
@@ -69,11 +85,18 @@
SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
SRII(BLND_CONTROL, BLND, 0),\
SRII(BLND_CONTROL, BLND, 1),\
- SR(BLNDV_CONTROL)
+ SR(BLNDV_CONTROL),\
+ HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
#define HWSEQ_DCE8_REG_LIST() \
HWSEQ_DCEF_REG_LIST_DCE8(), \
- HWSEQ_BLND_REG_LIST()
+ HWSEQ_BLND_REG_LIST(), \
+ HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
+
+#define HWSEQ_DCE10_REG_LIST() \
+ HWSEQ_DCEF_REG_LIST(), \
+ HWSEQ_BLND_REG_LIST(), \
+ HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
#define HWSEQ_ST_REG_LIST() \
HWSEQ_DCE11_REG_LIST_BASE(), \
@@ -93,9 +116,10 @@
.BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
.BLND_CONTROL[3] = mmBLNDV_CONTROL
-#define HWSEQ_COMMON_REG_LIST_BASE() \
- HWSEQ_DCEF_REG_LIST(), \
- HWSEQ_BLND_REG_LIST()
+#define HWSEQ_DCE112_REG_LIST() \
+ HWSEQ_DCE10_REG_LIST(), \
+ HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
+ HWSEQ_PHYPLL_REG_LIST(CRTC)
struct dce_hwseq_registers {
uint32_t DCFE_CLOCK_CONTROL[6];
@@ -104,12 +128,19 @@ struct dce_hwseq_registers {
uint32_t BLND_V_UPDATE_LOCK[6];
uint32_t BLND_CONTROL[6];
uint32_t BLNDV_CONTROL;
+
uint32_t CRTC_H_BLANK_START_END[6];
+ uint32_t PIXEL_RATE_CNTL[6];
+ uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
};
/* set field name */
#define HWS_SF(blk_name, reg_name, field_name, post_fix)\
.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
+#define HWS_SF1(blk_name, reg_name, field_name, post_fix)\
+ .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix
+
+
#define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
@@ -125,23 +156,35 @@ struct dce_hwseq_registers {
HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
+#define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\
+ HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
+ HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
+
+#define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\
+ HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
+ HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
+
#define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
- HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh)
+ HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
+ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
#define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
- HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_)
+ HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
+ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
#define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
- SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh)
+ SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
+ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
#define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
- HWSEQ_DCE10_MASK_SH_LIST(mask_sh)
+ HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
+ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
#define HWSEQ_REG_FIED_LIST(type) \
type DCFE_CLOCK_ENABLE; \
@@ -156,6 +199,10 @@ struct dce_hwseq_registers {
type BLND_ALPHA_MODE; \
type BLND_MODE; \
type BLND_MULTIPLIED_MODE; \
+ type DP_DTO0_ENABLE; \
+ type PIXEL_RATE_SOURCE; \
+ type PHYPLL_PIXEL_RATE_SOURCE; \
+ type PIXEL_RATE_PLL_SOURCE; \
struct dce_hwseq_shift {
HWSEQ_REG_FIED_LIST(uint8_t)
@@ -197,4 +244,7 @@ void dce_set_blender_mode(struct dce_hwseq *hws,
void dce_clock_gating_power_up(struct dce_hwseq *hws,
bool enable);
+void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
+ struct clock_source *clk_src,
+ unsigned int tg_inst);
#endif /*__DCE_HWSEQ_H__*/
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 4b8c1e79caaa..23791ca55856 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -451,7 +451,7 @@ static struct stream_encoder *dce100_stream_encoder_create(
.reg_name[id] = mm ## block ## id ## _ ## reg_name
static const struct dce_hwseq_registers hwseq_reg = {
- HWSEQ_COMMON_REG_LIST_BASE()
+ HWSEQ_DCE10_REG_LIST()
};
static const struct dce_hwseq_shift hwseq_shift = {
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 7ebe090c75f2..ef00588b8179 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -148,35 +148,6 @@ static void dce110_init_pte(struct dc_context *ctx)
dm_write_reg(ctx, addr, value);
}
}
-
-static void dce110_crtc_switch_to_clk_src(
- struct clock_source *clk_src, uint8_t crtc_inst)
-{
- uint32_t pixel_rate_cntl_value;
- uint32_t addr;
-
- /* These addresses are the same across DCE8 - DCE11.2 */
- addr = mmCRTC0_PIXEL_RATE_CNTL + crtc_inst *
- (mmCRTC1_PIXEL_RATE_CNTL - mmCRTC0_PIXEL_RATE_CNTL);
-
- pixel_rate_cntl_value = dm_read_reg(clk_src->ctx, addr);
-
- if (clk_src->dp_clk_src)
- set_reg_field_value(pixel_rate_cntl_value, 1,
- CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE);
- else {
- set_reg_field_value(pixel_rate_cntl_value,
- 0,
- CRTC0_PIXEL_RATE_CNTL,
- DP_DTO0_ENABLE);
-
- set_reg_field_value(pixel_rate_cntl_value,
- clk_src->id - CLOCK_SOURCE_ID_PLL0,
- CRTC0_PIXEL_RATE_CNTL,
- CRTC0_PIXEL_RATE_SOURCE);
- }
- dm_write_reg(clk_src->ctx, addr, pixel_rate_cntl_value);
-}
/**************************************************************************/
static void enable_display_pipe_clock_gating(
@@ -1037,7 +1008,8 @@ static void switch_dp_clock_sources(
res_ctx, pipe_ctx->clock_source);
pipe_ctx->clock_source = clk_src;
resource_reference_clock_source(res_ctx, clk_src);
- dc->hwss.crtc_switch_to_clk_src(clk_src, i);
+
+ dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i);
}
}
}
@@ -1278,7 +1250,7 @@ enum dc_status dce110_apply_ctx_to_hw(
if (pipe_ctx->stream == pipe_ctx_old->stream) {
if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
- dc->hwss.crtc_switch_to_clk_src(
+ dce_crtc_switch_to_clk_src(dc->hwseq,
pipe_ctx->clock_source, i);
continue;
}
@@ -1990,7 +1962,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.disable_stream = dce110_disable_stream,
.unblank_stream = dce110_unblank_stream,
.enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
- .crtc_switch_to_clk_src = dce110_crtc_switch_to_clk_src,
.enable_display_power_gating = dce110_enable_display_power_gating,
.power_down_front_end = dce110_power_down_fe,
.pipe_control_lock = dce_pipe_control_lock,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 3572301e09c0..87ae249779a9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -425,19 +425,6 @@ static struct stream_encoder *dce110_stream_encoder_create(
#define SRII(reg_name, block, id)\
.reg_name[id] = mm ## block ## id ## _ ## reg_name
-#define HWSEQ_DCE11_REG_LIST_BASE() \
- SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
- SR(DCFEV_CLOCK_CONTROL), \
- SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
- SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
- SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
- SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
- SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
- SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
- SRII(BLND_CONTROL, BLND, 0),\
- SRII(BLND_CONTROL, BLND, 1),\
- SR(BLNDV_CONTROL)
-
static const struct dce_hwseq_registers hwseq_stoney_reg = {
HWSEQ_ST_REG_LIST()
};
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
index 1b5182a0c79e..204f613467b7 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
@@ -66,40 +66,6 @@ static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
/*******************************************************************************
* Private definitions
******************************************************************************/
-/***************************PIPE_CONTROL***********************************/
-
-static void dce112_crtc_switch_to_clk_src(
- struct clock_source *clk_src, uint8_t crtc_inst)
-{
- uint32_t pixel_rate_cntl_value;
- uint32_t phypll_pixel_rate_cntl_value = 0;
- uint32_t addr, phypll_addr;
-
- phypll_addr = mmCRTC0_PHYPLL_PIXEL_RATE_CNTL + crtc_inst *
- (mmCRTC1_PHYPLL_PIXEL_RATE_CNTL - mmCRTC0_PHYPLL_PIXEL_RATE_CNTL);
- addr = mmCRTC0_PIXEL_RATE_CNTL + crtc_inst *
- (mmCRTC1_PIXEL_RATE_CNTL - mmCRTC0_PIXEL_RATE_CNTL);
-
- pixel_rate_cntl_value = dm_read_reg(clk_src->ctx, addr);
-
- if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO)
- set_reg_field_value(pixel_rate_cntl_value, 1,
- CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE);
- else {
-
- set_reg_field_value(pixel_rate_cntl_value,
- clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0,
- CRTC0_PIXEL_RATE_CNTL,
- CRTC0_PIXEL_RATE_SOURCE);
-
- set_reg_field_value(phypll_pixel_rate_cntl_value,
- clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0,
- CRTC0_PHYPLL_PIXEL_RATE_CNTL,
- CRTC0_PHYPLL_PIXEL_RATE_SOURCE);
- dm_write_reg(clk_src->ctx, phypll_addr, phypll_pixel_rate_cntl_value);
- }
- dm_write_reg(clk_src->ctx, addr, pixel_rate_cntl_value);
-}
static void dce112_init_pte(struct dc_context *ctx)
{
@@ -193,7 +159,6 @@ bool dce112_hw_sequencer_construct(struct core_dc *dc)
* structure
*/
dce110_hw_sequencer_construct(dc);
- dc->hwss.crtc_switch_to_clk_src = dce112_crtc_switch_to_clk_src;
dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
return true;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 514669153910..634541eb55c5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -476,7 +476,7 @@ static struct stream_encoder *dce112_stream_encoder_create(
.reg_name[id] = mm ## block ## id ## _ ## reg_name
static const struct dce_hwseq_registers hwseq_reg = {
- HWSEQ_COMMON_REG_LIST_BASE()
+ HWSEQ_DCE112_REG_LIST()
};
static const struct dce_hwseq_shift hwseq_shift = {
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index e568ed891a06..16b10dca6e58 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -96,8 +96,6 @@ struct hw_sequencer_funcs {
void (*encoder_set_lcd_backlight_level)(
struct link_encoder *enc, uint32_t level);
- void (*crtc_switch_to_clk_src)(struct clock_source *, uint8_t);
-
void (*enable_display_pipe_clock_gating)(
struct dc_context *ctx,
bool clock_gating);
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 71/76] drm/amd/dal: include dm_services.h in reg_helper.h
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (69 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 70/76] drm/amd/dal: dce_crtc_switch_to_clk_src Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 72/76] drm/amd/dal: consolidate mem_input Harry Wentland
` (5 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce/dce_audio.c | 5 +----
drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c | 4 +---
drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c | 2 --
drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h | 2 ++
4 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_audio.c
index 6296d8fda690..dc44053e8575 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_audio.c
@@ -23,7 +23,7 @@
*
*/
-#include "dm_services.h"
+#include "reg_helper.h"
#include "dce_audio.h"
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
@@ -31,9 +31,6 @@
#define DCE_AUD(audio)\
container_of(audio, struct dce_audio, base)
-
-#include "reg_helper.h"
-
#define CTX \
aud->base.ctx
#define REG(reg)\
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
index 3b3c01a647bc..968d4187273c 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_link_encoder.c
@@ -23,9 +23,8 @@
*
*/
+#include "reg_helper.h"
-
-#include "dm_services.h"
#include "core_types.h"
#include "link_encoder.h"
#include "dce_link_encoder.h"
@@ -38,7 +37,6 @@
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
#include "dce/dce_11_0_enum.h"
-#include "reg_helper.h"
#ifndef ATOM_S2_CURRENT_BL_LEVEL_MASK
#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
index 89e09150234e..050fef92f545 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
@@ -23,8 +23,6 @@
*
*/
-
-#include "dm_services.h"
#include "dc_bios_types.h"
#include "dce_stream_encoder.h"
#include "reg_helper.h"
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
index f0cf64b1d54e..7a05141484c9 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/reg_helper.h
@@ -25,6 +25,8 @@
#ifndef DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_REG_HELPER_H_
#define DRIVERS_GPU_DRM_AMD_DAL_DEV_DC_INC_REG_HELPER_H_
+#include "dm_services.h"
+
/* macro for register read/write
* user of macro need to define
*
--
2.10.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 72/76] drm/amd/dal: consolidate mem_input
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (70 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 71/76] drm/amd/dal: include dm_services.h in reg_helper.h Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 73/76] drm/amd/dal: Add reg check before access Harry Wentland
` (4 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tony Cheng
From: Tony Cheng <tony.cheng@amd.com>
- create dce_mem_input with regsiter offset/shift/mask abstracted
- move program_surface_config to new method
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce/Makefile | 3 +-
drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.c | 193 ++++++++++++++
drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h | 134 ++++++++++
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 29 ++-
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 278 +--------------------
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 25 +-
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 29 ++-
drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c | 2 +-
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 29 ++-
drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h | 6 +
drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 2 +
11 files changed, 439 insertions(+), 291 deletions(-)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/Makefile b/drivers/gpu/drm/amd/dal/dc/dce/Makefile
index 738f33f64d64..be757b84790a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce/Makefile
@@ -5,7 +5,8 @@
# - register programming through common macros that look up register
# offset/shift/mask stored in dce_hw struct
-DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o
+DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
+dce_mem_input.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.c
new file mode 100644
index 000000000000..1b4a5b9bb8b6
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "mem_input.h"
+#include "reg_helper.h"
+
+#define CTX \
+ mi->ctx
+#define REG(reg)\
+ mi->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+ mi->shifts->field_name, mi->masks->field_name
+
+
+
+static void program_tiling(struct mem_input *mi,
+ const union dc_tiling_info *info)
+{
+ if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */
+ REG_UPDATE_9(GRPH_CONTROL,
+ GRPH_NUM_BANKS, info->gfx8.num_banks,
+ GRPH_BANK_WIDTH, info->gfx8.bank_width,
+ GRPH_BANK_HEIGHT, info->gfx8.bank_height,
+ GRPH_MACRO_TILE_ASPECT, info->gfx8.tile_aspect,
+ GRPH_TILE_SPLIT, info->gfx8.tile_split,
+ GRPH_MICRO_TILE_MODE, info->gfx8.tile_mode,
+ GRPH_PIPE_CONFIG, info->gfx8.pipe_config,
+ GRPH_ARRAY_MODE, info->gfx8.array_mode,
+ GRPH_COLOR_EXPANSION_MODE, 1);
+ /* 01 - DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP: zero expansion for YCbCr */
+ /*
+ GRPH_Z, 0);
+ */
+ }
+}
+
+
+static void program_size_and_rotation(
+ struct mem_input *mi,
+ enum dc_rotation_angle rotation,
+ const union plane_size *plane_size)
+{
+ const struct rect *in_rect = &plane_size->grph.surface_size;
+ struct rect hw_rect = plane_size->grph.surface_size;
+ const uint32_t rotation_angles[ROTATION_ANGLE_COUNT] = {
+ [ROTATION_ANGLE_0] = 0,
+ [ROTATION_ANGLE_90] = 1,
+ [ROTATION_ANGLE_180] = 2,
+ [ROTATION_ANGLE_270] = 3,
+ };
+
+ if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) {
+ hw_rect.x = in_rect->y;
+ hw_rect.y = in_rect->x;
+
+ hw_rect.height = in_rect->width;
+ hw_rect.width = in_rect->height;
+ }
+
+ REG_SET(GRPH_X_START, 0,
+ GRPH_X_START, hw_rect.x);
+
+ REG_SET(GRPH_Y_START, 0,
+ GRPH_Y_START, hw_rect.y);
+
+ REG_SET(GRPH_X_END, 0,
+ GRPH_X_END, hw_rect.width);
+
+ REG_SET(GRPH_Y_END, 0,
+ GRPH_Y_END, hw_rect.height);
+
+ REG_SET(GRPH_PITCH, 0,
+ GRPH_PITCH, plane_size->grph.surface_pitch);
+
+ REG_SET(HW_ROTATION, 0,
+ GRPH_ROTATION_ANGLE, rotation_angles[rotation]);
+}
+
+static void program_grph_pixel_format(
+ struct mem_input *mi,
+ enum surface_pixel_format format)
+{
+ uint32_t red_xbar = 0, blue_xbar = 0; /* no swap */
+ uint32_t grph_depth, grph_format;
+ uint32_t sign = 0, floating = 0;
+
+ if (format == SURFACE_PIXEL_FORMAT_GRPH_BGRA8888 ||
+ /*todo: doesn't look like we handle BGRA here,
+ * should problem swap endian*/
+ format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 ||
+ format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS ||
+ format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
+ /* ABGR formats */
+ red_xbar = 2;
+ blue_xbar = 2;
+ }
+
+ REG_SET_2(GRPH_SWAP_CNTL, 0,
+ GRPH_RED_CROSSBAR, red_xbar,
+ GRPH_BLUE_CROSSBAR, blue_xbar);
+
+ switch (format) {
+ case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
+ grph_depth = 0;
+ grph_format = 0;
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
+ grph_depth = 1;
+ grph_format = 0;
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
+ grph_depth = 1;
+ grph_format = 1;
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
+ case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
+ grph_depth = 2;
+ grph_format = 0;
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
+ grph_depth = 2;
+ grph_format = 1;
+ break;
+ case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
+ sign = 1;
+ floating = 1;
+ /* no break */
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: /* shouldn't this get float too? */
+ case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+ grph_depth = 3;
+ grph_format = 0;
+ break;
+ default:
+ DC_ERR("unsupported grph pixel format");
+ break;
+ }
+
+ REG_UPDATE_2(GRPH_CONTROL,
+ GRPH_DEPTH, grph_depth,
+ GRPH_FORMAT, grph_format);
+
+ REG_UPDATE_4(PRESCALE_GRPH_CONTROL,
+ GRPH_PRESCALE_SELECT, floating,
+ GRPH_PRESCALE_R_SIGN, sign,
+ GRPH_PRESCALE_G_SIGN, sign,
+ GRPH_PRESCALE_B_SIGN, sign);
+}
+
+bool dce_mem_input_program_surface_config(struct mem_input *mi,
+ enum surface_pixel_format format,
+ union dc_tiling_info *tiling_info,
+ union plane_size *plane_size,
+ enum dc_rotation_angle rotation,
+ struct dc_plane_dcc_param *dcc,
+ bool horizontal_mirror)
+{
+ REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);
+
+ program_tiling(mi, tiling_info);
+ program_size_and_rotation(mi, rotation, plane_size);
+
+ if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
+ format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+ program_grph_pixel_format(mi, format);
+
+ return true;
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h
new file mode 100644
index 000000000000..20b6287efc78
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DCE_MEM_INPUT_H__
+#define __DCE_MEM_INPUT_H__
+
+#define MI_REG_LIST(id)\
+ SRI(GRPH_ENABLE, DCP, id),\
+ SRI(GRPH_CONTROL, DCP, id),\
+ SRI(GRPH_X_START, DCP, id),\
+ SRI(GRPH_Y_START, DCP, id),\
+ SRI(GRPH_X_END, DCP, id),\
+ SRI(GRPH_Y_END, DCP, id),\
+ SRI(GRPH_PITCH, DCP, id),\
+ SRI(HW_ROTATION, DCP, id),\
+ SRI(GRPH_SWAP_CNTL, DCP, id),\
+ SRI(PRESCALE_GRPH_CONTROL, DCP, id)
+
+struct dce_mem_input_registers {
+ uint32_t GRPH_ENABLE;
+ uint32_t GRPH_CONTROL;
+ uint32_t GRPH_X_START;
+ uint32_t GRPH_Y_START;
+ uint32_t GRPH_X_END;
+ uint32_t GRPH_Y_END;
+ uint32_t GRPH_PITCH;
+ uint32_t HW_ROTATION;
+ uint32_t GRPH_SWAP_CNTL;
+ uint32_t PRESCALE_GRPH_CONTROL;
+};
+
+/* Set_Filed_for_Block */
+#define SFB(blk_name, reg_name, field_name, post_fix)\
+ .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
+
+#define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
+ SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
+
+#define MI_DCP_MASK_SH_LIST(mask_sh, blk)\
+ SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
+ SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
+ SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
+ SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
+ SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
+ SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
+ SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
+ SFB(blk, HW_ROTATION, GRPH_ROTATION_ANGLE, mask_sh),\
+ SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
+ SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
+ SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
+ SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
+ SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
+ SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh)
+
+#define MI_DCE_MASK_SH_LIST(mask_sh)\
+ MI_DCP_MASK_SH_LIST(mask_sh, ),\
+ MI_GFX8_TILE_MASK_SH_LIST(mask_sh, )
+
+#define MI_REG_FIED_LIST(type) \
+ type GRPH_ENABLE; \
+ type GRPH_X_START; \
+ type GRPH_Y_START; \
+ type GRPH_X_END; \
+ type GRPH_Y_END; \
+ type GRPH_PITCH; \
+ type GRPH_ROTATION_ANGLE; \
+ type GRPH_RED_CROSSBAR; \
+ type GRPH_BLUE_CROSSBAR; \
+ type GRPH_PRESCALE_SELECT; \
+ type GRPH_PRESCALE_R_SIGN; \
+ type GRPH_PRESCALE_G_SIGN; \
+ type GRPH_PRESCALE_B_SIGN; \
+ type GRPH_DEPTH; \
+ type GRPH_FORMAT; \
+ type GRPH_NUM_BANKS; \
+ type GRPH_BANK_WIDTH;\
+ type GRPH_BANK_HEIGHT;\
+ type GRPH_MACRO_TILE_ASPECT;\
+ type GRPH_TILE_SPLIT;\
+ type GRPH_MICRO_TILE_MODE;\
+ type GRPH_PIPE_CONFIG;\
+ type GRPH_ARRAY_MODE;\
+ type GRPH_COLOR_EXPANSION_MODE;\
+ type GRPH_SW_MODE; \
+ type GRPH_NUM_SHADER_ENGINES; \
+ type GRPH_NUM_PIPES; \
+
+struct dce_mem_input_shift {
+ MI_REG_FIED_LIST(uint8_t)
+};
+
+struct dce_mem_input_mask {
+ MI_REG_FIED_LIST(uint32_t)
+};
+
+struct mem_input;
+bool dce_mem_input_program_surface_config(struct mem_input *mi,
+ enum surface_pixel_format format,
+ union dc_tiling_info *tiling_info,
+ union plane_size *plane_size,
+ enum dc_rotation_angle rotation,
+ struct dc_plane_dcc_param *dcc,
+ bool horizontal_mirror);
+
+#endif /*__DCE_MEM_INPUT_H__*/
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 23791ca55856..c94695e603bd 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -483,6 +483,24 @@ static const struct resource_create_funcs res_create_funcs = {
.create_hwseq = dce100_hwseq_create,
};
+#define mi_inst_regs(id) { MI_REG_LIST(id) }
+static const struct dce_mem_input_registers mi_regs[] = {
+ mi_inst_regs(0),
+ mi_inst_regs(1),
+ mi_inst_regs(2),
+ mi_inst_regs(3),
+ mi_inst_regs(4),
+ mi_inst_regs(5),
+};
+
+static const struct dce_mem_input_shift mi_shifts = {
+ MI_DCE_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_mem_input_mask mi_masks = {
+ MI_DCE_MASK_SH_LIST(_MASK)
+};
+
static struct mem_input *dce100_mem_input_create(
struct dc_context *ctx,
uint32_t inst,
@@ -494,9 +512,14 @@ static struct mem_input *dce100_mem_input_create(
if (!mem_input110)
return NULL;
- if (dce110_mem_input_construct(mem_input110,
- ctx, inst, offset))
- return &mem_input110->base;
+ if (dce110_mem_input_construct(mem_input110, ctx, inst, offset)) {
+ struct mem_input *mi = &mem_input110->base;
+
+ mi->regs = &mi_regs[inst];
+ mi->shifts = &mi_shifts;
+ mi->masks = &mi_masks;
+ return mi;
+ }
BREAK_TO_DEBUGGER();
dm_free(mem_input110);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
index 834a73222926..4092abe3812d 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
@@ -90,263 +90,6 @@ static void program_pri_addr(
DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS), value);
}
-static void enable(struct dce110_mem_input *mem_input110)
-{
- uint32_t value = 0;
-
- value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_ENABLE));
- set_reg_field_value(value, 1, GRPH_ENABLE, GRPH_ENABLE);
- dm_write_reg(mem_input110->base.ctx,
- DCP_REG(mmGRPH_ENABLE),
- value);
-}
-
-static void program_tiling(
- struct dce110_mem_input *mem_input110,
- const union dc_tiling_info *info,
- const enum surface_pixel_format pixel_format)
-{
- uint32_t value = 0;
-
- value = dm_read_reg(
- mem_input110->base.ctx,
- DCP_REG(mmGRPH_CONTROL));
-
- set_reg_field_value(value, info->gfx8.num_banks,
- GRPH_CONTROL, GRPH_NUM_BANKS);
-
- set_reg_field_value(value, info->gfx8.bank_width,
- GRPH_CONTROL, GRPH_BANK_WIDTH);
-
- set_reg_field_value(value, info->gfx8.bank_height,
- GRPH_CONTROL, GRPH_BANK_HEIGHT);
-
- set_reg_field_value(value, info->gfx8.tile_aspect,
- GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT);
-
- set_reg_field_value(value, info->gfx8.tile_split,
- GRPH_CONTROL, GRPH_TILE_SPLIT);
-
- set_reg_field_value(value, info->gfx8.tile_mode,
- GRPH_CONTROL, GRPH_MICRO_TILE_MODE);
-
- set_reg_field_value(value, info->gfx8.pipe_config,
- GRPH_CONTROL, GRPH_PIPE_CONFIG);
-
- set_reg_field_value(value, info->gfx8.array_mode,
- GRPH_CONTROL, GRPH_ARRAY_MODE);
-
- set_reg_field_value(value, 1,
- GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE);
-
- set_reg_field_value(value, 0,
- GRPH_CONTROL, GRPH_Z);
-
- dm_write_reg(
- mem_input110->base.ctx,
- DCP_REG(mmGRPH_CONTROL),
- value);
-}
-
-static void program_size_and_rotation(
- struct dce110_mem_input *mem_input110,
- enum dc_rotation_angle rotation,
- const union plane_size *plane_size)
-{
- uint32_t value = 0;
- union plane_size local_size = *plane_size;
-
- if (rotation == ROTATION_ANGLE_90 ||
- rotation == ROTATION_ANGLE_270) {
-
- uint32_t swap;
-
- swap = local_size.grph.surface_size.x;
- local_size.grph.surface_size.x =
- local_size.grph.surface_size.y;
- local_size.grph.surface_size.y = swap;
-
- swap = local_size.grph.surface_size.width;
- local_size.grph.surface_size.width =
- local_size.grph.surface_size.height;
- local_size.grph.surface_size.height = swap;
- }
-
- set_reg_field_value(value, local_size.grph.surface_size.x,
- GRPH_X_START, GRPH_X_START);
- dm_write_reg(
- mem_input110->base.ctx,
- DCP_REG(mmGRPH_X_START),
- value);
-
- value = 0;
- set_reg_field_value(value, local_size.grph.surface_size.y,
- GRPH_Y_START, GRPH_Y_START);
- dm_write_reg(
- mem_input110->base.ctx,
- DCP_REG(mmGRPH_Y_START),
- value);
-
- value = 0;
- set_reg_field_value(value, local_size.grph.surface_size.width,
- GRPH_X_END, GRPH_X_END);
- dm_write_reg(
- mem_input110->base.ctx,
- DCP_REG(mmGRPH_X_END),
- value);
-
- value = 0;
- set_reg_field_value(value, local_size.grph.surface_size.height,
- GRPH_Y_END, GRPH_Y_END);
- dm_write_reg(
- mem_input110->base.ctx,
- DCP_REG(mmGRPH_Y_END),
- value);
-
- value = 0;
- set_reg_field_value(value, local_size.grph.surface_pitch,
- GRPH_PITCH, GRPH_PITCH);
- dm_write_reg(
- mem_input110->base.ctx,
- DCP_REG(mmGRPH_PITCH),
- value);
-
- value = 0;
- switch (rotation) {
- case ROTATION_ANGLE_90:
- set_reg_field_value(value, 1,
- HW_ROTATION, GRPH_ROTATION_ANGLE);
- break;
- case ROTATION_ANGLE_180:
- set_reg_field_value(value, 2,
- HW_ROTATION, GRPH_ROTATION_ANGLE);
- break;
- case ROTATION_ANGLE_270:
- set_reg_field_value(value, 3,
- HW_ROTATION, GRPH_ROTATION_ANGLE);
- break;
- default:
- set_reg_field_value(value, 0,
- HW_ROTATION, GRPH_ROTATION_ANGLE);
- break;
- }
- dm_write_reg(
- mem_input110->base.ctx,
- DCP_REG(mmHW_ROTATION),
- value);
-}
-
-static void program_pixel_format(
- struct dce110_mem_input *mem_input110,
- enum surface_pixel_format format)
-{
- if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
- format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
- uint32_t value = 0;
-
- /* handle colour twizzle formats, swapping R and B */
- if (format == SURFACE_PIXEL_FORMAT_GRPH_BGRA8888 ||
- format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 ||
- format ==
- SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS ||
- format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
- set_reg_field_value(
- value, 2, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR);
- set_reg_field_value(
- value, 2, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR);
- }
-
- dm_write_reg(
- mem_input110->base.ctx,
- DCP_REG(mmGRPH_SWAP_CNTL),
- value);
-
- value = dm_read_reg(
- mem_input110->base.ctx,
- DCP_REG(mmGRPH_CONTROL));
-
- switch (format) {
- case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
- set_reg_field_value(
- value, 0, GRPH_CONTROL, GRPH_DEPTH);
- set_reg_field_value(
- value, 0, GRPH_CONTROL, GRPH_FORMAT);
- break;
- case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
- set_reg_field_value(
- value, 1, GRPH_CONTROL, GRPH_DEPTH);
- set_reg_field_value(
- value, 1, GRPH_CONTROL, GRPH_FORMAT);
- break;
- case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
- case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
- set_reg_field_value(
- value, 2, GRPH_CONTROL, GRPH_DEPTH);
- set_reg_field_value(
- value, 0, GRPH_CONTROL, GRPH_FORMAT);
- break;
- case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
- case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
- case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
- set_reg_field_value(
- value, 2, GRPH_CONTROL, GRPH_DEPTH);
- set_reg_field_value(
- value, 1, GRPH_CONTROL, GRPH_FORMAT);
- break;
- case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
- case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
- case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
- set_reg_field_value(
- value, 3, GRPH_CONTROL, GRPH_DEPTH);
- set_reg_field_value(
- value, 0, GRPH_CONTROL, GRPH_FORMAT);
- break;
- default:
- break;
- }
- dm_write_reg(
- mem_input110->base.ctx,
- DCP_REG(mmGRPH_CONTROL),
- value);
-
- value = dm_read_reg(
- mem_input110->base.ctx,
- DCP_REG(mmPRESCALE_GRPH_CONTROL));
-
- if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
- set_reg_field_value(
- value, 1, PRESCALE_GRPH_CONTROL,
- GRPH_PRESCALE_SELECT);
- set_reg_field_value(
- value, 1, PRESCALE_GRPH_CONTROL,
- GRPH_PRESCALE_R_SIGN);
- set_reg_field_value(
- value, 1, PRESCALE_GRPH_CONTROL,
- GRPH_PRESCALE_G_SIGN);
- set_reg_field_value(
- value, 1, PRESCALE_GRPH_CONTROL,
- GRPH_PRESCALE_B_SIGN);
- } else {
- set_reg_field_value(
- value, 0, PRESCALE_GRPH_CONTROL,
- GRPH_PRESCALE_SELECT);
- set_reg_field_value(
- value, 0, PRESCALE_GRPH_CONTROL,
- GRPH_PRESCALE_R_SIGN);
- set_reg_field_value(
- value, 0, PRESCALE_GRPH_CONTROL,
- GRPH_PRESCALE_G_SIGN);
- set_reg_field_value(
- value, 0, PRESCALE_GRPH_CONTROL,
- GRPH_PRESCALE_B_SIGN);
- }
- dm_write_reg(
- mem_input110->base.ctx,
- DCP_REG(mmPRESCALE_GRPH_CONTROL),
- value);
- }
-}
-
bool dce110_mem_input_is_flip_pending(struct mem_input *mem_input)
{
struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
@@ -518,25 +261,6 @@ bool dce110_mem_input_program_pte_vm(
return true;
}
-bool dce110_mem_input_program_surface_config(
- struct mem_input *mem_input,
- enum surface_pixel_format format,
- union dc_tiling_info *tiling_info,
- union plane_size *plane_size,
- enum dc_rotation_angle rotation,
- struct dc_plane_dcc_param *dcc,
- bool horizotal_mirror)
-{
- struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
-
- enable(mem_input110);
- program_tiling(mem_input110, tiling_info, format);
- program_size_and_rotation(mem_input110, rotation, plane_size);
- program_pixel_format(mem_input110, format);
-
- return true;
-}
-
static void program_urgency_watermark(
const struct dc_context *ctx,
const uint32_t offset,
@@ -981,7 +705,7 @@ static struct mem_input_funcs dce110_mem_input_funcs = {
.mem_input_program_pte_vm =
dce110_mem_input_program_pte_vm,
.mem_input_program_surface_config =
- dce110_mem_input_program_surface_config,
+ dce_mem_input_program_surface_config,
.mem_input_is_flip_pending =
dce110_mem_input_is_flip_pending,
.mem_input_update_dchub = NULL
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 87ae249779a9..f9cebc9680a6 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -464,6 +464,20 @@ static const struct resource_create_funcs res_create_funcs = {
.create_hwseq = dce110_hwseq_create,
};
+#define mi_inst_regs(id) { MI_REG_LIST(id) }
+static const struct dce_mem_input_registers mi_regs[] = {
+ mi_inst_regs(0),
+ mi_inst_regs(1),
+ mi_inst_regs(2),
+};
+
+static const struct dce_mem_input_shift mi_shifts = {
+ MI_DCE_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_mem_input_mask mi_masks = {
+ MI_DCE_MASK_SH_LIST(_MASK)
+};
static struct mem_input *dce110_mem_input_create(
struct dc_context *ctx,
@@ -476,9 +490,14 @@ static struct mem_input *dce110_mem_input_create(
if (!mem_input110)
return NULL;
- if (dce110_mem_input_construct(mem_input110,
- ctx, inst, offset))
- return &mem_input110->base;
+ if (dce110_mem_input_construct(mem_input110, ctx, inst, offset)) {
+ struct mem_input *mi = &mem_input110->base;
+
+ mi->regs = &mi_regs[inst];
+ mi->shifts = &mi_shifts;
+ mi->masks = &mi_masks;
+ return mi;
+ }
BREAK_TO_DEBUGGER();
dm_free(mem_input110);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 634541eb55c5..e0b3266fdef0 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -508,6 +508,24 @@ static const struct resource_create_funcs res_create_funcs = {
.create_hwseq = dce112_hwseq_create,
};
+#define mi_inst_regs(id) { MI_REG_LIST(id) }
+static const struct dce_mem_input_registers mi_regs[] = {
+ mi_inst_regs(0),
+ mi_inst_regs(1),
+ mi_inst_regs(2),
+ mi_inst_regs(3),
+ mi_inst_regs(4),
+ mi_inst_regs(5),
+};
+
+static const struct dce_mem_input_shift mi_shifts = {
+ MI_DCE_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_mem_input_mask mi_masks = {
+ MI_DCE_MASK_SH_LIST(_MASK)
+};
+
static struct mem_input *dce112_mem_input_create(
struct dc_context *ctx,
uint32_t inst,
@@ -519,9 +537,14 @@ static struct mem_input *dce112_mem_input_create(
if (!mem_input110)
return NULL;
- if (dce112_mem_input_construct(mem_input110,
- ctx, inst, offset))
- return &mem_input110->base;
+ if (dce112_mem_input_construct(mem_input110, ctx, inst, offset)) {
+ struct mem_input *mi = &mem_input110->base;
+
+ mi->regs = &mi_regs[inst];
+ mi->shifts = &mi_shifts;
+ mi->masks = &mi_masks;
+ return mi;
+ }
BREAK_TO_DEBUGGER();
dm_free(mem_input110);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
index 7cc3ae89b7ee..8da0e31f1b6a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
@@ -173,7 +173,7 @@ static struct mem_input_funcs dce80_mem_input_funcs = {
.mem_input_program_surface_flip_and_addr =
dce110_mem_input_program_surface_flip_and_addr,
.mem_input_program_surface_config =
- dce110_mem_input_program_surface_config,
+ dce_mem_input_program_surface_config,
.mem_input_is_flip_pending =
dce110_mem_input_is_flip_pending,
.mem_input_update_dchub = NULL
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index 1279136d1764..3de40302eb89 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -474,6 +474,24 @@ static const struct resource_create_funcs res_create_funcs = {
.create_hwseq = dce80_hwseq_create,
};
+#define mi_inst_regs(id) { MI_REG_LIST(id) }
+static const struct dce_mem_input_registers mi_regs[] = {
+ mi_inst_regs(0),
+ mi_inst_regs(1),
+ mi_inst_regs(2),
+ mi_inst_regs(3),
+ mi_inst_regs(4),
+ mi_inst_regs(5),
+};
+
+static const struct dce_mem_input_shift mi_shifts = {
+ MI_DCE_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_mem_input_mask mi_masks = {
+ MI_DCE_MASK_SH_LIST(_MASK)
+};
+
static struct mem_input *dce80_mem_input_create(
struct dc_context *ctx,
uint32_t inst,
@@ -485,9 +503,14 @@ static struct mem_input *dce80_mem_input_create(
if (!mem_input80)
return NULL;
- if (dce80_mem_input_construct(mem_input80,
- ctx, inst, offsets))
- return &mem_input80->base;
+ if (dce80_mem_input_construct(mem_input80, ctx, inst, offsets)) {
+ struct mem_input *mi = &mem_input80->base;
+
+ mi->regs = &mi_regs[inst];
+ mi->shifts = &mi_shifts;
+ mi->masks = &mi_masks;
+ return mi;
+ }
BREAK_TO_DEBUGGER();
dm_free(mem_input80);
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
index a4e91cc719d6..e7026ec87bce 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
@@ -29,6 +29,8 @@
#include "include/grph_object_id.h"
#include "inc/bandwidth_calcs.h"
+#include "dce/dce_mem_input.h" /* temporary */
+
struct stutter_modes {
bool enhanced;
bool quad_dmif_buffer;
@@ -42,6 +44,10 @@ struct mem_input {
struct dc_plane_address current_address;
uint32_t inst;
struct stutter_modes stutter_mode;
+
+ const struct dce_mem_input_registers *regs;
+ const struct dce_mem_input_shift *shifts;
+ const struct dce_mem_input_mask *masks;
};
struct mem_input_funcs {
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index 16b10dca6e58..d16e70103300 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -44,6 +44,8 @@ enum pipe_lock_control {
PIPE_LOCK_CONTROL_MODE = 1 << 4
};
+struct dce_hwseq;
+
struct hw_sequencer_funcs {
void (*init_hw)(struct core_dc *dc);
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 73/76] drm/amd/dal: Add reg check before access.
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (71 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 72/76] drm/amd/dal: consolidate mem_input Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 74/76] drm/amd/dal: Fix typo in mem_input Harry Wentland
` (3 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c | 4 ----
drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h | 8 --------
2 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
index 050fef92f545..93ce4967e56b 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
@@ -231,9 +231,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
uint32_t h_back_porch;
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
- /* for bring up, disable dp double TODO */
- REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
-
/* set pixel encoding */
switch (crtc_timing->pixel_encoding) {
case PIXEL_ENCODING_YCBCR422:
@@ -269,7 +266,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
}
- misc1 = REG_READ(DP_MSA_MISC);
/* set color depth */
switch (crtc_timing->display_color_depth) {
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
index 2778f89e5abf..c34b52a186b6 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
@@ -515,14 +515,6 @@ struct dce110_stream_enc_registers {
uint32_t HDMI_ACR_48_0;
uint32_t HDMI_ACR_48_1;
uint32_t TMDS_CNTL;
- uint32_t DP_DB_CNTL;
- uint32_t DP_MSA_MISC;
- uint32_t DP_MSA_COLORIMETRY;
- uint32_t DP_MSA_TIMING_PARAM1;
- uint32_t DP_MSA_TIMING_PARAM2;
- uint32_t DP_MSA_TIMING_PARAM3;
- uint32_t DP_MSA_TIMING_PARAM4;
- uint32_t HDMI_DB_CONTROL;
};
struct dce110_stream_encoder {
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 74/76] drm/amd/dal: Fix typo in mem_input
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (72 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 73/76] drm/amd/dal: Add reg check before access Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 75/76] drm/amd/dal: Make bunch of scaler structs static Harry Wentland
` (2 subsequent siblings)
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zeyu Fan
From: Zeyu Fan <Zeyu.Fan@amd.com>
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h
index 20b6287efc78..96c7736e223b 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h
@@ -85,7 +85,7 @@ struct dce_mem_input_registers {
MI_DCP_MASK_SH_LIST(mask_sh, ),\
MI_GFX8_TILE_MASK_SH_LIST(mask_sh, )
-#define MI_REG_FIED_LIST(type) \
+#define MI_REG_FIELD_LIST(type) \
type GRPH_ENABLE; \
type GRPH_X_START; \
type GRPH_Y_START; \
@@ -115,11 +115,11 @@ struct dce_mem_input_registers {
type GRPH_NUM_PIPES; \
struct dce_mem_input_shift {
- MI_REG_FIED_LIST(uint8_t)
+ MI_REG_FIELD_LIST(uint8_t)
};
struct dce_mem_input_mask {
- MI_REG_FIED_LIST(uint32_t)
+ MI_REG_FIELD_LIST(uint32_t)
};
struct mem_input;
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 75/76] drm/amd/dal: Make bunch of scaler structs static
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (73 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 74/76] drm/amd/dal: Fix typo in mem_input Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-21 23:01 ` [PATCH 76/76] drm/amd/dal: Expose Polaris validate functions Harry Wentland
2016-11-23 0:06 ` [PATCH 00/76] DAL Patches Nov 21, 2016 Jerome Glisse
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../drm/amd/dal/dc/dce110/dce110_transform_scl.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
index 5e8472e835ca..9dea5018c6b9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
@@ -44,7 +44,7 @@
#define SCL_PHASES 16
-const uint16_t filter_2tap_16p[18] = {
+static const uint16_t filter_2tap_16p[18] = {
4096, 0,
3840, 256,
3584, 512,
@@ -56,7 +56,7 @@ const uint16_t filter_2tap_16p[18] = {
2048, 2048
};
-const uint16_t filter_3tap_16p_upscale[27] = {
+static const uint16_t filter_3tap_16p_upscale[27] = {
2048, 2048, 0,
1708, 2424, 16348,
1372, 2796, 16308,
@@ -68,7 +68,7 @@ const uint16_t filter_3tap_16p_upscale[27] = {
0, 4096, 0
};
-const uint16_t filter_3tap_16p_117[27] = {
+static const uint16_t filter_3tap_16p_117[27] = {
2048, 2048, 0,
1824, 2276, 16376,
1600, 2496, 16380,
@@ -80,7 +80,7 @@ const uint16_t filter_3tap_16p_117[27] = {
428, 3236, 428
};
-const uint16_t filter_3tap_16p_150[27] = {
+static const uint16_t filter_3tap_16p_150[27] = {
2048, 2048, 0,
1872, 2184, 36,
1692, 2308, 88,
@@ -92,7 +92,7 @@ const uint16_t filter_3tap_16p_150[27] = {
696, 2696, 696
};
-const uint16_t filter_3tap_16p_183[27] = {
+static const uint16_t filter_3tap_16p_183[27] = {
2048, 2048, 0,
1892, 2104, 92,
1744, 2152, 196,
@@ -104,7 +104,7 @@ const uint16_t filter_3tap_16p_183[27] = {
900, 2292, 900
};
-const uint16_t filter_4tap_16p_upscale[36] = {
+static const uint16_t filter_4tap_16p_upscale[36] = {
0, 4096, 0, 0,
16240, 4056, 180, 16380,
16136, 3952, 404, 16364,
@@ -116,7 +116,7 @@ const uint16_t filter_4tap_16p_upscale[36] = {
16128, 2304, 2304, 16128
};
-const uint16_t filter_4tap_16p_117[36] = {
+static const uint16_t filter_4tap_16p_117[36] = {
428, 3236, 428, 0,
276, 3232, 604, 16364,
148, 3184, 800, 16340,
@@ -128,7 +128,7 @@ const uint16_t filter_4tap_16p_117[36] = {
16212, 2216, 2216, 16212
};
-const uint16_t filter_4tap_16p_150[36] = {
+static const uint16_t filter_4tap_16p_150[36] = {
696, 2700, 696, 0,
560, 2700, 848, 16364,
436, 2676, 1008, 16348,
@@ -140,7 +140,7 @@ const uint16_t filter_4tap_16p_150[36] = {
16376, 2052, 2052, 16376
};
-const uint16_t filter_4tap_16p_183[36] = {
+static const uint16_t filter_4tap_16p_183[36] = {
940, 2208, 940, 0,
832, 2200, 1052, 4,
728, 2180, 1164, 16,
@@ -325,7 +325,7 @@ static void set_coeff_update_complete(struct dce110_transform *xfm110)
dm_write_reg(xfm110->base.ctx, addr, value);
}
-const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio)
+static const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio)
{
if (ratio.value < dal_fixed31_32_one.value)
return filter_3tap_16p_upscale;
@@ -337,7 +337,7 @@ const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio)
return filter_3tap_16p_183;
}
-const uint16_t *get_filter_4tap_16p(struct fixed31_32 ratio)
+static const uint16_t *get_filter_4tap_16p(struct fixed31_32 ratio)
{
if (ratio.value < dal_fixed31_32_one.value)
return filter_4tap_16p_upscale;
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 76/76] drm/amd/dal: Expose Polaris validate functions
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (74 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 75/76] drm/amd/dal: Make bunch of scaler structs static Harry Wentland
@ 2016-11-21 23:01 ` Harry Wentland
2016-11-23 0:06 ` [PATCH 00/76] DAL Patches Nov 21, 2016 Jerome Glisse
76 siblings, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-21 23:01 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h
index 9d2427752389..f21eb57857d4 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.h
@@ -35,5 +35,21 @@ struct resource_pool *dce112_create_resource_pool(
uint8_t num_virtual_links,
struct core_dc *dc);
+enum dc_status dce112_validate_with_context(
+ const struct core_dc *dc,
+ const struct dc_validation_set set[],
+ int set_count,
+ struct validate_context *context);
+
+enum dc_status dce112_validate_guaranteed(
+ const struct core_dc *dc,
+ const struct dc_target *dc_target,
+ struct validate_context *context);
+
+enum dc_status dce112_validate_bandwidth(
+ const struct core_dc *dc,
+ struct validate_context *context);
+
+
#endif /* __DC_RESOURCE_DCE112_H__ */
--
2.10.1
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^ permalink raw reply related [flat|nested] 80+ messages in thread
* Re: [PATCH 00/76] DAL Patches Nov 21, 2016
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (75 preceding siblings ...)
2016-11-21 23:01 ` [PATCH 76/76] drm/amd/dal: Expose Polaris validate functions Harry Wentland
@ 2016-11-23 0:06 ` Jerome Glisse
[not found] ` <20161123000638.GA3312-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
76 siblings, 1 reply; 80+ messages in thread
From: Jerome Glisse @ 2016-11-23 0:06 UTC (permalink / raw)
To: harry.wentland-5C7GfCeVMHo; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
I hate to shime in but from review point of view what i don't undersntand is why
isn't there a single reviewable patchset for DAL ?
What i mean by that is a patchset in which you collapse all fixes and cleanup so
that there is an easy way to review thing. Yes this means loosing history and
major work to just spawn a new patchset but quite frankly in this state this thing
is just unreviewable. The only sane way today is to look at git tree with the whole
thing applied and avoid looking at individual patch. That not a sane way to do
review in my mind.
That just my opinion other might disagree but i thought i would say that outloud.
Cheers,
Jérôme
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^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 00/76] DAL Patches Nov 21, 2016
[not found] ` <20161123000638.GA3312-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2016-11-23 2:31 ` Harry Wentland
2016-11-23 18:56 ` Alex Deucher
1 sibling, 0 replies; 80+ messages in thread
From: Harry Wentland @ 2016-11-23 2:31 UTC (permalink / raw)
To: Jerome Glisse; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Hi Jerome,
I understand the frustration but the intention of this set isn't to
review the entirety of dal. Alex has been pulling our patches into his
amd-staging-4.7 branch and dal has been used in our PRO driver stack.
This is just making these patches a bit more public and inviting
feedback instead of pulling them quietly into some public tree.
Cheers,
Harry
On 2016-11-22 07:06 PM, Jerome Glisse wrote:
> I hate to shime in but from review point of view what i don't undersntand is why
> isn't there a single reviewable patchset for DAL ?
>
> What i mean by that is a patchset in which you collapse all fixes and cleanup so
> that there is an easy way to review thing. Yes this means loosing history and
> major work to just spawn a new patchset but quite frankly in this state this thing
> is just unreviewable. The only sane way today is to look at git tree with the whole
> thing applied and avoid looking at individual patch. That not a sane way to do
> review in my mind.
>
> That just my opinion other might disagree but i thought i would say that outloud.
>
> Cheers,
> Jérôme
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^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 00/76] DAL Patches Nov 21, 2016
[not found] ` <20161123000638.GA3312-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-11-23 2:31 ` Harry Wentland
@ 2016-11-23 18:56 ` Alex Deucher
1 sibling, 0 replies; 80+ messages in thread
From: Alex Deucher @ 2016-11-23 18:56 UTC (permalink / raw)
To: Jerome Glisse; +Cc: Wentland, Harry, amd-gfx list
On Tue, Nov 22, 2016 at 7:06 PM, Jerome Glisse <j.glisse@gmail.com> wrote:
> I hate to shime in but from review point of view what i don't undersntand is why
> isn't there a single reviewable patchset for DAL ?
>
> What i mean by that is a patchset in which you collapse all fixes and cleanup so
> that there is an easy way to review thing. Yes this means loosing history and
> major work to just spawn a new patchset but quite frankly in this state this thing
> is just unreviewable. The only sane way today is to look at git tree with the whole
> thing applied and avoid looking at individual patch. That not a sane way to do
> review in my mind.
As Harry mentioned, the display team is starting the process of moving
their development to this mailing list so Harry will start sending
regular development patches from the display team until they get fully
ramped up on using the public mailing list.
As for upstreaming the new display code, we are still working on
addressing all of the previous concerns, but it takes a while as we
have a lot of customer deliverables and new asic work so the clean up
and reorg has had to happen in parallel as time permits. I don't know
that it makes a lot of sense to re-generate new patches for upstream
again at this point if they are not likely to make it upstream. The
idea of flagging the new display code as staging code was suggested a
while ago so that we could work on clean up and better integration
upstream, but I think that got shot down. We don't have the resources
to rewrite the entire thing from scratch, so it needs to be an
iterative process. Right now we share the Linux display code with the
our pre-and post silicon validation and diagnostics teams (and we have
plans to move other platforms to this code as well down the road) so
we need to make sure we don't break them while we reorg the code for
upstream.
For the most part, I agree with many of the changes we need to make to
get the code upstream, it's just frustrating for us and for our users
to have to use out of tree code to enable most advanced display
functionality while we work through those issues. I understand the
arguments for general upstream maintainability absent our support, but
that has to be countered with being able to support features and asics
now. Moreover, we've been working upstream for a long time now, so I
don't think it's that likely that we are just going to disappear and
leave hard to maintain code. We end up having to spend a lot of
resources on maintaining big out of tree packages for OEMs and other
customers that we could be spent on getting the code ready for
upstream. It's a vicious cycle.
Alex
>
> That just my opinion other might disagree but i thought i would say that outloud.
>
> Cheers,
> Jérôme
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 80+ messages in thread
end of thread, other threads:[~2016-11-23 18:56 UTC | newest]
Thread overview: 80+ messages (download: mbox.gz follow: Atom feed
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2016-11-21 23:00 [PATCH 00/76] DAL Patches Nov 21, 2016 Harry Wentland
[not found] ` <20161121230136.5208-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2016-11-21 23:00 ` [PATCH 01/76] drm/amd/dal: bring all of dc under a single log category table Harry Wentland
2016-11-21 23:00 ` [PATCH 02/76] drm/amd/dal: clean up asic cap Harry Wentland
2016-11-21 23:00 ` [PATCH 03/76] drm/amd/dal: Remove unused code in dce112 hwss Harry Wentland
2016-11-21 23:00 ` [PATCH 04/76] drm/amd/dal: Consolidate link encoder from each dce version Harry Wentland
2016-11-21 23:00 ` [PATCH 05/76] drm/amd/dal: Remove wireless_data_source Harry Wentland
2016-11-21 23:00 ` [PATCH 06/76] drm/amd/dal: Move gpio_service out of adapter_service Harry Wentland
2016-11-21 23:00 ` [PATCH 07/76] drm/amd/dal: Fix warning about comparing different types Harry Wentland
2016-11-21 23:00 ` [PATCH 08/76] drm/amd/dal: fix dc creation Harry Wentland
2016-11-21 23:00 ` [PATCH 09/76] drm/amd/dal: add chroma support to program_size_and_rotation Harry Wentland
2016-11-21 23:00 ` [PATCH 10/76] drm/amd/dal: add meta address to video address struct Harry Wentland
2016-11-21 23:00 ` [PATCH 11/76] drm/amd/dal: Refactor i2c_hw_engine Harry Wentland
2016-11-21 23:00 ` [PATCH 12/76] drm/amd/dal: modify DCE HW sequence to be re-usable for next gen HW Harry Wentland
2016-11-21 23:00 ` [PATCH 13/76] drm/amd/dal: DCC support Harry Wentland
2016-11-21 23:00 ` [PATCH 14/76] drm/amd/dal: Expose some HWS functions so we can re-use them Harry Wentland
2016-11-21 23:00 ` [PATCH 15/76] drm/amd/dal: Modify regsiter access to use macro Harry Wentland
2016-11-21 23:00 ` [PATCH 16/76] drm/amd/dal: refactor bios scratch register access Harry Wentland
2016-11-21 23:00 ` [PATCH 17/76] drm/amd/dal: Remove adapter service from display clock Harry Wentland
2016-11-21 23:00 ` [PATCH 18/76] drm/amd/dal: Use future proof reg access for HPD and DDC Harry Wentland
2016-11-21 23:00 ` [PATCH 19/76] drm/amd/dal: Remove adapter service dependency from dc_link Harry Wentland
2016-11-21 23:00 ` [PATCH 20/76] drm/amd/dal: rotation and mirror support Harry Wentland
2016-11-21 23:00 ` [PATCH 21/76] drm/amd/dal: remove unnessary AS dependency Harry Wentland
2016-11-21 23:00 ` [PATCH 22/76] drm/amd/dal: remove AS dependency from i2c_aux Harry Wentland
2016-11-21 23:00 ` [PATCH 23/76] drm/amd/dal: remove dal_adapter_service_get_integrated_info Harry Wentland
2016-11-21 23:00 ` [PATCH 24/76] drm/amd/dal: instantiate i2caux outside of AS Harry Wentland
2016-11-21 23:00 ` [PATCH 25/76] drm/amd/dal: fix DDC pad mode detection logic Harry Wentland
2016-11-21 23:00 ` [PATCH 26/76] drm/amd/dal: Fix MST crash by skipping branch connector Harry Wentland
2016-11-21 23:00 ` [PATCH 27/76] drm/amd/dal: Lower max link cap by reportedLinkCap Harry Wentland
2016-11-21 23:00 ` [PATCH 28/76] drm/amd/dal: Allow timing with req_bw equal to max_bw Harry Wentland
2016-11-21 23:00 ` [PATCH 29/76] drm/amd/dal: Perform link training in dp_retrain_link Harry Wentland
2016-11-21 23:00 ` [PATCH 30/76] drm/amd/dal: Poll AUX_SW_DONE to 0 before AUX_SW_GO Harry Wentland
2016-11-21 23:00 ` [PATCH 31/76] drm/amd/dal: Fallback LT without retry in verify_link_cap Harry Wentland
2016-11-21 23:00 ` [PATCH 32/76] drm/amd/dal: Remove adapter service dependency in power_down Harry Wentland
2016-11-21 23:00 ` [PATCH 33/76] drm/amd/dal: remove supported_stream_engines Harry Wentland
2016-11-21 23:00 ` [PATCH 34/76] drm/amd/dal: Rotation and mirror support Harry Wentland
2016-11-21 23:00 ` [PATCH 35/76] drm/amd/dal: Pass in shift and mask for stream encoder Harry Wentland
2016-11-21 23:00 ` [PATCH 36/76] drm/amd/dal: Fixed wrong return value check condition Harry Wentland
2016-11-21 23:00 ` [PATCH 37/76] drm/amd/dal: Make set_overscan_blank_color optional Harry Wentland
2016-11-21 23:00 ` [PATCH 38/76] drm/amd/dal: Hard-coded LB_MEMORY_SIZE Harry Wentland
2016-11-21 23:00 ` [PATCH 39/76] drm/amd/dal: Rotation and mirror support Harry Wentland
2016-11-21 23:01 ` [PATCH 40/76] drm/amd/dal: remove unnessary adapter service functions Harry Wentland
2016-11-21 23:01 ` [PATCH 41/76] drm/amd/dal: remove dal_override_parameters Harry Wentland
2016-11-21 23:01 ` [PATCH 42/76] drm/amd/dal: remove unnessary adapter service functions Harry Wentland
2016-11-21 23:01 ` [PATCH 43/76] " Harry Wentland
2016-11-21 23:01 ` [PATCH 44/76] drm/amd/dal: Fix null pointer missed in earlier refactor Harry Wentland
2016-11-21 23:01 ` [PATCH 45/76] drm/amd/dal: fix typo disalbe_dfs_bypass Harry Wentland
2016-11-21 23:01 ` [PATCH 46/76] drm/amd/dal: Remove unused function from dc Harry Wentland
2016-11-21 23:01 ` [PATCH 47/76] drm/amd/dal: remove dal_adapter_service_should_optimize Harry Wentland
2016-11-21 23:01 ` [PATCH 48/76] drm/amd/dal: remove dal_adapter_service_get_feature_value Harry Wentland
2016-11-21 23:01 ` [PATCH 49/76] drm/amd/dal: remove adapter_service from Harry Wentland
2016-11-21 23:01 ` [PATCH 50/76] drm/amd/dal: remove adapter_service dependency Harry Wentland
2016-11-21 23:01 ` [PATCH 51/76] drm/amd/dal: remove SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT Harry Wentland
2016-11-21 23:01 ` [PATCH 52/76] drm/amd/dal: remove adapter_service and asic_capability Harry Wentland
2016-11-21 23:01 ` [PATCH 53/76] drm/amd/dal: Update stream_encoder programming sequence Harry Wentland
2016-11-21 23:01 ` [PATCH 54/76] drm/amd/dal: Disable bit depth reduction in set link test pattern Harry Wentland
2016-11-21 23:01 ` [PATCH 55/76] drm/amd/dal: Handle AUX error during RECIEVE state of transaction Harry Wentland
2016-11-21 23:01 ` [PATCH 56/76] drm/amd/dal: Remove unnecessary increment in scaler ratio calculation Harry Wentland
2016-11-21 23:01 ` [PATCH 57/76] drm/amd/dal: Add YCBCR420 to stream encoder Harry Wentland
2016-11-21 23:01 ` [PATCH 58/76] drm/amd/dal: Add surface log to dc Harry Wentland
2016-11-21 23:01 ` [PATCH 59/76] drm/amd/dal: add stoney bounding box to bw_calcs Harry Wentland
2016-11-21 23:01 ` [PATCH 60/76] drm/amd/dal: Implement DCHUB interface Harry Wentland
2016-11-21 23:01 ` [PATCH 61/76] drm/amd/dal: fix initial bw_calc parameters Harry Wentland
2016-11-21 23:01 ` [PATCH 62/76] drm/amd/dal: Don't read I2C_DATA register when in write mode Harry Wentland
2016-11-21 23:01 ` [PATCH 63/76] drm/amd/dal: disable break_to_debugger for bandwidth failures in diags Harry Wentland
2016-11-21 23:01 ` [PATCH 64/76] drm/amd/dal: PSR second monitor blackout fix Harry Wentland
2016-11-21 23:01 ` [PATCH 65/76] drm/amd/dal: Fixe linux compile error Harry Wentland
2016-11-21 23:01 ` [PATCH 66/76] drm/amd/dal: consolidate DCE hw_sequencer Harry Wentland
2016-11-21 23:01 ` [PATCH 67/76] " Harry Wentland
2016-11-21 23:01 ` [PATCH 68/76] drm/amd/dal: debug options Harry Wentland
2016-11-21 23:01 ` [PATCH 69/76] drm/amd/dal: remove dc_clock_gating in gpu Harry Wentland
2016-11-21 23:01 ` [PATCH 70/76] drm/amd/dal: dce_crtc_switch_to_clk_src Harry Wentland
2016-11-21 23:01 ` [PATCH 71/76] drm/amd/dal: include dm_services.h in reg_helper.h Harry Wentland
2016-11-21 23:01 ` [PATCH 72/76] drm/amd/dal: consolidate mem_input Harry Wentland
2016-11-21 23:01 ` [PATCH 73/76] drm/amd/dal: Add reg check before access Harry Wentland
2016-11-21 23:01 ` [PATCH 74/76] drm/amd/dal: Fix typo in mem_input Harry Wentland
2016-11-21 23:01 ` [PATCH 75/76] drm/amd/dal: Make bunch of scaler structs static Harry Wentland
2016-11-21 23:01 ` [PATCH 76/76] drm/amd/dal: Expose Polaris validate functions Harry Wentland
2016-11-23 0:06 ` [PATCH 00/76] DAL Patches Nov 21, 2016 Jerome Glisse
[not found] ` <20161123000638.GA3312-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-11-23 2:31 ` Harry Wentland
2016-11-23 18:56 ` Alex Deucher
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