From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 2/2] arm64: Work around Falkor erratum 1009
Date: Tue, 31 Jan 2017 14:38:44 +0000 [thread overview]
Message-ID: <20170131143843.GD22283@arm.com> (raw)
In-Reply-To: <20170130230818.9848-2-cov@codeaurora.org>
On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote:
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index deab52374119..fc434f421c7b 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -36,9 +36,21 @@
> * not. The macros handles invoking the asm with or without the
> * register argument as appropriate.
> */
> -#define __TLBI_0(op, arg) asm ("tlbi " #op)
> -#define __TLBI_1(op, arg) asm ("tlbi " #op ", %0" : : "r" (arg))
> -#define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg)
> +#define __TLBI_0(op, arg) asm volatile ("tlbi " #op "\n" \
> + ALTERNATIVE("nop\n nop", \
> + "dsb ish\n tlbi " #op, \
> + ARM64_WORKAROUND_REPEAT_TLBI, \
> + CONFIG_QCOM_FALKOR_ERRATUM_1009) \
> + : : )
> +
> +#define __TLBI_1(op, arg) asm volatile ("tlbi " #op ", %0\n" \
> + ALTERNATIVE("nop\n nop", \
> + "dsb ish\n tlbi " #op ", %0", \
> + ARM64_WORKAROUND_REPEAT_TLBI, \
> + CONFIG_QCOM_FALKOR_ERRATUM_1009) \
> + : : "r" (arg))
> +
Why are these now volatile? I asked the same question on the previous
version but didn't get a response:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-January/483579.html
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Christopher Covington <cov@codeaurora.org>
Cc: Jonathan Corbet <corbet@lwn.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Mark Rutland <mark.rutland@arm.com>,
linux-kernel@vger.kernel.org, shankerd@codeaurora.org,
timur@codeaurora.org, Mark Langsdorf <mlangsdo@redhat.com>,
Mark Salter <msalter@redhat.com>, Jon Masters <jcm@redhat.com>,
Neil Leeder <nleeder@codeaurora.org>
Subject: Re: [PATCH v5 2/2] arm64: Work around Falkor erratum 1009
Date: Tue, 31 Jan 2017 14:38:44 +0000 [thread overview]
Message-ID: <20170131143843.GD22283@arm.com> (raw)
In-Reply-To: <20170130230818.9848-2-cov@codeaurora.org>
On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote:
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index deab52374119..fc434f421c7b 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -36,9 +36,21 @@
> * not. The macros handles invoking the asm with or without the
> * register argument as appropriate.
> */
> -#define __TLBI_0(op, arg) asm ("tlbi " #op)
> -#define __TLBI_1(op, arg) asm ("tlbi " #op ", %0" : : "r" (arg))
> -#define __TLBI_N(op, arg, n, ...) __TLBI_##n(op, arg)
> +#define __TLBI_0(op, arg) asm volatile ("tlbi " #op "\n" \
> + ALTERNATIVE("nop\n nop", \
> + "dsb ish\n tlbi " #op, \
> + ARM64_WORKAROUND_REPEAT_TLBI, \
> + CONFIG_QCOM_FALKOR_ERRATUM_1009) \
> + : : )
> +
> +#define __TLBI_1(op, arg) asm volatile ("tlbi " #op ", %0\n" \
> + ALTERNATIVE("nop\n nop", \
> + "dsb ish\n tlbi " #op ", %0", \
> + ARM64_WORKAROUND_REPEAT_TLBI, \
> + CONFIG_QCOM_FALKOR_ERRATUM_1009) \
> + : : "r" (arg))
> +
Why are these now volatile? I asked the same question on the previous
version but didn't get a response:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-January/483579.html
Will
next prev parent reply other threads:[~2017-01-31 14:38 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-30 23:08 [PATCH v5 1/2] arm64: Work around Falkor erratum 1003 Christopher Covington
2017-01-30 23:08 ` Christopher Covington
2017-01-30 23:08 ` [PATCH v5 2/2] arm64: Work around Falkor erratum 1009 Christopher Covington
2017-01-30 23:08 ` Christopher Covington
2017-01-31 12:42 ` Mark Rutland
2017-01-31 12:42 ` Mark Rutland
2017-01-31 14:36 ` Will Deacon
2017-01-31 14:36 ` Will Deacon
2017-01-31 14:38 ` Will Deacon [this message]
2017-01-31 14:38 ` Will Deacon
2017-01-31 16:17 ` Christopher Covington
2017-01-31 16:17 ` Christopher Covington
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