[Qemu-devel] [PATCH Risu 0/5] PPC64 Improvements

[Qemu-devel] [PATCH Risu 0/5] PPC64 Improvements

[Jose Ricardo Ziviani]

This patchset include initial support to PPC64 (Big-Endian), that is pretty much the same: only some fixes in configure and risugen.
Also, it adds a better random initialization of VSX registers.
And does some cleanup.

Jose Ricardo Ziviani (5):
  risugen_ppc64: Load random 128-bit data to VSX registers
  risu_reginfo_ppc64le: Remove unused code from PPC64 register
    comparison
  configure: Add initial support to PPC64 (big endian)
  risugen,risugen_ppc64.pm: Add support ppc64 (big-endian)
  risugen_ppc64: Remove unused code

 configure              |  9 ++++-----
 risu_reginfo_ppc64le.c |  8 --------
 risugen                |  6 +++++-
 risugen_ppc64.pm       | 48 +++++++++++++++++++++++++++++++++---------------
 4 files changed, 42 insertions(+), 29 deletions(-)

-- 
2.7.4

[Qemu-devel] [PATCH Risu 1/5] risugen_ppc64: Load random 128-bit data to VSX registers

[Jose Ricardo Ziviani]

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 risugen_ppc64.pm | 40 +++++++++++++++++++++++++++++-----------
 1 file changed, 29 insertions(+), 11 deletions(-)

diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index cb75300..28b6792 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -99,6 +99,29 @@ sub write_mov_ri64($$)
     insn32((0x3e << 26) | (20 << 21) | (1 << 16) | 0x10);
 }
 
+sub write_mov_ri128($$$$)
+{
+    my ($imhh, $imh, $iml, $imll) = @_;
+
+    # store the lowest 32 bits
+    write_mov_ri32(20, $imll);
+    # stw r20, 16(r1)
+    insn32((0x24 << 26) | (20 << 21) | (1 << 16) | 0x10);
+    # store the lower 32 bits
+    write_mov_ri32(20, $iml);
+    # stw r20, 20(r1)
+    insn32((0x24 << 26) | (20 << 21) | (1 << 16) | 0x14);
+    # store the higher 32 bits
+    write_mov_ri32(20, $imh);
+    # stw r20, 24(r1)
+    insn32((0x24 << 26) | (20 << 21) | (1 << 16) | 0x18);
+    # store the highest 32 bits
+    write_mov_ri32(20, $imhh);
+    # stw r20, 28(r1)
+    insn32((0x24 << 26) | (20 << 21) | (1 << 16) | 0x1c);
+
+}
+
 sub write_random_ppc64_fpdata()
 {
     for (my $i = 0; $i < 32; $i++) {
@@ -106,22 +129,16 @@ sub write_random_ppc64_fpdata()
         write_mov_ri64(rand(0xfffff), rand(0xfffff));
         # since the EA is r1+16, load such value in FP reg
         insn32((0x32 << 26) | ($i << 21) | (0x1 << 16) | 0x10);
-        insn32((0x39 << 26) | ($i << 21) | (0x1 << 16) | 0x12);
-
     }
 }
 
-sub write_random_ppc64_fpdata_i()
+sub write_random_ppc64_vsxdata()
 {
-    # get an space from the stack
-    insn32(0x3ac10020); # addi r22, r1, 32
-    insn32(0x3ee03ff0); # lis r23, 0x3ff0
-    insn32(0x3af70000); # addi r23, r23, 0
-    insn32(0xfaf60000); # std r23, 0(r22)
-
     for (my $i = 0; $i < 32; $i++) {
-        # lfd f$i, 0(r22)
-        insn32((0x32 << 26 | $i << 21 | 0x16 << 16));
+        # load a random doubleword value at r0
+        write_mov_ri128(rand(0xffff), rand(0xffff), rand(0xfffff), rand(0xfffff));
+        # load the 128-bit data in a vector register
+        insn32((0x39 << 26) | ($i << 21) | (0x1 << 16) | 0x12);
     }
 }
 
@@ -172,6 +189,7 @@ sub write_random_register_data($)
 
     clear_vr_registers();
 
+    write_random_ppc64_vsxdata();
     if ($fp_enabled) {
         # load floating point / SIMD registers
         write_random_ppc64_fpdata();
-- 
2.7.4

Re: [Qemu-devel] [PATCH Risu 1/5] risugen_ppc64: Load random 128-bit data to VSX registers

[Nikunj A Dadhania]

Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> writes:

> Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
> ---
>  risugen_ppc64.pm | 40 +++++++++++++++++++++++++++++-----------
>  1 file changed, 29 insertions(+), 11 deletions(-)
>
> diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
> index cb75300..28b6792 100644
> --- a/risugen_ppc64.pm
> +++ b/risugen_ppc64.pm
> @@ -99,6 +99,29 @@ sub write_mov_ri64($$)
>      insn32((0x3e << 26) | (20 << 21) | (1 << 16) | 0x10);
>  }
>
> +sub write_mov_ri128($$$$)
> +{
> +    my ($imhh, $imh, $iml, $imll) = @_;
> +
> +    # store the lowest 32 bits
> +    write_mov_ri32(20, $imll);
> +    # stw r20, 16(r1)
> +    insn32((0x24 << 26) | (20 << 21) | (1 << 16) | 0x10);
> +    # store the lower 32 bits
> +    write_mov_ri32(20, $iml);
> +    # stw r20, 20(r1)
> +    insn32((0x24 << 26) | (20 << 21) | (1 << 16) | 0x14);
> +    # store the higher 32 bits
> +    write_mov_ri32(20, $imh);
> +    # stw r20, 24(r1)
> +    insn32((0x24 << 26) | (20 << 21) | (1 << 16) | 0x18);
> +    # store the highest 32 bits
> +    write_mov_ri32(20, $imhh);
> +    # stw r20, 28(r1)
> +    insn32((0x24 << 26) | (20 << 21) | (1 << 16) | 0x1c);
> +
> +}
> +
>  sub write_random_ppc64_fpdata()
>  {
>      for (my $i = 0; $i < 32; $i++) {
> @@ -106,22 +129,16 @@ sub write_random_ppc64_fpdata()
>          write_mov_ri64(rand(0xfffff), rand(0xfffff));
>          # since the EA is r1+16, load such value in FP reg
>          insn32((0x32 << 26) | ($i << 21) | (0x1 << 16) | 0x10);
> -        insn32((0x39 << 26) | ($i << 21) | (0x1 << 16) | 0x12);
> -
>      }
>  }
>
> -sub write_random_ppc64_fpdata_i()
> +sub write_random_ppc64_vsxdata()
>  {
> -    # get an space from the stack
> -    insn32(0x3ac10020); # addi r22, r1, 32
> -    insn32(0x3ee03ff0); # lis r23, 0x3ff0
> -    insn32(0x3af70000); # addi r23, r23, 0
> -    insn32(0xfaf60000); # std r23, 0(r22)
> -
>      for (my $i = 0; $i < 32; $i++) {
> -        # lfd f$i, 0(r22)
> -        insn32((0x32 << 26 | $i << 21 | 0x16 << 16));
> +        # load a random doubleword value at r0
> +        write_mov_ri128(rand(0xffff), rand(0xffff), rand(0xfffff), rand(0xfffff));
> +        # load the 128-bit data in a vector register
> +        insn32((0x39 << 26) | ($i << 21) | (0x1 << 16) | 0x12);

I think thats lxsd(ISA 3.0), and that only loads a doubleword and not a
quad word. Can't we use "lxv" (ISA 2.03) or "mtvsrdd" (ISA 3.0)

I would suggest lxv, as it will enable us to test older machines.

Regards
Nikunj

[Qemu-devel] [PATCH Risu 2/5] risu_reginfo_ppc64le: Remove unused code from PPC64 register comparison

[Jose Ricardo Ziviani]

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 risu_reginfo_ppc64le.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/risu_reginfo_ppc64le.c b/risu_reginfo_ppc64le.c
index e6bc0e0..a76f296 100644
--- a/risu_reginfo_ppc64le.c
+++ b/risu_reginfo_ppc64le.c
@@ -86,14 +86,6 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a, ucontext_t *uc)
                 m->vrregs.vrregs[i][1] != a->vrregs.vrregs[i][1] ||
                 m->vrregs.vrregs[i][2] != a->vrregs.vrregs[i][2] ||
                 m->vrregs.vrregs[i][3] != a->vrregs.vrregs[i][3]) {
-
-            if (uc != NULL && (m->gregs[CCR] & 0x10)) {
-                uc->uc_mcontext.v_regs->vrregs[i][0] = a->vrregs.vrregs[i][0];
-                uc->uc_mcontext.v_regs->vrregs[i][1] = a->vrregs.vrregs[i][1];
-                uc->uc_mcontext.v_regs->vrregs[i][2] = a->vrregs.vrregs[i][2];
-                uc->uc_mcontext.v_regs->vrregs[i][3] = a->vrregs.vrregs[i][3];
-                return 1;
-            }
             return 0;
         }
     }
-- 
2.7.4

Re: [Qemu-devel] [PATCH Risu 2/5] risu_reginfo_ppc64le: Remove unused code from PPC64 register comparison

[Peter Maydell]

On 27 February 2017 at 19:41, Jose Ricardo Ziviani
<joserz@linux.vnet.ibm.com> wrote:
> Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
> ---
>  risu_reginfo_ppc64le.c | 8 --------
>  1 file changed, 8 deletions(-)
>
> diff --git a/risu_reginfo_ppc64le.c b/risu_reginfo_ppc64le.c
> index e6bc0e0..a76f296 100644
> --- a/risu_reginfo_ppc64le.c
> +++ b/risu_reginfo_ppc64le.c
> @@ -86,14 +86,6 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a, ucontext_t *uc)
>                  m->vrregs.vrregs[i][1] != a->vrregs.vrregs[i][1] ||
>                  m->vrregs.vrregs[i][2] != a->vrregs.vrregs[i][2] ||
>                  m->vrregs.vrregs[i][3] != a->vrregs.vrregs[i][3]) {
> -
> -            if (uc != NULL && (m->gregs[CCR] & 0x10)) {
> -                uc->uc_mcontext.v_regs->vrregs[i][0] = a->vrregs.vrregs[i][0];
> -                uc->uc_mcontext.v_regs->vrregs[i][1] = a->vrregs.vrregs[i][1];
> -                uc->uc_mcontext.v_regs->vrregs[i][2] = a->vrregs.vrregs[i][2];
> -                uc->uc_mcontext.v_regs->vrregs[i][3] = a->vrregs.vrregs[i][3];
> -                return 1;
> -            }
>              return 0;
>          }
>      }
> --

I have a variation on this patch already in my set of refactoring
patches that I posted last week:

https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg06152.html

thanks
-- PMM

Re: [Qemu-devel] [PATCH Risu 2/5] risu_reginfo_ppc64le: Remove unused code from PPC64 register comparison

[joserz]

On Tue, Feb 28, 2017 at 01:43:22PM +0000, Peter Maydell wrote:
> On 27 February 2017 at 19:41, Jose Ricardo Ziviani
> <joserz@linux.vnet.ibm.com> wrote:
> > Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
> > ---
> >  risu_reginfo_ppc64le.c | 8 --------
> >  1 file changed, 8 deletions(-)
> >
> > diff --git a/risu_reginfo_ppc64le.c b/risu_reginfo_ppc64le.c
> > index e6bc0e0..a76f296 100644
> > --- a/risu_reginfo_ppc64le.c
> > +++ b/risu_reginfo_ppc64le.c
> > @@ -86,14 +86,6 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a, ucontext_t *uc)
> >                  m->vrregs.vrregs[i][1] != a->vrregs.vrregs[i][1] ||
> >                  m->vrregs.vrregs[i][2] != a->vrregs.vrregs[i][2] ||
> >                  m->vrregs.vrregs[i][3] != a->vrregs.vrregs[i][3]) {
> > -
> > -            if (uc != NULL && (m->gregs[CCR] & 0x10)) {
> > -                uc->uc_mcontext.v_regs->vrregs[i][0] = a->vrregs.vrregs[i][0];
> > -                uc->uc_mcontext.v_regs->vrregs[i][1] = a->vrregs.vrregs[i][1];
> > -                uc->uc_mcontext.v_regs->vrregs[i][2] = a->vrregs.vrregs[i][2];
> > -                uc->uc_mcontext.v_regs->vrregs[i][3] = a->vrregs.vrregs[i][3];
> > -                return 1;
> > -            }
> >              return 0;
> >          }
> >      }
> > --
> 
> I have a variation on this patch already in my set of refactoring
> patches that I posted last week:
> 
> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg06152.html

Sorry, I missed that commit. I'll send a v2 with the fix suggested by
Nikunj and without this one.

Thanks Peter

> 
> thanks
> -- PMM
> 

Re: [Qemu-devel] [PATCH Risu 2/5] risu_reginfo_ppc64le: Remove unused code from PPC64 register comparison

[Peter Maydell]

On 28 February 2017 at 14:29,  <joserz@linux.vnet.ibm.com> wrote:
> On Tue, Feb 28, 2017 at 01:43:22PM +0000, Peter Maydell wrote:
>> I have a variation on this patch already in my set of refactoring
>> patches that I posted last week:
>>
>> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg06152.html
>
> Sorry, I missed that commit. I'll send a v2 with the fix suggested by
> Nikunj and without this one.

No problem. I've just pushed that refactoring series to risu master
so you probably want to rebase on that. I've also grabbed patch 5
of this series because it was an obvious change.

thanks
-- PMM

[Qemu-devel] [PATCH Risu 3/5] configure: Add initial support to PPC64 (big endian)

[Jose Ricardo Ziviani]

This commit set Makefile to point to ppc64le source for both archs
(ppc64 and ppc64le) because they do the exact same thing. The
difference is in risugen and how the binary is build.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 configure | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/configure b/configure
index 1fbc27c..5a91f57 100755
--- a/configure
+++ b/configure
@@ -38,11 +38,7 @@ guess_arch() {
     elif check_define __aarch64__ ; then
         ARCH="aarch64"
     elif check_define __powerpc64__ ; then
-        if check_define __BIG_ENDIAN__; then
-            ARCH="ppc64"
-        else
-            ARCH="ppc64le"
-        fi
+        ARCH="ppc64le"
     else
         echo "This cpu is not supported by risu. Try -h. " >&2
         exit 1
@@ -114,6 +110,9 @@ OBJDUMP="${OBJDUMP-${CROSS_PREFIX}objdump}"
 
 if test "x${ARCH}" = "x"; then
     guess_arch
+elif test "x${ARCH}" = "xppc64"; then
+    # ppc64 and ppc64le uses the same C source code
+    ARCH="ppc64le"
 fi
 
 generate_makefilein
-- 
2.7.4

[Qemu-devel] [PATCH Risu 4/5] risugen, risugen_ppc64.pm: Add support ppc64 (big-endian)

[Jose Ricardo Ziviani]

This commit adds an option to risugen in order to give the opportunity
to generated big-endian instructions. By passing --be, users force
risugen to generated big-endian instructions for ppc64.

./risugen --be --numinsns 1000 --pattern "ADD" ppc64.risu test.bin
./risugen --numinsns 1000 --pattern "ADD" ppc64.risu test.bin

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 risugen          | 6 +++++-
 risugen_ppc64.pm | 4 ++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/risugen b/risugen
index 6aad626..086173c 100755
--- a/risugen
+++ b/risugen
@@ -264,6 +264,7 @@ Valid options:
                    a general set you have excluded.
      --no-fp      : disable floating point: no fp init, randomization etc.
                    Useful to test before support for FP is available.
+    --be         : generate instructions in Big-Endian order (ppc64 only).
     --help       : print this message
 EOT
 }
@@ -274,6 +275,7 @@ sub main()
     my $condprob = 0;
     my $fpscr = 0;
     my $fp_enabled = 1;
+    my $big_endian = 0;
     my ($infile, $outfile);
 
     GetOptions( "help" => sub { usage(); exit(0); },
@@ -287,6 +289,7 @@ sub main()
                         die "Value \"$condprob\" invalid for option condprob (must be between 0 and 1)\n";
                     }
                 },
+                "be" => sub { $big_endian = 1; },
                 "no-fp" => sub { $fp_enabled = 0; },
         ) or return 1;
     # allow "--pattern re,re" and "--pattern re --pattern re"
@@ -317,7 +320,8 @@ sub main()
         'not_pattern_re' => \@not_pattern_re,
         'details' => \%insn_details,
         'arch' => $full_arch[0],
-        'subarch' => $full_arch[1] || ''
+        'subarch' => $full_arch[1] || '',
+        'bigendian' => $big_endian
     );
 
     write_test_code(\%params);
diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 28b6792..46ab7b1 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -373,6 +373,10 @@ sub write_test_code($)
     my @not_pattern_re = @{ $params->{ 'not_pattern_re' } };
     my %insn_details = %{ $params->{ 'details' } };
 
+    if ($params->{ 'bigendian' } eq 1) {
+        set_endian(1);
+    }
+
     open_bin($outfile);
 
     # convert from probability that insn will be conditional to
-- 
2.7.4

[Qemu-devel] [PATCH Risu 5/5] risugen_ppc64: Remove unused code

[Jose Ricardo Ziviani]

Because we don't support custom fpsrc value yet it's better to remove
that code.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 risugen_ppc64.pm | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm
index 46ab7b1..4f7c709 100644
--- a/risugen_ppc64.pm
+++ b/risugen_ppc64.pm
@@ -404,10 +404,6 @@ sub write_test_code($)
     print "Generating code using patterns: @keys...\n";
     progress_start(78, $numinsns);
 
-    #if ($fp_enabled) {
-    #    write_set_fpscr($fpscr);
-    #}
-
     if (grep { defined($insn_details{$_}->{blocks}->{"memory"}) } @keys) {
         write_memblock_setup();
     }
-- 
2.7.4