From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Antoine Tenart <antoine.tenart@free-electrons.com>,
herbert@gondor.apana.org.au, davem@davemloft.net,
jason@lakedaemon.net, andrew@lunn.ch,
gregory.clement@free-electrons.com,
sebastian.hesselbarth@gmail.com,
boris.brezillon@free-electrons.com, igall@marvell.com,
nadavh@marvell.com, linux-crypto@vger.kernel.org,
robin.murphy@arm.com, oferh@marvell.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 1/3] Documentation/bindings: Document the SafeXel cryptographic engine driver
Date: Tue, 23 May 2017 14:56:27 +0200 [thread overview]
Message-ID: <20170523145627.63054e08@free-electrons.com> (raw)
In-Reply-To: <9a3961ee-1396-cc8f-64ca-12beacf75c2a@arm.com>
Hello,
On Tue, 23 May 2017 12:13:28 +0100, Marc Zyngier wrote:
> > The crypto block being in the CP part, it has a wired interrupt to the
> > ICU (also in the CP). The ICU then turns this wired interrupt into a
> > memory write transaction to a register called GICP SPI in the AP, which
> > triggers a SPI interrupt in the GIC.
>
> Is that some kind of Level-triggered MSI, à la GICv3 GICD_SETSPI_NSR?
It is some kind of MSI, and the registers are called
GICP_SETSPI/GICP_CLRSPI, so I would assume it's quite similar to this
GICv3 feature.
> > However, I have a patch series that I plan to submit hopefully in the
> > next days that adds an ICU driver, and changes the Device Tree to refer
> > to the ICU interrupt instead.
>
> OK, I'm quite interested to see that, specially if my above hunch is
> right...
I'll send the patches soon. I'm sure there will be lots of comments :)
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
WARNING: multiple messages have this Message-ID (diff)
From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/3] Documentation/bindings: Document the SafeXel cryptographic engine driver
Date: Tue, 23 May 2017 14:56:27 +0200 [thread overview]
Message-ID: <20170523145627.63054e08@free-electrons.com> (raw)
In-Reply-To: <9a3961ee-1396-cc8f-64ca-12beacf75c2a@arm.com>
Hello,
On Tue, 23 May 2017 12:13:28 +0100, Marc Zyngier wrote:
> > The crypto block being in the CP part, it has a wired interrupt to the
> > ICU (also in the CP). The ICU then turns this wired interrupt into a
> > memory write transaction to a register called GICP SPI in the AP, which
> > triggers a SPI interrupt in the GIC.
>
> Is that some kind of Level-triggered MSI, ? la GICv3 GICD_SETSPI_NSR?
It is some kind of MSI, and the registers are called
GICP_SETSPI/GICP_CLRSPI, so I would assume it's quite similar to this
GICv3 feature.
> > However, I have a patch series that I plan to submit hopefully in the
> > next days that adds an ICU driver, and changes the Device Tree to refer
> > to the ICU interrupt instead.
>
> OK, I'm quite interested to see that, specially if my above hunch is
> right...
I'll send the patches soon. I'm sure there will be lots of comments :)
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
next prev parent reply other threads:[~2017-05-23 12:56 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-24 7:54 [PATCH v3 0/3] arm64: marvell: add cryptographic engine support for 7k/8k Antoine Tenart
2017-04-24 7:54 ` Antoine Tenart
2017-04-24 7:54 ` [PATCH v3 1/3] Documentation/bindings: Document the SafeXel cryptographic engine driver Antoine Tenart
2017-04-24 7:54 ` Antoine Tenart
2017-05-03 16:36 ` Marc Zyngier
2017-05-03 16:36 ` Marc Zyngier
2017-05-22 14:30 ` Antoine Tenart
2017-05-22 14:30 ` Antoine Tenart
2017-05-22 14:48 ` Marc Zyngier
2017-05-22 14:48 ` Marc Zyngier
2017-05-22 14:54 ` Antoine Tenart
2017-05-22 14:54 ` Antoine Tenart
2017-05-22 15:02 ` Marc Zyngier
2017-05-22 15:02 ` Marc Zyngier
2017-05-22 19:37 ` Thomas Petazzoni
2017-05-22 19:37 ` Thomas Petazzoni
2017-05-23 11:13 ` Marc Zyngier
2017-05-23 11:13 ` Marc Zyngier
2017-05-23 12:56 ` Thomas Petazzoni [this message]
2017-05-23 12:56 ` Thomas Petazzoni
2017-04-24 7:54 ` [PATCH v3 2/3] crypto: inside-secure: add SafeXcel EIP197 crypto " Antoine Tenart
2017-04-24 7:54 ` Antoine Tenart
2017-04-24 8:50 ` Igal Liberman
2017-04-24 8:50 ` Igal Liberman
2017-04-24 8:57 ` Antoine Tenart
2017-04-24 8:57 ` Antoine Tenart
2017-05-03 17:14 ` Robin Murphy
2017-05-03 17:14 ` Robin Murphy
2017-05-08 8:46 ` Igal Liberman
2017-05-08 8:46 ` Igal Liberman
2017-04-24 12:59 ` Stephan Müller
2017-04-24 12:59 ` Stephan Müller
2017-04-25 6:53 ` Antoine Tenart
2017-04-25 6:53 ` Antoine Tenart
2017-05-03 11:57 ` Robin Murphy
2017-05-03 11:57 ` Robin Murphy
2017-05-03 14:03 ` Antoine Tenart
2017-05-03 14:03 ` Antoine Tenart
2017-04-24 7:54 ` [PATCH v3 3/3] MAINTAINERS: add a maintainer for the Inside Secure crypto driver Antoine Tenart
2017-04-24 7:54 ` Antoine Tenart
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