From: Shawn Guo <shawnguo@kernel.org>
To: "A.S. Dong" <aisheng.dong@nxp.com>
Cc: Stefan Agner <stefan@agner.ch>,
Mark Rutland <mark.rutland@arm.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Andy Duan <fugang.duan@nxp.com>, Jacky Bai <ping.bai@nxp.com>,
"linus.walleij@linaro.org" <linus.walleij@linaro.org>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH V2 4/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc
Date: Thu, 25 May 2017 11:16:21 +0800 [thread overview]
Message-ID: <20170525031620.GS26102@dragon> (raw)
In-Reply-To: <DBXPR04MB320A55DE4386DE561A1D4DC80F90@DBXPR04MB320.eurprd04.prod.outlook.com>
On Tue, May 23, 2017 at 10:37:27AM +0000, A.S. Dong wrote:
> > > +#ifndef __DTS_IMX7ULP_PINFUNC_H
> > > +#define __DTS_IMX7ULP_PINFUNC_H
> > > +
> > > +/*
> > > + * The pin function ID is a tuple of
> > > + * <mux_conf_reg input_reg mux_mode input_val> */
> > > +
> > > +#define ULP1_PAD_PTC0__PTC0
> > > 0x0000 0x0000 0x1 0x0
> >
> >
> > For consistency with other SoCs, can we add MX7 to the define? E.g.
> > MX7ULP1?
> >
>
> ULP1 is another SoC name of IMX7ULP.
> And there will be ULP0, ULPx in the future..
What is the external/formal SoC name for ULP0 and ULPx?
>
> It looks like not big issue, so I did not change it.
It's an easy change to make things more obvious, so +1 on Stefan's
opinion.
Shawn
WARNING: multiple messages have this Message-ID (diff)
From: shawnguo@kernel.org (Shawn Guo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V2 4/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc
Date: Thu, 25 May 2017 11:16:21 +0800 [thread overview]
Message-ID: <20170525031620.GS26102@dragon> (raw)
In-Reply-To: <DBXPR04MB320A55DE4386DE561A1D4DC80F90@DBXPR04MB320.eurprd04.prod.outlook.com>
On Tue, May 23, 2017 at 10:37:27AM +0000, A.S. Dong wrote:
> > > +#ifndef __DTS_IMX7ULP_PINFUNC_H
> > > +#define __DTS_IMX7ULP_PINFUNC_H
> > > +
> > > +/*
> > > + * The pin function ID is a tuple of
> > > + * <mux_conf_reg input_reg mux_mode input_val> */
> > > +
> > > +#define ULP1_PAD_PTC0__PTC0
> > > 0x0000 0x0000 0x1 0x0
> >
> >
> > For consistency with other SoCs, can we add MX7 to the define? E.g.
> > MX7ULP1?
> >
>
> ULP1 is another SoC name of IMX7ULP.
> And there will be ULP0, ULPx in the future..
What is the external/formal SoC name for ULP0 and ULPx?
>
> It looks like not big issue, so I did not change it.
It's an easy change to make things more obvious, so +1 on Stefan's
opinion.
Shawn
next prev parent reply other threads:[~2017-05-25 3:17 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-19 7:05 [PATCH V2 0/5] pinctrl: imx: add generic pin config and imx7ulp support Dong Aisheng
2017-05-19 7:05 ` Dong Aisheng
2017-05-19 7:05 ` [PATCH V2 1/5] pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case Dong Aisheng
2017-05-19 7:05 ` Dong Aisheng
2017-05-21 9:27 ` Shawn Guo
2017-05-21 9:27 ` Shawn Guo
2017-05-22 9:02 ` Linus Walleij
2017-05-22 9:02 ` Linus Walleij
2017-05-19 7:05 ` [PATCH V2 2/5] pinctrl: imx: add generic pin config core support Dong Aisheng
2017-05-19 7:05 ` Dong Aisheng
2017-05-21 9:27 ` Shawn Guo
2017-05-21 9:27 ` Shawn Guo
2017-05-22 9:04 ` Linus Walleij
2017-05-22 9:04 ` Linus Walleij
2017-05-19 7:05 ` [PATCH V2 3/5] pinctrl: imx: add soc specific mux_mode mask and shift property Dong Aisheng
2017-05-19 7:05 ` Dong Aisheng
2017-05-21 9:28 ` Shawn Guo
2017-05-21 9:28 ` Shawn Guo
2017-05-22 9:06 ` Linus Walleij
2017-05-22 9:06 ` Linus Walleij
2017-05-19 7:05 ` [PATCH V2 4/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc Dong Aisheng
2017-05-19 7:05 ` Dong Aisheng
2017-05-22 9:27 ` Linus Walleij
2017-05-22 9:27 ` Linus Walleij
[not found] ` <CACRpkdb6B-f0uHUo9ecUmGCzY8GfFbCjNtJFeQJqtKEYwyB87A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-05-22 12:30 ` A.S. Dong
2017-05-22 12:30 ` A.S. Dong
[not found] ` <1495177545-23006-5-git-send-email-aisheng.dong-3arQi8VN3Tc@public.gmane.org>
2017-05-21 9:30 ` Shawn Guo
2017-05-21 9:30 ` Shawn Guo
2017-05-21 9:40 ` A.S. Dong
2017-05-21 9:40 ` A.S. Dong
[not found] ` <AM3PR04MB306654DEA7C2B7676D5C0EC80FB0-f56W/S9L6NSIzFHTN1kKrAfhPeD8jYilXA4E9RH9d+qIuWR1G4zioA@public.gmane.org>
2017-05-21 11:00 ` Shawn Guo
2017-05-21 11:00 ` Shawn Guo
2017-05-22 16:15 ` Stefan Agner
2017-05-22 16:15 ` Stefan Agner
2017-05-23 10:37 ` A.S. Dong
2017-05-23 10:37 ` A.S. Dong
2017-05-25 3:16 ` Shawn Guo [this message]
2017-05-25 3:16 ` Shawn Guo
2017-05-25 5:04 ` A.S. Dong
2017-05-25 5:04 ` A.S. Dong
[not found] ` <AM3PR04MB3068FA0B94C9B0D6269FC9C80FF0-f56W/S9L6NSIzFHTN1kKrAfhPeD8jYilXA4E9RH9d+qIuWR1G4zioA@public.gmane.org>
2017-05-25 6:23 ` Shawn Guo
2017-05-25 6:23 ` Shawn Guo
2017-05-25 6:48 ` Stefan Agner
2017-05-25 6:48 ` Stefan Agner
2017-05-19 7:05 ` [PATCH V2 5/5] pinctrl: imx: add imx7ulp driver Dong Aisheng
2017-05-19 7:05 ` Dong Aisheng
2017-05-21 9:31 ` Shawn Guo
2017-05-21 9:31 ` Shawn Guo
2017-05-23 7:41 ` [PATCH V2 0/5] pinctrl: imx: add generic pin config and imx7ulp support Linus Walleij
2017-05-23 7:41 ` Linus Walleij
2017-05-23 9:17 ` A.S. Dong
2017-05-23 9:17 ` A.S. Dong
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