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From: leon@kernel.org (Leon Romanovsky)
Subject: [PATCH v2 2/2] IB/mlx5: set UMR wqe fence according to HCA cap
Date: Tue, 30 May 2017 20:15:02 +0300	[thread overview]
Message-ID: <20170530171502.GC5406@mtr-leonro.local> (raw)
In-Reply-To: <d23a5a6f-bd9f-3b1a-34d5-25e8eb2a041c@grimberg.me>

On Tue, May 30, 2017@01:51:33PM +0300, Sagi Grimberg wrote:
> Leon,
>
> > > We don't fence those WR's.
> > > Christoph just re-write it to be more intuitive code. I don't see logic
> > > difference, am I wrong here ?
> >
> > A little bit, before Christoph's suggestion, we calculated fence for
> > the paths which need such fence, after we will calculate for all paths.
>
> Every WQE posted to a send queue must include a fence bit. All work
> request posted on the send queue calculate the required fence, this
> used to happen in finish_wqe call-sites with get_fence(), Christoph
> just inlin'ed it.

Sagi,

Thanks, I found my mistake, I saw that IB_SEND_INLINE WR doesn't call to
get_fence and we have an if() which can skip finish_wqe, so I thought
that finish_wqe isn't called always, however it was for error path.

Thanks again.
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WARNING: multiple messages have this Message-ID (diff)
From: Leon Romanovsky <leon-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Sagi Grimberg <sagi-NQWnxTmZq1alnMjI0IkVqw@public.gmane.org>
Cc: Max Gurtovoy <maxg-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>,
	Christoph Hellwig <hch-jcswGhMUV9g@public.gmane.org>,
	linux-nvme-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	shahar.salzman-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
	joseph.r.gruher-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
	mrybczyn-FNhOzJFKnXGHXe+LvDLADg@public.gmane.org,
	vladimirk-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org,
	oren-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org
Subject: Re: [PATCH v2 2/2] IB/mlx5: set UMR wqe fence according to HCA cap
Date: Tue, 30 May 2017 20:15:02 +0300	[thread overview]
Message-ID: <20170530171502.GC5406@mtr-leonro.local> (raw)
In-Reply-To: <d23a5a6f-bd9f-3b1a-34d5-25e8eb2a041c-NQWnxTmZq1alnMjI0IkVqw@public.gmane.org>

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On Tue, May 30, 2017 at 01:51:33PM +0300, Sagi Grimberg wrote:
> Leon,
>
> > > We don't fence those WR's.
> > > Christoph just re-write it to be more intuitive code. I don't see logic
> > > difference, am I wrong here ?
> >
> > A little bit, before Christoph's suggestion, we calculated fence for
> > the paths which need such fence, after we will calculate for all paths.
>
> Every WQE posted to a send queue must include a fence bit. All work
> request posted on the send queue calculate the required fence, this
> used to happen in finish_wqe call-sites with get_fence(), Christoph
> just inlin'ed it.

Sagi,

Thanks, I found my mistake, I saw that IB_SEND_INLINE WR doesn't call to
get_fence and we have an if() which can skip finish_wqe, so I thought
that finish_wqe isn't called always, however it was for error path.

Thanks again.

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  reply	other threads:[~2017-05-30 17:15 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-28  7:53 [PATCH v2 1/2] net/mlx5: Define interface bits for fencing UMR wqe Max Gurtovoy
2017-05-28  7:53 ` Max Gurtovoy
2017-05-28  7:53 ` [PATCH v2 2/2] IB/mlx5: set UMR wqe fence according to HCA cap Max Gurtovoy
2017-05-28  7:53   ` Max Gurtovoy
2017-05-28  9:07   ` Christoph Hellwig
2017-05-28  9:07     ` Christoph Hellwig
2017-05-28  9:53     ` Max Gurtovoy
2017-05-28  9:53       ` Max Gurtovoy
2017-05-29 10:05       ` Leon Romanovsky
2017-05-29 10:05         ` Leon Romanovsky
2017-05-29 12:21         ` Max Gurtovoy
2017-05-29 12:21           ` Max Gurtovoy
2017-05-29 16:06           ` Leon Romanovsky
2017-05-29 16:06             ` Leon Romanovsky
2017-05-30 10:51             ` Sagi Grimberg
2017-05-30 10:51               ` Sagi Grimberg
2017-05-30 17:15               ` Leon Romanovsky [this message]
2017-05-30 17:15                 ` Leon Romanovsky
2017-05-30 10:48   ` Sagi Grimberg
2017-05-30 10:48     ` Sagi Grimberg
2017-05-30 11:15     ` Max Gurtovoy
2017-05-30 11:15       ` Max Gurtovoy
2017-05-30 11:22       ` Sagi Grimberg
2017-05-30 11:22         ` Sagi Grimberg
2017-05-30 11:24         ` Max Gurtovoy
2017-05-30 11:24           ` Max Gurtovoy
2017-05-30 14:28           ` Sagi Grimberg
2017-05-30 14:28             ` Sagi Grimberg
2017-05-30 20:41             ` Max Gurtovoy
2017-05-30 20:41               ` Max Gurtovoy
2017-05-28  9:14 ` [PATCH v2 1/2] net/mlx5: Define interface bits for fencing UMR wqe Christoph Hellwig
2017-05-28  9:14   ` Christoph Hellwig
2017-06-01 22:51 ` Doug Ledford
2017-06-01 22:51   ` Doug Ledford

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