[PATCH 00/23] Prep patches for new asics

[PATCH 00/23] Prep patches for new asics

[Alex Deucher]

This set of patches updates various infrastructure in the driver
to support new asics.

Alex Deucher (3):
  drm/amdgpu: switch ih handling to two levels
  drm/amdgpu/ih: store the full context id
  drm/amdgpu: add asic callback to get memsize register

Alex Xie (2):
  drm/amdgpu: set GART PTE asic specific flags
  drm/amdgpu: add a callback to set vm mapping flags

Chunming Zhou (1):
  drm/amdgpu: expand pte flags to uint64_t

Huang Rui (3):
  drm/amdgpu: add a ucode size member into firmware info
  drm/amdgpu: add DRM MGCG header
  drm/amdgpu: add DF MGCG flag

Junwei Zhang (1):
  drm/amdgpu: init aperture definitions

Ken Wang (3):
  drm/amdgpu: change wptr to 64 bits
  drm/amdgpu: add 64bit wb functions
  drm/amdgpu: add 64bit doorbell functions

Leo Liu (9):
  drm/amdgpu: add a ring func for end command
  drm/amdgpu: move amdgpu_uvd structure to uvd header
  drm/amdgpu: move amdgpu_vce structure to vce header
  drm/amdgpu: add uvd enc rings
  drm/amdgpu: add uvd enc run queue
  drm/amdgpu: add uvd enc ring type and functions
  uapi/drm: add AMDGPU_HW_IP_UVD_ENC
  drm/amdgpu: add AMDGPU_HW_IP_UVD_ENC to info query
  drm/amdgpu: get cs support of AMDGPU_HW_IP_UVD_ENC

Rex Zhu (1):
  drm/amdgpu: check function points valid before use.

 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  89 +++++++----------------
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c    |  24 +++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     |   9 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  93 ++++++++++++++++++++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c   |   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    |  12 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c     |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h     |  10 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c    | 111 ++++++++++++++++++++---------
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h    |  10 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c    |  10 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  60 +++++++++++-----
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h   |  19 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    |  10 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c  |   7 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h  |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h    |  29 ++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h    |  25 +++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     |  18 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h     |   6 ++
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c        |   6 +-
 drivers/gpu/drm/amd/amdgpu/cik.c           |   6 ++
 drivers/gpu/drm/amd/amdgpu/cik_ih.c        |   2 +-
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c      |  23 +++---
 drivers/gpu/drm/amd/amdgpu/cz_ih.c         |   3 +-
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c     |  16 ++---
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c     |  16 ++---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c      |  16 ++---
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c      |  16 ++---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c   |   2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c      |  16 ++---
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c      |  50 +++++++++----
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c      |  49 ++++++++-----
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |  25 +++++--
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |  32 +++++++--
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |  36 ++++++++--
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c    |   3 +-
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c        |   6 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c      |   4 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c     |  22 +++---
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c     |  26 ++++---
 drivers/gpu/drm/amd/amdgpu/si.c            |   7 ++
 drivers/gpu/drm/amd/amdgpu/si_dma.c        |  18 ++---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c        |   4 +-
 drivers/gpu/drm/amd/amdgpu/si_ih.c         |   2 +-
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c      |   3 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c      |  11 +--
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c      |  11 +--
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c      |  11 +--
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c      |  25 +++----
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c      |  31 ++++----
 drivers/gpu/drm/amd/amdgpu/vi.c            |   6 ++
 drivers/gpu/drm/amd/include/amd_shared.h   |   2 +
 drivers/gpu/drm/amd/include/cgs_linux.h    |  19 ++---
 include/uapi/drm/amdgpu_drm.h              |   3 +-
 55 files changed, 727 insertions(+), 352 deletions(-)

-- 
2.5.5

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[PATCH 01/23] drm/amdgpu: init aperture definitions

[Alex Deucher]

From: Junwei Zhang <Jerry.Zhang@amd.com>

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  6 ++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  | 24 +++++++++++++++++++++---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 17 +++++++++++++----
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  7 +++++++
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  7 +++++++
 5 files changed, 54 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 57eaf71..b2ff9e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -165,6 +165,12 @@ struct amdgpu_vm_manager {
 	/* partial resident texture handling */
 	spinlock_t				prt_lock;
 	atomic_t				num_prt_users;
+
+	/* vm aperture */
+	u64					shared_aperture_start;
+	u64					shared_aperture_end;
+	u64					private_aperture_start;
+	u64					private_aperture_end;
 };
 
 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index e471c08..cd6a6ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1889,7 +1889,8 @@ static void gfx_v7_0_config_init(struct amdgpu_device *adev)
  */
 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
 {
-	u32 tmp, sh_mem_cfg;
+	u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
+	u32 tmp;
 	int i;
 
 	WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
@@ -1920,15 +1921,32 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
 	/* where to put LDS, scratch, GPUVM in FSA64 space */
 	sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
 				   SH_MEM_ALIGNMENT_MODE_UNALIGNED);
+	sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
+				   MTYPE_NC);
+	sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
+				   MTYPE_UC);
+	sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
+
+	sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
+				   SWIZZLE_ENABLE, 1);
+	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
+				   ELEMENT_SIZE, 1);
+	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
+				   INDEX_STRIDE, 3);
 
 	mutex_lock(&adev->srbm_mutex);
-	for (i = 0; i < 16; i++) {
+	for (i = 0; i < adev->vm_manager.num_ids; i++) {
+		if (i == 0)
+			sh_mem_base = 0;
+		else
+			sh_mem_base = adev->vm_manager.shared_aperture_start >> 48;
 		cik_srbm_select(adev, 0, 0, 0, i);
 		/* CP and shaders */
 		WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
 		WREG32(mmSH_MEM_APE1_BASE, 1);
 		WREG32(mmSH_MEM_APE1_LIMIT, 0);
-		WREG32(mmSH_MEM_BASES, 0);
+		WREG32(mmSH_MEM_BASES, sh_mem_base);
+		WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
 	}
 	cik_srbm_select(adev, 0, 0, 0, 0);
 	mutex_unlock(&adev->srbm_mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 5dcf8db..af6294f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3859,7 +3859,7 @@ static void gfx_v8_0_config_init(struct amdgpu_device *adev)
 
 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
 {
-	u32 tmp;
+	u32 tmp, sh_static_mem_cfg;
 	int i;
 
 	WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
@@ -3874,8 +3874,14 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
 
 	/* XXX SH_MEM regs */
 	/* where to put LDS, scratch, GPUVM in FSA64 space */
+	sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
+				   SWIZZLE_ENABLE, 1);
+	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
+				   ELEMENT_SIZE, 1);
+	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
+				   INDEX_STRIDE, 3);
 	mutex_lock(&adev->srbm_mutex);
-	for (i = 0; i < 16; i++) {
+	for (i = 0; i < adev->vm_manager.num_ids; i++) {
 		vi_srbm_select(adev, 0, 0, 0, i);
 		/* CP and shaders */
 		if (i == 0) {
@@ -3884,17 +3890,20 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
 			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
 					    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
 			WREG32(mmSH_MEM_CONFIG, tmp);
+			WREG32(mmSH_MEM_BASES, 0);
 		} else {
 			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
-			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
+			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
 			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
 					    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
 			WREG32(mmSH_MEM_CONFIG, tmp);
+			tmp = adev->vm_manager.shared_aperture_start >> 48;
+			WREG32(mmSH_MEM_BASES, tmp);
 		}
 
 		WREG32(mmSH_MEM_APE1_BASE, 1);
 		WREG32(mmSH_MEM_APE1_LIMIT, 0);
-		WREG32(mmSH_MEM_BASES, 0);
+		WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
 	}
 	vi_srbm_select(adev, 0, 0, 0, 0);
 	mutex_unlock(&adev->srbm_mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 552bf6b..dc2b4c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -726,6 +726,13 @@ static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
 	 * amdkfd will use VMIDs 8-15
 	 */
 	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
+	adev->vm_manager.shared_aperture_start = 0x2000000000000000ULL;
+	adev->vm_manager.shared_aperture_end =
+		adev->vm_manager.shared_aperture_start + (4ULL << 30) - 1;
+	adev->vm_manager.private_aperture_start =
+		adev->vm_manager.shared_aperture_end + 1;
+	adev->vm_manager.private_aperture_end =
+		adev->vm_manager.private_aperture_start + (4ULL << 30) - 1;
 	amdgpu_vm_manager_init(adev);
 
 	/* base offset of vram pages */
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index f2bd016..81b1a49 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -857,6 +857,13 @@ static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
 	 * amdkfd will use VMIDs 8-15
 	 */
 	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
+	adev->vm_manager.shared_aperture_start = 0x2000000000000000ULL;
+	adev->vm_manager.shared_aperture_end =
+		adev->vm_manager.shared_aperture_start + (4ULL << 30) - 1;
+	adev->vm_manager.private_aperture_start =
+		adev->vm_manager.shared_aperture_end + 1;
+	adev->vm_manager.private_aperture_end =
+		adev->vm_manager.private_aperture_start + (4ULL << 30) - 1;
 	amdgpu_vm_manager_init(adev);
 
 	/* base offset of vram pages */
-- 
2.5.5

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Re: [PATCH 01/23] drm/amdgpu: init aperture definitions

[Christian König]

Am 09.03.2017 um 04:44 schrieb Alex Deucher:
> From: Junwei Zhang <Jerry.Zhang@amd.com>
>
> Signed-off-by: Flora Cui <Flora.Cui@amd.com>
> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |  6 ++++++
>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  | 24 +++++++++++++++++++++---
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 17 +++++++++++++----
>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c  |  7 +++++++
>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  |  7 +++++++
>   5 files changed, 54 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 57eaf71..b2ff9e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -165,6 +165,12 @@ struct amdgpu_vm_manager {
>   	/* partial resident texture handling */
>   	spinlock_t				prt_lock;
>   	atomic_t				num_prt_users;
> +
> +	/* vm aperture */
> +	u64					shared_aperture_start;
> +	u64					shared_aperture_end;
> +	u64					private_aperture_start;
> +	u64					private_aperture_end;

Apertures doesn't belong in the VM structure, but rather in amdgpu_mc.

Christian.

>   };
>   
>   void amdgpu_vm_manager_init(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index e471c08..cd6a6ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -1889,7 +1889,8 @@ static void gfx_v7_0_config_init(struct amdgpu_device *adev)
>    */
>   static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
>   {
> -	u32 tmp, sh_mem_cfg;
> +	u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
> +	u32 tmp;
>   	int i;
>   
>   	WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
> @@ -1920,15 +1921,32 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
>   	/* where to put LDS, scratch, GPUVM in FSA64 space */
>   	sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
>   				   SH_MEM_ALIGNMENT_MODE_UNALIGNED);
> +	sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
> +				   MTYPE_NC);
> +	sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
> +				   MTYPE_UC);
> +	sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
> +
> +	sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
> +				   SWIZZLE_ENABLE, 1);
> +	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
> +				   ELEMENT_SIZE, 1);
> +	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
> +				   INDEX_STRIDE, 3);
>   
>   	mutex_lock(&adev->srbm_mutex);
> -	for (i = 0; i < 16; i++) {
> +	for (i = 0; i < adev->vm_manager.num_ids; i++) {
> +		if (i == 0)
> +			sh_mem_base = 0;
> +		else
> +			sh_mem_base = adev->vm_manager.shared_aperture_start >> 48;
>   		cik_srbm_select(adev, 0, 0, 0, i);
>   		/* CP and shaders */
>   		WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
>   		WREG32(mmSH_MEM_APE1_BASE, 1);
>   		WREG32(mmSH_MEM_APE1_LIMIT, 0);
> -		WREG32(mmSH_MEM_BASES, 0);
> +		WREG32(mmSH_MEM_BASES, sh_mem_base);
> +		WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
>   	}
>   	cik_srbm_select(adev, 0, 0, 0, 0);
>   	mutex_unlock(&adev->srbm_mutex);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 5dcf8db..af6294f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -3859,7 +3859,7 @@ static void gfx_v8_0_config_init(struct amdgpu_device *adev)
>   
>   static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
>   {
> -	u32 tmp;
> +	u32 tmp, sh_static_mem_cfg;
>   	int i;
>   
>   	WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
> @@ -3874,8 +3874,14 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
>   
>   	/* XXX SH_MEM regs */
>   	/* where to put LDS, scratch, GPUVM in FSA64 space */
> +	sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
> +				   SWIZZLE_ENABLE, 1);
> +	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
> +				   ELEMENT_SIZE, 1);
> +	sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
> +				   INDEX_STRIDE, 3);
>   	mutex_lock(&adev->srbm_mutex);
> -	for (i = 0; i < 16; i++) {
> +	for (i = 0; i < adev->vm_manager.num_ids; i++) {
>   		vi_srbm_select(adev, 0, 0, 0, i);
>   		/* CP and shaders */
>   		if (i == 0) {
> @@ -3884,17 +3890,20 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
>   			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
>   					    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
>   			WREG32(mmSH_MEM_CONFIG, tmp);
> +			WREG32(mmSH_MEM_BASES, 0);
>   		} else {
>   			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
> -			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
> +			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
>   			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
>   					    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
>   			WREG32(mmSH_MEM_CONFIG, tmp);
> +			tmp = adev->vm_manager.shared_aperture_start >> 48;
> +			WREG32(mmSH_MEM_BASES, tmp);
>   		}
>   
>   		WREG32(mmSH_MEM_APE1_BASE, 1);
>   		WREG32(mmSH_MEM_APE1_LIMIT, 0);
> -		WREG32(mmSH_MEM_BASES, 0);
> +		WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
>   	}
>   	vi_srbm_select(adev, 0, 0, 0, 0);
>   	mutex_unlock(&adev->srbm_mutex);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 552bf6b..dc2b4c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -726,6 +726,13 @@ static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
>   	 * amdkfd will use VMIDs 8-15
>   	 */
>   	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
> +	adev->vm_manager.shared_aperture_start = 0x2000000000000000ULL;
> +	adev->vm_manager.shared_aperture_end =
> +		adev->vm_manager.shared_aperture_start + (4ULL << 30) - 1;
> +	adev->vm_manager.private_aperture_start =
> +		adev->vm_manager.shared_aperture_end + 1;
> +	adev->vm_manager.private_aperture_end =
> +		adev->vm_manager.private_aperture_start + (4ULL << 30) - 1;
>   	amdgpu_vm_manager_init(adev);
>   
>   	/* base offset of vram pages */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index f2bd016..81b1a49 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -857,6 +857,13 @@ static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
>   	 * amdkfd will use VMIDs 8-15
>   	 */
>   	adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
> +	adev->vm_manager.shared_aperture_start = 0x2000000000000000ULL;
> +	adev->vm_manager.shared_aperture_end =
> +		adev->vm_manager.shared_aperture_start + (4ULL << 30) - 1;
> +	adev->vm_manager.private_aperture_start =
> +		adev->vm_manager.shared_aperture_end + 1;
> +	adev->vm_manager.private_aperture_end =
> +		adev->vm_manager.private_aperture_start + (4ULL << 30) - 1;
>   	amdgpu_vm_manager_init(adev);
>   
>   	/* base offset of vram pages */


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[PATCH 02/23] drm/amdgpu: change wptr to 64 bits

[Alex Deucher]

From: Ken Wang <Qingqing.Wang@amd.com>

Newer asics use 64 bit wptrs

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  5 ++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 10 +++++++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 12 +++++++-----
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c    | 12 +++++++-----
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c    | 10 +++++-----
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c    | 18 ++++++++++--------
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 22 ++++++++++++----------
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   | 11 ++++++-----
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   | 15 ++++++++-------
 drivers/gpu/drm/amd/amdgpu/si_dma.c      | 12 +++++++-----
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c    |  9 +++++----
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c    |  9 +++++----
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c    |  9 +++++----
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c    | 17 +++++++++--------
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c    | 23 ++++++++++++-----------
 15 files changed, 109 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f0e8b2a..a23842d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1594,9 +1594,12 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
  */
 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
 {
+	u32 tmp;
 	if (ring->count_dw <= 0)
 		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
-	ring->ring[ring->wptr++] = v;
+	tmp = lower_32_bits(ring->wptr++);
+	tmp &= ring->buf_mask;
+	ring->ring[tmp] = v;
 	ring->wptr &= ring->ptr_mask;
 	ring->count_dw--;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index cead88a..f0515b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -126,7 +126,7 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring)
 
 	/* We pad to match fetch size */
 	count = ring->funcs->align_mask + 1 -
-		(ring->wptr & ring->funcs->align_mask);
+		(lower_32_bits(ring->wptr) & ring->funcs->align_mask);
 	count %= ring->funcs->align_mask + 1;
 	ring->funcs->insert_nop(ring, count);
 
@@ -232,7 +232,10 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 		}
 		amdgpu_ring_clear_ring(ring);
 	}
-	ring->ptr_mask = (ring->ring_size / 4) - 1;
+	ring->buf_mask = (ring->ring_size / 4) - 1;
+	ring->ptr_mask = ring->support_64bit_ptrs ?
+		0xffffffffffffffff : ring->buf_mask;
+
 	ring->max_dw = max_dw;
 
 	if (amdgpu_debugfs_ring_init(adev, ring)) {
@@ -284,7 +287,8 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
 {
 	struct amdgpu_ring *ring = file_inode(f)->i_private;
 	int r, i;
-	uint32_t value, result, early[3];
+	uint32_t value, result;
+	uint64_t early[3];
 
 	if (*pos & 3 || size & 3)
 		return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index da702dc..9f2d605 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -98,8 +98,8 @@ struct amdgpu_ring_funcs {
 	u32			nop;
 
 	/* ring read/write ptr handling */
-	u32 (*get_rptr)(struct amdgpu_ring *ring);
-	u32 (*get_wptr)(struct amdgpu_ring *ring);
+	u64 (*get_rptr)(struct amdgpu_ring *ring);
+	u64 (*get_wptr)(struct amdgpu_ring *ring);
 	void (*set_wptr)(struct amdgpu_ring *ring);
 	/* validating and patching of IBs */
 	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
@@ -148,13 +148,15 @@ struct amdgpu_ring {
 	struct amdgpu_bo	*ring_obj;
 	volatile uint32_t	*ring;
 	unsigned		rptr_offs;
-	unsigned		wptr;
-	unsigned		wptr_old;
+	u64			wptr;
+	u64			wptr_old;
+	bool			support_64bit_ptrs;
 	unsigned		ring_size;
 	unsigned		max_dw;
 	int			count_dw;
 	uint64_t		gpu_addr;
-	uint32_t		ptr_mask;
+	uint64_t		ptr_mask;
+	uint32_t		buf_mask;
 	bool			ready;
 	u32			idx;
 	u32			me;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index c33bc1b..b35ec4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -158,7 +158,7 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev)
  *
  * Get the current rptr from the hardware (CIK+).
  */
-static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
+static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	u32 rptr;
 
@@ -174,7 +174,7 @@ static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
  *
  * Get the current wptr from the hardware (CIK+).
  */
-static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
+static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
@@ -194,7 +194,8 @@ static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 	struct amdgpu_device *adev = ring->adev;
 	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 
-	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
+	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
+		       	(lower_32_bits(ring->wptr) << 2) & 0x3fffc);
 }
 
 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
@@ -225,7 +226,7 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
 	u32 extra_bits = vm_id & 0xf;
 
 	/* IB packet must end on a 8 DW boundary */
-	cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
+	cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8);
 
 	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
 	amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
@@ -432,7 +433,7 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 
 		ring->wptr = 0;
-		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
+		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
 
 		/* enable DMA RB */
 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
@@ -940,6 +941,7 @@ static int cik_sdma_sw_init(void *handle)
 		ring = &adev->sdma.instance[i].ring;
 		ring->ring_obj = NULL;
 		sprintf(ring->name, "sdma%d", i);
+		ring->support_64bit_ptrs = false;
 		r = amdgpu_ring_init(adev, ring, 1024,
 				     &adev->sdma.trap_irq,
 				     (i == 0) ?
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 02ca232..cb3d2816 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2192,12 +2192,12 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
 	return 0;
 }
 
-static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
+static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	return ring->adev->wb.wb[ring->rptr_offs];
 }
 
-static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
+static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -2215,7 +2215,7 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
-	WREG32(mmCP_RB0_WPTR, ring->wptr);
+	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
 	(void)RREG32(mmCP_RB0_WPTR);
 }
 
@@ -2224,10 +2224,10 @@ static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
 	struct amdgpu_device *adev = ring->adev;
 
 	if (ring == &adev->gfx.compute_ring[0]) {
-		WREG32(mmCP_RB1_WPTR, ring->wptr);
+		WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
 		(void)RREG32(mmCP_RB1_WPTR);
 	} else if (ring == &adev->gfx.compute_ring[1]) {
-		WREG32(mmCP_RB2_WPTR, ring->wptr);
+		WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
 		(void)RREG32(mmCP_RB2_WPTR);
 	} else {
 		BUG();
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index cd6a6ec..e6a25ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2629,7 +2629,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
 	/* Initialize the ring buffer's read and write pointers */
 	WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
 	ring->wptr = 0;
-	WREG32(mmCP_RB0_WPTR, ring->wptr);
+	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
 
 	/* set the wb address wether it's enabled or not */
 	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
@@ -2658,12 +2658,12 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
 	return 0;
 }
 
-static u32 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
+static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	return ring->adev->wb.wb[ring->rptr_offs];
 }
 
-static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
+static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -2674,11 +2674,11 @@ static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
-	WREG32(mmCP_RB0_WPTR, ring->wptr);
+	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
 	(void)RREG32(mmCP_RB0_WPTR);
 }
 
-static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
+static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
 {
 	/* XXX check if swapping is necessary on BE */
 	return ring->adev->wb.wb[ring->wptr_offs];
@@ -2689,8 +2689,8 @@ static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
 	struct amdgpu_device *adev = ring->adev;
 
 	/* XXX check if swapping is necessary on BE */
-	adev->wb.wb[ring->wptr_offs] = ring->wptr;
-	WDOORBELL32(ring->doorbell_index, ring->wptr);
+	adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+	WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 }
 
 /**
@@ -3160,7 +3160,7 @@ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
 
 		/* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
 		ring->wptr = 0;
-		mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
+		mqd->queue_state.cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
 		WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
 		mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
 
@@ -4708,6 +4708,7 @@ static int gfx_v7_0_sw_init(void *handle)
 		ring = &adev->gfx.gfx_ring[i];
 		ring->ring_obj = NULL;
 		sprintf(ring->name, "gfx");
+		ring->support_64bit_ptrs = false;
 		r = amdgpu_ring_init(adev, ring, 1024,
 				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
 		if (r)
@@ -4732,6 +4733,7 @@ static int gfx_v7_0_sw_init(void *handle)
 		ring->queue = i % 8;
 		sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
+		ring->support_64bit_ptrs = false;
 		/* type-2 packets are deprecated on MEC, use type-3 instead */
 		r = amdgpu_ring_init(adev, ring, 1024,
 				     &adev->gfx.eop_irq, irq_type);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index af6294f..304f28c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -2125,6 +2125,7 @@ static int gfx_v8_0_sw_init(void *handle)
 			ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
 		}
 
+		ring->support_64bit_ptrs = false;
 		r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
 				     AMDGPU_CP_IRQ_GFX_EOP);
 		if (r)
@@ -2149,6 +2150,7 @@ static int gfx_v8_0_sw_init(void *handle)
 		ring->queue = i % 8;
 		sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
+		ring->support_64bit_ptrs = false;
 		/* type-2 packets are deprecated on MEC, use type-3 instead */
 		r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
 				     irq_type);
@@ -4490,7 +4492,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
 	/* Initialize the ring buffer's read and write pointers */
 	WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
 	ring->wptr = 0;
-	WREG32(mmCP_RB0_WPTR, ring->wptr);
+	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
 
 	/* set the wb address wether it's enabled or not */
 	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
@@ -5204,7 +5206,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
 
 		/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
 		ring->wptr = 0;
-		mqd->cp_hqd_pq_wptr = ring->wptr;
+		mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
 		WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
 		mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
 
@@ -6458,12 +6460,12 @@ static int gfx_v8_0_set_clockgating_state(void *handle,
 	return 0;
 }
 
-static u32 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
+static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	return ring->adev->wb.wb[ring->rptr_offs];
 }
 
-static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
+static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -6480,10 +6482,10 @@ static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
 
 	if (ring->use_doorbell) {
 		/* XXX check if swapping is necessary on BE */
-		adev->wb.wb[ring->wptr_offs] = ring->wptr;
-		WDOORBELL32(ring->doorbell_index, ring->wptr);
+		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 	} else {
-		WREG32(mmCP_RB0_WPTR, ring->wptr);
+		WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
 		(void)RREG32(mmCP_RB0_WPTR);
 	}
 }
@@ -6671,7 +6673,7 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 	}
 }
 
-static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
+static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
 {
 	return ring->adev->wb.wb[ring->wptr_offs];
 }
@@ -6681,8 +6683,8 @@ static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
 	struct amdgpu_device *adev = ring->adev;
 
 	/* XXX check if swapping is necessary on BE */
-	adev->wb.wb[ring->wptr_offs] = ring->wptr;
-	WDOORBELL32(ring->doorbell_index, ring->wptr);
+	adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
+	WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 }
 
 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index a881cf4..f5ee5f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -186,7 +186,7 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
  *
  * Get the current rptr from the hardware (VI+).
  */
-static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
+static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	/* XXX check if swapping is necessary on BE */
 	return ring->adev->wb.wb[ring->rptr_offs] >> 2;
@@ -199,7 +199,7 @@ static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
  *
  * Get the current wptr from the hardware (VI+).
  */
-static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
+static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 	int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
@@ -220,7 +220,7 @@ static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 	struct amdgpu_device *adev = ring->adev;
 	int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 
-	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
+	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
 }
 
 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
@@ -251,7 +251,7 @@ static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 	u32 vmid = vm_id & 0xf;
 
 	/* IB packet must end on a 8 DW boundary */
-	sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
+	sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 
 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
@@ -466,7 +466,7 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 
 		ring->wptr = 0;
-		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
+		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
 
 		/* enable DMA RB */
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
@@ -946,6 +946,7 @@ static int sdma_v2_4_sw_init(void *handle)
 		ring->ring_obj = NULL;
 		ring->use_doorbell = false;
 		sprintf(ring->name, "sdma%d", i);
+		ring->support_64bit_ptrs = false;
 		r = amdgpu_ring_init(adev, ring, 1024,
 				     &adev->sdma.trap_irq,
 				     (i == 0) ?
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 1df5b34..e715385 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -337,7 +337,7 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
  *
  * Get the current rptr from the hardware (VI+).
  */
-static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
+static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	/* XXX check if swapping is necessary on BE */
 	return ring->adev->wb.wb[ring->rptr_offs] >> 2;
@@ -350,7 +350,7 @@ static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
  *
  * Get the current wptr from the hardware (VI+).
  */
-static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
+static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 	u32 wptr;
@@ -380,12 +380,12 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 
 	if (ring->use_doorbell) {
 		/* XXX check if swapping is necessary on BE */
-		adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
-		WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
+		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr) << 2;
+		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
 	} else {
 		int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 
-		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
+		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
 	}
 }
 
@@ -417,7 +417,7 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 	u32 vmid = vm_id & 0xf;
 
 	/* IB packet must end on a 8 DW boundary */
-	sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
+	sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 
 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
@@ -660,7 +660,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 
 		ring->wptr = 0;
-		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
+		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
 
 		doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 
@@ -1165,6 +1165,7 @@ static int sdma_v3_0_sw_init(void *handle)
 			AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
 
 		sprintf(ring->name, "sdma%d", i);
+		ring->support_64bit_ptrs = false;
 		r = amdgpu_ring_init(adev, ring, 1024,
 				     &adev->sdma.trap_irq,
 				     (i == 0) ?
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 3372a07..256a77b 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -37,12 +37,12 @@ static void si_dma_set_buffer_funcs(struct amdgpu_device *adev);
 static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev);
 static void si_dma_set_irq_funcs(struct amdgpu_device *adev);
 
-static uint32_t si_dma_ring_get_rptr(struct amdgpu_ring *ring)
+static uint64_t si_dma_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	return ring->adev->wb.wb[ring->rptr_offs>>2];
 }
 
-static uint32_t si_dma_ring_get_wptr(struct amdgpu_ring *ring)
+static uint64_t si_dma_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
@@ -55,7 +55,8 @@ static void si_dma_ring_set_wptr(struct amdgpu_ring *ring)
 	struct amdgpu_device *adev = ring->adev;
 	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 
-	WREG32(DMA_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
+	WREG32(DMA_RB_WPTR + sdma_offsets[me],
+	       (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
 }
 
 static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,
@@ -65,7 +66,7 @@ static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,
 	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
 	 * Pad as necessary with NOPs.
 	 */
-	while ((ring->wptr & 7) != 5)
+	while ((lower_32_bits(ring->wptr) & 7) != 5)
 		amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
 	amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vm_id, 0));
 	amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
@@ -184,7 +185,7 @@ static int si_dma_start(struct amdgpu_device *adev)
 		WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl);
 
 		ring->wptr = 0;
-		WREG32(DMA_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
+		WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
 		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE);
 
 		ring->ready = true;
@@ -530,6 +531,7 @@ static int si_dma_sw_init(void *handle)
 		ring->ring_obj = NULL;
 		ring->use_doorbell = false;
 		sprintf(ring->name, "sdma%d", i);
+		ring->support_64bit_ptrs = false;
 		r = amdgpu_ring_init(adev, ring, 1024,
 				     &adev->sdma.trap_irq,
 				     (i == 0) ?
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index b34cefc..580c658 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -55,7 +55,7 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
  *
  * Returns the current hardware read pointer
  */
-static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
+static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -69,7 +69,7 @@ static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
  *
  * Returns the current hardware write pointer
  */
-static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)
+static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -87,7 +87,7 @@ static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
-	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
+	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 }
 
 static int uvd_v4_2_early_init(void *handle)
@@ -121,6 +121,7 @@ static int uvd_v4_2_sw_init(void *handle)
 
 	ring = &adev->uvd.ring;
 	sprintf(ring->name, "uvd");
+	ring->support_64bit_ptrs = false;
 	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 
 	return r;
@@ -367,7 +368,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
 	WREG32(mmUVD_RBC_RB_RPTR, 0x0);
 
 	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
-	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
+	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 
 	/* set the ring address */
 	WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index ad8c02e..7a4fca0 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -51,7 +51,7 @@ static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
  *
  * Returns the current hardware read pointer
  */
-static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
+static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -65,7 +65,7 @@ static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
  *
  * Returns the current hardware write pointer
  */
-static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
+static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -83,7 +83,7 @@ static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
-	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
+	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 }
 
 static int uvd_v5_0_early_init(void *handle)
@@ -117,6 +117,7 @@ static int uvd_v5_0_sw_init(void *handle)
 
 	ring = &adev->uvd.ring;
 	sprintf(ring->name, "uvd");
+	ring->support_64bit_ptrs = false;
 	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 
 	return r;
@@ -424,7 +425,7 @@ static int uvd_v5_0_start(struct amdgpu_device *adev)
 	WREG32(mmUVD_RBC_RB_RPTR, 0);
 
 	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
-	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
+	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 
 	WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 18a6de4..2c5482e 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -54,7 +54,7 @@ static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
  *
  * Returns the current hardware read pointer
  */
-static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
+static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -68,7 +68,7 @@ static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  *
  * Returns the current hardware write pointer
  */
-static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
+static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -86,7 +86,7 @@ static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
-	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
+	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 }
 
 static int uvd_v6_0_early_init(void *handle)
@@ -120,6 +120,7 @@ static int uvd_v6_0_sw_init(void *handle)
 
 	ring = &adev->uvd.ring;
 	sprintf(ring->name, "uvd");
+	ring->support_64bit_ptrs = false;
 	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 
 	return r;
@@ -521,7 +522,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
 	WREG32(mmUVD_RBC_RB_RPTR, 0);
 
 	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
-	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
+	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 
 	WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index cb0b730f..9a4aa5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -52,7 +52,7 @@ static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
  *
  * Returns the current hardware read pointer
  */
-static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
+static uint64_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -69,7 +69,7 @@ static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
  *
  * Returns the current hardware write pointer
  */
-static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
+static uint64_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -91,9 +91,9 @@ static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
 	struct amdgpu_device *adev = ring->adev;
 
 	if (ring == &adev->vce.ring[0])
-		WREG32(mmVCE_RB_WPTR, ring->wptr);
+		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
 	else
-		WREG32(mmVCE_RB_WPTR2, ring->wptr);
+		WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
 }
 
 static int vce_v2_0_lmi_clean(struct amdgpu_device *adev)
@@ -241,15 +241,15 @@ static int vce_v2_0_start(struct amdgpu_device *adev)
 	vce_v2_0_mc_resume(adev);
 
 	ring = &adev->vce.ring[0];
-	WREG32(mmVCE_RB_RPTR, ring->wptr);
-	WREG32(mmVCE_RB_WPTR, ring->wptr);
+	WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
+	WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
 	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
 	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
 
 	ring = &adev->vce.ring[1];
-	WREG32(mmVCE_RB_RPTR2, ring->wptr);
-	WREG32(mmVCE_RB_WPTR2, ring->wptr);
+	WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
+	WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
 	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
 	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
@@ -446,6 +446,7 @@ static int vce_v2_0_sw_init(void *handle)
 	for (i = 0; i < adev->vce.num_rings; i++) {
 		ring = &adev->vce.ring[i];
 		sprintf(ring->name, "vce%d", i);
+		ring->support_64bit_ptrs = false;
 		r = amdgpu_ring_init(adev, ring, 512,
 				     &adev->vce.irq, 0);
 		if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 93ec881..7877a51 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -73,7 +73,7 @@ static int vce_v3_0_wait_for_idle(void *handle);
  *
  * Returns the current hardware read pointer
  */
-static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
+static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -92,7 +92,7 @@ static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
  *
  * Returns the current hardware write pointer
  */
-static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
+static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
 
@@ -116,11 +116,11 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 	struct amdgpu_device *adev = ring->adev;
 
 	if (ring == &adev->vce.ring[0])
-		WREG32(mmVCE_RB_WPTR, ring->wptr);
+		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
 	else if (ring == &adev->vce.ring[1])
-		WREG32(mmVCE_RB_WPTR2, ring->wptr);
+		WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
 	else
-		WREG32(mmVCE_RB_WPTR3, ring->wptr);
+		WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
 }
 
 static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)
@@ -231,22 +231,22 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
 	int idx, r;
 
 	ring = &adev->vce.ring[0];
-	WREG32(mmVCE_RB_RPTR, ring->wptr);
-	WREG32(mmVCE_RB_WPTR, ring->wptr);
+	WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
+	WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
 	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
 	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
 
 	ring = &adev->vce.ring[1];
-	WREG32(mmVCE_RB_RPTR2, ring->wptr);
-	WREG32(mmVCE_RB_WPTR2, ring->wptr);
+	WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
+	WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
 	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
 	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
 
 	ring = &adev->vce.ring[2];
-	WREG32(mmVCE_RB_RPTR3, ring->wptr);
-	WREG32(mmVCE_RB_WPTR3, ring->wptr);
+	WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
+	WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
 	WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
 	WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
 	WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
@@ -403,6 +403,7 @@ static int vce_v3_0_sw_init(void *handle)
 	for (i = 0; i < adev->vce.num_rings; i++) {
 		ring = &adev->vce.ring[i];
 		sprintf(ring->name, "vce%d", i);
+		ring->support_64bit_ptrs = false;
 		r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0);
 		if (r)
 			return r;
-- 
2.5.5

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Re: [PATCH 02/23] drm/amdgpu: change wptr to 64 bits

[Christian König]

Am 09.03.2017 um 04:44 schrieb Alex Deucher:
> From: Ken Wang <Qingqing.Wang@amd.com>
>
> Newer asics use 64 bit wptrs

We need a better patch description. Newer asics doesn't use 64bit wptrs, 
but rather need them!

E.g. if the wptr is now smaller than the rptr that doesn't indicate a 
wrap around any more.

>
> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  5 ++++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 10 +++++++---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 12 +++++++-----
>   drivers/gpu/drm/amd/amdgpu/cik_sdma.c    | 12 +++++++-----
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c    | 10 +++++-----
>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c    | 18 ++++++++++--------
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 22 ++++++++++++----------
>   drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   | 11 ++++++-----
>   drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   | 15 ++++++++-------
>   drivers/gpu/drm/amd/amdgpu/si_dma.c      | 12 +++++++-----
>   drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c    |  9 +++++----
>   drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c    |  9 +++++----
>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c    |  9 +++++----
>   drivers/gpu/drm/amd/amdgpu/vce_v2_0.c    | 17 +++++++++--------
>   drivers/gpu/drm/amd/amdgpu/vce_v3_0.c    | 23 ++++++++++++-----------
>   15 files changed, 109 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index f0e8b2a..a23842d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1594,9 +1594,12 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
>    */
>   static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
>   {
> +	u32 tmp;

Coding style we need a new line here.

>   	if (ring->count_dw <= 0)
>   		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
> -	ring->ring[ring->wptr++] = v;
> +	tmp = lower_32_bits(ring->wptr++);
> +	tmp &= ring->buf_mask;
> +	ring->ring[tmp] = v;

I would just code that as "ring->ring[ring->wptr++ & ring->buf_mask]".

Using lower_32_bits is mostly for documentation purpose when stitching 
together hardware packages, that doesn't apply here.

>   	ring->wptr &= ring->ptr_mask;
>   	ring->count_dw--;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> index cead88a..f0515b8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> @@ -126,7 +126,7 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring)
>   
>   	/* We pad to match fetch size */
>   	count = ring->funcs->align_mask + 1 -
> -		(ring->wptr & ring->funcs->align_mask);
> +		(lower_32_bits(ring->wptr) & ring->funcs->align_mask);

Dito, just drop that change.

The remaining lower_32_bits() bits usuages look valid to me.

>   	count %= ring->funcs->align_mask + 1;
>   	ring->funcs->insert_nop(ring, count);
>   
> @@ -232,7 +232,10 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
>   		}
>   		amdgpu_ring_clear_ring(ring);
>   	}
> -	ring->ptr_mask = (ring->ring_size / 4) - 1;
> +	ring->buf_mask = (ring->ring_size / 4) - 1;
> +	ring->ptr_mask = ring->support_64bit_ptrs ?
> +		0xffffffffffffffff : ring->buf_mask;
> +
>   	ring->max_dw = max_dw;
>   
>   	if (amdgpu_debugfs_ring_init(adev, ring)) {
> @@ -284,7 +287,8 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
>   {
>   	struct amdgpu_ring *ring = file_inode(f)->i_private;
>   	int r, i;
> -	uint32_t value, result, early[3];
> +	uint32_t value, result;
> +	uint64_t early[3];

Completely superfluous change, we should rather mask the values returned 
to userspace properly.

>   
>   	if (*pos & 3 || size & 3)
>   		return -EINVAL;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index da702dc..9f2d605 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -98,8 +98,8 @@ struct amdgpu_ring_funcs {
>   	u32			nop;
>   
>   	/* ring read/write ptr handling */
> -	u32 (*get_rptr)(struct amdgpu_ring *ring);
> -	u32 (*get_wptr)(struct amdgpu_ring *ring);
> +	u64 (*get_rptr)(struct amdgpu_ring *ring);
> +	u64 (*get_wptr)(struct amdgpu_ring *ring);
>   	void (*set_wptr)(struct amdgpu_ring *ring);
>   	/* validating and patching of IBs */
>   	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
> @@ -148,13 +148,15 @@ struct amdgpu_ring {
>   	struct amdgpu_bo	*ring_obj;
>   	volatile uint32_t	*ring;
>   	unsigned		rptr_offs;
> -	unsigned		wptr;
> -	unsigned		wptr_old;
> +	u64			wptr;
> +	u64			wptr_old;
> +	bool			support_64bit_ptrs;

That belongs into amdgpu_ring_funcs.

Regards,
Christian.

>   	unsigned		ring_size;
>   	unsigned		max_dw;
>   	int			count_dw;
>   	uint64_t		gpu_addr;
> -	uint32_t		ptr_mask;
> +	uint64_t		ptr_mask;
> +	uint32_t		buf_mask;
>   	bool			ready;
>   	u32			idx;
>   	u32			me;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index c33bc1b..b35ec4a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -158,7 +158,7 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev)
>    *
>    * Get the current rptr from the hardware (CIK+).
>    */
> -static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
> +static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
>   {
>   	u32 rptr;
>   
> @@ -174,7 +174,7 @@ static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
>    *
>    * Get the current wptr from the hardware (CIK+).
>    */
> -static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
> +static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
> @@ -194,7 +194,8 @@ static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
>   	struct amdgpu_device *adev = ring->adev;
>   	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>   
> -	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
> +	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
> +		       	(lower_32_bits(ring->wptr) << 2) & 0x3fffc);
>   }
>   
>   static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
> @@ -225,7 +226,7 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
>   	u32 extra_bits = vm_id & 0xf;
>   
>   	/* IB packet must end on a 8 DW boundary */
> -	cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
> +	cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8);
>   
>   	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
>   	amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
> @@ -432,7 +433,7 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
>   		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
>   
>   		ring->wptr = 0;
> -		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
> +		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
>   
>   		/* enable DMA RB */
>   		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
> @@ -940,6 +941,7 @@ static int cik_sdma_sw_init(void *handle)
>   		ring = &adev->sdma.instance[i].ring;
>   		ring->ring_obj = NULL;
>   		sprintf(ring->name, "sdma%d", i);
> +		ring->support_64bit_ptrs = false;
>   		r = amdgpu_ring_init(adev, ring, 1024,
>   				     &adev->sdma.trap_irq,
>   				     (i == 0) ?
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 02ca232..cb3d2816 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -2192,12 +2192,12 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
>   	return 0;
>   }
>   
> -static u32 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
> +static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
>   {
>   	return ring->adev->wb.wb[ring->rptr_offs];
>   }
>   
> -static u32 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
> +static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -2215,7 +2215,7 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> -	WREG32(mmCP_RB0_WPTR, ring->wptr);
> +	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
>   	(void)RREG32(mmCP_RB0_WPTR);
>   }
>   
> @@ -2224,10 +2224,10 @@ static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
>   	struct amdgpu_device *adev = ring->adev;
>   
>   	if (ring == &adev->gfx.compute_ring[0]) {
> -		WREG32(mmCP_RB1_WPTR, ring->wptr);
> +		WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
>   		(void)RREG32(mmCP_RB1_WPTR);
>   	} else if (ring == &adev->gfx.compute_ring[1]) {
> -		WREG32(mmCP_RB2_WPTR, ring->wptr);
> +		WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
>   		(void)RREG32(mmCP_RB2_WPTR);
>   	} else {
>   		BUG();
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index cd6a6ec..e6a25ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -2629,7 +2629,7 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
>   	/* Initialize the ring buffer's read and write pointers */
>   	WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
>   	ring->wptr = 0;
> -	WREG32(mmCP_RB0_WPTR, ring->wptr);
> +	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
>   
>   	/* set the wb address wether it's enabled or not */
>   	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
> @@ -2658,12 +2658,12 @@ static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
>   	return 0;
>   }
>   
> -static u32 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
> +static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
>   {
>   	return ring->adev->wb.wb[ring->rptr_offs];
>   }
>   
> -static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
> +static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -2674,11 +2674,11 @@ static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> -	WREG32(mmCP_RB0_WPTR, ring->wptr);
> +	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
>   	(void)RREG32(mmCP_RB0_WPTR);
>   }
>   
> -static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
> +static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
>   {
>   	/* XXX check if swapping is necessary on BE */
>   	return ring->adev->wb.wb[ring->wptr_offs];
> @@ -2689,8 +2689,8 @@ static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
>   	struct amdgpu_device *adev = ring->adev;
>   
>   	/* XXX check if swapping is necessary on BE */
> -	adev->wb.wb[ring->wptr_offs] = ring->wptr;
> -	WDOORBELL32(ring->doorbell_index, ring->wptr);
> +	adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
> +	WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
>   }
>   
>   /**
> @@ -3160,7 +3160,7 @@ static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
>   
>   		/* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
>   		ring->wptr = 0;
> -		mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
> +		mqd->queue_state.cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
>   		WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
>   		mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
>   
> @@ -4708,6 +4708,7 @@ static int gfx_v7_0_sw_init(void *handle)
>   		ring = &adev->gfx.gfx_ring[i];
>   		ring->ring_obj = NULL;
>   		sprintf(ring->name, "gfx");
> +		ring->support_64bit_ptrs = false;
>   		r = amdgpu_ring_init(adev, ring, 1024,
>   				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
>   		if (r)
> @@ -4732,6 +4733,7 @@ static int gfx_v7_0_sw_init(void *handle)
>   		ring->queue = i % 8;
>   		sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
>   		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
> +		ring->support_64bit_ptrs = false;
>   		/* type-2 packets are deprecated on MEC, use type-3 instead */
>   		r = amdgpu_ring_init(adev, ring, 1024,
>   				     &adev->gfx.eop_irq, irq_type);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index af6294f..304f28c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -2125,6 +2125,7 @@ static int gfx_v8_0_sw_init(void *handle)
>   			ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
>   		}
>   
> +		ring->support_64bit_ptrs = false;
>   		r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
>   				     AMDGPU_CP_IRQ_GFX_EOP);
>   		if (r)
> @@ -2149,6 +2150,7 @@ static int gfx_v8_0_sw_init(void *handle)
>   		ring->queue = i % 8;
>   		sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
>   		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
> +		ring->support_64bit_ptrs = false;
>   		/* type-2 packets are deprecated on MEC, use type-3 instead */
>   		r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
>   				     irq_type);
> @@ -4490,7 +4492,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
>   	/* Initialize the ring buffer's read and write pointers */
>   	WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
>   	ring->wptr = 0;
> -	WREG32(mmCP_RB0_WPTR, ring->wptr);
> +	WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
>   
>   	/* set the wb address wether it's enabled or not */
>   	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
> @@ -5204,7 +5206,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
>   
>   		/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
>   		ring->wptr = 0;
> -		mqd->cp_hqd_pq_wptr = ring->wptr;
> +		mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
>   		WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
>   		mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
>   
> @@ -6458,12 +6460,12 @@ static int gfx_v8_0_set_clockgating_state(void *handle,
>   	return 0;
>   }
>   
> -static u32 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
> +static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
>   {
>   	return ring->adev->wb.wb[ring->rptr_offs];
>   }
>   
> -static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
> +static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -6480,10 +6482,10 @@ static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
>   
>   	if (ring->use_doorbell) {
>   		/* XXX check if swapping is necessary on BE */
> -		adev->wb.wb[ring->wptr_offs] = ring->wptr;
> -		WDOORBELL32(ring->doorbell_index, ring->wptr);
> +		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
> +		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
>   	} else {
> -		WREG32(mmCP_RB0_WPTR, ring->wptr);
> +		WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
>   		(void)RREG32(mmCP_RB0_WPTR);
>   	}
>   }
> @@ -6671,7 +6673,7 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>   	}
>   }
>   
> -static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
> +static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
>   {
>   	return ring->adev->wb.wb[ring->wptr_offs];
>   }
> @@ -6681,8 +6683,8 @@ static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
>   	struct amdgpu_device *adev = ring->adev;
>   
>   	/* XXX check if swapping is necessary on BE */
> -	adev->wb.wb[ring->wptr_offs] = ring->wptr;
> -	WDOORBELL32(ring->doorbell_index, ring->wptr);
> +	adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
> +	WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
>   }
>   
>   static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index a881cf4..f5ee5f3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -186,7 +186,7 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
>    *
>    * Get the current rptr from the hardware (VI+).
>    */
> -static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
> +static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
>   {
>   	/* XXX check if swapping is necessary on BE */
>   	return ring->adev->wb.wb[ring->rptr_offs] >> 2;
> @@ -199,7 +199,7 @@ static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
>    *
>    * Get the current wptr from the hardware (VI+).
>    */
> -static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
> +static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   	int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
> @@ -220,7 +220,7 @@ static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
>   	struct amdgpu_device *adev = ring->adev;
>   	int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
>   
> -	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
> +	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
>   }
>   
>   static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
> @@ -251,7 +251,7 @@ static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
>   	u32 vmid = vm_id & 0xf;
>   
>   	/* IB packet must end on a 8 DW boundary */
> -	sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
> +	sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
>   
>   	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
>   			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
> @@ -466,7 +466,7 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
>   		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
>   
>   		ring->wptr = 0;
> -		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
> +		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
>   
>   		/* enable DMA RB */
>   		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
> @@ -946,6 +946,7 @@ static int sdma_v2_4_sw_init(void *handle)
>   		ring->ring_obj = NULL;
>   		ring->use_doorbell = false;
>   		sprintf(ring->name, "sdma%d", i);
> +		ring->support_64bit_ptrs = false;
>   		r = amdgpu_ring_init(adev, ring, 1024,
>   				     &adev->sdma.trap_irq,
>   				     (i == 0) ?
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 1df5b34..e715385 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -337,7 +337,7 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
>    *
>    * Get the current rptr from the hardware (VI+).
>    */
> -static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
> +static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
>   {
>   	/* XXX check if swapping is necessary on BE */
>   	return ring->adev->wb.wb[ring->rptr_offs] >> 2;
> @@ -350,7 +350,7 @@ static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
>    *
>    * Get the current wptr from the hardware (VI+).
>    */
> -static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
> +static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   	u32 wptr;
> @@ -380,12 +380,12 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
>   
>   	if (ring->use_doorbell) {
>   		/* XXX check if swapping is necessary on BE */
> -		adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
> -		WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
> +		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr) << 2;
> +		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
>   	} else {
>   		int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
>   
> -		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
> +		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
>   	}
>   }
>   
> @@ -417,7 +417,7 @@ static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
>   	u32 vmid = vm_id & 0xf;
>   
>   	/* IB packet must end on a 8 DW boundary */
> -	sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
> +	sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
>   
>   	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
>   			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
> @@ -660,7 +660,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
>   		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
>   
>   		ring->wptr = 0;
> -		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
> +		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
>   
>   		doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
>   
> @@ -1165,6 +1165,7 @@ static int sdma_v3_0_sw_init(void *handle)
>   			AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
>   
>   		sprintf(ring->name, "sdma%d", i);
> +		ring->support_64bit_ptrs = false;
>   		r = amdgpu_ring_init(adev, ring, 1024,
>   				     &adev->sdma.trap_irq,
>   				     (i == 0) ?
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index 3372a07..256a77b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -37,12 +37,12 @@ static void si_dma_set_buffer_funcs(struct amdgpu_device *adev);
>   static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev);
>   static void si_dma_set_irq_funcs(struct amdgpu_device *adev);
>   
> -static uint32_t si_dma_ring_get_rptr(struct amdgpu_ring *ring)
> +static uint64_t si_dma_ring_get_rptr(struct amdgpu_ring *ring)
>   {
>   	return ring->adev->wb.wb[ring->rptr_offs>>2];
>   }
>   
> -static uint32_t si_dma_ring_get_wptr(struct amdgpu_ring *ring)
> +static uint64_t si_dma_ring_get_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
> @@ -55,7 +55,8 @@ static void si_dma_ring_set_wptr(struct amdgpu_ring *ring)
>   	struct amdgpu_device *adev = ring->adev;
>   	u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
>   
> -	WREG32(DMA_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
> +	WREG32(DMA_RB_WPTR + sdma_offsets[me],
> +	       (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
>   }
>   
>   static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,
> @@ -65,7 +66,7 @@ static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,
>   	/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
>   	 * Pad as necessary with NOPs.
>   	 */
> -	while ((ring->wptr & 7) != 5)
> +	while ((lower_32_bits(ring->wptr) & 7) != 5)
>   		amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
>   	amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vm_id, 0));
>   	amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
> @@ -184,7 +185,7 @@ static int si_dma_start(struct amdgpu_device *adev)
>   		WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl);
>   
>   		ring->wptr = 0;
> -		WREG32(DMA_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
> +		WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
>   		WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE);
>   
>   		ring->ready = true;
> @@ -530,6 +531,7 @@ static int si_dma_sw_init(void *handle)
>   		ring->ring_obj = NULL;
>   		ring->use_doorbell = false;
>   		sprintf(ring->name, "sdma%d", i);
> +		ring->support_64bit_ptrs = false;
>   		r = amdgpu_ring_init(adev, ring, 1024,
>   				     &adev->sdma.trap_irq,
>   				     (i == 0) ?
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> index b34cefc..580c658 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> @@ -55,7 +55,7 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
>    *
>    * Returns the current hardware read pointer
>    */
> -static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
> +static uint64_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -69,7 +69,7 @@ static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
>    *
>    * Returns the current hardware write pointer
>    */
> -static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)
> +static uint64_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -87,7 +87,7 @@ static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> -	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
> +	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
>   }
>   
>   static int uvd_v4_2_early_init(void *handle)
> @@ -121,6 +121,7 @@ static int uvd_v4_2_sw_init(void *handle)
>   
>   	ring = &adev->uvd.ring;
>   	sprintf(ring->name, "uvd");
> +	ring->support_64bit_ptrs = false;
>   	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
>   
>   	return r;
> @@ -367,7 +368,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)
>   	WREG32(mmUVD_RBC_RB_RPTR, 0x0);
>   
>   	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
> -	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
> +	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
>   
>   	/* set the ring address */
>   	WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index ad8c02e..7a4fca0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -51,7 +51,7 @@ static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
>    *
>    * Returns the current hardware read pointer
>    */
> -static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
> +static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -65,7 +65,7 @@ static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
>    *
>    * Returns the current hardware write pointer
>    */
> -static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
> +static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -83,7 +83,7 @@ static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> -	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
> +	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
>   }
>   
>   static int uvd_v5_0_early_init(void *handle)
> @@ -117,6 +117,7 @@ static int uvd_v5_0_sw_init(void *handle)
>   
>   	ring = &adev->uvd.ring;
>   	sprintf(ring->name, "uvd");
> +	ring->support_64bit_ptrs = false;
>   	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
>   
>   	return r;
> @@ -424,7 +425,7 @@ static int uvd_v5_0_start(struct amdgpu_device *adev)
>   	WREG32(mmUVD_RBC_RB_RPTR, 0);
>   
>   	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
> -	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
> +	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
>   
>   	WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 18a6de4..2c5482e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -54,7 +54,7 @@ static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
>    *
>    * Returns the current hardware read pointer
>    */
> -static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
> +static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -68,7 +68,7 @@ static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
>    *
>    * Returns the current hardware write pointer
>    */
> -static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
> +static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -86,7 +86,7 @@ static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> -	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
> +	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
>   }
>   
>   static int uvd_v6_0_early_init(void *handle)
> @@ -120,6 +120,7 @@ static int uvd_v6_0_sw_init(void *handle)
>   
>   	ring = &adev->uvd.ring;
>   	sprintf(ring->name, "uvd");
> +	ring->support_64bit_ptrs = false;
>   	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
>   
>   	return r;
> @@ -521,7 +522,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
>   	WREG32(mmUVD_RBC_RB_RPTR, 0);
>   
>   	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
> -	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
> +	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
>   
>   	WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> index cb0b730f..9a4aa5e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> @@ -52,7 +52,7 @@ static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
>    *
>    * Returns the current hardware read pointer
>    */
> -static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
> +static uint64_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -69,7 +69,7 @@ static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
>    *
>    * Returns the current hardware write pointer
>    */
> -static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
> +static uint64_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -91,9 +91,9 @@ static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
>   	struct amdgpu_device *adev = ring->adev;
>   
>   	if (ring == &adev->vce.ring[0])
> -		WREG32(mmVCE_RB_WPTR, ring->wptr);
> +		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
>   	else
> -		WREG32(mmVCE_RB_WPTR2, ring->wptr);
> +		WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
>   }
>   
>   static int vce_v2_0_lmi_clean(struct amdgpu_device *adev)
> @@ -241,15 +241,15 @@ static int vce_v2_0_start(struct amdgpu_device *adev)
>   	vce_v2_0_mc_resume(adev);
>   
>   	ring = &adev->vce.ring[0];
> -	WREG32(mmVCE_RB_RPTR, ring->wptr);
> -	WREG32(mmVCE_RB_WPTR, ring->wptr);
> +	WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
> +	WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
>   	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
>   	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
>   	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
>   
>   	ring = &adev->vce.ring[1];
> -	WREG32(mmVCE_RB_RPTR2, ring->wptr);
> -	WREG32(mmVCE_RB_WPTR2, ring->wptr);
> +	WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
> +	WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
>   	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
>   	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
>   	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
> @@ -446,6 +446,7 @@ static int vce_v2_0_sw_init(void *handle)
>   	for (i = 0; i < adev->vce.num_rings; i++) {
>   		ring = &adev->vce.ring[i];
>   		sprintf(ring->name, "vce%d", i);
> +		ring->support_64bit_ptrs = false;
>   		r = amdgpu_ring_init(adev, ring, 512,
>   				     &adev->vce.irq, 0);
>   		if (r)
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 93ec881..7877a51 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -73,7 +73,7 @@ static int vce_v3_0_wait_for_idle(void *handle);
>    *
>    * Returns the current hardware read pointer
>    */
> -static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
> +static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -92,7 +92,7 @@ static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
>    *
>    * Returns the current hardware write pointer
>    */
> -static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
> +static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
>   
> @@ -116,11 +116,11 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
>   	struct amdgpu_device *adev = ring->adev;
>   
>   	if (ring == &adev->vce.ring[0])
> -		WREG32(mmVCE_RB_WPTR, ring->wptr);
> +		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
>   	else if (ring == &adev->vce.ring[1])
> -		WREG32(mmVCE_RB_WPTR2, ring->wptr);
> +		WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
>   	else
> -		WREG32(mmVCE_RB_WPTR3, ring->wptr);
> +		WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
>   }
>   
>   static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override)
> @@ -231,22 +231,22 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
>   	int idx, r;
>   
>   	ring = &adev->vce.ring[0];
> -	WREG32(mmVCE_RB_RPTR, ring->wptr);
> -	WREG32(mmVCE_RB_WPTR, ring->wptr);
> +	WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
> +	WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
>   	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
>   	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
>   	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
>   
>   	ring = &adev->vce.ring[1];
> -	WREG32(mmVCE_RB_RPTR2, ring->wptr);
> -	WREG32(mmVCE_RB_WPTR2, ring->wptr);
> +	WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
> +	WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
>   	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
>   	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
>   	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
>   
>   	ring = &adev->vce.ring[2];
> -	WREG32(mmVCE_RB_RPTR3, ring->wptr);
> -	WREG32(mmVCE_RB_WPTR3, ring->wptr);
> +	WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
> +	WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
>   	WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
>   	WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
>   	WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
> @@ -403,6 +403,7 @@ static int vce_v3_0_sw_init(void *handle)
>   	for (i = 0; i < adev->vce.num_rings; i++) {
>   		ring = &adev->vce.ring[i];
>   		sprintf(ring->name, "vce%d", i);
> +		ring->support_64bit_ptrs = false;
>   		r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0);
>   		if (r)
>   			return r;


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Re: [PATCH 02/23] drm/amdgpu: change wptr to 64 bits

[Jerome Glisse]

On Thu, Mar 09, 2017 at 10:57:27AM +0100, Christian König wrote:
> Am 09.03.2017 um 04:44 schrieb Alex Deucher:
> > From: Ken Wang <Qingqing.Wang@amd.com>
> > 
> > Newer asics use 64 bit wptrs
> 
> We need a better patch description. Newer asics doesn't use 64bit wptrs, but
> rather need them!
> 
> E.g. if the wptr is now smaller than the rptr that doesn't indicate a wrap
> around any more.

What does it means ? Doesn't make sense, you are allocating 1TB command
buffer and know you will never run out of space ? ;)

Either we are talking about a ring buffer and then wptr < rptr means wrap
around or we are talking about something new that is not a ring buffer.

64 bits or 32 bits doesn't matter from ring buffer point of view. So i
am puzzle about what this new thing is. Anywhere i can read about this
new command buffer thingy ? Because from where i stand it looks like it
would be better to be something else than a ring buffer if there is no
wrap around.

Cheers,
Jérôme 
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Re: [PATCH 02/23] drm/amdgpu: change wptr to 64 bits

[Christian König]

Am 16.06.2017 um 18:28 schrieb Jerome Glisse:
> On Thu, Mar 09, 2017 at 10:57:27AM +0100, Christian König wrote:
>> Am 09.03.2017 um 04:44 schrieb Alex Deucher:
>>> From: Ken Wang <Qingqing.Wang@amd.com>
>>>
>>> Newer asics use 64 bit wptrs
>> We need a better patch description. Newer asics doesn't use 64bit wptrs, but
>> rather need them!
>>
>> E.g. if the wptr is now smaller than the rptr that doesn't indicate a wrap
>> around any more.
> What does it means ? Doesn't make sense, you are allocating 1TB command
> buffer and know you will never run out of space ? ;)

When the pointers are actually evaluated to a memory address the higher 
bits are masked out.

So your still have a ring buffer of size N, but the pointers into the 
ring buffer are always 64bit. Since they are 64bit the assumption is 
that they never overflow and so the rptr is NEVER bigger than the wptr 
any more.

That solves a few the problems, e.g. when rptr=wptr you don't know if 
the ring buffer is completely full or completely empty (classical 
problem of a ring buffer).

Additional to that if you want to know how many entries are used in the 
ring buffer you just need to calculate wptr - rptr and are done, no wrap 
around handling any more.

Cheers,
Christian.

>
> Either we are talking about a ring buffer and then wptr < rptr means wrap
> around or we are talking about something new that is not a ring buffer.
>
> 64 bits or 32 bits doesn't matter from ring buffer point of view. So i
> am puzzle about what this new thing is. Anywhere i can read about this
> new command buffer thingy ? Because from where i stand it looks like it
> would be better to be something else than a ring buffer if there is no
> wrap around.
>
> Cheers,
> Jérôme


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[PATCH 03/23] drm/amdgpu: add 64bit wb functions

[Alex Deucher]

From: Ken Wang <Qingqing.Wang@amd.com>

Newer asics need 64 bit writeback slots.

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewe-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 39 +++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   | 50 ++++++++++++++++++++++--------
 3 files changed, 78 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a23842d..ab98e7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1016,6 +1016,8 @@ struct amdgpu_wb {
 
 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
+int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
+void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
 
 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 22de440..c2c535c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -516,6 +516,29 @@ int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 }
 
 /**
+ * amdgpu_wb_get_64bit - Allocate a wb entry
+ *
+ * @adev: amdgpu_device pointer
+ * @wb: wb index
+ *
+ * Allocate a wb slot for use by the driver (all asics).
+ * Returns 0 on success or -EINVAL on failure.
+ */
+int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb)
+{
+	unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
+				adev->wb.num_wb, 0, 2, 7, 0);
+	if ((offset + 1) < adev->wb.num_wb) {
+		__set_bit(offset, adev->wb.used);
+		__set_bit(offset + 1, adev->wb.used);
+		*wb = offset;
+		return 0;
+	} else {
+		return -EINVAL;
+	}
+}
+
+/**
  * amdgpu_wb_free - Free a wb entry
  *
  * @adev: amdgpu_device pointer
@@ -530,6 +553,22 @@ void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 }
 
 /**
+ * amdgpu_wb_free_64bit - Free a wb entry
+ *
+ * @adev: amdgpu_device pointer
+ * @wb: wb index
+ *
+ * Free a wb slot allocated for use by the driver (all asics)
+ */
+void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb)
+{
+	if ((wb + 1) < adev->wb.num_wb) {
+		__clear_bit(wb, adev->wb.used);
+		__clear_bit(wb + 1, adev->wb.used);
+	}
+}
+
+/**
  * amdgpu_vram_location - try to find VRAM location
  * @adev: amdgpu device structure holding all necessary informations
  * @mc: memory controller structure holding memory informations
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index f0515b8..fb31a35 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -182,16 +182,32 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 			return r;
 	}
 
-	r = amdgpu_wb_get(adev, &ring->rptr_offs);
-	if (r) {
-		dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
-		return r;
-	}
+	if (ring->support_64bit_ptrs) {
+		r = amdgpu_wb_get_64bit(adev, &ring->rptr_offs);
+		if (r) {
+			dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
+			return r;
+		}
+
+		r = amdgpu_wb_get_64bit(adev, &ring->wptr_offs);
+		if (r) {
+			dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
+			return r;
+		}
+
+	} else {
+		r = amdgpu_wb_get(adev, &ring->rptr_offs);
+		if (r) {
+			dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
+			return r;
+		}
+
+		r = amdgpu_wb_get(adev, &ring->wptr_offs);
+		if (r) {
+			dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
+			return r;
+		}
 
-	r = amdgpu_wb_get(adev, &ring->wptr_offs);
-	if (r) {
-		dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
-		return r;
 	}
 
 	r = amdgpu_wb_get(adev, &ring->fence_offs);
@@ -256,10 +272,18 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
 {
 	ring->ready = false;
 
-	amdgpu_wb_free(ring->adev, ring->cond_exe_offs);
-	amdgpu_wb_free(ring->adev, ring->fence_offs);
-	amdgpu_wb_free(ring->adev, ring->rptr_offs);
-	amdgpu_wb_free(ring->adev, ring->wptr_offs);
+	if (ring->support_64bit_ptrs) {
+		amdgpu_wb_free_64bit(ring->adev, ring->cond_exe_offs);
+		amdgpu_wb_free_64bit(ring->adev, ring->fence_offs);
+		amdgpu_wb_free_64bit(ring->adev, ring->rptr_offs);
+		amdgpu_wb_free_64bit(ring->adev, ring->wptr_offs);
+	} else {
+		amdgpu_wb_free(ring->adev, ring->cond_exe_offs);
+		amdgpu_wb_free(ring->adev, ring->fence_offs);
+		amdgpu_wb_free(ring->adev, ring->rptr_offs);
+		amdgpu_wb_free(ring->adev, ring->wptr_offs);
+	}
+
 
 	amdgpu_bo_free_kernel(&ring->ring_obj,
 			      &ring->gpu_addr,
-- 
2.5.5

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[PATCH 04/23] drm/amdgpu: add 64bit doorbell functions

[Alex Deucher]

From: Ken Wang <Qingqing.Wang@amd.com>

Newer asics need 64 bit doorbells.

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  4 ++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 38 ++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ab98e7f..e917c1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1516,6 +1516,8 @@ void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
 
 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
+u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
+void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
 
 /*
  * Registers read & write functions.
@@ -1570,6 +1572,8 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
 
 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
+#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
+#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
 
 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c2c535c..78b3b0b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -195,6 +195,44 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 }
 
 /**
+ * amdgpu_mm_rdoorbell64 - read a doorbell Qword
+ *
+ * @adev: amdgpu_device pointer
+ * @index: doorbell index
+ *
+ * Returns the value in the doorbell aperture at the
+ * requested doorbell index (VEGA10+).
+ */
+u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
+{
+	if (index < adev->doorbell.num_doorbells) {
+		return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
+	} else {
+		DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
+		return 0;
+	}
+}
+
+/**
+ * amdgpu_mm_wdoorbell64 - write a doorbell dword
+ *
+ * @adev: amdgpu_device pointer
+ * @index: doorbell index
+ * @v: value to write
+ *
+ * Writes @v to the doorbell aperture at the
+ * requested doorbell index (VEGA10+).
+ */
+void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
+{
+	if (index < adev->doorbell.num_doorbells) {
+		atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
+	} else {
+		DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
+	}
+}
+
+/**
  * amdgpu_invalid_rreg - dummy reg read function
  *
  * @adev: amdgpu device pointer
-- 
2.5.5

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[PATCH 05/23] drm/amdgpu: switch ih handling to two levels

[Alex Deucher]

Newer asics have a two levels of irq ids now:
client id - the IP
src id - the interrupt src within the IP

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  |  24 +++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h   |   6 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c  | 111 +++++++++++++++++++++----------
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h  |  10 ++-
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c      |   6 +-
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c    |   9 ++-
 drivers/gpu/drm/amd/amdgpu/cz_ih.c       |   1 +
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c   |   6 +-
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c   |   6 +-
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c    |   6 +-
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c    |   6 +-
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c |   2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c    |   6 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c    |   8 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    |  10 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c    |   4 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c    |   4 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c    |   4 +-
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c  |   1 +
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c      |   6 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c    |   4 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   |   9 ++-
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   |   9 ++-
 drivers/gpu/drm/amd/amdgpu/si_dma.c      |   4 +-
 drivers/gpu/drm/amd/amdgpu/si_dpm.c      |   4 +-
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c    |   1 +
 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c    |   2 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c    |   2 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c    |   2 +-
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c    |   2 +-
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c    |   2 +-
 drivers/gpu/drm/amd/include/cgs_linux.h  |  19 +++---
 32 files changed, 191 insertions(+), 105 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index d9e5aa4..f0e3624 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -571,7 +571,9 @@ static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
 	.process = cgs_process_irq,
 };
 
-static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src_id,
+static int amdgpu_cgs_add_irq_source(void *cgs_device,
+				     unsigned client_id,
+				     unsigned src_id,
 				     unsigned num_types,
 				     cgs_irq_source_set_func_t set,
 				     cgs_irq_handler_func_t handler,
@@ -597,7 +599,7 @@ static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src
 	irq_params->handler = handler;
 	irq_params->private_data = private_data;
 	source->data = (void *)irq_params;
-	ret = amdgpu_irq_add_id(adev, src_id, source);
+	ret = amdgpu_irq_add_id(adev, client_id, src_id, source);
 	if (ret) {
 		kfree(irq_params);
 		kfree(source);
@@ -606,16 +608,26 @@ static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src
 	return ret;
 }
 
-static int amdgpu_cgs_irq_get(struct cgs_device *cgs_device, unsigned src_id, unsigned type)
+static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id,
+			      unsigned src_id, unsigned type)
 {
 	CGS_FUNC_ADEV;
-	return amdgpu_irq_get(adev, adev->irq.sources[src_id], type);
+
+	if (!adev->irq.client[client_id].sources)
+		return -EINVAL;
+
+	return amdgpu_irq_get(adev, adev->irq.client[client_id].sources[src_id], type);
 }
 
-static int amdgpu_cgs_irq_put(struct cgs_device *cgs_device, unsigned src_id, unsigned type)
+static int amdgpu_cgs_irq_put(void *cgs_device, unsigned client_id,
+			      unsigned src_id, unsigned type)
 {
 	CGS_FUNC_ADEV;
-	return amdgpu_irq_put(adev, adev->irq.sources[src_id], type);
+
+	if (!adev->irq.client[client_id].sources)
+		return -EINVAL;
+
+	return amdgpu_irq_put(adev, adev->irq.client[client_id].sources[src_id], type);
 }
 
 static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index ba38ae6..6c5fb83 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -26,6 +26,10 @@
 
 struct amdgpu_device;
 
+#define AMDGPU_IH_CLIENT_ID_ANY 0
+
+#define AMDGPU_IH_CLIENTID_MAX 0x1f
+
 /*
  * R6xx+ IH ring
  */
@@ -47,10 +51,12 @@ struct amdgpu_ih_ring {
 };
 
 struct amdgpu_iv_entry {
+	unsigned client_id;
 	unsigned src_id;
 	unsigned src_data;
 	unsigned ring_id;
 	unsigned vm_id;
+	unsigned vm_id_src;
 	unsigned pas_id;
 	const uint32_t *iv_entry;
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index e63ece0..7e7acd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -89,23 +89,28 @@ static void amdgpu_irq_reset_work_func(struct work_struct *work)
 static void amdgpu_irq_disable_all(struct amdgpu_device *adev)
 {
 	unsigned long irqflags;
-	unsigned i, j;
+	unsigned i, j, k;
 	int r;
 
 	spin_lock_irqsave(&adev->irq.lock, irqflags);
-	for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
-		struct amdgpu_irq_src *src = adev->irq.sources[i];
-
-		if (!src || !src->funcs->set || !src->num_types)
+	for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
+		if (!adev->irq.client[i].sources)
 			continue;
 
-		for (j = 0; j < src->num_types; ++j) {
-			atomic_set(&src->enabled_types[j], 0);
-			r = src->funcs->set(adev, src, j,
-					    AMDGPU_IRQ_STATE_DISABLE);
-			if (r)
-				DRM_ERROR("error disabling interrupt (%d)\n",
-					  r);
+		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
+			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
+
+			if (!src || !src->funcs->set || !src->num_types)
+				continue;
+
+			for (k = 0; k < src->num_types; ++k) {
+				atomic_set(&src->enabled_types[k], 0);
+				r = src->funcs->set(adev, src, k,
+						    AMDGPU_IRQ_STATE_DISABLE);
+				if (r)
+					DRM_ERROR("error disabling interrupt (%d)\n",
+						  r);
+			}
 		}
 	}
 	spin_unlock_irqrestore(&adev->irq.lock, irqflags);
@@ -254,7 +259,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
  */
 void amdgpu_irq_fini(struct amdgpu_device *adev)
 {
-	unsigned i;
+	unsigned i, j;
 
 	drm_vblank_cleanup(adev->ddev);
 	if (adev->irq.installed) {
@@ -266,19 +271,25 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
 		cancel_work_sync(&adev->reset_work);
 	}
 
-	for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
-		struct amdgpu_irq_src *src = adev->irq.sources[i];
-
-		if (!src)
+	for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
+		if (!adev->irq.client[i].sources)
 			continue;
 
-		kfree(src->enabled_types);
-		src->enabled_types = NULL;
-		if (src->data) {
-			kfree(src->data);
-			kfree(src);
-			adev->irq.sources[i] = NULL;
+		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
+			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
+
+			if (!src)
+				continue;
+
+			kfree(src->enabled_types);
+			src->enabled_types = NULL;
+			if (src->data) {
+				kfree(src->data);
+				kfree(src);
+				adev->irq.client[i].sources[j] = NULL;
+			}
 		}
+		kfree(adev->irq.client[i].sources);
 	}
 }
 
@@ -290,18 +301,30 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
  * @source: irq source
  *
  */
-int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
+int amdgpu_irq_add_id(struct amdgpu_device *adev,
+		      unsigned client_id, unsigned src_id,
 		      struct amdgpu_irq_src *source)
 {
-	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
+	if (client_id >= AMDGPU_IH_CLIENTID_MAX)
 		return -EINVAL;
 
-	if (adev->irq.sources[src_id] != NULL)
+	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
 		return -EINVAL;
 
 	if (!source->funcs)
 		return -EINVAL;
 
+	if (!adev->irq.client[client_id].sources) {
+		adev->irq.client[client_id].sources = kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
+							      sizeof(struct amdgpu_irq_src),
+							      GFP_KERNEL);
+		if (!adev->irq.client[client_id].sources)
+			return -ENOMEM;
+	}
+
+	if (adev->irq.client[client_id].sources[src_id] != NULL)
+		return -EINVAL;
+
 	if (source->num_types && !source->enabled_types) {
 		atomic_t *types;
 
@@ -313,8 +336,7 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
 		source->enabled_types = types;
 	}
 
-	adev->irq.sources[src_id] = source;
-
+	adev->irq.client[client_id].sources[src_id] = source;
 	return 0;
 }
 
@@ -329,10 +351,16 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
 			 struct amdgpu_iv_entry *entry)
 {
+	unsigned client_id = entry->client_id;
 	unsigned src_id = entry->src_id;
 	struct amdgpu_irq_src *src;
 	int r;
 
+	if (client_id >= AMDGPU_IH_CLIENTID_MAX) {
+		DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
+		return;
+	}
+
 	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
 		DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
 		return;
@@ -341,7 +369,13 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
 	if (adev->irq.virq[src_id]) {
 		generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
 	} else {
-		src = adev->irq.sources[src_id];
+		if (!adev->irq.client[client_id].sources) {
+			DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
+				  client_id, src_id);
+			return;
+		}
+
+		src = adev->irq.client[client_id].sources[src_id];
 		if (!src) {
 			DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
 			return;
@@ -385,13 +419,20 @@ int amdgpu_irq_update(struct amdgpu_device *adev,
 
 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
 {
-	int i, j;
-	for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; i++) {
-		struct amdgpu_irq_src *src = adev->irq.sources[i];
-		if (!src)
+	int i, j, k;
+
+	for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
+		if (!adev->irq.client[i].sources)
 			continue;
-		for (j = 0; j < src->num_types; j++)
-			amdgpu_irq_update(adev, src, j);
+
+		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
+			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
+
+			if (!src)
+				continue;
+			for (k = 0; k < src->num_types; k++)
+				amdgpu_irq_update(adev, src, k);
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index 1642f41..0610cc4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -28,6 +28,7 @@
 #include "amdgpu_ih.h"
 
 #define AMDGPU_MAX_IRQ_SRC_ID	0x100
+#define AMDGPU_MAX_IRQ_CLIENT_ID	0x100
 
 struct amdgpu_device;
 struct amdgpu_iv_entry;
@@ -44,6 +45,10 @@ struct amdgpu_irq_src {
 	void *data;
 };
 
+struct amdgpu_irq_client {
+	struct amdgpu_irq_src **sources;
+};
+
 /* provided by interrupt generating IP blocks */
 struct amdgpu_irq_src_funcs {
 	int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
@@ -58,7 +63,7 @@ struct amdgpu_irq {
 	bool				installed;
 	spinlock_t			lock;
 	/* interrupt sources */
-	struct amdgpu_irq_src		*sources[AMDGPU_MAX_IRQ_SRC_ID];
+	struct amdgpu_irq_client	client[AMDGPU_IH_CLIENTID_MAX];
 
 	/* status, etc. */
 	bool				msi_enabled; /* msi enabled */
@@ -80,7 +85,8 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg);
 
 int amdgpu_irq_init(struct amdgpu_device *adev);
 void amdgpu_irq_fini(struct amdgpu_device *adev);
-int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
+int amdgpu_irq_add_id(struct amdgpu_device *adev,
+		      unsigned client_id, unsigned src_id,
 		      struct amdgpu_irq_src *source);
 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
 			 struct amdgpu_iv_entry *entry);
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index c8cb964..f0e7229 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6284,11 +6284,13 @@ static int ci_dpm_sw_init(void *handle)
 	int ret;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
+	ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 230,
+				&adev->pm.dpm.thermal.irq);
 	if (ret)
 		return ret;
 
-	ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
+	ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 231,
+				&adev->pm.dpm.thermal.irq);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index b35ec4a..88e92eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -923,17 +923,20 @@ static int cik_sdma_sw_init(void *handle)
 	}
 
 	/* SDMA trap event */
-	r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 224,
+			      &adev->sdma.trap_irq);
 	if (r)
 		return r;
 
 	/* SDMA Privileged inst */
-	r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 241,
+			      &adev->sdma.illegal_inst_irq);
 	if (r)
 		return r;
 
 	/* SDMA Privileged inst */
-	r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 247,
+			      &adev->sdma.illegal_inst_irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index fe7cbb2..124bacc 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -227,6 +227,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
 	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
 	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
 
+	entry->client_id = AMDGPU_IH_CLIENT_ID_ANY;
 	entry->src_id = dw[0] & 0xff;
 	entry->src_data = dw[1] & 0xfffffff;
 	entry->ring_id = dw[2] & 0xff;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index d4452d8..7996296 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2947,19 +2947,19 @@ static int dce_v10_0_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
-		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
+		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i + 1, &adev->crtc_irq);
 		if (r)
 			return r;
 	}
 
 	for (i = 8; i < 20; i += 2) {
-		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
+		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i, &adev->pageflip_irq);
 		if (r)
 			return r;
 	}
 
 	/* HPD hotplug */
-	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 42, &adev->hpd_irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 5b24e89..615049a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3007,19 +3007,19 @@ static int dce_v11_0_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
-		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
+		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i + 1, &adev->crtc_irq);
 		if (r)
 			return r;
 	}
 
 	for (i = 8; i < 20; i += 2) {
-		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
+		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i, &adev->pageflip_irq);
 		if (r)
 			return r;
 	}
 
 	/* HPD hotplug */
-	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 42, &adev->hpd_irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 809aa94..496be98 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2295,19 +2295,19 @@ static int dce_v6_0_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
-		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
+		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i + 1, &adev->crtc_irq);
 		if (r)
 			return r;
 	}
 
 	for (i = 8; i < 20; i += 2) {
-		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
+		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i, &adev->pageflip_irq);
 		if (r)
 			return r;
 	}
 
 	/* HPD hotplug */
-	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 42, &adev->hpd_irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index d2590d7..cd4362e 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2794,19 +2794,19 @@ static int dce_v8_0_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
-		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
+		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i + 1, &adev->crtc_irq);
 		if (r)
 			return r;
 	}
 
 	for (i = 8; i < 20; i += 2) {
-		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
+		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i, &adev->pageflip_irq);
 		if (r)
 			return r;
 	}
 
 	/* HPD hotplug */
-	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 42, &adev->hpd_irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 1538fd1..a2681a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -464,7 +464,7 @@ static int dce_virtual_sw_init(void *handle)
 	int r, i;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	r = amdgpu_irq_add_id(adev, 229, &adev->crtc_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 229, &adev->crtc_irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index cb3d2816..913690a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3242,15 +3242,15 @@ static int gfx_v6_0_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	int i, r;
 
-	r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 181, &adev->gfx.eop_irq);
 	if (r)
 		return r;
 
-	r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 184, &adev->gfx.priv_reg_irq);
 	if (r)
 		return r;
 
-	r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 185, &adev->gfx.priv_inst_irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index e6a25ee..62876b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4669,17 +4669,19 @@ static int gfx_v7_0_sw_init(void *handle)
 	int i, r;
 
 	/* EOP Event */
-	r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 181, &adev->gfx.eop_irq);
 	if (r)
 		return r;
 
 	/* Privileged reg */
-	r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 184,
+			      &adev->gfx.priv_reg_irq);
 	if (r)
 		return r;
 
 	/* Privileged inst */
-	r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 185,
+			      &adev->gfx.priv_inst_irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 304f28c..1af8650 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -2073,22 +2073,24 @@ static int gfx_v8_0_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	/* KIQ event */
-	r = amdgpu_irq_add_id(adev, 178, &adev->gfx.kiq.irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 178, &adev->gfx.kiq.irq);
 	if (r)
 		return r;
 
 	/* EOP Event */
-	r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 181, &adev->gfx.eop_irq);
 	if (r)
 		return r;
 
 	/* Privileged reg */
-	r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 184,
+			      &adev->gfx.priv_reg_irq);
 	if (r)
 		return r;
 
 	/* Privileged inst */
-	r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 185,
+			      &adev->gfx.priv_inst_irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 3328428..f27f565 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -823,11 +823,11 @@ static int gmc_v6_0_sw_init(void *handle)
 	int dma_bits;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 146, &adev->mc.vm_fault);
 	if (r)
 		return r;
 
-	r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 147, &adev->mc.vm_fault);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index dc2b4c7..83fe671 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -968,11 +968,11 @@ static int gmc_v7_0_sw_init(void *handle)
 		adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 	}
 
-	r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 146, &adev->mc.vm_fault);
 	if (r)
 		return r;
 
-	r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 147, &adev->mc.vm_fault);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 81b1a49..92f4832 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -980,11 +980,11 @@ static int gmc_v8_0_sw_init(void *handle)
 		adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
 	}
 
-	r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 146, &adev->mc.vm_fault);
 	if (r)
 		return r;
 
-	r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 147, &adev->mc.vm_fault);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index ac21bb7..8f7ea87 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -227,6 +227,7 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev,
 	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
 	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
 
+	entry->client_id = AMDGPU_IH_CLIENT_ID_ANY;
 	entry->src_id = dw[0] & 0xff;
 	entry->src_data = dw[1] & 0xfffffff;
 	entry->ring_id = dw[2] & 0xff;
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 13f3237..67de81d 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2981,11 +2981,13 @@ static int kv_dpm_sw_init(void *handle)
 	int ret;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
+	ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 230,
+				&adev->pm.dpm.thermal.irq);
 	if (ret)
 		return ret;
 
-	ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
+	ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 231,
+				&adev->pm.dpm.thermal.irq);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index 3164d61..6d06a93 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -566,11 +566,11 @@ int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev)
 {
 	int r;
 
-	r = amdgpu_irq_add_id(adev, 135, &adev->virt.rcv_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 135, &adev->virt.rcv_irq);
 	if (r)
 		return r;
 
-	r = amdgpu_irq_add_id(adev, 138, &adev->virt.ack_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 138, &adev->virt.ack_irq);
 	if (r) {
 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
 		return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index f5ee5f3..861b18b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -921,17 +921,20 @@ static int sdma_v2_4_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	/* SDMA trap event */
-	r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 224,
+			      &adev->sdma.trap_irq);
 	if (r)
 		return r;
 
 	/* SDMA Privileged inst */
-	r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 241,
+			      &adev->sdma.illegal_inst_irq);
 	if (r)
 		return r;
 
 	/* SDMA Privileged inst */
-	r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 247,
+			      &adev->sdma.illegal_inst_irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index e715385..149a18b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1137,17 +1137,20 @@ static int sdma_v3_0_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	/* SDMA trap event */
-	r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 224,
+			      &adev->sdma.trap_irq);
 	if (r)
 		return r;
 
 	/* SDMA Privileged inst */
-	r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 241,
+			      &adev->sdma.illegal_inst_irq);
 	if (r)
 		return r;
 
 	/* SDMA Privileged inst */
-	r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 247,
+			      &adev->sdma.illegal_inst_irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 256a77b..381ae97 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -517,12 +517,12 @@ static int si_dma_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	/* DMA0 trap event */
-	r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 224, &adev->sdma.trap_irq);
 	if (r)
 		return r;
 
 	/* DMA1 trap event */
-	r = amdgpu_irq_add_id(adev, 244, &adev->sdma.trap_irq_1);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 244, &adev->sdma.trap_irq_1);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index ded6b9b..bc4d947 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -7690,11 +7690,11 @@ static int si_dpm_sw_init(void *handle)
 	int ret;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
+	ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 230, &adev->pm.dpm.thermal.irq);
 	if (ret)
 		return ret;
 
-	ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
+	ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 231, &adev->pm.dpm.thermal.irq);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 52b71ee..08bf400 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -238,6 +238,7 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev,
 	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
 	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
 
+	entry->client_id = AMDGPU_IH_CLIENT_ID_ANY;
 	entry->src_id = dw[0] & 0xff;
 	entry->src_data = dw[1] & 0xfffffff;
 	entry->ring_id = dw[2] & 0xff;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 580c658..b9faaf1 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -107,7 +107,7 @@ static int uvd_v4_2_sw_init(void *handle)
 	int r;
 
 	/* UVD TRAP */
-	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 124, &adev->uvd.irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 7a4fca0..9237225 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -103,7 +103,7 @@ static int uvd_v5_0_sw_init(void *handle)
 	int r;
 
 	/* UVD TRAP */
-	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 124, &adev->uvd.irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 2c5482e..29cc982 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -106,7 +106,7 @@ static int uvd_v6_0_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	/* UVD TRAP */
-	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 124, &adev->uvd.irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 9a4aa5e..c06ca90 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -430,7 +430,7 @@ static int vce_v2_0_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	/* VCE */
-	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 167, &adev->vce.irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 7877a51..0605ed9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -383,7 +383,7 @@ static int vce_v3_0_sw_init(void *handle)
 	int r, i;
 
 	/* VCE */
-	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
+	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 167, &adev->vce.irq);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/include/cgs_linux.h b/drivers/gpu/drm/amd/include/cgs_linux.h
index ca4f600..bc7446c 100644
--- a/drivers/gpu/drm/amd/include/cgs_linux.h
+++ b/drivers/gpu/drm/amd/include/cgs_linux.h
@@ -66,7 +66,8 @@ typedef int (*cgs_irq_handler_func_t)(void *private_data,
  *
  * Return:  0 on success, -errno otherwise
  */
-typedef int (*cgs_add_irq_source_t)(struct cgs_device *cgs_device, unsigned src_id,
+typedef int (*cgs_add_irq_source_t)(void *cgs_device, unsigned client_id,
+				    unsigned src_id,
 				    unsigned num_types,
 				    cgs_irq_source_set_func_t set,
 				    cgs_irq_handler_func_t handler,
@@ -83,7 +84,7 @@ typedef int (*cgs_add_irq_source_t)(struct cgs_device *cgs_device, unsigned src_
  *
  * Return:  0 on success, -errno otherwise
  */
-typedef int (*cgs_irq_get_t)(struct cgs_device *cgs_device, unsigned src_id, unsigned type);
+typedef int (*cgs_irq_get_t)(void *cgs_device, unsigned client_id, unsigned src_id, unsigned type);
 
 /**
  * cgs_irq_put() - Indicate IRQ source is no longer needed
@@ -98,7 +99,7 @@ typedef int (*cgs_irq_get_t)(struct cgs_device *cgs_device, unsigned src_id, uns
  *
  * Return:  0 on success, -errno otherwise
  */
-typedef int (*cgs_irq_put_t)(struct cgs_device *cgs_device, unsigned src_id, unsigned type);
+typedef int (*cgs_irq_put_t)(void *cgs_device, unsigned client_id, unsigned src_id, unsigned type);
 
 struct cgs_os_ops {
 	/* IRQ handling */
@@ -107,12 +108,12 @@ struct cgs_os_ops {
 	cgs_irq_put_t irq_put;
 };
 
-#define cgs_add_irq_source(dev,src_id,num_types,set,handler,private_data) \
-	CGS_OS_CALL(add_irq_source,dev,src_id,num_types,set,handler,	\
+#define cgs_add_irq_source(dev,client_id,src_id,num_types,set,handler,private_data) \
+	CGS_OS_CALL(add_irq_source,dev,client_id,src_id,num_types,set,handler, \
 		    private_data)
-#define cgs_irq_get(dev,src_id,type)		\
-	CGS_OS_CALL(irq_get,dev,src_id,type)
-#define cgs_irq_put(dev,src_id,type)		\
-	CGS_OS_CALL(irq_put,dev,src_id,type)
+#define cgs_irq_get(dev,client_id,src_id,type)	\
+	CGS_OS_CALL(irq_get,dev,client_id,src_id,type)
+#define cgs_irq_put(dev,client_id,src_id,type)	\
+	CGS_OS_CALL(irq_put,dev,client_id,src_id,type)
 
 #endif /* _CGS_LINUX_H */
-- 
2.5.5

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Re: [PATCH 05/23] drm/amdgpu: switch ih handling to two levels

[Christian König]

Am 09.03.2017 um 04:44 schrieb Alex Deucher:
> Newer asics have a two levels of irq ids now:
> client id - the IP
> src id - the interrupt src within the IP
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  |  24 +++++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h   |   6 ++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c  | 111 +++++++++++++++++++++----------
>   drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h  |  10 ++-
>   drivers/gpu/drm/amd/amdgpu/ci_dpm.c      |   6 +-
>   drivers/gpu/drm/amd/amdgpu/cik_sdma.c    |   9 ++-
>   drivers/gpu/drm/amd/amdgpu/cz_ih.c       |   1 +
>   drivers/gpu/drm/amd/amdgpu/dce_v10_0.c   |   6 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v11_0.c   |   6 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v6_0.c    |   6 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v8_0.c    |   6 +-
>   drivers/gpu/drm/amd/amdgpu/dce_virtual.c |   2 +-
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c    |   6 +-
>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c    |   8 ++-
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    |  10 +--
>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c    |   4 +-
>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c    |   4 +-
>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c    |   4 +-
>   drivers/gpu/drm/amd/amdgpu/iceland_ih.c  |   1 +
>   drivers/gpu/drm/amd/amdgpu/kv_dpm.c      |   6 +-
>   drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c    |   4 +-
>   drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   |   9 ++-
>   drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   |   9 ++-
>   drivers/gpu/drm/amd/amdgpu/si_dma.c      |   4 +-
>   drivers/gpu/drm/amd/amdgpu/si_dpm.c      |   4 +-
>   drivers/gpu/drm/amd/amdgpu/tonga_ih.c    |   1 +
>   drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c    |   2 +-
>   drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c    |   2 +-
>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c    |   2 +-
>   drivers/gpu/drm/amd/amdgpu/vce_v2_0.c    |   2 +-
>   drivers/gpu/drm/amd/amdgpu/vce_v3_0.c    |   2 +-
>   drivers/gpu/drm/amd/include/cgs_linux.h  |  19 +++---
>   32 files changed, 191 insertions(+), 105 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> index d9e5aa4..f0e3624 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> @@ -571,7 +571,9 @@ static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
>   	.process = cgs_process_irq,
>   };
>   
> -static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src_id,
> +static int amdgpu_cgs_add_irq_source(void *cgs_device,
> +				     unsigned client_id,
> +				     unsigned src_id,
>   				     unsigned num_types,
>   				     cgs_irq_source_set_func_t set,
>   				     cgs_irq_handler_func_t handler,
> @@ -597,7 +599,7 @@ static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src
>   	irq_params->handler = handler;
>   	irq_params->private_data = private_data;
>   	source->data = (void *)irq_params;
> -	ret = amdgpu_irq_add_id(adev, src_id, source);
> +	ret = amdgpu_irq_add_id(adev, client_id, src_id, source);
>   	if (ret) {
>   		kfree(irq_params);
>   		kfree(source);
> @@ -606,16 +608,26 @@ static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src
>   	return ret;
>   }
>   
> -static int amdgpu_cgs_irq_get(struct cgs_device *cgs_device, unsigned src_id, unsigned type)
> +static int amdgpu_cgs_irq_get(void *cgs_device, unsigned client_id,
> +			      unsigned src_id, unsigned type)
>   {
>   	CGS_FUNC_ADEV;
> -	return amdgpu_irq_get(adev, adev->irq.sources[src_id], type);
> +
> +	if (!adev->irq.client[client_id].sources)
> +		return -EINVAL;
> +
> +	return amdgpu_irq_get(adev, adev->irq.client[client_id].sources[src_id], type);
>   }
>   
> -static int amdgpu_cgs_irq_put(struct cgs_device *cgs_device, unsigned src_id, unsigned type)
> +static int amdgpu_cgs_irq_put(void *cgs_device, unsigned client_id,
> +			      unsigned src_id, unsigned type)
>   {
>   	CGS_FUNC_ADEV;
> -	return amdgpu_irq_put(adev, adev->irq.sources[src_id], type);
> +
> +	if (!adev->irq.client[client_id].sources)
> +		return -EINVAL;
> +
> +	return amdgpu_irq_put(adev, adev->irq.client[client_id].sources[src_id], type);
>   }
>   
>   static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> index ba38ae6..6c5fb83 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
> @@ -26,6 +26,10 @@
>   
>   struct amdgpu_device;
>   
> +#define AMDGPU_IH_CLIENT_ID_ANY 0

We should probably rename that to something like 
AMDGPU_IH_CLIENT_ID_LEGACY or similar.

> +
> +#define AMDGPU_IH_CLIENTID_MAX 0x1f

We should probably straighten up the name here, either CLIENT_ID or 
CLIENTID but not mixing it.

Apart from that looks good to me on first glance.

Christian.

> +
>   /*
>    * R6xx+ IH ring
>    */
> @@ -47,10 +51,12 @@ struct amdgpu_ih_ring {
>   };
>   
>   struct amdgpu_iv_entry {
> +	unsigned client_id;
>   	unsigned src_id;
>   	unsigned src_data;
>   	unsigned ring_id;
>   	unsigned vm_id;
> +	unsigned vm_id_src;
>   	unsigned pas_id;
>   	const uint32_t *iv_entry;
>   };
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index e63ece0..7e7acd4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -89,23 +89,28 @@ static void amdgpu_irq_reset_work_func(struct work_struct *work)
>   static void amdgpu_irq_disable_all(struct amdgpu_device *adev)
>   {
>   	unsigned long irqflags;
> -	unsigned i, j;
> +	unsigned i, j, k;
>   	int r;
>   
>   	spin_lock_irqsave(&adev->irq.lock, irqflags);
> -	for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
> -		struct amdgpu_irq_src *src = adev->irq.sources[i];
> -
> -		if (!src || !src->funcs->set || !src->num_types)
> +	for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
> +		if (!adev->irq.client[i].sources)
>   			continue;
>   
> -		for (j = 0; j < src->num_types; ++j) {
> -			atomic_set(&src->enabled_types[j], 0);
> -			r = src->funcs->set(adev, src, j,
> -					    AMDGPU_IRQ_STATE_DISABLE);
> -			if (r)
> -				DRM_ERROR("error disabling interrupt (%d)\n",
> -					  r);
> +		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
> +			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
> +
> +			if (!src || !src->funcs->set || !src->num_types)
> +				continue;
> +
> +			for (k = 0; k < src->num_types; ++k) {
> +				atomic_set(&src->enabled_types[k], 0);
> +				r = src->funcs->set(adev, src, k,
> +						    AMDGPU_IRQ_STATE_DISABLE);
> +				if (r)
> +					DRM_ERROR("error disabling interrupt (%d)\n",
> +						  r);
> +			}
>   		}
>   	}
>   	spin_unlock_irqrestore(&adev->irq.lock, irqflags);
> @@ -254,7 +259,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
>    */
>   void amdgpu_irq_fini(struct amdgpu_device *adev)
>   {
> -	unsigned i;
> +	unsigned i, j;
>   
>   	drm_vblank_cleanup(adev->ddev);
>   	if (adev->irq.installed) {
> @@ -266,19 +271,25 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
>   		cancel_work_sync(&adev->reset_work);
>   	}
>   
> -	for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
> -		struct amdgpu_irq_src *src = adev->irq.sources[i];
> -
> -		if (!src)
> +	for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
> +		if (!adev->irq.client[i].sources)
>   			continue;
>   
> -		kfree(src->enabled_types);
> -		src->enabled_types = NULL;
> -		if (src->data) {
> -			kfree(src->data);
> -			kfree(src);
> -			adev->irq.sources[i] = NULL;
> +		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
> +			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
> +
> +			if (!src)
> +				continue;
> +
> +			kfree(src->enabled_types);
> +			src->enabled_types = NULL;
> +			if (src->data) {
> +				kfree(src->data);
> +				kfree(src);
> +				adev->irq.client[i].sources[j] = NULL;
> +			}
>   		}
> +		kfree(adev->irq.client[i].sources);
>   	}
>   }
>   
> @@ -290,18 +301,30 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
>    * @source: irq source
>    *
>    */
> -int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
> +int amdgpu_irq_add_id(struct amdgpu_device *adev,
> +		      unsigned client_id, unsigned src_id,
>   		      struct amdgpu_irq_src *source)
>   {
> -	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
> +	if (client_id >= AMDGPU_IH_CLIENTID_MAX)
>   		return -EINVAL;
>   
> -	if (adev->irq.sources[src_id] != NULL)
> +	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
>   		return -EINVAL;
>   
>   	if (!source->funcs)
>   		return -EINVAL;
>   
> +	if (!adev->irq.client[client_id].sources) {
> +		adev->irq.client[client_id].sources = kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
> +							      sizeof(struct amdgpu_irq_src),
> +							      GFP_KERNEL);
> +		if (!adev->irq.client[client_id].sources)
> +			return -ENOMEM;
> +	}
> +
> +	if (adev->irq.client[client_id].sources[src_id] != NULL)
> +		return -EINVAL;
> +
>   	if (source->num_types && !source->enabled_types) {
>   		atomic_t *types;
>   
> @@ -313,8 +336,7 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
>   		source->enabled_types = types;
>   	}
>   
> -	adev->irq.sources[src_id] = source;
> -
> +	adev->irq.client[client_id].sources[src_id] = source;
>   	return 0;
>   }
>   
> @@ -329,10 +351,16 @@ int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
>   void amdgpu_irq_dispatch(struct amdgpu_device *adev,
>   			 struct amdgpu_iv_entry *entry)
>   {
> +	unsigned client_id = entry->client_id;
>   	unsigned src_id = entry->src_id;
>   	struct amdgpu_irq_src *src;
>   	int r;
>   
> +	if (client_id >= AMDGPU_IH_CLIENTID_MAX) {
> +		DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
> +		return;
> +	}
> +
>   	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
>   		DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
>   		return;
> @@ -341,7 +369,13 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
>   	if (adev->irq.virq[src_id]) {
>   		generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
>   	} else {
> -		src = adev->irq.sources[src_id];
> +		if (!adev->irq.client[client_id].sources) {
> +			DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
> +				  client_id, src_id);
> +			return;
> +		}
> +
> +		src = adev->irq.client[client_id].sources[src_id];
>   		if (!src) {
>   			DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
>   			return;
> @@ -385,13 +419,20 @@ int amdgpu_irq_update(struct amdgpu_device *adev,
>   
>   void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
>   {
> -	int i, j;
> -	for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; i++) {
> -		struct amdgpu_irq_src *src = adev->irq.sources[i];
> -		if (!src)
> +	int i, j, k;
> +
> +	for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
> +		if (!adev->irq.client[i].sources)
>   			continue;
> -		for (j = 0; j < src->num_types; j++)
> -			amdgpu_irq_update(adev, src, j);
> +
> +		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
> +			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
> +
> +			if (!src)
> +				continue;
> +			for (k = 0; k < src->num_types; k++)
> +				amdgpu_irq_update(adev, src, k);
> +		}
>   	}
>   }
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> index 1642f41..0610cc4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> @@ -28,6 +28,7 @@
>   #include "amdgpu_ih.h"
>   
>   #define AMDGPU_MAX_IRQ_SRC_ID	0x100
> +#define AMDGPU_MAX_IRQ_CLIENT_ID	0x100
>   
>   struct amdgpu_device;
>   struct amdgpu_iv_entry;
> @@ -44,6 +45,10 @@ struct amdgpu_irq_src {
>   	void *data;
>   };
>   
> +struct amdgpu_irq_client {
> +	struct amdgpu_irq_src **sources;
> +};
> +
>   /* provided by interrupt generating IP blocks */
>   struct amdgpu_irq_src_funcs {
>   	int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
> @@ -58,7 +63,7 @@ struct amdgpu_irq {
>   	bool				installed;
>   	spinlock_t			lock;
>   	/* interrupt sources */
> -	struct amdgpu_irq_src		*sources[AMDGPU_MAX_IRQ_SRC_ID];
> +	struct amdgpu_irq_client	client[AMDGPU_IH_CLIENTID_MAX];
>   
>   	/* status, etc. */
>   	bool				msi_enabled; /* msi enabled */
> @@ -80,7 +85,8 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg);
>   
>   int amdgpu_irq_init(struct amdgpu_device *adev);
>   void amdgpu_irq_fini(struct amdgpu_device *adev);
> -int amdgpu_irq_add_id(struct amdgpu_device *adev, unsigned src_id,
> +int amdgpu_irq_add_id(struct amdgpu_device *adev,
> +		      unsigned client_id, unsigned src_id,
>   		      struct amdgpu_irq_src *source);
>   void amdgpu_irq_dispatch(struct amdgpu_device *adev,
>   			 struct amdgpu_iv_entry *entry);
> diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> index c8cb964..f0e7229 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
> @@ -6284,11 +6284,13 @@ static int ci_dpm_sw_init(void *handle)
>   	int ret;
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> -	ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
> +	ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 230,
> +				&adev->pm.dpm.thermal.irq);
>   	if (ret)
>   		return ret;
>   
> -	ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
> +	ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 231,
> +				&adev->pm.dpm.thermal.irq);
>   	if (ret)
>   		return ret;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index b35ec4a..88e92eb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -923,17 +923,20 @@ static int cik_sdma_sw_init(void *handle)
>   	}
>   
>   	/* SDMA trap event */
> -	r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 224,
> +			      &adev->sdma.trap_irq);
>   	if (r)
>   		return r;
>   
>   	/* SDMA Privileged inst */
> -	r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 241,
> +			      &adev->sdma.illegal_inst_irq);
>   	if (r)
>   		return r;
>   
>   	/* SDMA Privileged inst */
> -	r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 247,
> +			      &adev->sdma.illegal_inst_irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index fe7cbb2..124bacc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -227,6 +227,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
>   	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
>   	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
>   
> +	entry->client_id = AMDGPU_IH_CLIENT_ID_ANY;
>   	entry->src_id = dw[0] & 0xff;
>   	entry->src_data = dw[1] & 0xfffffff;
>   	entry->ring_id = dw[2] & 0xff;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index d4452d8..7996296 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -2947,19 +2947,19 @@ static int dce_v10_0_sw_init(void *handle)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
>   	for (i = 0; i < adev->mode_info.num_crtc; i++) {
> -		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
> +		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i + 1, &adev->crtc_irq);
>   		if (r)
>   			return r;
>   	}
>   
>   	for (i = 8; i < 20; i += 2) {
> -		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
> +		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i, &adev->pageflip_irq);
>   		if (r)
>   			return r;
>   	}
>   
>   	/* HPD hotplug */
> -	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 42, &adev->hpd_irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 5b24e89..615049a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -3007,19 +3007,19 @@ static int dce_v11_0_sw_init(void *handle)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
>   	for (i = 0; i < adev->mode_info.num_crtc; i++) {
> -		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
> +		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i + 1, &adev->crtc_irq);
>   		if (r)
>   			return r;
>   	}
>   
>   	for (i = 8; i < 20; i += 2) {
> -		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
> +		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i, &adev->pageflip_irq);
>   		if (r)
>   			return r;
>   	}
>   
>   	/* HPD hotplug */
> -	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 42, &adev->hpd_irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 809aa94..496be98 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -2295,19 +2295,19 @@ static int dce_v6_0_sw_init(void *handle)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
>   	for (i = 0; i < adev->mode_info.num_crtc; i++) {
> -		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
> +		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i + 1, &adev->crtc_irq);
>   		if (r)
>   			return r;
>   	}
>   
>   	for (i = 8; i < 20; i += 2) {
> -		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
> +		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i, &adev->pageflip_irq);
>   		if (r)
>   			return r;
>   	}
>   
>   	/* HPD hotplug */
> -	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 42, &adev->hpd_irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index d2590d7..cd4362e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> @@ -2794,19 +2794,19 @@ static int dce_v8_0_sw_init(void *handle)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
>   	for (i = 0; i < adev->mode_info.num_crtc; i++) {
> -		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
> +		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i + 1, &adev->crtc_irq);
>   		if (r)
>   			return r;
>   	}
>   
>   	for (i = 8; i < 20; i += 2) {
> -		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
> +		r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, i, &adev->pageflip_irq);
>   		if (r)
>   			return r;
>   	}
>   
>   	/* HPD hotplug */
> -	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 42, &adev->hpd_irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> index 1538fd1..a2681a8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> @@ -464,7 +464,7 @@ static int dce_virtual_sw_init(void *handle)
>   	int r, i;
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> -	r = amdgpu_irq_add_id(adev, 229, &adev->crtc_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 229, &adev->crtc_irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index cb3d2816..913690a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -3242,15 +3242,15 @@ static int gfx_v6_0_sw_init(void *handle)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   	int i, r;
>   
> -	r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 181, &adev->gfx.eop_irq);
>   	if (r)
>   		return r;
>   
> -	r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 184, &adev->gfx.priv_reg_irq);
>   	if (r)
>   		return r;
>   
> -	r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 185, &adev->gfx.priv_inst_irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index e6a25ee..62876b0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -4669,17 +4669,19 @@ static int gfx_v7_0_sw_init(void *handle)
>   	int i, r;
>   
>   	/* EOP Event */
> -	r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 181, &adev->gfx.eop_irq);
>   	if (r)
>   		return r;
>   
>   	/* Privileged reg */
> -	r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 184,
> +			      &adev->gfx.priv_reg_irq);
>   	if (r)
>   		return r;
>   
>   	/* Privileged inst */
> -	r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 185,
> +			      &adev->gfx.priv_inst_irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 304f28c..1af8650 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -2073,22 +2073,24 @@ static int gfx_v8_0_sw_init(void *handle)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
>   	/* KIQ event */
> -	r = amdgpu_irq_add_id(adev, 178, &adev->gfx.kiq.irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 178, &adev->gfx.kiq.irq);
>   	if (r)
>   		return r;
>   
>   	/* EOP Event */
> -	r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 181, &adev->gfx.eop_irq);
>   	if (r)
>   		return r;
>   
>   	/* Privileged reg */
> -	r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 184,
> +			      &adev->gfx.priv_reg_irq);
>   	if (r)
>   		return r;
>   
>   	/* Privileged inst */
> -	r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 185,
> +			      &adev->gfx.priv_inst_irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 3328428..f27f565 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -823,11 +823,11 @@ static int gmc_v6_0_sw_init(void *handle)
>   	int dma_bits;
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> -	r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 146, &adev->mc.vm_fault);
>   	if (r)
>   		return r;
>   
> -	r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 147, &adev->mc.vm_fault);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index dc2b4c7..83fe671 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -968,11 +968,11 @@ static int gmc_v7_0_sw_init(void *handle)
>   		adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
>   	}
>   
> -	r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 146, &adev->mc.vm_fault);
>   	if (r)
>   		return r;
>   
> -	r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 147, &adev->mc.vm_fault);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 81b1a49..92f4832 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -980,11 +980,11 @@ static int gmc_v8_0_sw_init(void *handle)
>   		adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
>   	}
>   
> -	r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 146, &adev->mc.vm_fault);
>   	if (r)
>   		return r;
>   
> -	r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 147, &adev->mc.vm_fault);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index ac21bb7..8f7ea87 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -227,6 +227,7 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev,
>   	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
>   	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
>   
> +	entry->client_id = AMDGPU_IH_CLIENT_ID_ANY;
>   	entry->src_id = dw[0] & 0xff;
>   	entry->src_data = dw[1] & 0xfffffff;
>   	entry->ring_id = dw[2] & 0xff;
> diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> index 13f3237..67de81d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
> @@ -2981,11 +2981,13 @@ static int kv_dpm_sw_init(void *handle)
>   	int ret;
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> -	ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
> +	ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 230,
> +				&adev->pm.dpm.thermal.irq);
>   	if (ret)
>   		return ret;
>   
> -	ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
> +	ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 231,
> +				&adev->pm.dpm.thermal.irq);
>   	if (ret)
>   		return ret;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> index 3164d61..6d06a93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> @@ -566,11 +566,11 @@ int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev)
>   {
>   	int r;
>   
> -	r = amdgpu_irq_add_id(adev, 135, &adev->virt.rcv_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 135, &adev->virt.rcv_irq);
>   	if (r)
>   		return r;
>   
> -	r = amdgpu_irq_add_id(adev, 138, &adev->virt.ack_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 138, &adev->virt.ack_irq);
>   	if (r) {
>   		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
>   		return r;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index f5ee5f3..861b18b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -921,17 +921,20 @@ static int sdma_v2_4_sw_init(void *handle)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
>   	/* SDMA trap event */
> -	r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 224,
> +			      &adev->sdma.trap_irq);
>   	if (r)
>   		return r;
>   
>   	/* SDMA Privileged inst */
> -	r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 241,
> +			      &adev->sdma.illegal_inst_irq);
>   	if (r)
>   		return r;
>   
>   	/* SDMA Privileged inst */
> -	r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 247,
> +			      &adev->sdma.illegal_inst_irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index e715385..149a18b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -1137,17 +1137,20 @@ static int sdma_v3_0_sw_init(void *handle)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
>   	/* SDMA trap event */
> -	r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 224,
> +			      &adev->sdma.trap_irq);
>   	if (r)
>   		return r;
>   
>   	/* SDMA Privileged inst */
> -	r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 241,
> +			      &adev->sdma.illegal_inst_irq);
>   	if (r)
>   		return r;
>   
>   	/* SDMA Privileged inst */
> -	r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 247,
> +			      &adev->sdma.illegal_inst_irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index 256a77b..381ae97 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -517,12 +517,12 @@ static int si_dma_sw_init(void *handle)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
>   	/* DMA0 trap event */
> -	r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 224, &adev->sdma.trap_irq);
>   	if (r)
>   		return r;
>   
>   	/* DMA1 trap event */
> -	r = amdgpu_irq_add_id(adev, 244, &adev->sdma.trap_irq_1);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 244, &adev->sdma.trap_irq_1);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> index ded6b9b..bc4d947 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
> @@ -7690,11 +7690,11 @@ static int si_dpm_sw_init(void *handle)
>   	int ret;
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> -	ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
> +	ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 230, &adev->pm.dpm.thermal.irq);
>   	if (ret)
>   		return ret;
>   
> -	ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
> +	ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 231, &adev->pm.dpm.thermal.irq);
>   	if (ret)
>   		return ret;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 52b71ee..08bf400 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -238,6 +238,7 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev,
>   	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
>   	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
>   
> +	entry->client_id = AMDGPU_IH_CLIENT_ID_ANY;
>   	entry->src_id = dw[0] & 0xff;
>   	entry->src_data = dw[1] & 0xfffffff;
>   	entry->ring_id = dw[2] & 0xff;
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> index 580c658..b9faaf1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> @@ -107,7 +107,7 @@ static int uvd_v4_2_sw_init(void *handle)
>   	int r;
>   
>   	/* UVD TRAP */
> -	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 124, &adev->uvd.irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index 7a4fca0..9237225 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -103,7 +103,7 @@ static int uvd_v5_0_sw_init(void *handle)
>   	int r;
>   
>   	/* UVD TRAP */
> -	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 124, &adev->uvd.irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 2c5482e..29cc982 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -106,7 +106,7 @@ static int uvd_v6_0_sw_init(void *handle)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
>   	/* UVD TRAP */
> -	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 124, &adev->uvd.irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> index 9a4aa5e..c06ca90 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> @@ -430,7 +430,7 @@ static int vce_v2_0_sw_init(void *handle)
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
>   	/* VCE */
> -	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 167, &adev->vce.irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 7877a51..0605ed9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -383,7 +383,7 @@ static int vce_v3_0_sw_init(void *handle)
>   	int r, i;
>   
>   	/* VCE */
> -	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
> +	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENT_ID_ANY, 167, &adev->vce.irq);
>   	if (r)
>   		return r;
>   
> diff --git a/drivers/gpu/drm/amd/include/cgs_linux.h b/drivers/gpu/drm/amd/include/cgs_linux.h
> index ca4f600..bc7446c 100644
> --- a/drivers/gpu/drm/amd/include/cgs_linux.h
> +++ b/drivers/gpu/drm/amd/include/cgs_linux.h
> @@ -66,7 +66,8 @@ typedef int (*cgs_irq_handler_func_t)(void *private_data,
>    *
>    * Return:  0 on success, -errno otherwise
>    */
> -typedef int (*cgs_add_irq_source_t)(struct cgs_device *cgs_device, unsigned src_id,
> +typedef int (*cgs_add_irq_source_t)(void *cgs_device, unsigned client_id,
> +				    unsigned src_id,
>   				    unsigned num_types,
>   				    cgs_irq_source_set_func_t set,
>   				    cgs_irq_handler_func_t handler,
> @@ -83,7 +84,7 @@ typedef int (*cgs_add_irq_source_t)(struct cgs_device *cgs_device, unsigned src_
>    *
>    * Return:  0 on success, -errno otherwise
>    */
> -typedef int (*cgs_irq_get_t)(struct cgs_device *cgs_device, unsigned src_id, unsigned type);
> +typedef int (*cgs_irq_get_t)(void *cgs_device, unsigned client_id, unsigned src_id, unsigned type);
>   
>   /**
>    * cgs_irq_put() - Indicate IRQ source is no longer needed
> @@ -98,7 +99,7 @@ typedef int (*cgs_irq_get_t)(struct cgs_device *cgs_device, unsigned src_id, uns
>    *
>    * Return:  0 on success, -errno otherwise
>    */
> -typedef int (*cgs_irq_put_t)(struct cgs_device *cgs_device, unsigned src_id, unsigned type);
> +typedef int (*cgs_irq_put_t)(void *cgs_device, unsigned client_id, unsigned src_id, unsigned type);
>   
>   struct cgs_os_ops {
>   	/* IRQ handling */
> @@ -107,12 +108,12 @@ struct cgs_os_ops {
>   	cgs_irq_put_t irq_put;
>   };
>   
> -#define cgs_add_irq_source(dev,src_id,num_types,set,handler,private_data) \
> -	CGS_OS_CALL(add_irq_source,dev,src_id,num_types,set,handler,	\
> +#define cgs_add_irq_source(dev,client_id,src_id,num_types,set,handler,private_data) \
> +	CGS_OS_CALL(add_irq_source,dev,client_id,src_id,num_types,set,handler, \
>   		    private_data)
> -#define cgs_irq_get(dev,src_id,type)		\
> -	CGS_OS_CALL(irq_get,dev,src_id,type)
> -#define cgs_irq_put(dev,src_id,type)		\
> -	CGS_OS_CALL(irq_put,dev,src_id,type)
> +#define cgs_irq_get(dev,client_id,src_id,type)	\
> +	CGS_OS_CALL(irq_get,dev,client_id,src_id,type)
> +#define cgs_irq_put(dev,client_id,src_id,type)	\
> +	CGS_OS_CALL(irq_put,dev,client_id,src_id,type)
>   
>   #endif /* _CGS_LINUX_H */


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[PATCH 06/23] drm/amdgpu/ih: store the full context id

[Alex Deucher]

The contextID field (formerly known as src_data) of the IH
vector stores client specific information about an interrupt.
It was expanded from 32 bits to 128 on newer asics.  Expand the
src_id field to handle this.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h  |  4 +++-
 drivers/gpu/drm/amd/amdgpu/cik_ih.c     |  2 +-
 drivers/gpu/drm/amd/amdgpu/cz_ih.c      |  2 +-
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c  | 10 +++++-----
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c  | 10 +++++-----
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c   | 10 +++++-----
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c   | 10 +++++-----
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   |  4 ++--
 drivers/gpu/drm/amd/amdgpu/iceland_ih.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/si_ih.c      |  2 +-
 drivers/gpu/drm/amd/amdgpu/tonga_ih.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c   |  6 +++---
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c   |  6 +++---
 15 files changed, 38 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 6c5fb83..657d0ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -50,10 +50,12 @@ struct amdgpu_ih_ring {
 	dma_addr_t		rb_dma_addr; /* only used when use_bus_addr = true */
 };
 
+#define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4
+
 struct amdgpu_iv_entry {
 	unsigned client_id;
 	unsigned src_id;
-	unsigned src_data;
+	unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
 	unsigned ring_id;
 	unsigned vm_id;
 	unsigned vm_id_src;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 319b32c..163ffa3 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -249,7 +249,7 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
 	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
 
 	entry->src_id = dw[0] & 0xff;
-	entry->src_data = dw[1] & 0xfffffff;
+	entry->src_data[0] = dw[1] & 0xfffffff;
 	entry->ring_id = dw[2] & 0xff;
 	entry->vm_id = (dw[2] >> 8) & 0xff;
 	entry->pas_id = (dw[2] >> 16) & 0xffff;
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 124bacc..351f915 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -229,7 +229,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
 
 	entry->client_id = AMDGPU_IH_CLIENT_ID_ANY;
 	entry->src_id = dw[0] & 0xff;
-	entry->src_data = dw[1] & 0xfffffff;
+	entry->src_data[0] = dw[1] & 0xfffffff;
 	entry->ring_id = dw[2] & 0xff;
 	entry->vm_id = (dw[2] >> 8) & 0xff;
 	entry->pas_id = (dw[2] >> 16) & 0xffff;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 7996296..d71bca3 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3398,7 +3398,7 @@ static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
 	unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
 
-	switch (entry->src_data) {
+	switch (entry->src_data[0]) {
 	case 0: /* vblank */
 		if (disp_int & interrupt_status_offsets[crtc].vblank)
 			dce_v10_0_crtc_vblank_int_ack(adev, crtc);
@@ -3421,7 +3421,7 @@ static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
 
 		break;
 	default:
-		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
 		break;
 	}
 
@@ -3435,12 +3435,12 @@ static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
 	uint32_t disp_int, mask;
 	unsigned hpd;
 
-	if (entry->src_data >= adev->mode_info.num_hpd) {
-		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+	if (entry->src_data[0] >= adev->mode_info.num_hpd) {
+		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
 		return 0;
 	}
 
-	hpd = entry->src_data;
+	hpd = entry->src_data[0];
 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
 	mask = interrupt_status_offsets[hpd].hpd;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 615049a..9df88ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3462,7 +3462,7 @@ static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
 	unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
 
-	switch (entry->src_data) {
+	switch (entry->src_data[0]) {
 	case 0: /* vblank */
 		if (disp_int & interrupt_status_offsets[crtc].vblank)
 			dce_v11_0_crtc_vblank_int_ack(adev, crtc);
@@ -3485,7 +3485,7 @@ static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
 
 		break;
 	default:
-		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
 		break;
 	}
 
@@ -3499,12 +3499,12 @@ static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
 	uint32_t disp_int, mask;
 	unsigned hpd;
 
-	if (entry->src_data >= adev->mode_info.num_hpd) {
-		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+	if (entry->src_data[0] >= adev->mode_info.num_hpd) {
+		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
 		return 0;
 	}
 
-	hpd = entry->src_data;
+	hpd = entry->src_data[0];
 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
 	mask = interrupt_status_offsets[hpd].hpd;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 496be98..027d612 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2592,7 +2592,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
 	unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
 
-	switch (entry->src_data) {
+	switch (entry->src_data[0]) {
 	case 0: /* vblank */
 		if (disp_int & interrupt_status_offsets[crtc].vblank)
 			WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
@@ -2613,7 +2613,7 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
 		DRM_DEBUG("IH: D%d vline\n", crtc + 1);
 		break;
 	default:
-		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
 		break;
 	}
 
@@ -2703,12 +2703,12 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
 	uint32_t disp_int, mask, tmp;
 	unsigned hpd;
 
-	if (entry->src_data >= adev->mode_info.num_hpd) {
-		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+	if (entry->src_data[0] >= adev->mode_info.num_hpd) {
+		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
 		return 0;
 	}
 
-	hpd = entry->src_data;
+	hpd = entry->src_data[0];
 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
 	mask = interrupt_status_offsets[hpd].hpd;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index cd4362e..df59257 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -3159,7 +3159,7 @@ static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
 	unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
 
-	switch (entry->src_data) {
+	switch (entry->src_data[0]) {
 	case 0: /* vblank */
 		if (disp_int & interrupt_status_offsets[crtc].vblank)
 			WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
@@ -3180,7 +3180,7 @@ static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
 		DRM_DEBUG("IH: D%d vline\n", crtc + 1);
 		break;
 	default:
-		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
 		break;
 	}
 
@@ -3270,12 +3270,12 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
 	uint32_t disp_int, mask, tmp;
 	unsigned hpd;
 
-	if (entry->src_data >= adev->mode_info.num_hpd) {
-		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+	if (entry->src_data[0] >= adev->mode_info.num_hpd) {
+		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
 		return 0;
 	}
 
-	hpd = entry->src_data;
+	hpd = entry->src_data[0];
 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
 	mask = interrupt_status_offsets[hpd].hpd;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index f27f565..f69464c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -1093,7 +1093,7 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
 
 	if (printk_ratelimit()) {
 		dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
-			entry->src_id, entry->src_data);
+			entry->src_id, entry->src_data[0]);
 		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
 			addr);
 		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 83fe671..984d4cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1263,7 +1263,7 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
 
 	if (printk_ratelimit()) {
 		dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
-			entry->src_id, entry->src_data);
+			entry->src_id, entry->src_data[0]);
 		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
 			addr);
 		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 92f4832..d031fa8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1300,7 +1300,7 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
 
 	if (amdgpu_sriov_vf(adev)) {
 		dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
-			entry->src_id, entry->src_data);
+			entry->src_id, entry->src_data[0]);
 		dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
 		return 0;
 	}
@@ -1319,7 +1319,7 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
 
 	if (printk_ratelimit()) {
 		dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
-			entry->src_id, entry->src_data);
+			entry->src_id, entry->src_data[0]);
 		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
 			addr);
 		dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 8f7ea87..111276d 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -229,7 +229,7 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev,
 
 	entry->client_id = AMDGPU_IH_CLIENT_ID_ANY;
 	entry->src_id = dw[0] & 0xff;
-	entry->src_data = dw[1] & 0xfffffff;
+	entry->src_data[0] = dw[1] & 0xfffffff;
 	entry->ring_id = dw[2] & 0xff;
 	entry->vm_id = (dw[2] >> 8) & 0xff;
 	entry->pas_id = (dw[2] >> 16) & 0xffff;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 81f9080..8db9ce7 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -130,7 +130,7 @@ static void si_ih_decode_iv(struct amdgpu_device *adev,
 	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
 
 	entry->src_id = dw[0] & 0xff;
-	entry->src_data = dw[1] & 0xfffffff;
+	entry->src_data[0] = dw[1] & 0xfffffff;
 	entry->ring_id = dw[2] & 0xff;
 	entry->vm_id = (dw[2] >> 8) & 0xff;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 08bf400..f79e62a 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -240,7 +240,7 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev,
 
 	entry->client_id = AMDGPU_IH_CLIENT_ID_ANY;
 	entry->src_id = dw[0] & 0xff;
-	entry->src_data = dw[1] & 0xfffffff;
+	entry->src_data[0] = dw[1] & 0xfffffff;
 	entry->ring_id = dw[2] & 0xff;
 	entry->vm_id = (dw[2] >> 8) & 0xff;
 	entry->pas_id = (dw[2] >> 16) & 0xffff;
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index c06ca90..dfaf898 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -561,14 +561,14 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
 				      struct amdgpu_iv_entry *entry)
 {
 	DRM_DEBUG("IH: VCE\n");
-	switch (entry->src_data) {
+	switch (entry->src_data[0]) {
 	case 0:
 	case 1:
-		amdgpu_fence_process(&adev->vce.ring[entry->src_data]);
+		amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);
 		break;
 	default:
 		DRM_ERROR("Unhandled interrupt: %d %d\n",
-			  entry->src_id, entry->src_data);
+			  entry->src_id, entry->src_data[0]);
 		break;
 	}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 0605ed9..83f753b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -696,15 +696,15 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
 
 	WREG32_FIELD(VCE_SYS_INT_STATUS, VCE_SYS_INT_TRAP_INTERRUPT_INT, 1);
 
-	switch (entry->src_data) {
+	switch (entry->src_data[0]) {
 	case 0:
 	case 1:
 	case 2:
-		amdgpu_fence_process(&adev->vce.ring[entry->src_data]);
+		amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);
 		break;
 	default:
 		DRM_ERROR("Unhandled interrupt: %d %d\n",
-			  entry->src_id, entry->src_data);
+			  entry->src_id, entry->src_data[0]);
 		break;
 	}
 
-- 
2.5.5

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[PATCH 07/23] drm/amdgpu: expand pte flags to uint64_t

[Alex Deucher]

From: Chunming Zhou <David1.Zhou@amd.com>

Necessary for new asics.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  8 ++++----
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |  6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 18 +++++++++---------
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c    |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c    |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c    |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c    |  2 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/si_dma.c      |  2 +-
 11 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e917c1d..8c3f47b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -280,7 +280,7 @@ struct amdgpu_vm_pte_funcs {
 	void (*set_pte_pde)(struct amdgpu_ib *ib,
 			    uint64_t pe,
 			    uint64_t addr, unsigned count,
-			    uint32_t incr, uint32_t flags);
+			    uint32_t incr, uint64_t flags);
 };
 
 /* provided by the gmc block */
@@ -293,7 +293,7 @@ struct amdgpu_gart_funcs {
 			   void *cpu_pt_addr, /* cpu addr of page table */
 			   uint32_t gpu_page_idx, /* pte/pde to update */
 			   uint64_t addr, /* addr to write into pte/pde */
-			   uint32_t flags); /* access flags */
+			   uint64_t flags); /* access flags */
 	/* enable/disable PRT support */
 	void (*set_prt)(struct amdgpu_device *adev, bool enable);
 };
@@ -539,7 +539,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
 			int pages);
 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
 		     int pages, struct page **pagelist,
-		     dma_addr_t *dma_addr, uint32_t flags);
+		     dma_addr_t *dma_addr, uint64_t flags);
 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
 
 /*
@@ -1744,7 +1744,7 @@ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
 				       int *last_invalidated);
 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
-uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
+uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 				 struct ttm_mem_reg *mem);
 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 964d2a94..2916fab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -229,7 +229,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
 	unsigned p;
 	int i, j;
 	u64 page_base;
-	uint32_t flags = AMDGPU_PTE_SYSTEM;
+	uint64_t flags = AMDGPU_PTE_SYSTEM;
 
 	if (!adev->gart.ready) {
 		WARN(1, "trying to unbind memory from uninitialized GART !\n");
@@ -271,7 +271,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
  */
 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
 		     int pages, struct page **pagelist, dma_addr_t *dma_addr,
-		     uint32_t flags)
+		     uint64_t flags)
 {
 	unsigned t;
 	unsigned p;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 4c6094e..f2241bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -746,7 +746,7 @@ int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
 {
 	struct ttm_tt *ttm = bo->ttm;
 	struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
-	uint32_t flags;
+	uint64_t flags;
 	int r;
 
 	if (!ttm || amdgpu_ttm_is_bound(ttm))
@@ -1027,10 +1027,10 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 	return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 }
 
-uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
+uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 				 struct ttm_mem_reg *mem)
 {
-	uint32_t flags = 0;
+	uint64_t flags = 0;
 
 	if (mem && mem->mem_type != TTM_PL_SYSTEM)
 		flags |= AMDGPU_PTE_VALID;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 7e22c35..a45de6e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -64,7 +64,7 @@ struct amdgpu_pte_update_params {
 	/* Function which actually does the update */
 	void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe,
 		     uint64_t addr, unsigned count, uint32_t incr,
-		     uint32_t flags);
+		     uint64_t flags);
 	/* indicate update pt or its shadow */
 	bool shadow;
 };
@@ -496,7 +496,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
 				  uint64_t pe, uint64_t addr,
 				  unsigned count, uint32_t incr,
-				  uint32_t flags)
+				  uint64_t flags)
 {
 	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
 
@@ -525,7 +525,7 @@ static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
 				   uint64_t pe, uint64_t addr,
 				   unsigned count, uint32_t incr,
-				   uint32_t flags)
+				   uint64_t flags)
 {
 	uint64_t src = (params->src + (addr >> 12) * 8);
 
@@ -718,7 +718,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
 static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
 				  struct amdgpu_vm *vm,
 				  uint64_t start, uint64_t end,
-				  uint64_t dst, uint32_t flags)
+				  uint64_t dst, uint64_t flags)
 {
 	const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
 
@@ -808,7 +808,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
 static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params	*params,
 				struct amdgpu_vm *vm,
 				uint64_t start, uint64_t end,
-				uint64_t dst, uint32_t flags)
+				uint64_t dst, uint64_t flags)
 {
 	/**
 	 * The MC L1 TLB supports variable sized pages, based on a fragment
@@ -885,7 +885,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 				       dma_addr_t *pages_addr,
 				       struct amdgpu_vm *vm,
 				       uint64_t start, uint64_t last,
-				       uint32_t flags, uint64_t addr,
+				       uint64_t flags, uint64_t addr,
 				       struct dma_fence **fence)
 {
 	struct amdgpu_ring *ring;
@@ -1023,11 +1023,11 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
  */
 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
 				      struct dma_fence *exclusive,
-				      uint32_t gtt_flags,
+				      uint64_t gtt_flags,
 				      dma_addr_t *pages_addr,
 				      struct amdgpu_vm *vm,
 				      struct amdgpu_bo_va_mapping *mapping,
-				      uint32_t flags,
+				      uint64_t flags,
 				      struct drm_mm_node *nodes,
 				      struct dma_fence **fence)
 {
@@ -1114,7 +1114,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 	struct amdgpu_vm *vm = bo_va->vm;
 	struct amdgpu_bo_va_mapping *mapping;
 	dma_addr_t *pages_addr = NULL;
-	uint32_t gtt_flags, flags;
+	uint64_t gtt_flags, flags;
 	struct ttm_mem_reg *mem;
 	struct drm_mm_node *nodes;
 	struct dma_fence *exclusive;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 88e92eb..57592e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -749,7 +749,7 @@ static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
  */
 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 				    uint64_t addr, unsigned count,
-				    uint32_t incr, uint32_t flags)
+				    uint32_t incr, uint64_t flags)
 {
 	/* for physically contiguous pages (vram) */
 	ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index f69464c..1146570 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -367,7 +367,7 @@ static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
 				     void *cpu_pt_addr,
 				     uint32_t gpu_page_idx,
 				     uint64_t addr,
-				     uint32_t flags)
+				     uint64_t flags)
 {
 	void __iomem *ptr = (void *)cpu_pt_addr;
 	uint64_t value;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 984d4cb..08dc42e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -439,7 +439,7 @@ static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 				     void *cpu_pt_addr,
 				     uint32_t gpu_page_idx,
 				     uint64_t addr,
-				     uint32_t flags)
+				     uint64_t flags)
 {
 	void __iomem *ptr = (void *)cpu_pt_addr;
 	uint64_t value;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index d031fa8..0307e0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -531,7 +531,7 @@ static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 				     void *cpu_pt_addr,
 				     uint32_t gpu_page_idx,
 				     uint64_t addr,
-				     uint32_t flags)
+				     uint64_t flags)
 {
 	void __iomem *ptr = (void *)cpu_pt_addr;
 	uint64_t value;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 861b18b..2937ba3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -798,7 +798,7 @@ static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
  */
 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 				     uint64_t addr, unsigned count,
-				     uint32_t incr, uint32_t flags)
+				     uint32_t incr, uint64_t flags)
 {
 	/* for physically contiguous pages (vram) */
 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 149a18b..e88520c 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1007,7 +1007,7 @@ static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
  */
 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 				     uint64_t addr, unsigned count,
-				     uint32_t incr, uint32_t flags)
+				     uint32_t incr, uint64_t flags)
 {
 	/* for physically contiguous pages (vram) */
 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 381ae97..3af7799 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -398,7 +398,7 @@ static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib,
 				     uint64_t pe,
 				     uint64_t addr, unsigned count,
-				     uint32_t incr, uint32_t flags)
+				     uint32_t incr, uint64_t flags)
 {
 	uint64_t value;
 	unsigned ndw;
-- 
2.5.5

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[PATCH 08/23] drm/amdgpu: add a ucode size member into firmware info

[Alex Deucher]

From: Huang Rui <ray.huang@amd.com>

This will be used for newer asics.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 7 +++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 2 ++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 0f0b381..be16377 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -232,9 +232,12 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_firmware_info *ucode,
 		return 0;
 
 	header = (const struct common_firmware_header *)ucode->fw->data;
+
+	ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
+
 	memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
-		le32_to_cpu(header->ucode_array_offset_bytes)),
-		le32_to_cpu(header->ucode_size_bytes));
+	       le32_to_cpu(header->ucode_array_offset_bytes)),
+	       ucode->ucode_size);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index a8a4230..19a584c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -161,6 +161,8 @@ struct amdgpu_firmware_info {
 	uint64_t mc_addr;
 	/* kernel linear address */
 	void *kaddr;
+	/* ucode_size_bytes */
+	uint32_t ucode_size;
 };
 
 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
-- 
2.5.5

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[PATCH 09/23] drm/amdgpu: set GART PTE asic specific flags

[Alex Deucher]

From: Alex Xie <AlexBin.Xie@amd.com>

Set asic specific gart pte flags in the gmc IP module for
each asic.

Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 4 ++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 +---
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 1 +
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 1 +
 5 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8c3f47b..45877f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -524,6 +524,10 @@ struct amdgpu_gart {
 	struct page			**pages;
 #endif
 	bool				ready;
+
+	/* Asic default pte flags */
+	uint64_t			gart_pte_flags;
+
 	const struct amdgpu_gart_funcs *gart_funcs;
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index f2241bb..987f8f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1042,9 +1042,7 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 			flags |= AMDGPU_PTE_SNOOPED;
 	}
 
-	if (adev->asic_type >= CHIP_TONGA)
-		flags |= AMDGPU_PTE_EXECUTABLE;
-
+	flags |= adev->gart.gart_pte_flags;
 	flags |= AMDGPU_PTE_READABLE;
 
 	if (!amdgpu_ttm_tt_is_readonly(ttm))
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 1146570..30c5939 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -554,6 +554,7 @@ static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
 	if (r)
 		return r;
 	adev->gart.table_size = adev->gart.num_gpu_pages * 8;
+	adev->gart.gart_pte_flags = 0;
 	return amdgpu_gart_table_vram_alloc(adev);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 08dc42e..9d5aaf1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -658,6 +658,7 @@ static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 	if (r)
 		return r;
 	adev->gart.table_size = adev->gart.num_gpu_pages * 8;
+	adev->gart.gart_pte_flags = 0;
 	return amdgpu_gart_table_vram_alloc(adev);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 0307e0f..dc3b12a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -789,6 +789,7 @@ static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 	if (r)
 		return r;
 	adev->gart.table_size = adev->gart.num_gpu_pages * 8;
+	adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 	return amdgpu_gart_table_vram_alloc(adev);
 }
 
-- 
2.5.5

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[PATCH 10/23] drm/amdgpu: add a callback to set vm mapping flags

[Alex Deucher]

From: Alex Xie <AlexBin.Xie@amd.com>

This lets each asic set whichever flags it supports.

Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h     |  4 ++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 12 +++---------
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   | 16 ++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 16 ++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 18 ++++++++++++++++++
 5 files changed, 57 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 45877f8..3299980 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -296,6 +296,9 @@ struct amdgpu_gart_funcs {
 			   uint64_t flags); /* access flags */
 	/* enable/disable PRT support */
 	void (*set_prt)(struct amdgpu_device *adev, bool enable);
+	/* set pte flags based per asic */
+	uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
+				     uint32_t flags);
 };
 
 /* provided by the ih block */
@@ -1680,6 +1683,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
+#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 3c22656..6daf004 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -569,7 +569,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 	struct ttm_validate_buffer tv;
 	struct ww_acquire_ctx ticket;
 	struct list_head list;
-	uint64_t va_flags = 0;
+	uint64_t va_flags;
 	int r = 0;
 
 	if (!adev->vm_manager.enabled)
@@ -631,14 +631,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 
 	switch (args->operation) {
 	case AMDGPU_VA_OP_MAP:
-		if (args->flags & AMDGPU_VM_PAGE_READABLE)
-			va_flags |= AMDGPU_PTE_READABLE;
-		if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
-			va_flags |= AMDGPU_PTE_WRITEABLE;
-		if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
-			va_flags |= AMDGPU_PTE_EXECUTABLE;
-		if (args->flags & AMDGPU_VM_PAGE_PRT)
-			va_flags |= AMDGPU_PTE_PRT;
+		va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
+
 		r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
 				     args->offset_in_bo, args->map_size,
 				     va_flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 30c5939..eac780f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -379,6 +379,21 @@ static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
 	return 0;
 }
 
+static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
+					  uint32_t flags)
+{
+	uint64_t pte_flag = 0;
+
+	if (flags & AMDGPU_VM_PAGE_READABLE)
+		pte_flag |= AMDGPU_PTE_READABLE;
+	if (flags & AMDGPU_VM_PAGE_WRITEABLE)
+		pte_flag |= AMDGPU_PTE_WRITEABLE;
+	if (flags & AMDGPU_VM_PAGE_PRT)
+		pte_flag |= AMDGPU_PTE_PRT;
+
+	return pte_flag;
+}
+
 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
 					      bool value)
 {
@@ -1138,6 +1153,7 @@ static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
 	.flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
 	.set_pte_pde = gmc_v6_0_gart_set_pte_pde,
 	.set_prt = gmc_v6_0_set_prt,
+	.get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 9d5aaf1..da4cba8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -451,6 +451,21 @@ static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 	return 0;
 }
 
+static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev,
+					  uint32_t flags)
+{
+	uint64_t pte_flag = 0;
+
+	if (flags & AMDGPU_VM_PAGE_READABLE)
+		pte_flag |= AMDGPU_PTE_READABLE;
+	if (flags & AMDGPU_VM_PAGE_WRITEABLE)
+		pte_flag |= AMDGPU_PTE_WRITEABLE;
+	if (flags & AMDGPU_VM_PAGE_PRT)
+		pte_flag |= AMDGPU_PTE_PRT;
+
+	return pte_flag;
+}
+
 /**
  * gmc_v8_0_set_fault_enable_default - update VM fault handling
  *
@@ -1322,6 +1337,7 @@ static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = {
 	.flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb,
 	.set_pte_pde = gmc_v7_0_gart_set_pte_pde,
 	.set_prt = gmc_v7_0_set_prt,
+	.get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index dc3b12a..299d007 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -563,6 +563,23 @@ static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 	return 0;
 }
 
+static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
+					  uint32_t flags)
+{
+	uint64_t pte_flag = 0;
+
+	if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
+		pte_flag |= AMDGPU_PTE_EXECUTABLE;
+	if (flags & AMDGPU_VM_PAGE_READABLE)
+		pte_flag |= AMDGPU_PTE_READABLE;
+	if (flags & AMDGPU_VM_PAGE_WRITEABLE)
+		pte_flag |= AMDGPU_PTE_WRITEABLE;
+	if (flags & AMDGPU_VM_PAGE_PRT)
+		pte_flag |= AMDGPU_PTE_PRT;
+
+	return pte_flag;
+}
+
 /**
  * gmc_v8_0_set_fault_enable_default - update VM fault handling
  *
@@ -1561,6 +1578,7 @@ static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
 	.flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
 	.set_pte_pde = gmc_v8_0_gart_set_pte_pde,
 	.set_prt = gmc_v8_0_set_prt,
+	.get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags
 };
 
 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
-- 
2.5.5

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[PATCH 11/23] drm/amdgpu: check function points valid before use.

[Alex Deucher]

From: Rex Zhu <Rex.Zhu@amd.com>

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 78b3b0b..5854357 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1191,9 +1191,10 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 		if (!adev->ip_blocks[i].status.valid)
 			continue;
-		if (adev->ip_blocks[i].version->type == block_type) {
-			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
-										     state);
+		if (adev->ip_blocks[i].version->type == block_type &&
+			adev->ip_blocks[i].version->funcs->set_clockgating_state) {
+			r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
+							(void *)adev, state);
 			if (r)
 				return r;
 			break;
@@ -1211,9 +1212,10 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev,
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 		if (!adev->ip_blocks[i].status.valid)
 			continue;
-		if (adev->ip_blocks[i].version->type == block_type) {
-			r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
-										     state);
+		if (adev->ip_blocks[i].version->type == block_type &&
+			adev->ip_blocks[i].version->funcs->set_powergating_state) {
+			r = adev->ip_blocks[i].version->funcs->set_powergating_state(
+							(void *)adev, state);
 			if (r)
 				return r;
 			break;
-- 
2.5.5

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Re: [PATCH 11/23] drm/amdgpu: check function points valid before use.

[Christian König]

Am 09.03.2017 um 04:44 schrieb Alex Deucher:
> From: Rex Zhu <Rex.Zhu@amd.com>
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 ++++++++------
>   1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 78b3b0b..5854357 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1191,9 +1191,10 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
>   		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		if (adev->ip_blocks[i].version->type == block_type) {
> -			r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
> -										     state);
> +		if (adev->ip_blocks[i].version->type == block_type &&
> +			adev->ip_blocks[i].version->funcs->set_clockgating_state) {

Could be my mail client, but the indentation doesn't looks correct here.

Additional to that checking that as prerequisites would be easier to 
read I think, e.g. coding it like this:

if (adev->ip_blocks[i].version->type != block_type)
     continue;

if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
     continue;

Regards,
Christian.

> +			r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
> +							(void *)adev, state);
>   			if (r)
>   				return r;
>   			break;
> @@ -1211,9 +1212,10 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev,
>   	for (i = 0; i < adev->num_ip_blocks; i++) {
>   		if (!adev->ip_blocks[i].status.valid)
>   			continue;
> -		if (adev->ip_blocks[i].version->type == block_type) {
> -			r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
> -										     state);
> +		if (adev->ip_blocks[i].version->type == block_type &&
> +			adev->ip_blocks[i].version->funcs->set_powergating_state) {
> +			r = adev->ip_blocks[i].version->funcs->set_powergating_state(
> +							(void *)adev, state);
>   			if (r)
>   				return r;
>   			break;


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[PATCH 12/23] drm/amdgpu: add asic callback to get memsize register

[Alex Deucher]

Newer asics use different registers so abstract it.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        | 3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/cik.c           | 6 ++++++
 drivers/gpu/drm/amd/amdgpu/si.c            | 7 +++++++
 drivers/gpu/drm/amd/amdgpu/vi.c            | 6 ++++++
 5 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3299980..b51ea98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1216,6 +1216,8 @@ struct amdgpu_asic_funcs {
 	/* static power management */
 	int (*get_pcie_lanes)(struct amdgpu_device *adev);
 	void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
+	/* get config memsize register */
+	u32 (*get_config_memsize)(struct amdgpu_device *adev);
 };
 
 /*
@@ -1678,6 +1680,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
+#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5854357..56c3b31 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -713,7 +713,7 @@ bool amdgpu_need_post(struct amdgpu_device *adev)
 		return true;
 	}
 	/* then check MEM_SIZE, in case the crtcs are off */
-	reg = RREG32(mmCONFIG_MEMSIZE);
+	reg = amdgpu_asic_get_config_memsize(adev);
 
 	if (reg)
 		return false;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index c4d4b35..dbaedb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1212,6 +1212,11 @@ static int cik_asic_reset(struct amdgpu_device *adev)
 	return r;
 }
 
+static u32 cik_get_config_memsize(struct amdgpu_device *adev)
+{
+	return RREG32(mmCONFIG_MEMSIZE);
+}
+
 static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 			      u32 cntl_reg, u32 status_reg)
 {
@@ -1641,6 +1646,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
 	.get_xclk = &cik_get_xclk,
 	.set_uvd_clocks = &cik_set_uvd_clocks,
 	.set_vce_clocks = &cik_set_vce_clocks,
+	.get_config_memsize = &cik_get_config_memsize,
 };
 
 static int cik_common_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index b71e3fa..c0b1aab 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -45,6 +45,7 @@
 #include "gmc/gmc_6_0_d.h"
 #include "dce/dce_6_0_d.h"
 #include "uvd/uvd_4_0_d.h"
+#include "bif/bif_3_0_d.h"
 
 static const u32 tahiti_golden_registers[] =
 {
@@ -1155,6 +1156,11 @@ static int si_asic_reset(struct amdgpu_device *adev)
 	return 0;
 }
 
+static u32 si_get_config_memsize(struct amdgpu_device *adev)
+{
+	return RREG32(mmCONFIG_MEMSIZE);
+}
+
 static void si_vga_set_state(struct amdgpu_device *adev, bool state)
 {
 	uint32_t temp;
@@ -1206,6 +1212,7 @@ static const struct amdgpu_asic_funcs si_asic_funcs =
 	.get_xclk = &si_get_xclk,
 	.set_uvd_clocks = &si_set_uvd_clocks,
 	.set_vce_clocks = NULL,
+	.get_config_memsize = &si_get_config_memsize,
 };
 
 static uint32_t si_get_rev_id(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 717a332..5bd21fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -751,6 +751,11 @@ static int vi_asic_reset(struct amdgpu_device *adev)
 	return r;
 }
 
+static u32 vi_get_config_memsize(struct amdgpu_device *adev)
+{
+	return RREG32(mmCONFIG_MEMSIZE);
+}
+
 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 			u32 cntl_reg, u32 status_reg)
 {
@@ -900,6 +905,7 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
 	.get_xclk = &vi_get_xclk,
 	.set_uvd_clocks = &vi_set_uvd_clocks,
 	.set_vce_clocks = &vi_set_vce_clocks,
+	.get_config_memsize = &vi_get_config_memsize,
 };
 
 static int vi_common_early_init(void *handle)
-- 
2.5.5

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[PATCH 13/23] drm/amdgpu: add DRM MGCG header

[Alex Deucher]

From: Huang Rui <ray.huang@amd.com>

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/include/amd_shared.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index f7425c3..13acc52 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -157,6 +157,7 @@ struct amd_pp_profile {
 #define AMD_CG_SUPPORT_BIF_MGCG			(1 << 19)
 #define AMD_CG_SUPPORT_GFX_3D_CGCG		(1 << 20)
 #define AMD_CG_SUPPORT_GFX_3D_CGLS		(1 << 21)
+#define AMD_CG_SUPPORT_DRM_MGCG			(1 << 22)
 
 /* PG flags */
 #define AMD_PG_SUPPORT_GFX_PG			(1 << 0)
-- 
2.5.5

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[PATCH 14/23] drm/amdgpu: add DF MGCG flag

[Alex Deucher]

From: Huang Rui <ray.huang@amd.com>

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/include/amd_shared.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 13acc52..4f61879 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -158,6 +158,7 @@ struct amd_pp_profile {
 #define AMD_CG_SUPPORT_GFX_3D_CGCG		(1 << 20)
 #define AMD_CG_SUPPORT_GFX_3D_CGLS		(1 << 21)
 #define AMD_CG_SUPPORT_DRM_MGCG			(1 << 22)
+#define AMD_CG_SUPPORT_DF_MGCG			(1 << 23)
 
 /* PG flags */
 #define AMD_PG_SUPPORT_GFX_PG			(1 << 0)
-- 
2.5.5

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[PATCH 15/23] drm/amdgpu: add a ring func for end command

[Alex Deucher]

From: Leo Liu <leo.liu@amd.com>

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   | 3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index e357e42..c485708 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -222,6 +222,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 		return r;
 	}
 
+	if (ring->funcs->insert_end)
+		ring->funcs->insert_end(ring);
+
 	/* wrap the last IB with fence */
 	if (job && job->uf_addr) {
 		amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 9f2d605..8a34ae2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -126,6 +126,7 @@ struct amdgpu_ring_funcs {
 	int (*test_ib)(struct amdgpu_ring *ring, long timeout);
 	/* insert NOP packets */
 	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
+	void (*insert_end)(struct amdgpu_ring *ring);
 	/* pad the indirect buffer to the necessary number of dw */
 	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
 	unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
-- 
2.5.5

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[PATCH 16/23] drm/amdgpu: move amdgpu_uvd structure to uvd header

[Alex Deucher]

From: Leo Liu <leo.liu@amd.com>

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 30 +-----------------------------
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 26 ++++++++++++++++++++++++++
 2 files changed, 27 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b51ea98..9eef3f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -59,6 +59,7 @@
 #include "amd_powerplay.h"
 #include "amdgpu_dpm.h"
 #include "amdgpu_acp.h"
+#include "amdgpu_uvd.h"
 
 #include "gpu_scheduler.h"
 #include "amdgpu_virt.h"
@@ -1029,35 +1030,6 @@ void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
 
 /*
- * UVD
- */
-#define AMDGPU_DEFAULT_UVD_HANDLES	10
-#define AMDGPU_MAX_UVD_HANDLES		40
-#define AMDGPU_UVD_STACK_SIZE		(200*1024)
-#define AMDGPU_UVD_HEAP_SIZE		(256*1024)
-#define AMDGPU_UVD_SESSION_SIZE		(50*1024)
-#define AMDGPU_UVD_FIRMWARE_OFFSET	256
-
-struct amdgpu_uvd {
-	struct amdgpu_bo	*vcpu_bo;
-	void			*cpu_addr;
-	uint64_t		gpu_addr;
-	unsigned		fw_version;
-	void			*saved_bo;
-	unsigned		max_handles;
-	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];
-	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];
-	struct delayed_work	idle_work;
-	const struct firmware	*fw;	/* UVD firmware */
-	struct amdgpu_ring	ring;
-	struct amdgpu_irq_src	irq;
-	bool			address_64_bit;
-	bool			use_ctx_buf;
-	struct amd_sched_entity entity;
-	uint32_t                srbm_soft_reset;
-};
-
-/*
  * VCE
  */
 #define AMDGPU_MAX_VCE_HANDLES	16
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index c10682b..797210d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -24,6 +24,32 @@
 #ifndef __AMDGPU_UVD_H__
 #define __AMDGPU_UVD_H__
 
+#define AMDGPU_DEFAULT_UVD_HANDLES	10
+#define AMDGPU_MAX_UVD_HANDLES		40
+#define AMDGPU_UVD_STACK_SIZE		(200*1024)
+#define AMDGPU_UVD_HEAP_SIZE		(256*1024)
+#define AMDGPU_UVD_SESSION_SIZE		(50*1024)
+#define AMDGPU_UVD_FIRMWARE_OFFSET	256
+
+struct amdgpu_uvd {
+	struct amdgpu_bo	*vcpu_bo;
+	void			*cpu_addr;
+	uint64_t		gpu_addr;
+	unsigned		fw_version;
+	void			*saved_bo;
+	unsigned		max_handles;
+	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];
+	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];
+	struct delayed_work	idle_work;
+	const struct firmware	*fw;	/* UVD firmware */
+	struct amdgpu_ring	ring;
+	struct amdgpu_irq_src	irq;
+	bool			address_64_bit;
+	bool			use_ctx_buf;
+	struct amd_sched_entity entity;
+	uint32_t                srbm_soft_reset;
+};
+
 int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev);
 int amdgpu_uvd_suspend(struct amdgpu_device *adev);
-- 
2.5.5

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[PATCH 17/23] drm/amdgpu: move amdgpu_vce structure to vce header

[Alex Deucher]

From: Leo Liu <leo.liu@amd.com>

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 29 +----------------------------
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 25 +++++++++++++++++++++++++
 2 files changed, 26 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 9eef3f8..7b7424b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -60,6 +60,7 @@
 #include "amdgpu_dpm.h"
 #include "amdgpu_acp.h"
 #include "amdgpu_uvd.h"
+#include "amdgpu_vce.h"
 
 #include "gpu_scheduler.h"
 #include "amdgpu_virt.h"
@@ -1030,34 +1031,6 @@ void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
 
 /*
- * VCE
- */
-#define AMDGPU_MAX_VCE_HANDLES	16
-#define AMDGPU_VCE_FIRMWARE_OFFSET 256
-
-#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
-#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
-
-struct amdgpu_vce {
-	struct amdgpu_bo	*vcpu_bo;
-	uint64_t		gpu_addr;
-	unsigned		fw_version;
-	unsigned		fb_version;
-	atomic_t		handles[AMDGPU_MAX_VCE_HANDLES];
-	struct drm_file		*filp[AMDGPU_MAX_VCE_HANDLES];
-	uint32_t		img_size[AMDGPU_MAX_VCE_HANDLES];
-	struct delayed_work	idle_work;
-	struct mutex		idle_mutex;
-	const struct firmware	*fw;	/* VCE firmware */
-	struct amdgpu_ring	ring[AMDGPU_MAX_VCE_RINGS];
-	struct amdgpu_irq_src	irq;
-	unsigned		harvest_config;
-	struct amd_sched_entity	entity;
-	uint32_t                srbm_soft_reset;
-	unsigned		num_rings;
-};
-
-/*
  * SDMA
  */
 struct amdgpu_sdma_instance {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
index d98041f..0a7f18c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
@@ -24,6 +24,31 @@
 #ifndef __AMDGPU_VCE_H__
 #define __AMDGPU_VCE_H__
 
+#define AMDGPU_MAX_VCE_HANDLES	16
+#define AMDGPU_VCE_FIRMWARE_OFFSET 256
+
+#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
+#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
+
+struct amdgpu_vce {
+	struct amdgpu_bo	*vcpu_bo;
+	uint64_t		gpu_addr;
+	unsigned		fw_version;
+	unsigned		fb_version;
+	atomic_t		handles[AMDGPU_MAX_VCE_HANDLES];
+	struct drm_file		*filp[AMDGPU_MAX_VCE_HANDLES];
+	uint32_t		img_size[AMDGPU_MAX_VCE_HANDLES];
+	struct delayed_work	idle_work;
+	struct mutex		idle_mutex;
+	const struct firmware	*fw;	/* VCE firmware */
+	struct amdgpu_ring	ring[AMDGPU_MAX_VCE_RINGS];
+	struct amdgpu_irq_src	irq;
+	unsigned		harvest_config;
+	struct amd_sched_entity	entity;
+	uint32_t                srbm_soft_reset;
+	unsigned		num_rings;
+};
+
 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size);
 int amdgpu_vce_sw_fini(struct amdgpu_device *adev);
 int amdgpu_vce_suspend(struct amdgpu_device *adev);
-- 
2.5.5

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[PATCH 18/23] drm/amdgpu: add uvd enc rings

[Alex Deucher]

From: Leo Liu <leo.liu@amd.com>

And initialize them

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h  | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 8a34ae2..ef574c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -27,10 +27,11 @@
 #include "gpu_scheduler.h"
 
 /* max number of rings */
-#define AMDGPU_MAX_RINGS		16
+#define AMDGPU_MAX_RINGS		18
 #define AMDGPU_MAX_GFX_RINGS		1
 #define AMDGPU_MAX_COMPUTE_RINGS	8
 #define AMDGPU_MAX_VCE_RINGS		3
+#define AMDGPU_MAX_UVD_ENC_RINGS	2
 
 /* some special values for the owner field */
 #define AMDGPU_FENCE_OWNER_UNDEFINED	((void*)0ul)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index 797210d..7b7f468 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -43,11 +43,13 @@ struct amdgpu_uvd {
 	struct delayed_work	idle_work;
 	const struct firmware	*fw;	/* UVD firmware */
 	struct amdgpu_ring	ring;
+	struct amdgpu_ring	ring_enc[AMDGPU_MAX_UVD_ENC_RINGS];
 	struct amdgpu_irq_src	irq;
 	bool			address_64_bit;
 	bool			use_ctx_buf;
 	struct amd_sched_entity entity;
 	uint32_t                srbm_soft_reset;
+	unsigned		num_enc_rings;
 };
 
 int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
-- 
2.5.5

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[PATCH 19/23] drm/amdgpu: add uvd enc run queue

[Alex Deucher]

From: Leo Liu <leo.liu@amd.com>

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index 7b7f468..3553b92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -48,6 +48,7 @@ struct amdgpu_uvd {
 	bool			address_64_bit;
 	bool			use_ctx_buf;
 	struct amd_sched_entity entity;
+	struct amd_sched_entity entity_enc;
 	uint32_t                srbm_soft_reset;
 	unsigned		num_enc_rings;
 };
-- 
2.5.5

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[PATCH 20/23] drm/amdgpu: add uvd enc ring type and functions

[Alex Deucher]

From: Leo Liu <leo.liu@amd.com>

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index ef574c9..1c657ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -46,7 +46,8 @@ enum amdgpu_ring_type {
 	AMDGPU_RING_TYPE_SDMA,
 	AMDGPU_RING_TYPE_UVD,
 	AMDGPU_RING_TYPE_VCE,
-	AMDGPU_RING_TYPE_KIQ
+	AMDGPU_RING_TYPE_KIQ,
+	AMDGPU_RING_TYPE_UVD_ENC
 };
 
 struct amdgpu_device;
-- 
2.5.5

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[PATCH 21/23] uapi/drm: add AMDGPU_HW_IP_UVD_ENC

[Alex Deucher]

From: Leo Liu <leo.liu@amd.com>

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 include/uapi/drm/amdgpu_drm.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 732c662..2c30e32 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -385,7 +385,8 @@ struct drm_amdgpu_gem_va {
 #define AMDGPU_HW_IP_DMA          2
 #define AMDGPU_HW_IP_UVD          3
 #define AMDGPU_HW_IP_VCE          4
-#define AMDGPU_HW_IP_NUM          5
+#define AMDGPU_HW_IP_UVD_ENC      5
+#define AMDGPU_HW_IP_NUM          6
 
 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 
-- 
2.5.5

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[PATCH 22/23] drm/amdgpu: add AMDGPU_HW_IP_UVD_ENC to info query

[Alex Deucher]

From: Leo Liu <leo.liu@amd.com>

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 0963865..6b596dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -309,6 +309,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
 			ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 			ib_size_alignment = 1;
 			break;
+		case AMDGPU_HW_IP_UVD_ENC:
+			type = AMD_IP_BLOCK_TYPE_UVD;
+			for (i = 0; i < adev->uvd.num_enc_rings; i++)
+				ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i);
+			ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+			ib_size_alignment = 1;
+			break;
 		default:
 			return -EINVAL;
 		}
@@ -348,6 +355,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
 		case AMDGPU_HW_IP_VCE:
 			type = AMD_IP_BLOCK_TYPE_VCE;
 			break;
+		case AMDGPU_HW_IP_UVD_ENC:
+			type = AMD_IP_BLOCK_TYPE_UVD;
+			break;
 		default:
 			return -EINVAL;
 		}
-- 
2.5.5

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[PATCH 23/23] drm/amdgpu: get cs support of AMDGPU_HW_IP_UVD_ENC

[Alex Deucher]

From: Leo Liu <leo.liu@amd.com>

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 2bfb2bec..b39f30f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -82,6 +82,15 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
 			return -EINVAL;
 		}
 		break;
+	case AMDGPU_HW_IP_UVD_ENC:
+		if (ring < adev->uvd.num_enc_rings){
+			*out_ring = &adev->uvd.ring_enc[ring];
+		} else {
+			DRM_ERROR("only %d UVD ENC rings are supported\n",
+				adev->uvd.num_enc_rings);
+			return -EINVAL;
+		}
+		break;
 	}
 
 	if (!(*out_ring && (*out_ring)->adev)) {
-- 
2.5.5

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Re: [PATCH 00/23] Prep patches for new asics

[Christian König]

Patches #3, #4, #12, #15 - #23 are Reviewed-by: Christian König 
<christian.koenig@amd.com>.

Patch #8, #13, #14 are Acked-by: Christian König <christian.koenig@amd.com>.

The rest I've either send comments for or are already Reviewed by me.

Regards,
Christian.

Am 09.03.2017 um 04:44 schrieb Alex Deucher:
> This set of patches updates various infrastructure in the driver
> to support new asics.
>
> Alex Deucher (3):
>    drm/amdgpu: switch ih handling to two levels
>    drm/amdgpu/ih: store the full context id
>    drm/amdgpu: add asic callback to get memsize register
>
> Alex Xie (2):
>    drm/amdgpu: set GART PTE asic specific flags
>    drm/amdgpu: add a callback to set vm mapping flags
>
> Chunming Zhou (1):
>    drm/amdgpu: expand pte flags to uint64_t
>
> Huang Rui (3):
>    drm/amdgpu: add a ucode size member into firmware info
>    drm/amdgpu: add DRM MGCG header
>    drm/amdgpu: add DF MGCG flag
>
> Junwei Zhang (1):
>    drm/amdgpu: init aperture definitions
>
> Ken Wang (3):
>    drm/amdgpu: change wptr to 64 bits
>    drm/amdgpu: add 64bit wb functions
>    drm/amdgpu: add 64bit doorbell functions
>
> Leo Liu (9):
>    drm/amdgpu: add a ring func for end command
>    drm/amdgpu: move amdgpu_uvd structure to uvd header
>    drm/amdgpu: move amdgpu_vce structure to vce header
>    drm/amdgpu: add uvd enc rings
>    drm/amdgpu: add uvd enc run queue
>    drm/amdgpu: add uvd enc ring type and functions
>    uapi/drm: add AMDGPU_HW_IP_UVD_ENC
>    drm/amdgpu: add AMDGPU_HW_IP_UVD_ENC to info query
>    drm/amdgpu: get cs support of AMDGPU_HW_IP_UVD_ENC
>
> Rex Zhu (1):
>    drm/amdgpu: check function points valid before use.
>
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  89 +++++++----------------
>   drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c    |  24 +++++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     |   9 +++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  93 ++++++++++++++++++++++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c   |   4 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    |  12 +---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c     |   3 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h     |  10 ++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c    | 111 ++++++++++++++++++++---------
>   drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h    |  10 ++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c    |  10 +++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  60 +++++++++++-----
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h   |  19 +++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    |  10 ++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c  |   7 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h  |   2 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h    |  29 ++++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h    |  25 +++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     |  18 ++---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h     |   6 ++
>   drivers/gpu/drm/amd/amdgpu/ci_dpm.c        |   6 +-
>   drivers/gpu/drm/amd/amdgpu/cik.c           |   6 ++
>   drivers/gpu/drm/amd/amdgpu/cik_ih.c        |   2 +-
>   drivers/gpu/drm/amd/amdgpu/cik_sdma.c      |  23 +++---
>   drivers/gpu/drm/amd/amdgpu/cz_ih.c         |   3 +-
>   drivers/gpu/drm/amd/amdgpu/dce_v10_0.c     |  16 ++---
>   drivers/gpu/drm/amd/amdgpu/dce_v11_0.c     |  16 ++---
>   drivers/gpu/drm/amd/amdgpu/dce_v6_0.c      |  16 ++---
>   drivers/gpu/drm/amd/amdgpu/dce_v8_0.c      |  16 ++---
>   drivers/gpu/drm/amd/amdgpu/dce_virtual.c   |   2 +-
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c      |  16 ++---
>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c      |  50 +++++++++----
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c      |  49 ++++++++-----
>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |  25 +++++--
>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |  32 +++++++--
>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |  36 ++++++++--
>   drivers/gpu/drm/amd/amdgpu/iceland_ih.c    |   3 +-
>   drivers/gpu/drm/amd/amdgpu/kv_dpm.c        |   6 +-
>   drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c      |   4 +-
>   drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c     |  22 +++---
>   drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c     |  26 ++++---
>   drivers/gpu/drm/amd/amdgpu/si.c            |   7 ++
>   drivers/gpu/drm/amd/amdgpu/si_dma.c        |  18 ++---
>   drivers/gpu/drm/amd/amdgpu/si_dpm.c        |   4 +-
>   drivers/gpu/drm/amd/amdgpu/si_ih.c         |   2 +-
>   drivers/gpu/drm/amd/amdgpu/tonga_ih.c      |   3 +-
>   drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c      |  11 +--
>   drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c      |  11 +--
>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c      |  11 +--
>   drivers/gpu/drm/amd/amdgpu/vce_v2_0.c      |  25 +++----
>   drivers/gpu/drm/amd/amdgpu/vce_v3_0.c      |  31 ++++----
>   drivers/gpu/drm/amd/amdgpu/vi.c            |   6 ++
>   drivers/gpu/drm/amd/include/amd_shared.h   |   2 +
>   drivers/gpu/drm/amd/include/cgs_linux.h    |  19 ++---
>   include/uapi/drm/amdgpu_drm.h              |   3 +-
>   55 files changed, 727 insertions(+), 352 deletions(-)
>

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