From: Boris Brezillon <boris.brezillon@free-electrons.com>
To: Quentin Schulz <quentin.schulz@free-electrons.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
alsa-devel@alsa-project.org, thomas.petazzoni@free-electrons.com,
lgirdwood@gmail.com, linux-kernel@vger.kernel.org,
mturquette@baylibre.com, tiwai@suse.com, sboyd@codeaurora.org,
nicolas.ferre@microchip.com, linux@armlinux.org.uk,
robh+dt@kernel.org, alexandre.belloni@free-electrons.com,
broonie@kernel.org, Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 5/6] clk: at91: clk-generated: make gclk determine audio_pll rate
Date: Mon, 3 Jul 2017 16:19:05 +0200 [thread overview]
Message-ID: <20170703161905.5f994151@bbrezillon> (raw)
In-Reply-To: <20170623090059.8371-6-quentin.schulz@free-electrons.com>
On Fri, 23 Jun 2017 11:00:58 +0200
Quentin Schulz <quentin.schulz@free-electrons.com> wrote:
> This allows gclk to determine audio_pll rate and set the parent rate
> accordingly.
>
> However, there are multiple children clocks that could technically
> change the rate of audio_pll. Since the clock rate is usually critical
> for IPs, it isn't a good idea to have multiple clocks changing audio_pll
> clock rate. There isn't any rate locking system for the moment, thus
> we enforce that classd_gclk be the only one allowed to change audio_pll
> rate. To remain consistent, we deny other clocks to be children of
> audio_pll so classd_gclk altering audio_pll rate does not impact any
> other device.
>
> This needs to be re-worked once we have a rate locking system so two
> clocks could be children of the same clock and be sure the clock rate
> isn't changed by one or the other.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
> ---
> drivers/clk/at91/clk-generated.c | 41 ++++++++++++++++++++++++++++++++++------
> 1 file changed, 35 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
> index 6530a2e7e84d..e66ee735a569 100644
> --- a/drivers/clk/at91/clk-generated.c
> +++ b/drivers/clk/at91/clk-generated.c
> @@ -26,6 +26,9 @@
> #define GENERATED_SOURCE_MAX 6
> #define GENERATED_MAX_DIV 255
>
> +#define GCK_ID_CLASSD 59
> +#define GCK_INDEX_DT_AUDIO_PLL 5
> +
> struct clk_generated {
> struct clk_hw hw;
> struct regmap *regmap;
> @@ -126,15 +129,14 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> {
> struct clk_generated *gck = to_clk_generated(hw);
> struct clk_hw *parent = NULL;
> + struct clk_rate_request req_parent = *req;
> long best_rate = -EINVAL;
> - unsigned long min_rate;
> + unsigned long min_rate, parent_rate;
> int best_diff = -1;
> int i;
> + u32 div;
>
> - for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
> - u32 div;
> - unsigned long parent_rate;
> -
> + for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
> parent = clk_hw_get_parent_by_index(hw, i);
> if (!parent)
> continue;
> @@ -150,11 +152,37 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> clk_generated_best_diff(req, parent, parent_rate, div,
> &best_diff, &best_rate);
>
> + if (!best_diff)
> + break;
> + }
> +
> + /*
> + * The audio_pll rate can be modified unlike the five others clocks that
> + * should never be altered.
> + * The audio_pll can technically be used by multiple consumers. However,
> + * they all are likely to want to modify its rate while the rate is
> + * critical for each one. Since we do not have a rate locking for the
> + * moment, let classd_gclk be the only consumer of the audio_pll clock.
> + */
> +
> + if (gck->id != GCK_ID_CLASSD)
> + goto end;
As discussed on IRC with Nicolas and Cyrille, it seems we have other
potential users of the audio-pll: SSC and I2S. Can you extend the test
to let these GCK clks take the audio-pll?
> +
> + parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
> + if (!parent)
> + goto end;
> +
> + for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
> + req_parent.rate = req->rate * div;
> + __clk_determine_rate(parent, &req_parent);
> + clk_generated_best_diff(req, parent, req_parent.rate, div,
> + &best_diff, &best_rate);
>
> if (!best_diff)
> break;
> }
>
> +end:
> pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
> __func__, best_rate,
> __clk_get_name((req->best_parent_hw)->clk),
> @@ -264,7 +292,8 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
> init.ops = &generated_ops;
> init.parent_names = parent_names;
> init.num_parents = num_parents;
> - init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
> + init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
> + CLK_SET_RATE_PARENT;
>
> gck->id = id;
> gck->hw.init = &init;
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@free-electrons.com>
To: Quentin Schulz <quentin.schulz@free-electrons.com>
Cc: mturquette@baylibre.com, sboyd@codeaurora.org,
robh+dt@kernel.org, mark.rutland@arm.com,
nicolas.ferre@microchip.com,
alexandre.belloni@free-electrons.com, linux@armlinux.org.uk,
lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz,
tiwai@suse.com, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
alsa-devel@alsa-project.org, thomas.petazzoni@free-electrons.com,
Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Subject: Re: [PATCH 5/6] clk: at91: clk-generated: make gclk determine audio_pll rate
Date: Mon, 3 Jul 2017 16:19:05 +0200 [thread overview]
Message-ID: <20170703161905.5f994151@bbrezillon> (raw)
In-Reply-To: <20170623090059.8371-6-quentin.schulz@free-electrons.com>
On Fri, 23 Jun 2017 11:00:58 +0200
Quentin Schulz <quentin.schulz@free-electrons.com> wrote:
> This allows gclk to determine audio_pll rate and set the parent rate
> accordingly.
>
> However, there are multiple children clocks that could technically
> change the rate of audio_pll. Since the clock rate is usually critical
> for IPs, it isn't a good idea to have multiple clocks changing audio_pll
> clock rate. There isn't any rate locking system for the moment, thus
> we enforce that classd_gclk be the only one allowed to change audio_pll
> rate. To remain consistent, we deny other clocks to be children of
> audio_pll so classd_gclk altering audio_pll rate does not impact any
> other device.
>
> This needs to be re-worked once we have a rate locking system so two
> clocks could be children of the same clock and be sure the clock rate
> isn't changed by one or the other.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
> ---
> drivers/clk/at91/clk-generated.c | 41 ++++++++++++++++++++++++++++++++++------
> 1 file changed, 35 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
> index 6530a2e7e84d..e66ee735a569 100644
> --- a/drivers/clk/at91/clk-generated.c
> +++ b/drivers/clk/at91/clk-generated.c
> @@ -26,6 +26,9 @@
> #define GENERATED_SOURCE_MAX 6
> #define GENERATED_MAX_DIV 255
>
> +#define GCK_ID_CLASSD 59
> +#define GCK_INDEX_DT_AUDIO_PLL 5
> +
> struct clk_generated {
> struct clk_hw hw;
> struct regmap *regmap;
> @@ -126,15 +129,14 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> {
> struct clk_generated *gck = to_clk_generated(hw);
> struct clk_hw *parent = NULL;
> + struct clk_rate_request req_parent = *req;
> long best_rate = -EINVAL;
> - unsigned long min_rate;
> + unsigned long min_rate, parent_rate;
> int best_diff = -1;
> int i;
> + u32 div;
>
> - for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
> - u32 div;
> - unsigned long parent_rate;
> -
> + for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
> parent = clk_hw_get_parent_by_index(hw, i);
> if (!parent)
> continue;
> @@ -150,11 +152,37 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> clk_generated_best_diff(req, parent, parent_rate, div,
> &best_diff, &best_rate);
>
> + if (!best_diff)
> + break;
> + }
> +
> + /*
> + * The audio_pll rate can be modified unlike the five others clocks that
> + * should never be altered.
> + * The audio_pll can technically be used by multiple consumers. However,
> + * they all are likely to want to modify its rate while the rate is
> + * critical for each one. Since we do not have a rate locking for the
> + * moment, let classd_gclk be the only consumer of the audio_pll clock.
> + */
> +
> + if (gck->id != GCK_ID_CLASSD)
> + goto end;
As discussed on IRC with Nicolas and Cyrille, it seems we have other
potential users of the audio-pll: SSC and I2S. Can you extend the test
to let these GCK clks take the audio-pll?
> +
> + parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
> + if (!parent)
> + goto end;
> +
> + for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
> + req_parent.rate = req->rate * div;
> + __clk_determine_rate(parent, &req_parent);
> + clk_generated_best_diff(req, parent, req_parent.rate, div,
> + &best_diff, &best_rate);
>
> if (!best_diff)
> break;
> }
>
> +end:
> pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
> __func__, best_rate,
> __clk_get_name((req->best_parent_hw)->clk),
> @@ -264,7 +292,8 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
> init.ops = &generated_ops;
> init.parent_names = parent_names;
> init.num_parents = num_parents;
> - init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
> + init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
> + CLK_SET_RATE_PARENT;
>
> gck->id = id;
> gck->hw.init = &init;
WARNING: multiple messages have this Message-ID (diff)
From: boris.brezillon@free-electrons.com (Boris Brezillon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/6] clk: at91: clk-generated: make gclk determine audio_pll rate
Date: Mon, 3 Jul 2017 16:19:05 +0200 [thread overview]
Message-ID: <20170703161905.5f994151@bbrezillon> (raw)
In-Reply-To: <20170623090059.8371-6-quentin.schulz@free-electrons.com>
On Fri, 23 Jun 2017 11:00:58 +0200
Quentin Schulz <quentin.schulz@free-electrons.com> wrote:
> This allows gclk to determine audio_pll rate and set the parent rate
> accordingly.
>
> However, there are multiple children clocks that could technically
> change the rate of audio_pll. Since the clock rate is usually critical
> for IPs, it isn't a good idea to have multiple clocks changing audio_pll
> clock rate. There isn't any rate locking system for the moment, thus
> we enforce that classd_gclk be the only one allowed to change audio_pll
> rate. To remain consistent, we deny other clocks to be children of
> audio_pll so classd_gclk altering audio_pll rate does not impact any
> other device.
>
> This needs to be re-worked once we have a rate locking system so two
> clocks could be children of the same clock and be sure the clock rate
> isn't changed by one or the other.
>
> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
> ---
> drivers/clk/at91/clk-generated.c | 41 ++++++++++++++++++++++++++++++++++------
> 1 file changed, 35 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
> index 6530a2e7e84d..e66ee735a569 100644
> --- a/drivers/clk/at91/clk-generated.c
> +++ b/drivers/clk/at91/clk-generated.c
> @@ -26,6 +26,9 @@
> #define GENERATED_SOURCE_MAX 6
> #define GENERATED_MAX_DIV 255
>
> +#define GCK_ID_CLASSD 59
> +#define GCK_INDEX_DT_AUDIO_PLL 5
> +
> struct clk_generated {
> struct clk_hw hw;
> struct regmap *regmap;
> @@ -126,15 +129,14 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> {
> struct clk_generated *gck = to_clk_generated(hw);
> struct clk_hw *parent = NULL;
> + struct clk_rate_request req_parent = *req;
> long best_rate = -EINVAL;
> - unsigned long min_rate;
> + unsigned long min_rate, parent_rate;
> int best_diff = -1;
> int i;
> + u32 div;
>
> - for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
> - u32 div;
> - unsigned long parent_rate;
> -
> + for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
> parent = clk_hw_get_parent_by_index(hw, i);
> if (!parent)
> continue;
> @@ -150,11 +152,37 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> clk_generated_best_diff(req, parent, parent_rate, div,
> &best_diff, &best_rate);
>
> + if (!best_diff)
> + break;
> + }
> +
> + /*
> + * The audio_pll rate can be modified unlike the five others clocks that
> + * should never be altered.
> + * The audio_pll can technically be used by multiple consumers. However,
> + * they all are likely to want to modify its rate while the rate is
> + * critical for each one. Since we do not have a rate locking for the
> + * moment, let classd_gclk be the only consumer of the audio_pll clock.
> + */
> +
> + if (gck->id != GCK_ID_CLASSD)
> + goto end;
As discussed on IRC with Nicolas and Cyrille, it seems we have other
potential users of the audio-pll: SSC and I2S. Can you extend the test
to let these GCK clks take the audio-pll?
> +
> + parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
> + if (!parent)
> + goto end;
> +
> + for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
> + req_parent.rate = req->rate * div;
> + __clk_determine_rate(parent, &req_parent);
> + clk_generated_best_diff(req, parent, req_parent.rate, div,
> + &best_diff, &best_rate);
>
> if (!best_diff)
> break;
> }
>
> +end:
> pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
> __func__, best_rate,
> __clk_get_name((req->best_parent_hw)->clk),
> @@ -264,7 +292,8 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
> init.ops = &generated_ops;
> init.parent_names = parent_names;
> init.num_parents = num_parents;
> - init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
> + init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
> + CLK_SET_RATE_PARENT;
>
> gck->id = id;
> gck->hw.init = &init;
next prev parent reply other threads:[~2017-07-03 14:19 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-23 9:00 [PATCH 0/6] add support for Sama5d2 audio PLL and enable ClassD Quentin Schulz
2017-06-23 9:00 ` Quentin Schulz
2017-06-23 9:00 ` Quentin Schulz
[not found] ` <20170623090059.8371-1-quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-06-23 9:00 ` [PATCH 1/6] clk: at91: clk-generated: remove useless divisor loop Quentin Schulz
2017-06-23 9:00 ` Quentin Schulz
2017-06-23 9:00 ` Quentin Schulz
2017-07-03 13:58 ` Boris Brezillon
2017-07-03 13:58 ` Boris Brezillon
2017-07-03 13:58 ` Boris Brezillon
2017-06-23 9:00 ` [PATCH 2/6] clk: at91: add audio pll clock driver Quentin Schulz
2017-06-23 9:00 ` Quentin Schulz
2017-06-23 9:00 ` Quentin Schulz
2017-06-23 15:39 ` Alexandre Belloni
2017-06-23 15:39 ` Alexandre Belloni
2017-06-29 21:47 ` Rob Herring
2017-06-29 21:47 ` Rob Herring
2017-06-29 22:11 ` Alexandre Belloni
2017-06-29 22:11 ` Alexandre Belloni
2017-07-03 14:01 ` Boris Brezillon
2017-07-03 14:01 ` Boris Brezillon
2017-07-03 14:01 ` Boris Brezillon
2017-06-23 9:00 ` [PATCH 3/6] ARM: dts: at91: sama5d2: add classd nodes Quentin Schulz
2017-06-23 9:00 ` Quentin Schulz
2017-06-23 9:00 ` Quentin Schulz
2017-06-23 9:00 ` [PATCH 4/6] clk: at91: clk-generated: create function to find best_diff Quentin Schulz
2017-06-23 9:00 ` Quentin Schulz
2017-06-23 9:00 ` Quentin Schulz
2017-07-03 14:02 ` Boris Brezillon
2017-07-03 14:02 ` Boris Brezillon
2017-07-03 14:02 ` Boris Brezillon
2017-06-23 9:00 ` [PATCH 5/6] clk: at91: clk-generated: make gclk determine audio_pll rate Quentin Schulz
2017-06-23 9:00 ` Quentin Schulz
2017-07-03 14:19 ` Boris Brezillon [this message]
2017-07-03 14:19 ` Boris Brezillon
2017-07-03 14:19 ` Boris Brezillon
2017-06-23 9:00 ` [PATCH 6/6] ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd Quentin Schulz
2017-06-23 9:00 ` Quentin Schulz
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