[RFC] PCI: dwc: designware: allow customize unroll registers' readl/writel

[RFC] PCI: dwc: designware: allow customize unroll registers' readl/writel

[Jisheng Zhang]

Hi Joao, Jingoo,

Now, the PCIE_GET_ATU_OUTB_UNR_REG_OFFSET macro is defined as:

/* Register address builder */
#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)        \
                        ((0x3 << 20) | ((region) << 9))

I have one question: where does the (0x3 << 20) come from? 2MB space, a bit
large. And I didn't find it in the databook. Is it platform specific?
If yes, I want to cook one patch to customize unroll registers' readl/writel.

And how does (0x3 << 20) enable DBI2 access?

Thanks in advance,
Jisheng

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[RFC] PCI: dwc: designware: allow customize unroll registers' readl/writel

[Jisheng Zhang]

Hi Joao, Jingoo,

Now, the PCIE_GET_ATU_OUTB_UNR_REG_OFFSET macro is defined as:

/* Register address builder */
#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)        \
                        ((0x3 << 20) | ((region) << 9))

I have one question: where does the (0x3 << 20) come from? 2MB space, a bit
large. And I didn't find it in the databook. Is it platform specific?
If yes, I want to cook one patch to customize unroll registers' readl/writel.

And how does (0x3 << 20) enable DBI2 access?

Thanks in advance,
Jisheng

Re: [RFC] PCI: dwc: designware: allow customize unroll registers' readl/writel

[Jisheng Zhang]

On Thu, 13 Jul 2017 18:48:37 +0800 Jisheng Zhang wrote:

> Hi Joao, Jingoo,
> 
> Now, the PCIE_GET_ATU_OUTB_UNR_REG_OFFSET macro is defined as:
> 
> /* Register address builder */
> #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)        \
>                         ((0x3 << 20) | ((region) << 9))
> 
> I have one question: where does the (0x3 << 20) come from? 2MB space, a bit

sorry, typo. (0x3 << 20) should be 3MB.

> large. And I didn't find it in the databook. Is it platform specific?
> If yes, I want to cook one patch to customize unroll registers' readl/writel.
> 
> And how does (0x3 << 20) enable DBI2 access?
> 
> Thanks in advance,
> Jisheng


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[RFC] PCI: dwc: designware: allow customize unroll registers' readl/writel

[Jisheng Zhang]

On Thu, 13 Jul 2017 18:48:37 +0800 Jisheng Zhang wrote:

> Hi Joao, Jingoo,
> 
> Now, the PCIE_GET_ATU_OUTB_UNR_REG_OFFSET macro is defined as:
> 
> /* Register address builder */
> #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)        \
>                         ((0x3 << 20) | ((region) << 9))
> 
> I have one question: where does the (0x3 << 20) come from? 2MB space, a bit

sorry, typo. (0x3 << 20) should be 3MB.

> large. And I didn't find it in the databook. Is it platform specific?
> If yes, I want to cook one patch to customize unroll registers' readl/writel.
> 
> And how does (0x3 << 20) enable DBI2 access?
> 
> Thanks in advance,
> Jisheng

Re: [RFC] PCI: dwc: designware: allow customize unroll registers' readl/writel

[Joao Pinto]

SGkgSmlzaGVuZywKCsOAcyAxMTo1MiBBTSBkZSA3LzEzLzIwMTcsIEppc2hlbmcgWmhhbmcgZXNj
cmV2ZXU6Cj4gT24gVGh1LCAxMyBKdWwgMjAxNyAxODo0ODozNyArMDgwMCBKaXNoZW5nIFpoYW5n
IHdyb3RlOgo+IAo+PiBIaSBKb2FvLCBKaW5nb28sCj4+Cj4+IE5vdywgdGhlIFBDSUVfR0VUX0FU
VV9PVVRCX1VOUl9SRUdfT0ZGU0VUIG1hY3JvIGlzIGRlZmluZWQgYXM6Cj4+Cj4+IC8qIFJlZ2lz
dGVyIGFkZHJlc3MgYnVpbGRlciAqLwo+PiAjZGVmaW5lIFBDSUVfR0VUX0FUVV9PVVRCX1VOUl9S
RUdfT0ZGU0VUKHJlZ2lvbikgICAgICAgIFwKPj4gICAgICAgICAgICAgICAgICAgICAgICAgKCgw
eDMgPDwgMjApIHwgKChyZWdpb24pIDw8IDkpKQo+Pgo+PiBJIGhhdmUgb25lIHF1ZXN0aW9uOiB3
aGVyZSBkb2VzIHRoZSAoMHgzIDw8IDIwKSBjb21lIGZyb20/IDJNQiBzcGFjZSwgYSBiaXQKCkZy
b20sIHRoZSBQQ0llIENvcmUgNC44MCB5b3UgaGF2ZSB0aGUgbmV3IGZlYXR1cmUgVW5yb2xsLCB3
aGljaCB3YXMgZGV2ZWxvcGVkCmZvciBib3RoIGlBVFUgYW5kIERNQS4KVG8gaW5mb3JtIHRoZSBD
b3JlIHRoYXQgeW91IHdhbnQgdG8gYWNjZXNzIGFuIFVucm9sbCByZWdpc3RlciBhZGRyZXNzLCBi
aXRzIDIwCmFuZCAyMSBtdXN0IGJlIHNldCwgYW5kIHRoYXRzIHdoZXJlIDB4MyBjb21lcyBmcm9t
LgoKSWYgaXQgaXMgbm90IGNsZWFyIHBsZWFzZSBsZXQgbWUga25vdy4KCj4gCj4gc29ycnksIHR5
cG8uICgweDMgPDwgMjApIHNob3VsZCBiZSAzTUIuCj4gCj4+IGxhcmdlLiBBbmQgSSBkaWRuJ3Qg
ZmluZCBpdCBpbiB0aGUgZGF0YWJvb2suIElzIGl0IHBsYXRmb3JtIHNwZWNpZmljPwo+PiBJZiB5
ZXMsIEkgd2FudCB0byBjb29rIG9uZSBwYXRjaCB0byBjdXN0b21pemUgdW5yb2xsIHJlZ2lzdGVy
cycgcmVhZGwvd3JpdGVsLgo+Pgo+PiBBbmQgaG93IGRvZXMgKDB4MyA8PCAyMCkgZW5hYmxlIERC
STIgYWNjZXNzPwo+Pgo+PiBUaGFua3MgaW4gYWR2YW5jZSwKPj4gSmlzaGVuZwo+IAoKVGhhbmtz
LApKb2FvCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwps
aW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJh
ZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51
eC1hcm0ta2VybmVsCg==

[RFC] PCI: dwc: designware: allow customize unroll registers' readl/writel

[Joao Pinto]

Hi Jisheng,

?s 11:52 AM de 7/13/2017, Jisheng Zhang escreveu:
> On Thu, 13 Jul 2017 18:48:37 +0800 Jisheng Zhang wrote:
> 
>> Hi Joao, Jingoo,
>>
>> Now, the PCIE_GET_ATU_OUTB_UNR_REG_OFFSET macro is defined as:
>>
>> /* Register address builder */
>> #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)        \
>>                         ((0x3 << 20) | ((region) << 9))
>>
>> I have one question: where does the (0x3 << 20) come from? 2MB space, a bit

From, the PCIe Core 4.80 you have the new feature Unroll, which was developed
for both iATU and DMA.
To inform the Core that you want to access an Unroll register address, bits 20
and 21 must be set, and thats where 0x3 comes from.

If it is not clear please let me know.

> 
> sorry, typo. (0x3 << 20) should be 3MB.
> 
>> large. And I didn't find it in the databook. Is it platform specific?
>> If yes, I want to cook one patch to customize unroll registers' readl/writel.
>>
>> And how does (0x3 << 20) enable DBI2 access?
>>
>> Thanks in advance,
>> Jisheng
> 

Thanks,
Joao