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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/8] drm/i915: decouple gen9 and gen10 dp signal levels.
Date: Wed, 30 Aug 2017 17:06:39 +0300	[thread overview]
Message-ID: <20170830140639.GZ4914@intel.com> (raw)
In-Reply-To: <20170829232230.23051-2-rodrigo.vivi@intel.com>

On Tue, Aug 29, 2017 at 04:22:24PM -0700, Rodrigo Vivi wrote:
> Let's decouple bxt, glk and cnl dp signal levels
> from other DDIs to avoid confusion.
> 
> No functional change. Only a reorg to avoid messing
> with currently working DP signal levels when
> moving voltage swing sequences around to match spec.
> 
> v2: ddi_signal_levels is also called from other ddi
>     platforms, so don't remove IS_GEN9_BC check from
>     skl_ddi_set_iboos. (Ville).
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 27 ++++++++++++++++++---------
>  drivers/gpu/drm/i915/intel_dp.c  | 10 ++++------
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  3 files changed, 23 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 7e875e05d053..9a887780f99f 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2063,23 +2063,32 @@ static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
>  	return translate_signal_level(signal_levels);
>  }
>  
> -uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> +u32 bxt_signal_levels(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
>  	struct intel_encoder *encoder = &dport->base;
>  	enum port port = dport->port;
> +	u32 level = intel_ddi_dp_level(intel_dp);
> +
> +	if (IS_CANNONLAKE(dev_priv))
> +		cnl_ddi_vswing_sequence(encoder, level);
> +	else
> +		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> +
> +	return 0;
> +}
> +
> +uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> +	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
> +	struct intel_encoder *encoder = &dport->base;
>  	uint32_t level = intel_ddi_dp_level(intel_dp);
>  
>  	if (IS_GEN9_BC(dev_priv))
> -		skl_ddi_set_iboost(encoder, level);
> -	else if (IS_GEN9_LP(dev_priv))
> -		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> -	else if (IS_CANNONLAKE(dev_priv)) {
> -		cnl_ddi_vswing_sequence(encoder, level);
> -		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
> -		return 0;
> -	}
> +	    skl_ddi_set_iboost(encoder, level);
	^^^^
Tab got changed into spaces somehow.

With that fixed
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
>  	return DDI_BUF_TRANS_SELECT(level);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d3e5fdf0d2fa..49a8c339b2b0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3506,13 +3506,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  	uint32_t signal_levels, mask = 0;
>  	uint8_t train_set = intel_dp->train_set[0];
>  
> -	if (HAS_DDI(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> +		signal_levels = bxt_signal_levels(intel_dp);
> +	} else if (HAS_DDI(dev_priv)) {
>  		signal_levels = ddi_signal_levels(intel_dp);
> -
> -		if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
> -			signal_levels = 0;
> -		else
> -			mask = DDI_BUF_EMP_MASK;
> +		mask = DDI_BUF_EMP_MASK;
>  	} else if (IS_CHERRYVIEW(dev_priv)) {
>  		signal_levels = chv_signal_levels(intel_dp);
>  	} else if (IS_VALLEYVIEW(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 17649f13091c..469c06000774 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1271,6 +1271,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
>  			 struct intel_crtc_state *pipe_config);
>  void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
>  				    bool state);
> +u32 bxt_signal_levels(struct intel_dp *intel_dp);
>  uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
>  u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
>  
> -- 
> 2.13.2

-- 
Ville Syrjälä
Intel OTC
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2017-08-30 14:06 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-29 23:22 [PATCH 1/8] drm/i915: Introduce intel_ddi_dp_level Rodrigo Vivi
2017-08-29 23:22 ` [PATCH 2/8] drm/i915: decouple gen9 and gen10 dp signal levels Rodrigo Vivi
2017-08-30 14:06   ` Ville Syrjälä [this message]
2017-08-29 23:22 ` [PATCH 3/8] drm/i915: Align vswing sequences with old ddi buffer registers Rodrigo Vivi
2017-08-30 14:16   ` Ville Syrjälä
2017-08-29 23:22 ` [PATCH 4/8] drm/i915: Enable voltage swing before enabling DDI_BUF_CTL Rodrigo Vivi
2017-08-30 14:17   ` Ville Syrjälä
2017-08-29 23:22 ` [PATCH 5/8] drm/i915/cnl: Move voltage check into ddi buf trans functions Rodrigo Vivi
2017-08-30 14:11   ` Ville Syrjälä
2017-08-29 23:22 ` [PATCH 6/8] drm/i915/cnl: Move ddi buf trans related functions up Rodrigo Vivi
2017-08-30 14:17   ` Ville Syrjälä
2017-08-29 23:22 ` [PATCH 7/8] drm/i915/cnl: Fix DDI hdmi level selection Rodrigo Vivi
2017-08-30 14:13   ` Ville Syrjälä
2017-08-29 23:22 ` [PATCH 8/8] drm/i915/cnl: Fix DP max voltage Rodrigo Vivi
2017-08-30 14:14   ` Ville Syrjälä
2017-08-30 14:20   ` Ville Syrjälä
2017-08-30  0:35 ` ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915: Introduce intel_ddi_dp_level Patchwork
2017-08-30  5:26 ` ✓ Fi.CI.IGT: " Patchwork
2017-08-30 14:15 ` [PATCH 1/8] " Ville Syrjälä
     [not found] <Message-id: <20170830142037.GH4914@intel.com>
2017-08-31  0:00 ` [PATCH] drm/i915/cnl: Fix DP max voltage Rodrigo Vivi
2017-08-31 12:34   ` Ville Syrjälä
     [not found] <Message-id: <20170831123436.GO4914@intel.com>
2017-08-31 14:53 ` Rodrigo Vivi
2017-08-31 15:06   ` Ville Syrjälä
2017-08-31 16:49     ` Vivi, Rodrigo

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