From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 7/8] drm/i915/cnl: Fix DDI hdmi level selection.
Date: Wed, 30 Aug 2017 17:13:22 +0300 [thread overview]
Message-ID: <20170830141322.GB4914@intel.com> (raw)
In-Reply-To: <20170829232230.23051-7-rodrigo.vivi@intel.com>
On Tue, Aug 29, 2017 at 04:22:29PM -0700, Rodrigo Vivi wrote:
> Let's get a proper HDMI DDI entry level for vswing programming
> sequences on CNL.
>
> Spec doesn't specify any default for HDMI tables,
> so let's pick the last entry as the default for now.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 3ce02cbd4483..f1757a8e481a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -660,7 +660,10 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
> if (IS_GEN9_LP(dev_priv))
> return hdmi_level;
>
> - if (IS_GEN9_BC(dev_priv)) {
> + if (IS_CANNONLAKE(dev_priv)) {
> + cnl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
> + hdmi_default_entry = n_hdmi_entries - 1;
Hmm. I guess we might try to do the same thing for BXT, for extra
consistency. But that's a separate issue.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + } else if (IS_GEN9_BC(dev_priv)) {
> skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
> hdmi_default_entry = 8;
> } else if (IS_BROADWELL(dev_priv)) {
> --
> 2.13.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2017-08-30 14:13 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-29 23:22 [PATCH 1/8] drm/i915: Introduce intel_ddi_dp_level Rodrigo Vivi
2017-08-29 23:22 ` [PATCH 2/8] drm/i915: decouple gen9 and gen10 dp signal levels Rodrigo Vivi
2017-08-30 14:06 ` Ville Syrjälä
2017-08-29 23:22 ` [PATCH 3/8] drm/i915: Align vswing sequences with old ddi buffer registers Rodrigo Vivi
2017-08-30 14:16 ` Ville Syrjälä
2017-08-29 23:22 ` [PATCH 4/8] drm/i915: Enable voltage swing before enabling DDI_BUF_CTL Rodrigo Vivi
2017-08-30 14:17 ` Ville Syrjälä
2017-08-29 23:22 ` [PATCH 5/8] drm/i915/cnl: Move voltage check into ddi buf trans functions Rodrigo Vivi
2017-08-30 14:11 ` Ville Syrjälä
2017-08-29 23:22 ` [PATCH 6/8] drm/i915/cnl: Move ddi buf trans related functions up Rodrigo Vivi
2017-08-30 14:17 ` Ville Syrjälä
2017-08-29 23:22 ` [PATCH 7/8] drm/i915/cnl: Fix DDI hdmi level selection Rodrigo Vivi
2017-08-30 14:13 ` Ville Syrjälä [this message]
2017-08-29 23:22 ` [PATCH 8/8] drm/i915/cnl: Fix DP max voltage Rodrigo Vivi
2017-08-30 14:14 ` Ville Syrjälä
2017-08-30 14:20 ` Ville Syrjälä
2017-08-30 0:35 ` ✓ Fi.CI.BAT: success for series starting with [1/8] drm/i915: Introduce intel_ddi_dp_level Patchwork
2017-08-30 5:26 ` ✓ Fi.CI.IGT: " Patchwork
2017-08-30 14:15 ` [PATCH 1/8] " Ville Syrjälä
[not found] <Message-id: <20170830142037.GH4914@intel.com>
2017-08-31 0:00 ` [PATCH] drm/i915/cnl: Fix DP max voltage Rodrigo Vivi
2017-08-31 12:34 ` Ville Syrjälä
[not found] <Message-id: <20170831123436.GO4914@intel.com>
2017-08-31 14:53 ` Rodrigo Vivi
2017-08-31 15:06 ` Ville Syrjälä
2017-08-31 16:49 ` Vivi, Rodrigo
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