From: hch@lst.de (Christoph Hellwig)
Subject: [PATCH] nvme: fix lightnvm check
Date: Thu, 7 Sep 2017 14:20:46 +0200 [thread overview]
Message-ID: <20170907122046.GA19161@lst.de> (raw)
In-Reply-To: <4735ef51-e4a8-d34a-d6e4-fa969a3c1b58@lightnvm.io>
On Thu, Sep 07, 2017@02:15:52PM +0200, Matias Bj?rling wrote:
> I must have misunderstood when we discussed it. I understood it as to add
> detection to the NVMe specification.
>
> Going with Class code might not be the right way due to them describing the
> base protocol.
Well - existing NVMe (except Linux with lighnvm) simply expect a NVMe
PCIe device to support the NVM I/O command set. So if you have a drive
that wants to speak a different one it needs to be bindable to a new
driver and thus have a different PCIe class code.
But even with that in place we should also have the new command set
in CAP - so that a common code base can work all these devices, and
the command set can be used over fabrics as well for example.
> bit. Another approach, as OCSSD has grown, might be to use the existing
> command set, and teach the identify command about Zones/Chunks, where one
> writes sequentially within.
Even then we need a way to identify such devices. SCSI is a great
example - if the device has zones that MUST be written sequentially
it's a new ZBC device type. If the device just wants zones to be
written sequentially but can handle random writes with a performance
penalty it's the good old SBC type with a few extensions.
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: "Matias Bjørling" <mb@lightnvm.io>
Cc: Christoph Hellwig <hch@lst.de>,
Keith Busch <keith.busch@intel.com>,
stable@vger.kernel.org, linux-nvme@lists.infradead.org,
sagi@grimberg.me
Subject: Re: [PATCH] nvme: fix lightnvm check
Date: Thu, 7 Sep 2017 14:20:46 +0200 [thread overview]
Message-ID: <20170907122046.GA19161@lst.de> (raw)
In-Reply-To: <4735ef51-e4a8-d34a-d6e4-fa969a3c1b58@lightnvm.io>
On Thu, Sep 07, 2017 at 02:15:52PM +0200, Matias Bj�rling wrote:
> I must have misunderstood when we discussed it. I understood it as to add
> detection to the NVMe specification.
>
> Going with Class code might not be the right way due to them describing the
> base protocol.
Well - existing NVMe (except Linux with lighnvm) simply expect a NVMe
PCIe device to support the NVM I/O command set. So if you have a drive
that wants to speak a different one it needs to be bindable to a new
driver and thus have a different PCIe class code.
But even with that in place we should also have the new command set
in CAP - so that a common code base can work all these devices, and
the command set can be used over fabrics as well for example.
> bit. Another approach, as OCSSD has grown, might be to use the existing
> command set, and teach the identify command about Zones/Chunks, where one
> writes sequentially within.
Even then we need a way to identify such devices. SCSI is a great
example - if the device has zones that MUST be written sequentially
it's a new ZBC device type. If the device just wants zones to be
written sequentially but can handle random writes with a performance
penalty it's the good old SBC type with a few extensions.
next prev parent reply other threads:[~2017-09-07 12:20 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-06 9:48 [PATCH] nvme: fix lightnvm check Christoph Hellwig
2017-09-06 10:22 ` Sagi Grimberg
2017-09-06 10:25 ` Sagi Grimberg
2017-09-06 15:06 ` Keith Busch
2017-09-07 12:01 ` Christoph Hellwig
2017-09-07 12:01 ` Christoph Hellwig
2017-09-07 12:15 ` Matias Bjørling
2017-09-07 12:15 ` Matias Bjørling
2017-09-07 12:20 ` Christoph Hellwig [this message]
2017-09-07 12:20 ` Christoph Hellwig
2017-09-07 12:34 ` Matias Bjørling
2017-09-07 12:34 ` Matias Bjørling
-- strict thread matches above, loose matches on Subject: below --
2017-09-06 9:50 Christoph Hellwig
2017-09-06 9:50 ` Christoph Hellwig
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