* [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
@ 2017-10-05 8:58 ` Jacopo Mondi
0 siblings, 0 replies; 30+ messages in thread
From: Jacopo Mondi @ 2017-10-05 8:58 UTC (permalink / raw)
To: linux-arm-kernel
Add pin configuration subnode for ETHER pin group and enable the interface.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
arch/arm/boot/dts/r7s72100-gr-peach.dts | 38 +++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
index ad6a627..8b5a2c5 100644
--- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
+++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
@@ -68,6 +68,28 @@
/* P6_2 as RxD2; P6_3 as TxD2 */
pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
};
+
+ ether_pins: ether {
+ /* Ethernet on Ports 1,3,5,10 */
+ pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
+ <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
+ <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
+ <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
+ <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
+ <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
+ <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
+ <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
+ <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
+ <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
+ <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
+ <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
+ <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
+ <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
+ <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
+ <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
+ <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
+ <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
+ };
};
&extal_clk {
@@ -88,3 +110,19 @@
status = "okay";
};
+
+ðer {
+ pinctrl-names = "default";
+ pinctrl-0 = <ðer_pins>;
+
+ status = "okay";
+
+ reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <5>;
+
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
2017-10-05 8:58 ` Jacopo Mondi
@ 2017-10-05 9:09 ` Geert Uytterhoeven
-1 siblings, 0 replies; 30+ messages in thread
From: Geert Uytterhoeven @ 2017-10-05 9:09 UTC (permalink / raw)
To: Jacopo Mondi
Cc: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland,
Russell King, Linux-Renesas, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Hi Jacopo,
On Thu, Oct 5, 2017 at 10:58 AM, Jacopo Mondi <jacopo+renesas@jmondi.org> wrote:
> Add pin configuration subnode for ETHER pin group and enable the interface.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
> +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
> @@ -88,3 +110,19 @@
>
> status = "okay";
> };
> +
> +ðer {
> + pinctrl-names = "default";
> + pinctrl-0 = <ðer_pins>;
> +
> + status = "okay";
> +
> + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
> + reset-delay-us = <5>;
I'm afraid the PHY people (not CCed ;-) will want you to move these reset
properties to the phy subnode these days, despite
Documentation/devicetree/bindings/net/mdio.txt...
> +
> + renesas,no-ether-link;
> + phy-handle = <&phy0>;
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + };
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 30+ messages in thread* [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
@ 2017-10-05 9:09 ` Geert Uytterhoeven
0 siblings, 0 replies; 30+ messages in thread
From: Geert Uytterhoeven @ 2017-10-05 9:09 UTC (permalink / raw)
To: linux-arm-kernel
Hi Jacopo,
On Thu, Oct 5, 2017 at 10:58 AM, Jacopo Mondi <jacopo+renesas@jmondi.org> wrote:
> Add pin configuration subnode for ETHER pin group and enable the interface.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
> +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
> @@ -88,3 +110,19 @@
>
> status = "okay";
> };
> +
> +ðer {
> + pinctrl-names = "default";
> + pinctrl-0 = <ðer_pins>;
> +
> + status = "okay";
> +
> + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
> + reset-delay-us = <5>;
I'm afraid the PHY people (not CCed ;-) will want you to move these reset
properties to the phy subnode these days, despite
Documentation/devicetree/bindings/net/mdio.txt...
> +
> + renesas,no-ether-link;
> + phy-handle = <&phy0>;
> + phy0: ethernet-phy at 0 {
> + reg = <0>;
> + };
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
2017-10-05 9:09 ` Geert Uytterhoeven
(?)
@ 2017-10-05 9:39 ` jacopo mondi
2017-10-05 13:43 ` Andrew Lunn
-1 siblings, 1 reply; 30+ messages in thread
From: jacopo mondi @ 2017-10-05 9:39 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Chris Brandt, andrew, f.fainelli, netdev
Hi Geert
On Thu, Oct 05, 2017 at 11:09:40AM +0200, Geert Uytterhoeven wrote:
> Hi Jacopo,
>
> On Thu, Oct 5, 2017 at 10:58 AM, Jacopo Mondi <jacopo+renesas@jmondi.org> wrote:
> > Add pin configuration subnode for ETHER pin group and enable the interface.
> >
> > Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
> > +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
>
> > @@ -88,3 +110,19 @@
> >
> > status = "okay";
> > };
> > +
> > +ðer {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <ðer_pins>;
> > +
> > + status = "okay";
> > +
> > + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
> > + reset-delay-us = <5>;
>
> I'm afraid the PHY people (not CCed ;-) will want you to move these reset
> properties to the phy subnode these days, despite
> Documentation/devicetree/bindings/net/mdio.txt...
Extending to:
+andrew@lunn.ch
+f.fainelli@gmail.com
+netdev@vger.kernel.org
To hear from them when and how they like to move those properties and
if we can apply this in this shape or not.
Otherwise, if you think it's the case, I can move them nonetheless.
Thanks
j
>
> > +
> > + renesas,no-ether-link;
> > + phy-handle = <&phy0>;
> > + phy0: ethernet-phy@0 {
> > + reg = <0>;
> > + };
> > +};
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
2017-10-05 9:39 ` jacopo mondi
@ 2017-10-05 13:43 ` Andrew Lunn
2017-10-05 15:42 ` jacopo mondi
0 siblings, 1 reply; 30+ messages in thread
From: Andrew Lunn @ 2017-10-05 13:43 UTC (permalink / raw)
To: jacopo mondi; +Cc: Geert Uytterhoeven, Chris Brandt, f.fainelli, netdev
On Thu, Oct 05, 2017 at 11:39:15AM +0200, jacopo mondi wrote:
> Hi Geert
>
> On Thu, Oct 05, 2017 at 11:09:40AM +0200, Geert Uytterhoeven wrote:
> > Hi Jacopo,
> >
> > On Thu, Oct 5, 2017 at 10:58 AM, Jacopo Mondi <jacopo+renesas@jmondi.org> wrote:
> > > Add pin configuration subnode for ETHER pin group and enable the interface.
> > >
> > > Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > > --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
> > > +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
> >
> > > @@ -88,3 +110,19 @@
> > >
> > > status = "okay";
> > > };
> > > +
> > > +ðer {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <ðer_pins>;
> > > +
> > > + status = "okay";
> > > +
> > > + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
> > > + reset-delay-us = <5>;
> >
> > I'm afraid the PHY people (not CCed ;-) will want you to move these reset
> > properties to the phy subnode these days, despite
> > Documentation/devicetree/bindings/net/mdio.txt...
Hi Jocopo
So what is this reset resetting?
The MAC?
The PHY?
Andrew
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
2017-10-05 13:43 ` Andrew Lunn
@ 2017-10-05 15:42 ` jacopo mondi
2017-10-05 16:48 ` Andrew Lunn
0 siblings, 1 reply; 30+ messages in thread
From: jacopo mondi @ 2017-10-05 15:42 UTC (permalink / raw)
To: Andrew Lunn; +Cc: Geert Uytterhoeven, Chris Brandt, f.fainelli, netdev
Hi Andrew,
On Thu, Oct 05, 2017 at 03:43:39PM +0200, Andrew Lunn wrote:
> On Thu, Oct 05, 2017 at 11:39:15AM +0200, jacopo mondi wrote:
> > Hi Geert
> >
> > On Thu, Oct 05, 2017 at 11:09:40AM +0200, Geert Uytterhoeven wrote:
> > > Hi Jacopo,
> > >
> > > On Thu, Oct 5, 2017 at 10:58 AM, Jacopo Mondi <jacopo+renesas@jmondi.org> wrote:
> > > > Add pin configuration subnode for ETHER pin group and enable the interface.
> > > >
> > > > Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> > >
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > >
> > > > --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
> > > > +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
> > >
> > > > @@ -88,3 +110,19 @@
> > > >
> > > > status = "okay";
> > > > };
> > > > +
> > > > +ðer {
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <ðer_pins>;
> > > > +
> > > > + status = "okay";
> > > > +
> > > > + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
> > > > + reset-delay-us = <5>;
> > >
> > > I'm afraid the PHY people (not CCed ;-) will want you to move these reset
> > > properties to the phy subnode these days, despite
> > > Documentation/devicetree/bindings/net/mdio.txt...
>
> Hi Jocopo
>
> So what is this reset resetting?
>
> The MAC?
> The PHY?
The reset line goes from our SoC to LAN8710A PHY chip external reset pin.
Thanks
j
>
> Andrew
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
2017-10-05 15:42 ` jacopo mondi
@ 2017-10-05 16:48 ` Andrew Lunn
2017-10-06 12:24 ` jacopo mondi
0 siblings, 1 reply; 30+ messages in thread
From: Andrew Lunn @ 2017-10-05 16:48 UTC (permalink / raw)
To: jacopo mondi; +Cc: Geert Uytterhoeven, Chris Brandt, f.fainelli, netdev
On Thu, Oct 05, 2017 at 05:42:39PM +0200, jacopo mondi wrote:
> Hi Andrew,
>
> On Thu, Oct 05, 2017 at 03:43:39PM +0200, Andrew Lunn wrote:
> > On Thu, Oct 05, 2017 at 11:39:15AM +0200, jacopo mondi wrote:
> > > Hi Geert
> > >
> > > On Thu, Oct 05, 2017 at 11:09:40AM +0200, Geert Uytterhoeven wrote:
> > > > Hi Jacopo,
> > > >
> > > > On Thu, Oct 5, 2017 at 10:58 AM, Jacopo Mondi <jacopo+renesas@jmondi.org> wrote:
> > > > > Add pin configuration subnode for ETHER pin group and enable the interface.
> > > > >
> > > > > Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> > > >
> > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > >
> > > > > --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
> > > > > +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
> > > >
> > > > > @@ -88,3 +110,19 @@
> > > > >
> > > > > status = "okay";
> > > > > };
> > > > > +
> > > > > +ðer {
> > > > > + pinctrl-names = "default";
> > > > > + pinctrl-0 = <ðer_pins>;
> > > > > +
> > > > > + status = "okay";
> > > > > +
> > > > > + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
> > > > > + reset-delay-us = <5>;
> > > >
> > > > I'm afraid the PHY people (not CCed ;-) will want you to move these reset
> > > > properties to the phy subnode these days, despite
> > > > Documentation/devicetree/bindings/net/mdio.txt...
> >
> > Hi Jocopo
> >
> > So what is this reset resetting?
> >
> > The MAC?
> > The PHY?
>
> The reset line goes from our SoC to LAN8710A PHY chip external reset pin.
So yes, this is a PHY property, and should be in the PHY node.
Documentation/devicetree/bindings/net/mdio.txt does not apply here
anyway. That is for an MDIO binding. This node is an ethernet MAC.
So your binding whats to look something like
ether: ethernet@e8203000 {
compatible = "renesas,ether-r7s72100";
reg = <0xe8203000 0x800>,
<0xe8204800 0x200>;
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
power-domains = <&cpg_clocks>;
phy-mode = "mii";
phy-handle = <&phy0>;
#address-cells = <1>;
#size-cells = <0>;
mdio: bus-bus {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
reset-delay-us = <5>;
};
};
};
Andrew
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
2017-10-05 16:48 ` Andrew Lunn
@ 2017-10-06 12:24 ` jacopo mondi
2017-10-14 15:13 ` Andrew Lunn
0 siblings, 1 reply; 30+ messages in thread
From: jacopo mondi @ 2017-10-06 12:24 UTC (permalink / raw)
To: Andrew Lunn; +Cc: Geert Uytterhoeven, Chris Brandt, f.fainelli, netdev
Hi Andrew,
thanks for the suggestion
On Thu, Oct 05, 2017 at 06:48:26PM +0200, Andrew Lunn wrote:
> On Thu, Oct 05, 2017 at 05:42:39PM +0200, jacopo mondi wrote:
> > Hi Andrew,
[snip]
> > > Hi Jocopo
> > >
> > > So what is this reset resetting?
> > >
> > > The MAC?
> > > The PHY?
> >
> > The reset line goes from our SoC to LAN8710A PHY chip external reset pin.
>
> So yes, this is a PHY property, and should be in the PHY node.
>
> Documentation/devicetree/bindings/net/mdio.txt does not apply here
> anyway. That is for an MDIO binding. This node is an ethernet MAC.
>
> So your binding whats to look something like
>
> ether: ethernet@e8203000 {
> compatible = "renesas,ether-r7s72100";
> reg = <0xe8203000 0x800>,
> <0xe8204800 0x200>;
> interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
> power-domains = <&cpg_clocks>;
> phy-mode = "mii";
> phy-handle = <&phy0>;
> #address-cells = <1>;
> #size-cells = <0>;
>
> mdio: bus-bus {
> #address-cells = <1>;
> #size-cells = <0>;
>
> phy0: ethernet-phy@1 {
> reg = <1>;
Why reg = <1> ?
Shouldn't this be 0, or even better with no reg property at all?
mdio: bus-bus {
phy-0 {
reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
reset-delay-us = <5>;
};
};
Thanks
j
> reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
> reset-delay-us = <5>;
> };
> };
> };
>
> Andrew
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
2017-10-06 12:24 ` jacopo mondi
@ 2017-10-14 15:13 ` Andrew Lunn
0 siblings, 0 replies; 30+ messages in thread
From: Andrew Lunn @ 2017-10-14 15:13 UTC (permalink / raw)
To: jacopo mondi; +Cc: Geert Uytterhoeven, Chris Brandt, f.fainelli, netdev
> > So your binding whats to look something like
> >
> > ether: ethernet@e8203000 {
> > compatible = "renesas,ether-r7s72100";
> > reg = <0xe8203000 0x800>,
> > <0xe8204800 0x200>;
> > interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
> > power-domains = <&cpg_clocks>;
> > phy-mode = "mii";
> > phy-handle = <&phy0>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> >
> > mdio: bus-bus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> >
> > phy0: ethernet-phy@1 {
> > reg = <1>;
>
> Why reg = <1> ?
> Shouldn't this be 0, or even better with no reg property at all?
This is the address of the PHY on the MDIO bus. There can be up to 32
devices on the bus. I have no idea what address your PHY is using, so
i just picked a value. 0 can be special, so i avoided it.
Andrew
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
2017-10-05 8:58 ` Jacopo Mondi
@ 2017-10-06 12:25 ` jacopo mondi
-1 siblings, 0 replies; 30+ messages in thread
From: jacopo mondi @ 2017-10-06 12:25 UTC (permalink / raw)
To: Jacopo Mondi
Cc: horms, geert, magnus.damm, robh+dt, mark.rutland, linux,
linux-renesas-soc, devicetree, linux-arm-kernel, linux-kernel
Hi Simon,
On Thu, Oct 05, 2017 at 10:58:20AM +0200, Jacopo Mondi wrote:
> Add pin configuration subnode for ETHER pin group and enable the interface.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> ---
> arch/arm/boot/dts/r7s72100-gr-peach.dts | 38 +++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
Can you confirm you have not applied this yet?
I have received indications from netdev people to change location of
the reset pin properties, as they belong to PHY node, and also to
change the node layout.
If you have applied the first 2 but not this one, I will re-submit this one only
Thanks
j
> diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
> index ad6a627..8b5a2c5 100644
> --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
> +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
> @@ -68,6 +68,28 @@
> /* P6_2 as RxD2; P6_3 as TxD2 */
> pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
> };
> +
> + ether_pins: ether {
> + /* Ethernet on Ports 1,3,5,10 */
> + pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
> + <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
> + <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
> + <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
> + <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
> + <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
> + <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
> + <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
> + <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
> + <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
> + <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
> + <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
> + <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
> + <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
> + <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
> + <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
> + <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
> + <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
> + };
> };
>
> &extal_clk {
> @@ -88,3 +110,19 @@
>
> status = "okay";
> };
> +
> +ðer {
> + pinctrl-names = "default";
> + pinctrl-0 = <ðer_pins>;
> +
> + status = "okay";
> +
> + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
> + reset-delay-us = <5>;
> +
> + renesas,no-ether-link;
> + phy-handle = <&phy0>;
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 30+ messages in thread* [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
@ 2017-10-06 12:25 ` jacopo mondi
0 siblings, 0 replies; 30+ messages in thread
From: jacopo mondi @ 2017-10-06 12:25 UTC (permalink / raw)
To: linux-arm-kernel
Hi Simon,
On Thu, Oct 05, 2017 at 10:58:20AM +0200, Jacopo Mondi wrote:
> Add pin configuration subnode for ETHER pin group and enable the interface.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> ---
> arch/arm/boot/dts/r7s72100-gr-peach.dts | 38 +++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
Can you confirm you have not applied this yet?
I have received indications from netdev people to change location of
the reset pin properties, as they belong to PHY node, and also to
change the node layout.
If you have applied the first 2 but not this one, I will re-submit this one only
Thanks
j
> diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
> index ad6a627..8b5a2c5 100644
> --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
> +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
> @@ -68,6 +68,28 @@
> /* P6_2 as RxD2; P6_3 as TxD2 */
> pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
> };
> +
> + ether_pins: ether {
> + /* Ethernet on Ports 1,3,5,10 */
> + pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
> + <RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
> + <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
> + <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
> + <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
> + <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
> + <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
> + <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
> + <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
> + <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
> + <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
> + <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
> + <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
> + <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
> + <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
> + <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
> + <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
> + <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
> + };
> };
>
> &extal_clk {
> @@ -88,3 +110,19 @@
>
> status = "okay";
> };
> +
> +ðer {
> + pinctrl-names = "default";
> + pinctrl-0 = <ðer_pins>;
> +
> + status = "okay";
> +
> + reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
> + reset-delay-us = <5>;
> +
> + renesas,no-ether-link;
> + phy-handle = <&phy0>;
> + phy0: ethernet-phy at 0 {
> + reg = <0>;
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
2017-10-06 12:25 ` jacopo mondi
@ 2017-10-09 5:57 ` Simon Horman
-1 siblings, 0 replies; 30+ messages in thread
From: Simon Horman @ 2017-10-09 5:57 UTC (permalink / raw)
To: jacopo mondi
Cc: Jacopo Mondi, geert, magnus.damm, robh+dt, mark.rutland, linux,
linux-renesas-soc, devicetree, linux-arm-kernel, linux-kernel
On Fri, Oct 06, 2017 at 02:25:23PM +0200, jacopo mondi wrote:
> Hi Simon,
>
> On Thu, Oct 05, 2017 at 10:58:20AM +0200, Jacopo Mondi wrote:
> > Add pin configuration subnode for ETHER pin group and enable the interface.
> >
> > Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> > ---
> > arch/arm/boot/dts/r7s72100-gr-peach.dts | 38 +++++++++++++++++++++++++++++++++
> > 1 file changed, 38 insertions(+)
> >
>
> Can you confirm you have not applied this yet?
Confirmed.
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 3/3] ARM: dts: gr-peach: Add ETHER pin group
@ 2017-10-09 5:57 ` Simon Horman
0 siblings, 0 replies; 30+ messages in thread
From: Simon Horman @ 2017-10-09 5:57 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Oct 06, 2017 at 02:25:23PM +0200, jacopo mondi wrote:
> Hi Simon,
>
> On Thu, Oct 05, 2017 at 10:58:20AM +0200, Jacopo Mondi wrote:
> > Add pin configuration subnode for ETHER pin group and enable the interface.
> >
> > Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> > ---
> > arch/arm/boot/dts/r7s72100-gr-peach.dts | 38 +++++++++++++++++++++++++++++++++
> > 1 file changed, 38 insertions(+)
> >
>
> Can you confirm you have not applied this yet?
Confirmed.
^ permalink raw reply [flat|nested] 30+ messages in thread