From: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
To: Enric Balletbo i Serra
<enric.balletbo-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Cc: MyungJoo Ham
<myungjoo.ham-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>,
dianders-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
groeck-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Alexandru Stan <amstan-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
Frank Wang <frank.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Subject: Re: [PATCH 3/3] arm64: dts: rockchip: add extcon nodes and enable tcphy.
Date: Wed, 6 Dec 2017 09:29:20 -0800 [thread overview]
Message-ID: <20171206172919.GA87458@google.com> (raw)
In-Reply-To: <20171206111008.3079-3-enric.balletbo-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
+ Alex, Jeffy, Frank Wang
Hi,
On Wed, Dec 06, 2017 at 12:10:08PM +0100, Enric Balletbo i Serra wrote:
> Enable tcphy and create the cros-ec's extcon node for the USB Type-C port.
>
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> ---
> arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> index 470105d..03f1950 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> @@ -855,6 +855,20 @@ ap_i2c_audio: &i2c8 {
> compatible = "google,cros-ec-pwm";
> #pwm-cells = <1>;
> };
> +
> + usbc_extcon0: extcon@0 {
> + compatible = "google,extcon-usbc-cros-ec";
> + google,usb-port-id = <0>;
> +
> + #extcon-cells = <0>;
> + };
> +
> + usbc_extcon1: extcon@1 {
> + compatible = "google,extcon-usbc-cros-ec";
> + google,usb-port-id = <1>;
> +
> + #extcon-cells = <0>;
> + };
> };
> };
>
> @@ -865,6 +879,16 @@ ap_i2c_audio: &i2c8 {
> rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
> };
>
> +&tcphy0 {
> + status = "okay";
> + extcon = <&usbc_extcon0>;
> +};
> +
> +&tcphy1 {
> + status = "okay";
> + extcon = <&usbc_extcon1>;
> +};
> +
> &u2phy0 {
> status = "okay";
> };
> @@ -911,6 +935,7 @@ ap_i2c_audio: &i2c8 {
>
> &usbdrd3_0 {
> status = "okay";
> + extcon = <&usbc_extcon0>;
> };
>
> &usbdrd_dwc3_0 {
> @@ -920,6 +945,7 @@ ap_i2c_audio: &i2c8 {
>
> &usbdrd3_1 {
> status = "okay";
> + extcon = <&usbc_extcon1>;
> };
>
> &usbdrd_dwc3_1 {
Seems OK.
Also, IIUC, I think if we ever want to support dual-role/OTG, we need an
extcon reference in the USB2/OTG PHY that serves these ports too. i.e.,
u2phy0 and u2phy1? Notably, the PHY driver supports the extcon
properties, but it's not documented in
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt yet (we
should probably get that fixed).
So, anyway, maybe the above isn't a blocker for this patch. Just noticed
it while reading. Assuming the driver stuff falls into place:
Reviewed-by: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
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WARNING: multiple messages have this Message-ID (diff)
From: briannorris@chromium.org (Brian Norris)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/3] arm64: dts: rockchip: add extcon nodes and enable tcphy.
Date: Wed, 6 Dec 2017 09:29:20 -0800 [thread overview]
Message-ID: <20171206172919.GA87458@google.com> (raw)
In-Reply-To: <20171206111008.3079-3-enric.balletbo@collabora.com>
+ Alex, Jeffy, Frank Wang
Hi,
On Wed, Dec 06, 2017 at 12:10:08PM +0100, Enric Balletbo i Serra wrote:
> Enable tcphy and create the cros-ec's extcon node for the USB Type-C port.
>
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> index 470105d..03f1950 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> @@ -855,6 +855,20 @@ ap_i2c_audio: &i2c8 {
> compatible = "google,cros-ec-pwm";
> #pwm-cells = <1>;
> };
> +
> + usbc_extcon0: extcon at 0 {
> + compatible = "google,extcon-usbc-cros-ec";
> + google,usb-port-id = <0>;
> +
> + #extcon-cells = <0>;
> + };
> +
> + usbc_extcon1: extcon at 1 {
> + compatible = "google,extcon-usbc-cros-ec";
> + google,usb-port-id = <1>;
> +
> + #extcon-cells = <0>;
> + };
> };
> };
>
> @@ -865,6 +879,16 @@ ap_i2c_audio: &i2c8 {
> rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
> };
>
> +&tcphy0 {
> + status = "okay";
> + extcon = <&usbc_extcon0>;
> +};
> +
> +&tcphy1 {
> + status = "okay";
> + extcon = <&usbc_extcon1>;
> +};
> +
> &u2phy0 {
> status = "okay";
> };
> @@ -911,6 +935,7 @@ ap_i2c_audio: &i2c8 {
>
> &usbdrd3_0 {
> status = "okay";
> + extcon = <&usbc_extcon0>;
> };
>
> &usbdrd_dwc3_0 {
> @@ -920,6 +945,7 @@ ap_i2c_audio: &i2c8 {
>
> &usbdrd3_1 {
> status = "okay";
> + extcon = <&usbc_extcon1>;
> };
>
> &usbdrd_dwc3_1 {
Seems OK.
Also, IIUC, I think if we ever want to support dual-role/OTG, we need an
extcon reference in the USB2/OTG PHY that serves these ports too. i.e.,
u2phy0 and u2phy1? Notably, the PHY driver supports the extcon
properties, but it's not documented in
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt yet (we
should probably get that fixed).
So, anyway, maybe the above isn't a blocker for this patch. Just noticed
it while reading. Assuming the driver stuff falls into place:
Reviewed-by: Brian Norris <briannorris@chromium.org>
WARNING: multiple messages have this Message-ID (diff)
From: Brian Norris <briannorris@chromium.org>
To: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Cc: MyungJoo Ham <myungjoo.ham@samsung.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
Lee Jones <lee.jones@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
dianders@google.com, groeck@chromium.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
Alexandru Stan <amstan@chromium.org>,
Jeffy Chen <jeffy.chen@rock-chips.com>,
Frank Wang <frank.wang@rock-chips.com>
Subject: Re: [PATCH 3/3] arm64: dts: rockchip: add extcon nodes and enable tcphy.
Date: Wed, 6 Dec 2017 09:29:20 -0800 [thread overview]
Message-ID: <20171206172919.GA87458@google.com> (raw)
In-Reply-To: <20171206111008.3079-3-enric.balletbo@collabora.com>
+ Alex, Jeffy, Frank Wang
Hi,
On Wed, Dec 06, 2017 at 12:10:08PM +0100, Enric Balletbo i Serra wrote:
> Enable tcphy and create the cros-ec's extcon node for the USB Type-C port.
>
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> index 470105d..03f1950 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> @@ -855,6 +855,20 @@ ap_i2c_audio: &i2c8 {
> compatible = "google,cros-ec-pwm";
> #pwm-cells = <1>;
> };
> +
> + usbc_extcon0: extcon@0 {
> + compatible = "google,extcon-usbc-cros-ec";
> + google,usb-port-id = <0>;
> +
> + #extcon-cells = <0>;
> + };
> +
> + usbc_extcon1: extcon@1 {
> + compatible = "google,extcon-usbc-cros-ec";
> + google,usb-port-id = <1>;
> +
> + #extcon-cells = <0>;
> + };
> };
> };
>
> @@ -865,6 +879,16 @@ ap_i2c_audio: &i2c8 {
> rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
> };
>
> +&tcphy0 {
> + status = "okay";
> + extcon = <&usbc_extcon0>;
> +};
> +
> +&tcphy1 {
> + status = "okay";
> + extcon = <&usbc_extcon1>;
> +};
> +
> &u2phy0 {
> status = "okay";
> };
> @@ -911,6 +935,7 @@ ap_i2c_audio: &i2c8 {
>
> &usbdrd3_0 {
> status = "okay";
> + extcon = <&usbc_extcon0>;
> };
>
> &usbdrd_dwc3_0 {
> @@ -920,6 +945,7 @@ ap_i2c_audio: &i2c8 {
>
> &usbdrd3_1 {
> status = "okay";
> + extcon = <&usbc_extcon1>;
> };
>
> &usbdrd_dwc3_1 {
Seems OK.
Also, IIUC, I think if we ever want to support dual-role/OTG, we need an
extcon reference in the USB2/OTG PHY that serves these ports too. i.e.,
u2phy0 and u2phy1? Notably, the PHY driver supports the extcon
properties, but it's not documented in
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt yet (we
should probably get that fixed).
So, anyway, maybe the above isn't a blocker for this patch. Just noticed
it while reading. Assuming the driver stuff falls into place:
Reviewed-by: Brian Norris <briannorris@chromium.org>
next prev parent reply other threads:[~2017-12-06 17:29 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20171206111048epcas3p2b412288717b0f8197c85edaab5c9a242@epcas3p2.samsung.com>
2017-12-06 11:10 ` [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables Enric Balletbo i Serra
2017-12-06 11:10 ` Enric Balletbo i Serra
2017-12-06 11:10 ` Enric Balletbo i Serra
2017-12-06 11:10 ` [PATCH 2/3] arm64: dts: rockchip: add usb3-phy phandle for dwc3 Enric Balletbo i Serra
2017-12-06 11:10 ` Enric Balletbo i Serra
2017-12-06 11:10 ` Enric Balletbo i Serra
[not found] ` <20171206111008.3079-2-enric.balletbo-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2017-12-06 11:20 ` Heiko Stübner
2017-12-06 11:20 ` Heiko Stübner
2017-12-06 11:20 ` Heiko Stübner
2017-12-06 11:27 ` Enric Balletbo i Serra
2017-12-06 11:27 ` Enric Balletbo i Serra
2017-12-06 11:27 ` Enric Balletbo i Serra
2017-12-06 15:43 ` [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables Lee Jones
2017-12-06 15:43 ` Lee Jones
2017-12-06 15:43 ` Lee Jones
[not found] ` <20171206111008.3079-1-enric.balletbo-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2017-12-06 11:10 ` [PATCH 3/3] arm64: dts: rockchip: add extcon nodes and enable tcphy Enric Balletbo i Serra
2017-12-06 11:10 ` Enric Balletbo i Serra
2017-12-06 11:10 ` Enric Balletbo i Serra
[not found] ` <20171206111008.3079-3-enric.balletbo-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2017-12-06 17:29 ` Brian Norris [this message]
2017-12-06 17:29 ` Brian Norris
2017-12-06 17:29 ` Brian Norris
[not found] ` <20171206172919.GA87458-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
2017-12-13 10:28 ` Enric Balletbo Serra
2017-12-13 10:28 ` Enric Balletbo Serra
2017-12-13 10:28 ` Enric Balletbo Serra
2017-12-07 2:12 ` [PATCH 1/3] extcon: usbc-cros-ec: add support to notify USB type cables Chanwoo Choi
2017-12-07 2:12 ` Chanwoo Choi
2017-12-07 2:12 ` Chanwoo Choi
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