Re: [PATCH v4 1/4] x86emul: Support GFNI insns

[Yang Zhong <yang.zhong@intel.com>]

On Wed, Jan 03, 2018 at 10:00:51AM -0700, Jan Beulich wrote:
> >>> On 03.01.18 at 09:26, <yang.zhong@intel.com> wrote:
> > @@ -7741,6 +7752,16 @@ x86_emulate(
> >          op_bytes = 16;
> >          goto simd_0f3a_common;
> >  
> > +    case X86EMUL_OPC_66(0x0f3a, 0xce):     /* gf2p8affineqb $imm8,xmm/m128,xmm,xmm */
> > +    case X86EMUL_OPC_VEX_66(0x0f3a, 0xce): /* vgf2p8affineqb $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
> > +    case X86EMUL_OPC_66(0x0f3a, 0xcf):     /* gf2p8affineinvqb $imm8,xmm/m128,xmm,xmm */
> > +    case X86EMUL_OPC_VEX_66(0x0f3a, 0xcf): /* vgf2p8affineinvqb $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
> > +        host_and_vcpu_must_have(gfni);
> > +        if ( vex.opcx == vex_none )
> > +            goto simd_0f3a_common;
> > +        generate_exception_if(vex.w, EXC_UD);
> 
> The documentation says .W1, but I of course don't know whether
> you meanwhile tested your code (you still don't add a test case)
> and the doc is wrong, or this needs to be !vex.w.
>
  Thanks Jan pointed out this issue, you are right!

  vgf2p8affineqb and vgf2p8affineinvqb are W1, but vgf2p8mulb is W0.

  So, for vgf2p8affineqb and vgf2p8affineinvqb, !vex.w is right.
  for vgf2p8mulb vex.w is right.

  As for the test case for those insns, i am writing those related test cases in tools/tests/x86_emulator.

  How many test cases will you need ? One test case for one CPU feature(vaes,gfni and vpclmulqdq)？

  Another issue is would you please share your test guide? i will verify those insns on my simics enviornment.

  thanks a lot!

  Yang
 
> Jan

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