[PATCH v4 0/4] x86/cpuid: enable new cpu features

[PATCH v4 0/4] x86/cpuid: enable new cpu features

[Yang Zhong]

The new cpu features in intel icelake: AVX512VBMI2/GFNI/VAES/
AVX512VNNI/AVX512BITALG/VPCLMULQDQ.

v4: changes from Jan's comments in v3
    patch 1:
      simd_size set issue.
      remove else.
      add vex.w exception check. 
      gfni insns comments issue.
      double blank lines issue.
    patch 2:
      generate_exception_if(vex.l, EXC_UD) is not useful.
      comments for vex insns.
      if ( vex.l ) for vpclmulqdq.
      add simd_0f_imm8_ymm for vpclmulqdq flag.
    patch 3:
      remove fall through comments.
      add comments for vex insns.
      vaesimc(128 bit) issue.
      simd_0f_avx is changed to simd_0f_ymm for VAES flag.
   patch 4:
      rebased patch, which was acked by Jan in v3.

v3: adjust the patches sequence from Jan

v2: need implement x86 emulation for Legacy and VEX insns,
    EVEX insns in next time suggested by Jan

Yang Zhong (4):
  x86emul: Support GFNI insns
  x86emul: Support vpclmulqdq
  x86emul: Support vaes insns
  x86/cpuid: Enable new SSE/AVX/AVX512 cpu features

 docs/man/xl.cfg.pod.5.in                    |  3 +-
 tools/libxl/libxl_cpuid.c                   |  6 ++++
 tools/misc/xen-cpuid.c                      | 12 +++++---
 xen/arch/x86/x86_emulate/x86_emulate.c      | 48 ++++++++++++++++++++++++-----
 xen/include/asm-x86/cpufeature.h            |  5 +++
 xen/include/public/arch-x86/cpufeatureset.h |  6 ++++
 xen/tools/gen-cpuid.py                      |  3 +-
 7 files changed, 69 insertions(+), 14 deletions(-)

-- 
1.9.1


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[PATCH v4 1/4] x86emul: Support GFNI insns

[Yang Zhong]

Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 21 +++++++++++++++++++++
 xen/include/asm-x86/cpufeature.h       |  3 +++
 2 files changed, 24 insertions(+)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 54a2756..2d331ea 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -385,6 +385,7 @@ static const struct {
     [0x40] = { .simd_size = simd_packed_int },
     [0x41] = { .simd_size = simd_packed_int, .two_op = 1 },
     [0xc8 ... 0xcd] = { .simd_size = simd_other },
+    [0xcf] = { .simd_size = simd_packed_int },
     [0xdb] = { .simd_size = simd_packed_int, .two_op = 1 },
     [0xdc ... 0xdf] = { .simd_size = simd_packed_int },
     [0xf0] = { .two_op = 1 },
@@ -421,6 +422,7 @@ static const struct {
     [0x4c] = { .simd_size = simd_packed_int, .four_op = 1 },
     [0x60 ... 0x63] = { .simd_size = simd_packed_int, .two_op = 1 },
     [0xcc] = { .simd_size = simd_other },
+    [0xce ... 0xcf] = { .simd_size = simd_packed_int },
     [0xdf] = { .simd_size = simd_packed_int, .two_op = 1 },
     [0xf0] = {},
 };
@@ -1623,6 +1625,7 @@ static bool vcpu_has(
 #define vcpu_has_clflushopt()  vcpu_has(         7, EBX, 23, ctxt, ops)
 #define vcpu_has_clwb()        vcpu_has(         7, EBX, 24, ctxt, ops)
 #define vcpu_has_sha()         vcpu_has(         7, EBX, 29, ctxt, ops)
+#define vcpu_has_gfni()        vcpu_has(         7, ECX,  8, ctxt, ops)
 #define vcpu_has_rdpid()       vcpu_has(         7, ECX, 22, ctxt, ops)
 #define vcpu_has_clzero()      vcpu_has(0x80000008, EBX,  0, ctxt, ops)
 
@@ -7356,6 +7359,14 @@ x86_emulate(
         op_bytes = 16;
         goto simd_0f38_common;
 
+    case X86EMUL_OPC_66(0x0f38, 0xcf):       /* gf2p8mulb xmm/m128,xmm */
+    case X86EMUL_OPC_VEX_66(0x0f38, 0xcf):   /* vgf2p8mulb {x,y}mm/mem,{x,y}mm,{x,y}mm */
+        host_and_vcpu_must_have(gfni);
+        if ( vex.opcx == vex_none )
+            goto simd_0f38_common;
+        generate_exception_if(vex.w, EXC_UD);
+        goto simd_0f_avx;
+
     case X86EMUL_OPC(0x0f38, 0xf0): /* movbe m,r */
     case X86EMUL_OPC(0x0f38, 0xf1): /* movbe r,m */
         vcpu_must_have(movbe);
@@ -7741,6 +7752,16 @@ x86_emulate(
         op_bytes = 16;
         goto simd_0f3a_common;
 
+    case X86EMUL_OPC_66(0x0f3a, 0xce):     /* gf2p8affineqb $imm8,xmm/m128,xmm,xmm */
+    case X86EMUL_OPC_VEX_66(0x0f3a, 0xce): /* vgf2p8affineqb $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
+    case X86EMUL_OPC_66(0x0f3a, 0xcf):     /* gf2p8affineinvqb $imm8,xmm/m128,xmm,xmm */
+    case X86EMUL_OPC_VEX_66(0x0f3a, 0xcf): /* vgf2p8affineinvqb $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
+        host_and_vcpu_must_have(gfni);
+        if ( vex.opcx == vex_none )
+            goto simd_0f3a_common;
+        generate_exception_if(vex.w, EXC_UD);
+        goto simd_0f_imm8_avx;
+
     case X86EMUL_OPC_66(0x0f3a, 0xdf):     /* aeskeygenassist $imm8,xmm/m128,xmm */
     case X86EMUL_OPC_VEX_66(0x0f3a, 0xdf): /* vaeskeygenassist $imm8,xmm/m128,xmm */
         host_and_vcpu_must_have(aesni);
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 84cc51d..9c43cd8 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -97,6 +97,9 @@
 #define cpu_has_smap            boot_cpu_has(X86_FEATURE_SMAP)
 #define cpu_has_sha             boot_cpu_has(X86_FEATURE_SHA)
 
+/* CPUID level 0x00000007:0.ecx */
+#define cpu_has_gfni            boot_cpu_has(X86_FEATURE_GFNI)
+
 /* CPUID level 0x80000007.edx */
 #define cpu_has_itsc            boot_cpu_has(X86_FEATURE_ITSC)
 
-- 
1.9.1


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[PATCH v4 2/4] x86emul: Support vpclmulqdq

[Yang Zhong]

The previous vpclmulqdq only support AVX128.
Icelake added AVX256 support.

Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 10 ++++++++--
 xen/include/asm-x86/cpufeature.h       |  1 +
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 2d331ea..15f37e4 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -1626,6 +1626,7 @@ static bool vcpu_has(
 #define vcpu_has_clwb()        vcpu_has(         7, EBX, 24, ctxt, ops)
 #define vcpu_has_sha()         vcpu_has(         7, EBX, 29, ctxt, ops)
 #define vcpu_has_gfni()        vcpu_has(         7, ECX,  8, ctxt, ops)
+#define vcpu_has_vpclmulqdq()  vcpu_has(         7, ECX, 10, ctxt, ops)
 #define vcpu_has_rdpid()       vcpu_has(         7, ECX, 22, ctxt, ops)
 #define vcpu_has_clzero()      vcpu_has(0x80000008, EBX,  0, ctxt, ops)
 
@@ -6168,6 +6169,7 @@ x86_emulate(
     simd_0f_imm8_avx:
                 host_and_vcpu_must_have(avx);
             }
+    simd_0f_imm8_ymm:
             get_fpu(X86EMUL_FPU_ymm, &fic);
         }
         else if ( vex.pfx )
@@ -7668,11 +7670,15 @@ x86_emulate(
         goto simd_0f_imm8_avx;
 
     case X86EMUL_OPC_66(0x0f3a, 0x44):     /* pclmulqdq $imm8,xmm/m128,xmm */
-    case X86EMUL_OPC_VEX_66(0x0f3a, 0x44): /* vpclmulqdq $imm8,xmm/m128,xmm,xmm */
+    case X86EMUL_OPC_VEX_66(0x0f3a, 0x44): /* vpclmulqdq $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
+        if ( vex.l )
+        {
+            host_and_vcpu_must_have(vpclmulqdq);
+            goto simd_0f_imm8_ymm;
+        }
         host_and_vcpu_must_have(pclmulqdq);
         if ( vex.opcx == vex_none )
             goto simd_0f3a_common;
-        generate_exception_if(vex.l, EXC_UD);
         goto simd_0f_imm8_avx;
 
     case X86EMUL_OPC_VEX_66(0x0f3a, 0x4a): /* vblendvps {x,y}mm,{x,y}mm/mem,{x,y}mm,{x,y}mm */
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 9c43cd8..3f24f06 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -99,6 +99,7 @@
 
 /* CPUID level 0x00000007:0.ecx */
 #define cpu_has_gfni            boot_cpu_has(X86_FEATURE_GFNI)
+#define cpu_has_vpclmulqdq      boot_cpu_has(X86_FEATURE_VPCLMULQDQ)
 
 /* CPUID level 0x80000007.edx */
 #define cpu_has_itsc            boot_cpu_has(X86_FEATURE_ITSC)
-- 
1.9.1


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[PATCH v4 3/4] x86emul: Support vaes insns

[Yang Zhong]

The previous aes insns only support legacy and AVX128.
Icelake added AVX256 support.

Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
 xen/arch/x86/x86_emulate/x86_emulate.c | 17 ++++++++++++-----
 xen/include/asm-x86/cpufeature.h       |  1 +
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 15f37e4..fa09990 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -1626,6 +1626,7 @@ static bool vcpu_has(
 #define vcpu_has_clwb()        vcpu_has(         7, EBX, 24, ctxt, ops)
 #define vcpu_has_sha()         vcpu_has(         7, EBX, 29, ctxt, ops)
 #define vcpu_has_gfni()        vcpu_has(         7, ECX,  8, ctxt, ops)
+#define vcpu_has_vaes()        vcpu_has(         7, ECX,  9, ctxt, ops)
 #define vcpu_has_vpclmulqdq()  vcpu_has(         7, ECX, 10, ctxt, ops)
 #define vcpu_has_rdpid()       vcpu_has(         7, ECX, 22, ctxt, ops)
 #define vcpu_has_clzero()      vcpu_has(0x80000008, EBX,  0, ctxt, ops)
@@ -7336,17 +7337,23 @@ x86_emulate(
     case X86EMUL_OPC_66(0x0f38, 0xdb):     /* aesimc xmm/m128,xmm */
     case X86EMUL_OPC_VEX_66(0x0f38, 0xdb): /* vaesimc xmm/m128,xmm */
     case X86EMUL_OPC_66(0x0f38, 0xdc):     /* aesenc xmm/m128,xmm,xmm */
-    case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc xmm/m128,xmm,xmm */
+    case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc {x,y}mm/mem,{x,y}mm,{x,y}mm */
     case X86EMUL_OPC_66(0x0f38, 0xdd):     /* aesenclast xmm/m128,xmm,xmm */
-    case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast xmm/m128,xmm,xmm */
+    case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast {x,y}mm/mem,{x,y}mm,{x,y}mm */
     case X86EMUL_OPC_66(0x0f38, 0xde):     /* aesdec xmm/m128,xmm,xmm */
-    case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec xmm/m128,xmm,xmm */
+    case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec {x,y}mm/mem,{x,y}mm,{x,y}mm */
     case X86EMUL_OPC_66(0x0f38, 0xdf):     /* aesdeclast xmm/m128,xmm,xmm */
-    case X86EMUL_OPC_VEX_66(0x0f38, 0xdf): /* vaesdeclast xmm/m128,xmm,xmm */
+    case X86EMUL_OPC_VEX_66(0x0f38, 0xdf): /* vaesdeclast {x,y}mm/mem,{x,y}mm,{x,y}mm */
+        if ( vex.l )
+        {
+            host_and_vcpu_must_have(vaes);
+            goto simd_0f_ymm;
+        }
         host_and_vcpu_must_have(aesni);
         if ( vex.opcx == vex_none )
             goto simd_0f38_common;
-        /* fall through */
+        goto simd_0f_avx;
+
     case X86EMUL_OPC_VEX_66(0x0f38, 0x41): /* vphminposuw xmm/m128,xmm,xmm */
         generate_exception_if(vex.l, EXC_UD);
         goto simd_0f_avx;
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 3f24f06..ffa110e 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -99,6 +99,7 @@
 
 /* CPUID level 0x00000007:0.ecx */
 #define cpu_has_gfni            boot_cpu_has(X86_FEATURE_GFNI)
+#define cpu_has_vaes            boot_cpu_has(X86_FEATURE_VAES)
 #define cpu_has_vpclmulqdq      boot_cpu_has(X86_FEATURE_VPCLMULQDQ)
 
 /* CPUID level 0x80000007.edx */
-- 
1.9.1


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[PATCH v4 4/4] x86/cpuid: Enable new SSE/AVX/AVX512 cpu features

[Yang Zhong]

Intel IceLake cpu has added new cpu features: AVX512VBMI2/GFNI/
VAES/AVX512VNNI/AVX512BITALG/VPCLMULQDQ. Those new cpu features
need expose to guest.

The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512VBMI2
CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI
CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES
CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512VNNI
CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG

The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
 docs/man/xl.cfg.pod.5.in                    |  3 ++-
 tools/libxl/libxl_cpuid.c                   |  6 ++++++
 tools/misc/xen-cpuid.c                      | 12 +++++++-----
 xen/include/public/arch-x86/cpufeatureset.h |  6 ++++++
 xen/tools/gen-cpuid.py                      |  3 ++-
 5 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/docs/man/xl.cfg.pod.5.in b/docs/man/xl.cfg.pod.5.in
index b7b91d8..d056768 100644
--- a/docs/man/xl.cfg.pod.5.in
+++ b/docs/man/xl.cfg.pod.5.in
@@ -1731,7 +1731,8 @@ perfctr_core perfctr_nb pge pku popcnt pse pse36 psn rdrand rdseed rdtscp rtm
 sha skinit smap smep smx ss sse sse2 sse3 sse4.1 sse4.2 sse4_1 sse4_2 sse4a
 ssse3 svm svm_decode svm_lbrv svm_npt svm_nrips svm_pausefilt svm_tscrate
 svm_vmcbclean syscall sysenter tbm tm tm2 topoext tsc tsc-deadline tsc_adjust
-umip vme vmx wdt x2apic xop xsave xtpr
+umip vme vmx wdt x2apic xop xsave xtpr avx512_vbmi2 gfni vaes vpclmulqdq
+avx512_vnni avx512_bitalg
 
 
 The xend syntax is a list of values in the form of
diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
index e692b61..614991f 100644
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -199,6 +199,12 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
         {"umip",         0x00000007,  0, CPUID_REG_ECX,  2,  1},
         {"pku",          0x00000007,  0, CPUID_REG_ECX,  3,  1},
         {"ospke",        0x00000007,  0, CPUID_REG_ECX,  4,  1},
+        {"avx512_vbmi2", 0x00000007,  0, CPUID_REG_ECX,  6,  1},
+        {"gfni",         0x00000007,  0, CPUID_REG_ECX,  8,  1},
+        {"vaes",         0x00000007,  0, CPUID_REG_ECX,  9,  1},
+        {"vpclmulqdq",   0x00000007,  0, CPUID_REG_ECX, 10,  1},
+        {"avx512_vnni",  0x00000007,  0, CPUID_REG_ECX, 11,  1},
+        {"avx512_bitalg",0x00000007,  0, CPUID_REG_ECX, 12,  1},
 
         {"avx512-4vnniw",0x00000007,  0, CPUID_REG_EDX,  2,  1},
         {"avx512-4fmaps",0x00000007,  0, CPUID_REG_EDX,  3,  1},
diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index 0831f75..ef15252 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -120,11 +120,13 @@ static const char *str_Da1[32] =
 
 static const char *str_7c0[32] =
 {
-    [ 0] = "prechwt1", [ 1] = "avx512vbmi",
-    [ 2] = "umip",     [ 3] = "pku",
-    [ 4] = "ospke",
-
-    [5 ... 13] = "REZ",
+    [ 0] = "prechwt1",     [ 1] = "avx512vbmi",
+    [ 2] = "umip",         [ 3] = "pku",
+    [ 4] = "ospke",        [ 5] = "REZ",
+    [ 6] = "avx512_vbmi2", [ 7] = "REZ",
+    [ 8] = "gfni",         [ 9] = "vaes",
+    [10] = "vpclmulqdq",   [11] = "avx512_vnni",
+    [12] = "avx512_bitalg",[13] = "REZ",
 
     [14] = "avx512_vpopcntdq",
 
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index be6da8e..85ad59a 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -228,6 +228,12 @@ XEN_CPUFEATURE(AVX512VBMI,    6*32+ 1) /*A  AVX-512 Vector Byte Manipulation Ins
 XEN_CPUFEATURE(UMIP,          6*32+ 2) /*S  User Mode Instruction Prevention */
 XEN_CPUFEATURE(PKU,           6*32+ 3) /*H  Protection Keys for Userspace */
 XEN_CPUFEATURE(OSPKE,         6*32+ 4) /*!  OS Protection Keys Enable */
+XEN_CPUFEATURE(AVX512_VBMI2,  6*32+ 6) /*A  addition AVX-512 VBMI Instructions */
+XEN_CPUFEATURE(GFNI,          6*32+ 8) /*A  Galois Field New Instructions */
+XEN_CPUFEATURE(VAES,          6*32+ 9) /*A  Vector AES instructions */
+XEN_CPUFEATURE(VPCLMULQDQ,    6*32+ 10) /*A  vector PCLMULQDQ instructions */
+XEN_CPUFEATURE(AVX512_VNNI,   6*32+ 11) /*A  Vector Neural Network Instructions */
+XEN_CPUFEATURE(AVX512_BITALG, 6*32+ 12) /*A  support for VPOPCNT[B,W] and VPSHUFBITQMB */
 XEN_CPUFEATURE(AVX512_VPOPCNTDQ, 6*32+14) /*A  POPCNT for vectors of DW/QW */
 XEN_CPUFEATURE(RDPID,         6*32+22) /*A  RDPID instruction */
 
diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 9ec4486..be8df48 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -255,7 +255,8 @@ def crunch_numbers(state):
         # top of AVX512F
         AVX512F: [AVX512DQ, AVX512IFMA, AVX512PF, AVX512ER, AVX512CD,
                   AVX512BW, AVX512VL, AVX512VBMI, AVX512_4VNNIW,
-                  AVX512_4FMAPS, AVX512_VPOPCNTDQ],
+                  AVX512_4FMAPS, AVX512_VPOPCNTDQ, AVX512_VBMI2,
+                  AVX512_VNNI, AVX512_BITALG],
     }
 
     deep_features = tuple(sorted(deps.keys()))
-- 
1.9.1


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Re: [PATCH v4 4/4] x86/cpuid: Enable new SSE/AVX/AVX512 cpu features

[Jan Beulich]

>>> On 03.01.18 at 09:26, <yang.zhong@intel.com> wrote:
> Intel IceLake cpu has added new cpu features: AVX512VBMI2/GFNI/
> VAES/AVX512VNNI/AVX512BITALG/VPCLMULQDQ. Those new cpu features
> need expose to guest.
> 
> The bit definition:
> CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512VBMI2
> CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI
> CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES
> CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
> CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512VNNI
> CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
> 
> The release document ref below link:
> https://software.intel.com/sites/default/files/managed/c5/15/\ 
> architecture-instruction-set-extensions-programming-reference.pdf
> 
> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> Acked-by: Jan Beulich <jbeulich@suse.com>

I have to withdraw my ack here.

> --- a/xen/include/public/arch-x86/cpufeatureset.h
> +++ b/xen/include/public/arch-x86/cpufeatureset.h
> @@ -228,6 +228,12 @@ XEN_CPUFEATURE(AVX512VBMI,    6*32+ 1) /*A  AVX-512 Vector Byte Manipulation Ins
>  XEN_CPUFEATURE(UMIP,          6*32+ 2) /*S  User Mode Instruction Prevention */
>  XEN_CPUFEATURE(PKU,           6*32+ 3) /*H  Protection Keys for Userspace */
>  XEN_CPUFEATURE(OSPKE,         6*32+ 4) /*!  OS Protection Keys Enable */
> +XEN_CPUFEATURE(AVX512_VBMI2,  6*32+ 6) /*A  addition AVX-512 VBMI Instructions */

"additional"?

> --- a/xen/tools/gen-cpuid.py
> +++ b/xen/tools/gen-cpuid.py
> @@ -255,7 +255,8 @@ def crunch_numbers(state):
>          # top of AVX512F
>          AVX512F: [AVX512DQ, AVX512IFMA, AVX512PF, AVX512ER, AVX512CD,
>                    AVX512BW, AVX512VL, AVX512VBMI, AVX512_4VNNIW,
> -                  AVX512_4FMAPS, AVX512_VPOPCNTDQ],
> +                  AVX512_4FMAPS, AVX512_VPOPCNTDQ, AVX512_VBMI2,
> +                  AVX512_VNNI, AVX512_BITALG],
>      }

This is insufficient afaict: VAES and VPCLMULQDQ ought to be
made dependent upon AVX.

Jan


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Re: [PATCH v4 1/4] x86emul: Support GFNI insns

[Jan Beulich]

>>> On 03.01.18 at 09:26, <yang.zhong@intel.com> wrote:
> @@ -7741,6 +7752,16 @@ x86_emulate(
>          op_bytes = 16;
>          goto simd_0f3a_common;
>  
> +    case X86EMUL_OPC_66(0x0f3a, 0xce):     /* gf2p8affineqb $imm8,xmm/m128,xmm,xmm */
> +    case X86EMUL_OPC_VEX_66(0x0f3a, 0xce): /* vgf2p8affineqb $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
> +    case X86EMUL_OPC_66(0x0f3a, 0xcf):     /* gf2p8affineinvqb $imm8,xmm/m128,xmm,xmm */
> +    case X86EMUL_OPC_VEX_66(0x0f3a, 0xcf): /* vgf2p8affineinvqb $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
> +        host_and_vcpu_must_have(gfni);
> +        if ( vex.opcx == vex_none )
> +            goto simd_0f3a_common;
> +        generate_exception_if(vex.w, EXC_UD);

The documentation says .W1, but I of course don't know whether
you meanwhile tested your code (you still don't add a test case)
and the doc is wrong, or this needs to be !vex.w.

Jan


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Re: [PATCH v4 4/4] x86/cpuid: Enable new SSE/AVX/AVX512 cpu features

[Yang Zhong]

On Wed, Jan 03, 2018 at 01:46:09AM -0700, Jan Beulich wrote:

> > --- a/xen/include/public/arch-x86/cpufeatureset.h
> > +++ b/xen/include/public/arch-x86/cpufeatureset.h
> > @@ -228,6 +228,12 @@ XEN_CPUFEATURE(AVX512VBMI,    6*32+ 1) /*A  AVX-512 Vector Byte Manipulation Ins
> >  XEN_CPUFEATURE(UMIP,          6*32+ 2) /*S  User Mode Instruction Prevention */
> >  XEN_CPUFEATURE(PKU,           6*32+ 3) /*H  Protection Keys for Userspace */
> >  XEN_CPUFEATURE(OSPKE,         6*32+ 4) /*!  OS Protection Keys Enable */
> > +XEN_CPUFEATURE(AVX512_VBMI2,  6*32+ 6) /*A  addition AVX-512 VBMI Instructions */
> 
> "additional"?
  Jan, i will change "addition" to "additional", thanks! Yang.
 
> > --- a/xen/tools/gen-cpuid.py
> > +++ b/xen/tools/gen-cpuid.py
> > @@ -255,7 +255,8 @@ def crunch_numbers(state):
> >          # top of AVX512F
> >          AVX512F: [AVX512DQ, AVX512IFMA, AVX512PF, AVX512ER, AVX512CD,
> >                    AVX512BW, AVX512VL, AVX512VBMI, AVX512_4VNNIW,
> > -                  AVX512_4FMAPS, AVX512_VPOPCNTDQ],
> > +                  AVX512_4FMAPS, AVX512_VPOPCNTDQ, AVX512_VBMI2,
> > +                  AVX512_VNNI, AVX512_BITALG],
> >      }
> 
> This is insufficient afaict: VAES and VPCLMULQDQ ought to be
> made dependent upon AVX.

  Thanks Jan, i will do below changes for this.  Yang.

-        AVX: [FMA, FMA4, F16C, AVX2, XOP],
+        AVX: [FMA, FMA4, F16C, AVX2, XOP, VAES, VPCLMULQDQ],

> 
> Jan

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Re: [PATCH v4 0/4] x86/cpuid: enable new cpu features

[Yang Zhong]

On Wed, Jan 03, 2018 at 01:38:13AM -0700, Jan Beulich wrote:
> >>> On 03.01.18 at 09:26, <yang.zhong@intel.com> wrote:
> > The new cpu features in intel icelake: AVX512VBMI2/GFNI/VAES/
> > AVX512VNNI/AVX512BITALG/VPCLMULQDQ.
> 
> Could you please play by patch submission rules: They are to be
> sent _to_ the list, with maintainers (and perhaps other interested
> parties) _cc_-ed.
> 
  Thanks Jan, i will be care of this in next version. thanks! Yang. 

> Jan

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Re: [PATCH v4 1/4] x86emul: Support GFNI insns

[Yang Zhong]

On Wed, Jan 03, 2018 at 10:00:51AM -0700, Jan Beulich wrote:
> >>> On 03.01.18 at 09:26, <yang.zhong@intel.com> wrote:
> > @@ -7741,6 +7752,16 @@ x86_emulate(
> >          op_bytes = 16;
> >          goto simd_0f3a_common;
> >  
> > +    case X86EMUL_OPC_66(0x0f3a, 0xce):     /* gf2p8affineqb $imm8,xmm/m128,xmm,xmm */
> > +    case X86EMUL_OPC_VEX_66(0x0f3a, 0xce): /* vgf2p8affineqb $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
> > +    case X86EMUL_OPC_66(0x0f3a, 0xcf):     /* gf2p8affineinvqb $imm8,xmm/m128,xmm,xmm */
> > +    case X86EMUL_OPC_VEX_66(0x0f3a, 0xcf): /* vgf2p8affineinvqb $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
> > +        host_and_vcpu_must_have(gfni);
> > +        if ( vex.opcx == vex_none )
> > +            goto simd_0f3a_common;
> > +        generate_exception_if(vex.w, EXC_UD);
> 
> The documentation says .W1, but I of course don't know whether
> you meanwhile tested your code (you still don't add a test case)
> and the doc is wrong, or this needs to be !vex.w.
>
  Thanks Jan pointed out this issue, you are right!

  vgf2p8affineqb and vgf2p8affineinvqb are W1, but vgf2p8mulb is W0.

  So, for vgf2p8affineqb and vgf2p8affineinvqb, !vex.w is right.
  for vgf2p8mulb vex.w is right.

  As for the test case for those insns, i am writing those related test cases in tools/tests/x86_emulator.

  How many test cases will you need ? One test case for one CPU feature(vaes,gfni and vpclmulqdq)？

  Another issue is would you please share your test guide? i will verify those insns on my simics enviornment.

  thanks a lot!

  Yang
 
> Jan

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Re: [PATCH v4 1/4] x86emul: Support GFNI insns

[Jan Beulich]

>>> On 04.01.18 at 10:20, <yang.zhong@intel.com> wrote:
>   As for the test case for those insns, i am writing those related test 
> cases in tools/tests/x86_emulator.
> 
>   How many test cases will you need ? One test case for one CPU 
> feature(vaes,gfni and vpclmulqdq)？

My rule of thumb is that I'd like to have tests for everything that isn't
fully matching "default" behavior of insn groups. That includes (but is
not limited to) unusual encoding or unusual memory operand sizes.
Therefore I think VAES and maybe also VPCLMULQDQ don't strictly
need individual tests (I still have on my todo list an entry to create a
blowfish-like test for AES and SHA, but that's independent of what
I'd like you to do), but the unusual .W1 encoding of some of the
GFNI insns certainly warrants one (whether that would be an
individual insn test or a blowfish-like one I'd leave to you). But
please realize that I'm writing this without having looked at the latest
version of the other two patches yet, so my opinion regarding the
former two may change once I get to that.

>   Another issue is would you please share your test guide?

I'm afraid I don't understand "test guide".

Jan

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Re: [PATCH v4 2/4] x86emul: Support vpclmulqdq

[Jan Beulich]

>>> On 03.01.18 at 09:26, <yang.zhong@intel.com> wrote:
> The previous vpclmulqdq only support AVX128.
> Icelake added AVX256 support.

And 512-bit support as well; you only don't add support for the EVEX
encoding forms in your patch.

The patch itself looks fine, but please clarify its testing status.

> @@ -6168,6 +6169,7 @@ x86_emulate(
>      simd_0f_imm8_avx:
>                  host_and_vcpu_must_have(avx);
>              }
> +    simd_0f_imm8_ymm:
>              get_fpu(X86EMUL_FPU_ymm, &fic);
>          }
>          else if ( vex.pfx )

One remark as I see this: Personally I don't see any of this series go
in ahead of my larger emulator series (or at least large parts of it),
considering that it's been pending for much longer. I'm sorry for this
meaning that you also won't be able to report this task as completed
any time soon. Other maintainers may have a different opinion here,
though.

Jan


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Re: [PATCH v4 3/4] x86emul: Support vaes insns

[Jan Beulich]

>>> On 03.01.18 at 09:26, <yang.zhong@intel.com> wrote:
> The previous aes insns only support legacy and AVX128.
> Icelake added AVX256 support.

Same remark here as for the pclmulqdq patch.

> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> ---

Please provide a brief list of changes at this spot in each patch.

> @@ -7336,17 +7337,23 @@ x86_emulate(
>      case X86EMUL_OPC_66(0x0f38, 0xdb):     /* aesimc xmm/m128,xmm */
>      case X86EMUL_OPC_VEX_66(0x0f38, 0xdb): /* vaesimc xmm/m128,xmm */
>      case X86EMUL_OPC_66(0x0f38, 0xdc):     /* aesenc xmm/m128,xmm,xmm */
> -    case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc xmm/m128,xmm,xmm */
> +    case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc {x,y}mm/mem,{x,y}mm,{x,y}mm */
>      case X86EMUL_OPC_66(0x0f38, 0xdd):     /* aesenclast xmm/m128,xmm,xmm */
> -    case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast xmm/m128,xmm,xmm */
> +    case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast {x,y}mm/mem,{x,y}mm,{x,y}mm */
>      case X86EMUL_OPC_66(0x0f38, 0xde):     /* aesdec xmm/m128,xmm,xmm */
> -    case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec xmm/m128,xmm,xmm */
> +    case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec {x,y}mm/mem,{x,y}mm,{x,y}mm */
>      case X86EMUL_OPC_66(0x0f38, 0xdf):     /* aesdeclast xmm/m128,xmm,xmm */
> -    case X86EMUL_OPC_VEX_66(0x0f38, 0xdf): /* vaesdeclast xmm/m128,xmm,xmm */
> +    case X86EMUL_OPC_VEX_66(0x0f38, 0xdf): /* vaesdeclast {x,y}mm/mem,{x,y}mm,{x,y}mm */
> +        if ( vex.l )
> +        {
> +            host_and_vcpu_must_have(vaes);
> +            goto simd_0f_ymm;
> +        }
>          host_and_vcpu_must_have(aesni);
>          if ( vex.opcx == vex_none )
>              goto simd_0f38_common;
> -        /* fall through */
> +        goto simd_0f_avx;
> +
>      case X86EMUL_OPC_VEX_66(0x0f38, 0x41): /* vphminposuw xmm/m128,xmm,xmm */

Hmm, you've reacted to my v3 comments, but you didn't really address
them: VAESIMC still is mishandled with the code above. Note that I didn't
say "remove the fall-through", but instead "move out the block no longer
wanting this fall-through".

Jan


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Re: [PATCH v4 3/4] x86emul: Support vaes insns

[Yang Zhong]

On Thu, Jan 18, 2018 at 07:13:21AM -0700, Jan Beulich wrote:
> >>> On 03.01.18 at 09:26, <yang.zhong@intel.com> wrote:
> > The previous aes insns only support legacy and AVX128.
> > Icelake added AVX256 support.
> 
> Same remark here as for the pclmulqdq patch.
> 
> > Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> > ---
> 
> Please provide a brief list of changes at this spot in each patch.
> 
> > @@ -7336,17 +7337,23 @@ x86_emulate(
> >      case X86EMUL_OPC_66(0x0f38, 0xdb):     /* aesimc xmm/m128,xmm */
> >      case X86EMUL_OPC_VEX_66(0x0f38, 0xdb): /* vaesimc xmm/m128,xmm */
> >      case X86EMUL_OPC_66(0x0f38, 0xdc):     /* aesenc xmm/m128,xmm,xmm */
> > -    case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc xmm/m128,xmm,xmm */
> > +    case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc {x,y}mm/mem,{x,y}mm,{x,y}mm */
> >      case X86EMUL_OPC_66(0x0f38, 0xdd):     /* aesenclast xmm/m128,xmm,xmm */
> > -    case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast xmm/m128,xmm,xmm */
> > +    case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast {x,y}mm/mem,{x,y}mm,{x,y}mm */
> >      case X86EMUL_OPC_66(0x0f38, 0xde):     /* aesdec xmm/m128,xmm,xmm */
> > -    case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec xmm/m128,xmm,xmm */
> > +    case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec {x,y}mm/mem,{x,y}mm,{x,y}mm */
> >      case X86EMUL_OPC_66(0x0f38, 0xdf):     /* aesdeclast xmm/m128,xmm,xmm */
> > -    case X86EMUL_OPC_VEX_66(0x0f38, 0xdf): /* vaesdeclast xmm/m128,xmm,xmm */
> > +    case X86EMUL_OPC_VEX_66(0x0f38, 0xdf): /* vaesdeclast {x,y}mm/mem,{x,y}mm,{x,y}mm */
> > +        if ( vex.l )
> > +        {
> > +            host_and_vcpu_must_have(vaes);
> > +            goto simd_0f_ymm;
> > +        }
> >          host_and_vcpu_must_have(aesni);
> >          if ( vex.opcx == vex_none )
> >              goto simd_0f38_common;
> > -        /* fall through */
> > +        goto simd_0f_avx;
> > +
> >      case X86EMUL_OPC_VEX_66(0x0f38, 0x41): /* vphminposuw xmm/m128,xmm,xmm */
> 
> Hmm, you've reacted to my v3 comments, but you didn't really address
> them: VAESIMC still is mishandled with the code above. Note that I didn't
> say "remove the fall-through", but instead "move out the block no longer
> wanting this fall-through".
> 
> Jan

Hello Jan,

I did below TEMP patch, please help me check whther this patch meet your 
requirements, many thanks!

I moved vaesimc insn before host_and_vcpu_must_have(aesni), this method
can make sure there is not any change for vaesimc. by the way, the fall
through still be kept for avx128.


+#define vcpu_has_vaes()        vcpu_has(         7, ECX,  9, ctxt, ops)
 #define vcpu_has_vpclmulqdq()  vcpu_has(         7, ECX, 10, ctxt, ops)
 #define vcpu_has_rdpid()       vcpu_has(         7, ECX, 22, ctxt, ops)
 #define vcpu_has_clzero()      vcpu_has(0x80000008, EBX,  0, ctxt, ops)
@@ -7334,15 +7335,20 @@ x86_emulate(
         goto simd_0f38_common;

     case X86EMUL_OPC_66(0x0f38, 0xdb):     /* aesimc xmm/m128,xmm */
-    case X86EMUL_OPC_VEX_66(0x0f38, 0xdb): /* vaesimc xmm/m128,xmm */
     case X86EMUL_OPC_66(0x0f38, 0xdc):     /* aesenc xmm/m128,xmm,xmm */
-    case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc xmm/m128,xmm,xmm */
+    case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc {x,y}mm/mem,{x,y}mm,{x,y}mm */
     case X86EMUL_OPC_66(0x0f38, 0xdd):     /* aesenclast xmm/m128,xmm,xmm */
-    case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast xmm/m128,xmm,xmm */
+    case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast {x,y}mm/mem,{x,y}mm,{x,y}mm */
     case X86EMUL_OPC_66(0x0f38, 0xde):     /* aesdec xmm/m128,xmm,xmm */
-    case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec xmm/m128,xmm,xmm */
+    case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec {x,y}mm/mem,{x,y}mm,{x,y}mm */
     case X86EMUL_OPC_66(0x0f38, 0xdf):     /* aesdeclast xmm/m128,xmm,xmm */
-    case X86EMUL_OPC_VEX_66(0x0f38, 0xdf): /* vaesdeclast xmm/m128,xmm,xmm */
+    case X86EMUL_OPC_VEX_66(0x0f38, 0xdf): /* vaesdeclast {x,y}mm/mem,{x,y}mm,{x,y}mm */
+        if ( vex.l )
+        {
+            host_and_vcpu_must_have(vaes);
+            goto simd_0f_ymm;
+        }
+    case X86EMUL_OPC_VEX_66(0x0f38, 0xdb): /* vaesimc xmm/m128,xmm */
         host_and_vcpu_must_have(aesni);
         if ( vex.opcx == vex_none )
             goto simd_0f38_common;


Regards,

Yang



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Re: [PATCH v4 3/4] x86emul: Support vaes insns

[Jan Beulich]

>>> On 23.01.18 at 13:56, <yang.zhong@intel.com> wrote:
> I did below TEMP patch, please help me check whther this patch meet your 
> requirements, many thanks!

Looks reasonable at the first glance, provided you add a proper
fall-through annotation to the new fall-through.

Jan


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