[RFC 00/15] Selectable platform support

[RFC 00/15] Selectable platform support

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

For Joonas basically. :)

Rough goal - add Kconfig options to turn off supported platforms and count on
compiler DCE to make the driver smaller.

Tested as so much that it boots and renders on Skylake with all platforms/gens
older than Gen8 turned off.

   text    data     bss     dec     hex filename
1502847   54223    2888 1559958  17cd96 i915.ko.original
1375647   51939    2888 1430474  15d3ca i915.ko.gen8+

So only ~124kiB saving. Or ~8.5%. Perhaps once GCC LTO support lands it would be
better than this?

Starts with smaller patches to show the idea step by step on Gen2, then proceeds
in larger chunks, to finish with some invasive Coccinelle works to enable the
last few kilo-bytes of savings.

Let the flames begin! :)

Tvrtko Ursulin (15):
  drm/i915: Make I830 platform support optional
  drm/i915: Make I845G platform support optional
  drm/i915: Make I85X platform support optional
  drm/i915: Make I865G platform support optional
  drm/i915: Make GEN2 support optional
  drm/i915: Make Gen3 platforms support optional
  drm/i915: Make Gen4 platforms support optional
  drm/i915: Make Ironlake/Gen5 platforms support optional
  drm/i915: Make Sandybridge/Gen6 platforms support optional
  drm/i915: Make Gen7/7.5 platform support optional
  drm/i915: Use INTEL_GEN everywhere
  drm/i915: Favour IS_GENx
  drm/i915: IS_GEN range helpers
  drm/i915: Use new IS_GEN range helpers
  drm/i915: Replace some negative Gen checks

 drivers/gpu/drm/i915/Kconfig                       |   5 +
 drivers/gpu/drm/i915/Kconfig.platforms             | 169 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_debugfs.c                |  86 ++++-----
 drivers/gpu/drm/i915/i915_drv.c                    |  16 +-
 drivers/gpu/drm/i915/i915_drv.h                    | 133 ++++++++++----
 drivers/gpu/drm/i915/i915_gem.c                    |  18 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c         |   2 +-
 drivers/gpu/drm/i915/i915_gem_fence_reg.c          |   4 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c                |  30 ++--
 drivers/gpu/drm/i915/i915_gem_request.c            |   2 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c             |   8 +-
 drivers/gpu/drm/i915/i915_gem_tiling.c             |   8 +-
 drivers/gpu/drm/i915/i915_gpu_error.c              |  40 ++---
 drivers/gpu/drm/i915/i915_irq.c                    |  58 +++---
 drivers/gpu/drm/i915/i915_pci.c                    |  84 ++++++++-
 drivers/gpu/drm/i915/i915_perf.c                   |   2 +-
 drivers/gpu/drm/i915/i915_pmu.c                    |   6 +-
 drivers/gpu/drm/i915/i915_reg.h                    |   4 +-
 drivers/gpu/drm/i915/i915_suspend.c                |  12 +-
 drivers/gpu/drm/i915/i915_sysfs.c                  |   2 +-
 drivers/gpu/drm/i915/intel_atomic_plane.c          |   2 +-
 drivers/gpu/drm/i915/intel_audio.c                 |   2 +-
 drivers/gpu/drm/i915/intel_bios.c                  |   2 +-
 drivers/gpu/drm/i915/intel_cdclk.c                 |   8 +-
 drivers/gpu/drm/i915/intel_color.c                 |   2 +-
 drivers/gpu/drm/i915/intel_crt.c                   |   6 +-
 drivers/gpu/drm/i915/intel_ddi.c                   |  10 +-
 drivers/gpu/drm/i915/intel_device_info.c           |  18 +-
 drivers/gpu/drm/i915/intel_display.c               | 194 ++++++++++-----------
 drivers/gpu/drm/i915/intel_dp.c                    |  28 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c              |   4 +-
 drivers/gpu/drm/i915/intel_engine_cs.c             |  22 +--
 drivers/gpu/drm/i915/intel_fbc.c                   |  32 ++--
 drivers/gpu/drm/i915/intel_fifo_underrun.c         |   2 +-
 drivers/gpu/drm/i915/intel_hangcheck.c             |   2 +-
 drivers/gpu/drm/i915/intel_hdcp.c                  |   2 +-
 drivers/gpu/drm/i915/intel_hdmi.c                  |  10 +-
 drivers/gpu/drm/i915/intel_lrc.c                   |   6 +-
 drivers/gpu/drm/i915/intel_lvds.c                  |  10 +-
 drivers/gpu/drm/i915/intel_mocs.c                  |   2 +-
 drivers/gpu/drm/i915/intel_overlay.c               |   2 +-
 drivers/gpu/drm/i915/intel_panel.c                 |  10 +-
 drivers/gpu/drm/i915/intel_pipe_crc.c              |   2 +-
 drivers/gpu/drm/i915/intel_pm.c                    | 106 +++++------
 drivers/gpu/drm/i915/intel_psr.c                   |   6 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c            |  34 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.h            |   4 +-
 drivers/gpu/drm/i915/intel_sdvo.c                  |  14 +-
 drivers/gpu/drm/i915/intel_sprite.c                |  30 ++--
 drivers/gpu/drm/i915/intel_tv.c                    |   2 +-
 drivers/gpu/drm/i915/intel_uncore.c                |  20 +--
 .../gpu/drm/i915/selftests/i915_gem_coherency.c    |   4 +-
 drivers/gpu/drm/i915/selftests/i915_gem_context.c  |   2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_object.c   |  12 +-
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c   |   8 +-
 drivers/gpu/drm/i915/selftests/intel_uncore.c      |   2 +-
 56 files changed, 816 insertions(+), 495 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/Kconfig.platforms

-- 
2.14.1

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[RFC 01/15] drm/i915: Make I830 platform support optional

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Kconfig           | 5 +++++
 drivers/gpu/drm/i915/Kconfig.platforms | 6 ++++++
 drivers/gpu/drm/i915/i915_drv.h        | 5 ++++-
 drivers/gpu/drm/i915/i915_pci.c        | 4 ++++
 4 files changed, 19 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/Kconfig.platforms

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index dfd95889f4b7..1363d05e6ec5 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -131,3 +131,8 @@ depends on DRM_I915
 depends on EXPERT
 source drivers/gpu/drm/i915/Kconfig.debug
 endmenu
+
+menu "Platform support"
+depends on DRM_I915
+source drivers/gpu/drm/i915/Kconfig.platforms
+endmenu
diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
new file mode 100644
index 000000000000..f3949fff21e9
--- /dev/null
+++ b/drivers/gpu/drm/i915/Kconfig.platforms
@@ -0,0 +1,6 @@
+config DRM_I915_PLATFORM_INTEL_I830
+	bool "Intel i830 platform support"
+	default y
+	depends on DRM_I915
+	help
+	  Include support for Intel i830 platform.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 28a2671a26c7..6acd9789b452 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2575,7 +2575,10 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
 
-#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
+#define IS_OPT_PLATFORM(dev_priv, p) \
+	(IS_ENABLED(CONFIG_DRM_I915_PLATFORM_##p) && IS_PLATFORM(dev_priv, p))
+
+#define IS_I830(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I830)
 #define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
 #define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
 #define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4e7a10c89782..81573073dceb 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -74,12 +74,14 @@
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I830
 static const struct intel_device_info intel_i830_info = {
 	GEN2_FEATURES,
 	.platform = INTEL_I830,
 	.is_mobile = 1, .cursor_needs_physical = 1,
 	.num_pipes = 2, /* legal, last one wins */
 };
+#endif
 
 static const struct intel_device_info intel_i845g_info = {
 	GEN2_FEATURES,
@@ -599,7 +601,9 @@ static const struct intel_device_info intel_icelake_11_info = {
  * PCI ID matches, otherwise we'll use the wrong info struct above.
  */
 static const struct pci_device_id pciidlist[] = {
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I830
 	INTEL_I830_IDS(&intel_i830_info),
+#endif
 	INTEL_I845G_IDS(&intel_i845g_info),
 	INTEL_I85X_IDS(&intel_i85x_info),
 	INTEL_I865G_IDS(&intel_i865g_info),
-- 
2.14.1

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Re: [RFC 01/15] drm/i915: Make I830 platform support optional

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-08 13:05:52)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/Kconfig           | 5 +++++
>  drivers/gpu/drm/i915/Kconfig.platforms | 6 ++++++
>  drivers/gpu/drm/i915/i915_drv.h        | 5 ++++-
>  drivers/gpu/drm/i915/i915_pci.c        | 4 ++++
>  4 files changed, 19 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/i915/Kconfig.platforms
> 
> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> index dfd95889f4b7..1363d05e6ec5 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -131,3 +131,8 @@ depends on DRM_I915
>  depends on EXPERT
>  source drivers/gpu/drm/i915/Kconfig.debug
>  endmenu
> +
> +menu "Platform support"
> +depends on DRM_I915
> +source drivers/gpu/drm/i915/Kconfig.platforms
> +endmenu
> diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
> new file mode 100644
> index 000000000000..f3949fff21e9
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/Kconfig.platforms
> @@ -0,0 +1,6 @@
> +config DRM_I915_PLATFORM_INTEL_I830
> +       bool "Intel i830 platform support"
> +       default y
> +       depends on DRM_I915
> +       help
> +         Include support for Intel i830 platform.
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 28a2671a26c7..6acd9789b452 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2575,7 +2575,10 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
>  
> -#define IS_I830(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I830)
> +#define IS_OPT_PLATFORM(dev_priv, p) \
> +       (IS_ENABLED(CONFIG_DRM_I915_PLATFORM_##p) && IS_PLATFORM(dev_priv, p))
> +
> +#define IS_I830(dev_priv)      IS_OPT_PLATFORM(dev_priv, INTEL_I830)
>  #define IS_I845G(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I845G)
>  #define IS_I85X(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I85X)
>  #define IS_I865G(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I865G)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 4e7a10c89782..81573073dceb 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -74,12 +74,14 @@
>         GEN_DEFAULT_PAGE_SIZES, \
>         CURSOR_OFFSETS
>  
> +#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I830

Be modern throughout, #if IS_ENABLED?

>  static const struct intel_device_info intel_i830_info = {
>         GEN2_FEATURES,
>         .platform = INTEL_I830,
>         .is_mobile = 1, .cursor_needs_physical = 1,
>         .num_pipes = 2, /* legal, last one wins */
>  };
> +#endif
>  
>  static const struct intel_device_info intel_i845g_info = {
>         GEN2_FEATURES,
> @@ -599,7 +601,9 @@ static const struct intel_device_info intel_icelake_11_info = {
>   * PCI ID matches, otherwise we'll use the wrong info struct above.
>   */
>  static const struct pci_device_id pciidlist[] = {
> +#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I830
>         INTEL_I830_IDS(&intel_i830_info),
> +#endif

This is exactly what I had in mind for the first draft. I was also
wondering how easy is it for us to create .section.platform. (Modules
within modules)
-Chris
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Re: [RFC 01/15] drm/i915: Make I830 platform support optional

[Jani Nikula]

On Thu, 08 Feb 2018, Tvrtko Ursulin <tursulin@ursulin.net> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/Kconfig           | 5 +++++
>  drivers/gpu/drm/i915/Kconfig.platforms | 6 ++++++
>  drivers/gpu/drm/i915/i915_drv.h        | 5 ++++-
>  drivers/gpu/drm/i915/i915_pci.c        | 4 ++++
>  4 files changed, 19 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/i915/Kconfig.platforms
>
> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> index dfd95889f4b7..1363d05e6ec5 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -131,3 +131,8 @@ depends on DRM_I915
>  depends on EXPERT
>  source drivers/gpu/drm/i915/Kconfig.debug
>  endmenu
> +
> +menu "Platform support"
> +depends on DRM_I915
> +source drivers/gpu/drm/i915/Kconfig.platforms
> +endmenu
> diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
> new file mode 100644
> index 000000000000..f3949fff21e9
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/Kconfig.platforms
> @@ -0,0 +1,6 @@
> +config DRM_I915_PLATFORM_INTEL_I830
> +	bool "Intel i830 platform support"
> +	default y
> +	depends on DRM_I915
> +	help
> +	  Include support for Intel i830 platform.
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 28a2671a26c7..6acd9789b452 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2575,7 +2575,10 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
>  
> -#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
> +#define IS_OPT_PLATFORM(dev_priv, p) \
> +	(IS_ENABLED(CONFIG_DRM_I915_PLATFORM_##p) && IS_PLATFORM(dev_priv, p))
> +
> +#define IS_I830(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I830)
>  #define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
>  #define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
>  #define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 4e7a10c89782..81573073dceb 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -74,12 +74,14 @@
>  	GEN_DEFAULT_PAGE_SIZES, \
>  	CURSOR_OFFSETS
>  
> +#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I830
>  static const struct intel_device_info intel_i830_info = {
>  	GEN2_FEATURES,
>  	.platform = INTEL_I830,
>  	.is_mobile = 1, .cursor_needs_physical = 1,
>  	.num_pipes = 2, /* legal, last one wins */
>  };
> +#endif

Is the compiler not smart enough to throw the device info away without
the #ifdefs? You're removing the only reference to it below after
all. Ditto throughout the series.

BR,
Jani.

>  
>  static const struct intel_device_info intel_i845g_info = {
>  	GEN2_FEATURES,
> @@ -599,7 +601,9 @@ static const struct intel_device_info intel_icelake_11_info = {
>   * PCI ID matches, otherwise we'll use the wrong info struct above.
>   */
>  static const struct pci_device_id pciidlist[] = {
> +#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I830
>  	INTEL_I830_IDS(&intel_i830_info),
> +#endif
>  	INTEL_I845G_IDS(&intel_i845g_info),
>  	INTEL_I85X_IDS(&intel_i85x_info),
>  	INTEL_I865G_IDS(&intel_i865g_info),

-- 
Jani Nikula, Intel Open Source Technology Center
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[RFC 02/15] drm/i915: Make I845G platform support optional

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.platforms | 7 +++++++
 drivers/gpu/drm/i915/i915_drv.h        | 2 +-
 drivers/gpu/drm/i915/i915_pci.c        | 4 ++++
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
index f3949fff21e9..cf06ed3b0727 100644
--- a/drivers/gpu/drm/i915/Kconfig.platforms
+++ b/drivers/gpu/drm/i915/Kconfig.platforms
@@ -4,3 +4,10 @@ config DRM_I915_PLATFORM_INTEL_I830
 	depends on DRM_I915
 	help
 	  Include support for Intel i830 platform.
+
+config DRM_I915_PLATFORM_INTEL_I845G
+	bool "Intel i845G platform support"
+	default y
+	depends on DRM_I915
+	help
+	  Include support for Intel i845G platform.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6acd9789b452..ea7a23044e99 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2579,7 +2579,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 	(IS_ENABLED(CONFIG_DRM_I915_PLATFORM_##p) && IS_PLATFORM(dev_priv, p))
 
 #define IS_I830(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I830)
-#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
+#define IS_I845G(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I845G)
 #define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
 #define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
 #define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 81573073dceb..d98c35d2ff9d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -83,10 +83,12 @@ static const struct intel_device_info intel_i830_info = {
 };
 #endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I845G
 static const struct intel_device_info intel_i845g_info = {
 	GEN2_FEATURES,
 	.platform = INTEL_I845G,
 };
+#endif
 
 static const struct intel_device_info intel_i85x_info = {
 	GEN2_FEATURES,
@@ -604,7 +606,9 @@ static const struct pci_device_id pciidlist[] = {
 #ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I830
 	INTEL_I830_IDS(&intel_i830_info),
 #endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I845G
 	INTEL_I845G_IDS(&intel_i845g_info),
+#endif
 	INTEL_I85X_IDS(&intel_i85x_info),
 	INTEL_I865G_IDS(&intel_i865g_info),
 	INTEL_I915G_IDS(&intel_i915g_info),
-- 
2.14.1

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[RFC 03/15] drm/i915: Make I85X platform support optional

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.platforms | 7 +++++++
 drivers/gpu/drm/i915/i915_drv.h        | 2 +-
 drivers/gpu/drm/i915/i915_pci.c        | 4 ++++
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
index cf06ed3b0727..ab5ad0eaf4e7 100644
--- a/drivers/gpu/drm/i915/Kconfig.platforms
+++ b/drivers/gpu/drm/i915/Kconfig.platforms
@@ -11,3 +11,10 @@ config DRM_I915_PLATFORM_INTEL_I845G
 	depends on DRM_I915
 	help
 	  Include support for Intel i845G platform.
+
+config DRM_I915_PLATFORM_INTEL_I85X
+	bool "Intel i85X platform support"
+	default y
+	depends on DRM_I915
+	help
+	  Include support for Intel i85X platforms.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea7a23044e99..f7bef161a6a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2580,7 +2580,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define IS_I830(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I830)
 #define IS_I845G(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I845G)
-#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
+#define IS_I85X(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I85X)
 #define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
 #define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
 #define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d98c35d2ff9d..47aeaf817b8c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -90,6 +90,7 @@ static const struct intel_device_info intel_i845g_info = {
 };
 #endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I85X
 static const struct intel_device_info intel_i85x_info = {
 	GEN2_FEATURES,
 	.platform = INTEL_I85X, .is_mobile = 1,
@@ -97,6 +98,7 @@ static const struct intel_device_info intel_i85x_info = {
 	.cursor_needs_physical = 1,
 	.has_fbc = 1,
 };
+#endif
 
 static const struct intel_device_info intel_i865g_info = {
 	GEN2_FEATURES,
@@ -609,7 +611,9 @@ static const struct pci_device_id pciidlist[] = {
 #ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I845G
 	INTEL_I845G_IDS(&intel_i845g_info),
 #endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I85X
 	INTEL_I85X_IDS(&intel_i85x_info),
+#endif
 	INTEL_I865G_IDS(&intel_i865g_info),
 	INTEL_I915G_IDS(&intel_i915g_info),
 	INTEL_I915GM_IDS(&intel_i915gm_info),
-- 
2.14.1

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[RFC 04/15] drm/i915: Make I865G platform support optional

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.platforms | 7 +++++++
 drivers/gpu/drm/i915/i915_drv.h        | 2 +-
 drivers/gpu/drm/i915/i915_pci.c        | 4 ++++
 3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
index ab5ad0eaf4e7..46b78425e6da 100644
--- a/drivers/gpu/drm/i915/Kconfig.platforms
+++ b/drivers/gpu/drm/i915/Kconfig.platforms
@@ -18,3 +18,10 @@ config DRM_I915_PLATFORM_INTEL_I85X
 	depends on DRM_I915
 	help
 	  Include support for Intel i85X platforms.
+
+config DRM_I915_PLATFORM_INTEL_I865G
+	bool "Intel i865G platform support"
+	default y
+	depends on DRM_I915
+	help
+	  Include support for Intel i865G platform.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f7bef161a6a0..f52e4a4aac9c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2581,7 +2581,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_I830(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I830)
 #define IS_I845G(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I845G)
 #define IS_I85X(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I85X)
-#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
+#define IS_I865G(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I865G)
 #define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
 #define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
 #define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 47aeaf817b8c..9f5054c009b6 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -100,10 +100,12 @@ static const struct intel_device_info intel_i85x_info = {
 };
 #endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I865G
 static const struct intel_device_info intel_i865g_info = {
 	GEN2_FEATURES,
 	.platform = INTEL_I865G,
 };
+#endif
 
 #define GEN3_FEATURES \
 	.gen = 3, .num_pipes = 2, \
@@ -614,7 +616,9 @@ static const struct pci_device_id pciidlist[] = {
 #ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I85X
 	INTEL_I85X_IDS(&intel_i85x_info),
 #endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I865G
 	INTEL_I865G_IDS(&intel_i865g_info),
+#endif
 	INTEL_I915G_IDS(&intel_i915g_info),
 	INTEL_I915GM_IDS(&intel_i915gm_info),
 	INTEL_I945G_IDS(&intel_i945g_info),
-- 
2.14.1

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[RFC 05/15] drm/i915: Make GEN2 support optional

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

By adding a hidden Kconfig option selected by all Gen2 platforms, we can
eliminate more code when none of those is selected.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.platforms | 7 +++++++
 drivers/gpu/drm/i915/i915_drv.h        | 4 +++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
index 46b78425e6da..23a44c8eb07b 100644
--- a/drivers/gpu/drm/i915/Kconfig.platforms
+++ b/drivers/gpu/drm/i915/Kconfig.platforms
@@ -1,7 +1,11 @@
+config DRM_I915_GEN2
+	bool
+
 config DRM_I915_PLATFORM_INTEL_I830
 	bool "Intel i830 platform support"
 	default y
 	depends on DRM_I915
+	select DRM_I915_GEN2
 	help
 	  Include support for Intel i830 platform.
 
@@ -9,6 +13,7 @@ config DRM_I915_PLATFORM_INTEL_I845G
 	bool "Intel i845G platform support"
 	default y
 	depends on DRM_I915
+	select DRM_I915_GEN2
 	help
 	  Include support for Intel i845G platform.
 
@@ -16,6 +21,7 @@ config DRM_I915_PLATFORM_INTEL_I85X
 	bool "Intel i85X platform support"
 	default y
 	depends on DRM_I915
+	select DRM_I915_GEN2
 	help
 	  Include support for Intel i85X platforms.
 
@@ -23,5 +29,6 @@ config DRM_I915_PLATFORM_INTEL_I865G
 	bool "Intel i865G platform support"
 	default y
 	depends on DRM_I915
+	select DRM_I915_GEN2
 	help
 	  Include support for Intel i865G platform.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f52e4a4aac9c..f92bd631caba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2714,7 +2714,9 @@ intel_info(const struct drm_i915_private *dev_priv)
  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  * chips, etc.).
  */
-#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
+#define IS_GEN2(dev_priv) \
+	(IS_ENABLED(CONFIG_DRM_I915_GEN2) && \
+	 ((dev_priv)->info.gen_mask & BIT(1)))
 #define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
 #define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
 #define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
-- 
2.14.1

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[RFC 06/15] drm/i915: Make Gen3 platforms support optional

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.platforms | 51 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h        | 22 +++++++++------
 drivers/gpu/drm/i915/i915_pci.c        | 28 +++++++++++++++++--
 3 files changed, 90 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
index 23a44c8eb07b..1fa09884a290 100644
--- a/drivers/gpu/drm/i915/Kconfig.platforms
+++ b/drivers/gpu/drm/i915/Kconfig.platforms
@@ -32,3 +32,54 @@ config DRM_I915_PLATFORM_INTEL_I865G
 	select DRM_I915_GEN2
 	help
 	  Include support for Intel i865G platform.
+
+config DRM_I915_GEN3
+	bool
+
+config DRM_I915_PLATFORM_INTEL_I915G
+	bool "Intel i915G platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN3
+	help
+	  Include support for Intel i915G platform.
+
+config DRM_I915_PLATFORM_INTEL_I915GM
+	bool "Intel i915GM platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN3
+	help
+	  Include support for Intel i915GM platform.
+
+config DRM_I915_PLATFORM_INTEL_I945G
+	bool "Intel i945G platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN3
+	help
+	  Include support for Intel i945G platform.
+
+config DRM_I915_PLATFORM_INTEL_I945GM
+	bool "Intel i945GM platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN3
+	help
+	  Include support for Intel i945GM platform.
+
+config DRM_I915_PLATFORM_INTEL_G33
+	bool "Intel G33 platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN3
+	help
+	  Include support for Intel G33 platform.
+
+config DRM_I915_PLATFORM_INTEL_PINEVIEW
+	bool "Intel Pineview platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN3
+	help
+	  Include support for Intel Pineview platform.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f92bd631caba..ec37f949ba40 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2582,19 +2582,21 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_I845G(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I845G)
 #define IS_I85X(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I85X)
 #define IS_I865G(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I865G)
-#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
-#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
-#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
-#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
+#define IS_I915G(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I915G)
+#define IS_I915GM(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I915GM)
+#define IS_I945G(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I945G)
+#define IS_I945GM(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I945GM)
 #define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
 #define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
 #define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
 #define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
 #define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
-#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
-#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
-#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
-#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
+#define IS_PINEVIEW_G(dev_priv)	(IS_OPT_PLATFORM(dev_priv, INTEL_PINEVIEW) && \
+				(INTEL_DEVID(dev_priv) == 0xa001))
+#define IS_PINEVIEW_M(dev_priv)	(IS_OPT_PLATFORM(dev_priv, INTEL_PINEVIEW) && \
+				(INTEL_DEVID(dev_priv) == 0xa011))
+#define IS_PINEVIEW(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_PINEVIEW)
+#define IS_G33(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_G33)
 #define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
 #define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 #define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
@@ -2717,7 +2719,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN2(dev_priv) \
 	(IS_ENABLED(CONFIG_DRM_I915_GEN2) && \
 	 ((dev_priv)->info.gen_mask & BIT(1)))
-#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
+#define IS_GEN3(dev_priv) \
+	(IS_ENABLED(CONFIG_DRM_I915_GEN3) && \
+	 ((dev_priv)->info.gen_mask & BIT(2)))
 #define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
 #define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
 #define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9f5054c009b6..9b47cba66d3d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -116,6 +116,7 @@ static const struct intel_device_info intel_i865g_info = {
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I915G
 static const struct intel_device_info intel_i915g_info = {
 	GEN3_FEATURES,
 	.platform = INTEL_I915G, .cursor_needs_physical = 1,
@@ -123,7 +124,9 @@ static const struct intel_device_info intel_i915g_info = {
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I915GM
 static const struct intel_device_info intel_i915gm_info = {
 	GEN3_FEATURES,
 	.platform = INTEL_I915GM,
@@ -135,7 +138,9 @@ static const struct intel_device_info intel_i915gm_info = {
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I945G
 static const struct intel_device_info intel_i945g_info = {
 	GEN3_FEATURES,
 	.platform = INTEL_I945G,
@@ -144,7 +149,9 @@ static const struct intel_device_info intel_i945g_info = {
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I945GM
 static const struct intel_device_info intel_i945gm_info = {
 	GEN3_FEATURES,
 	.platform = INTEL_I945GM, .is_mobile = 1,
@@ -155,20 +162,25 @@ static const struct intel_device_info intel_i945gm_info = {
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_G33
 static const struct intel_device_info intel_g33_info = {
 	GEN3_FEATURES,
 	.platform = INTEL_G33,
 	.has_hotplug = 1,
 	.has_overlay = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_PINEVIEW
 static const struct intel_device_info intel_pineview_info = {
 	GEN3_FEATURES,
 	.platform = INTEL_PINEVIEW, .is_mobile = 1,
 	.has_hotplug = 1,
 	.has_overlay = 1,
 };
+#endif
 
 #define GEN4_FEATURES \
 	.gen = 4, .num_pipes = 2, \
@@ -619,16 +631,28 @@ static const struct pci_device_id pciidlist[] = {
 #ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I865G
 	INTEL_I865G_IDS(&intel_i865g_info),
 #endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I915G
 	INTEL_I915G_IDS(&intel_i915g_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I915GM
 	INTEL_I915GM_IDS(&intel_i915gm_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I945G
 	INTEL_I945G_IDS(&intel_i945g_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I945GM
 	INTEL_I945GM_IDS(&intel_i945gm_info),
-	INTEL_I965G_IDS(&intel_i965g_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_G33
 	INTEL_G33_IDS(&intel_g33_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_PINEVIEW
+	INTEL_PINEVIEW_IDS(&intel_pineview_info),
+#endif
+	INTEL_I965G_IDS(&intel_i965g_info),
 	INTEL_I965GM_IDS(&intel_i965gm_info),
 	INTEL_GM45_IDS(&intel_gm45_info),
 	INTEL_G45_IDS(&intel_g45_info),
-	INTEL_PINEVIEW_IDS(&intel_pineview_info),
 	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 	INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
-- 
2.14.1

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[RFC 07/15] drm/i915: Make Gen4 platforms support optional

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.platforms | 35 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h        | 12 +++++++-----
 drivers/gpu/drm/i915/i915_pci.c        | 16 ++++++++++++++++
 3 files changed, 58 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
index 1fa09884a290..559d563e8f2e 100644
--- a/drivers/gpu/drm/i915/Kconfig.platforms
+++ b/drivers/gpu/drm/i915/Kconfig.platforms
@@ -83,3 +83,38 @@ config DRM_I915_PLATFORM_INTEL_PINEVIEW
 	select DRM_I915_GEN3
 	help
 	  Include support for Intel Pineview platform.
+
+config DRM_I915_GEN4
+	bool
+
+config DRM_I915_PLATFORM_INTEL_I965G
+	bool "Intel i965G platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN4
+	help
+	  Include support for Intel i965G platform.
+
+config DRM_I915_PLATFORM_INTEL_I965GM
+	bool "Intel i965GM platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN4
+	help
+	  Include support for Intel i965GM platform.
+
+config DRM_I915_PLATFORM_INTEL_G45
+	bool "Intel G45 platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN4
+	help
+	  Include support for Intel G45 platform.
+
+config DRM_I915_PLATFORM_INTEL_GM45
+	bool "Intel GM45 platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN4
+	help
+	  Include support for Intel GM45 platform.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ec37f949ba40..37b62f8833ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2586,10 +2586,10 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_I915GM(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I915GM)
 #define IS_I945G(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I945G)
 #define IS_I945GM(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I945GM)
-#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
-#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
-#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
-#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
+#define IS_I965G(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I965G)
+#define IS_I965GM(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_I965GM)
+#define IS_G45(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_G45)
+#define IS_GM45(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_GM45)
 #define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
 #define IS_PINEVIEW_G(dev_priv)	(IS_OPT_PLATFORM(dev_priv, INTEL_PINEVIEW) && \
 				(INTEL_DEVID(dev_priv) == 0xa001))
@@ -2722,7 +2722,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN3(dev_priv) \
 	(IS_ENABLED(CONFIG_DRM_I915_GEN3) && \
 	 ((dev_priv)->info.gen_mask & BIT(2)))
-#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
+#define IS_GEN4(dev_priv) \
+	(IS_ENABLED(CONFIG_DRM_I915_GEN4) && \
+	 ((dev_priv)->info.gen_mask & BIT(3)))
 #define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
 #define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
 #define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9b47cba66d3d..20043a75b40f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -192,6 +192,7 @@ static const struct intel_device_info intel_pineview_info = {
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I965G
 static const struct intel_device_info intel_i965g_info = {
 	GEN4_FEATURES,
 	.platform = INTEL_I965G,
@@ -199,7 +200,9 @@ static const struct intel_device_info intel_i965g_info = {
 	.hws_needs_physical = 1,
 	.has_snoop = false,
 };
+#endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I965GM
 static const struct intel_device_info intel_i965gm_info = {
 	GEN4_FEATURES,
 	.platform = INTEL_I965GM,
@@ -209,13 +212,17 @@ static const struct intel_device_info intel_i965gm_info = {
 	.hws_needs_physical = 1,
 	.has_snoop = false,
 };
+#endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_G45
 static const struct intel_device_info intel_g45_info = {
 	GEN4_FEATURES,
 	.platform = INTEL_G45,
 	.ring_mask = RENDER_RING | BSD_RING,
 };
+#endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_GM45
 static const struct intel_device_info intel_gm45_info = {
 	GEN4_FEATURES,
 	.platform = INTEL_GM45,
@@ -223,6 +230,7 @@ static const struct intel_device_info intel_gm45_info = {
 	.supports_tv = 1,
 	.ring_mask = RENDER_RING | BSD_RING,
 };
+#endif
 
 #define GEN5_FEATURES \
 	.gen = 5, .num_pipes = 2, \
@@ -649,10 +657,18 @@ static const struct pci_device_id pciidlist[] = {
 #ifdef CONFIG_DRM_I915_PLATFORM_INTEL_PINEVIEW
 	INTEL_PINEVIEW_IDS(&intel_pineview_info),
 #endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I965G
 	INTEL_I965G_IDS(&intel_i965g_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_I965GM
 	INTEL_I965GM_IDS(&intel_i965gm_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_GM45
 	INTEL_GM45_IDS(&intel_gm45_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_G45
 	INTEL_G45_IDS(&intel_g45_info),
+#endif
 	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 	INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
-- 
2.14.1

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[RFC 08/15] drm/i915: Make Ironlake/Gen5 platforms support optional

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.platforms | 11 +++++++++++
 drivers/gpu/drm/i915/i915_drv.h        |  7 +++++--
 drivers/gpu/drm/i915/i915_pci.c        |  4 ++++
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
index 559d563e8f2e..ade0520a1559 100644
--- a/drivers/gpu/drm/i915/Kconfig.platforms
+++ b/drivers/gpu/drm/i915/Kconfig.platforms
@@ -118,3 +118,14 @@ config DRM_I915_PLATFORM_INTEL_GM45
 	select DRM_I915_GEN4
 	help
 	  Include support for Intel GM45 platform.
+
+config DRM_I915_GEN5
+	bool
+
+config DRM_I915_PLATFORM_INTEL_IRONLAKE
+	bool "Intel Ironlake platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN5
+	help
+	  Include support for Intel Ironlake platforms.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 37b62f8833ba..3c8970a83f51 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2597,7 +2597,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 				(INTEL_DEVID(dev_priv) == 0xa011))
 #define IS_PINEVIEW(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_PINEVIEW)
 #define IS_G33(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_G33)
-#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
+#define IS_IRONLAKE_M(dev_priv)	(IS_OPT_PLATFORM(dev_priv, INTEL_IRONLAKE) && \
+				 (INTEL_DEVID(dev_priv) == 0x0046))
 #define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 #define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
 				 (dev_priv)->info.gt == 1)
@@ -2725,7 +2726,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN4(dev_priv) \
 	(IS_ENABLED(CONFIG_DRM_I915_GEN4) && \
 	 ((dev_priv)->info.gen_mask & BIT(3)))
-#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
+#define IS_GEN5(dev_priv) \
+	(IS_ENABLED(CONFIG_DRM_I915_GEN5) && \
+	 ((dev_priv)->info.gen_mask & BIT(4)))
 #define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
 #define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
 #define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 20043a75b40f..dbc580f05678 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -243,6 +243,7 @@ static const struct intel_device_info intel_gm45_info = {
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_IRONLAKE
 static const struct intel_device_info intel_ironlake_d_info = {
 	GEN5_FEATURES,
 	.platform = INTEL_IRONLAKE,
@@ -253,6 +254,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.platform = INTEL_IRONLAKE,
 	.is_mobile = 1, .has_fbc = 1,
 };
+#endif
 
 #define GEN6_FEATURES \
 	.gen = 6, .num_pipes = 2, \
@@ -669,8 +671,10 @@ static const struct pci_device_id pciidlist[] = {
 #ifdef CONFIG_DRM_I915_PLATFORM_INTEL_G45
 	INTEL_G45_IDS(&intel_g45_info),
 #endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_IRONLAKE
 	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
+#endif
 	INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 	INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 	INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
-- 
2.14.1

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[RFC 09/15] drm/i915: Make Sandybridge/Gen6 platforms support optional

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.platforms | 12 ++++++++++++
 drivers/gpu/drm/i915/i915_drv.h        |  4 +++-
 drivers/gpu/drm/i915/i915_pci.c        |  6 ++++++
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
index ade0520a1559..1302eb3989be 100644
--- a/drivers/gpu/drm/i915/Kconfig.platforms
+++ b/drivers/gpu/drm/i915/Kconfig.platforms
@@ -129,3 +129,15 @@ config DRM_I915_PLATFORM_INTEL_IRONLAKE
 	select DRM_I915_GEN5
 	help
 	  Include support for Intel Ironlake platforms.
+
+config DRM_I915_GEN6
+	bool
+
+config DRM_I915_PLATFORM_INTEL_SANDYBRIDGE
+	bool "Intel Sandybridge platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN6
+	help
+	  Include support for Intel Sandybridge platforms.
+
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3c8970a83f51..311ddb8009b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2729,7 +2729,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN5(dev_priv) \
 	(IS_ENABLED(CONFIG_DRM_I915_GEN5) && \
 	 ((dev_priv)->info.gen_mask & BIT(4)))
-#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
+#define IS_GEN6(dev_priv) \
+	(IS_ENABLED(CONFIG_DRM_I915_GEN6) && \
+	 ((dev_priv)->info.gen_mask & BIT(5)))
 #define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
 #define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
 #define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index dbc580f05678..8a7399787f4b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -273,6 +273,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	GEN6_FEATURES, \
 	.platform = INTEL_SANDYBRIDGE
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_SANDYBRIDGE
 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
 	SNB_D_PLATFORM,
 	.gt = 1,
@@ -282,6 +283,7 @@ static const struct intel_device_info intel_sandybridge_d_gt2_info = {
 	SNB_D_PLATFORM,
 	.gt = 2,
 };
+#endif
 
 #define SNB_M_PLATFORM \
 	GEN6_FEATURES, \
@@ -289,6 +291,7 @@ static const struct intel_device_info intel_sandybridge_d_gt2_info = {
 	.is_mobile = 1
 
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_SANDYBRIDGE
 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
 	SNB_M_PLATFORM,
 	.gt = 1,
@@ -298,6 +301,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	SNB_M_PLATFORM,
 	.gt = 2,
 };
+#endif
 
 #define GEN7_FEATURES  \
 	.gen = 7, .num_pipes = 3, \
@@ -675,10 +679,12 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 #endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_SANDYBRIDGE
 	INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 	INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 	INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 	INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
+#endif
 	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 	INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 	INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
-- 
2.14.1

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[RFC 10/15] drm/i915: Make Gen7/7.5 platform support optional

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.platforms | 26 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h        | 10 ++++++----
 drivers/gpu/drm/i915/i915_pci.c        | 14 ++++++++++++++
 3 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
index 1302eb3989be..1fe95996879a 100644
--- a/drivers/gpu/drm/i915/Kconfig.platforms
+++ b/drivers/gpu/drm/i915/Kconfig.platforms
@@ -141,3 +141,29 @@ config DRM_I915_PLATFORM_INTEL_SANDYBRIDGE
 	help
 	  Include support for Intel Sandybridge platforms.
 
+config DRM_I915_GEN7
+	bool
+
+config DRM_I915_PLATFORM_INTEL_IVYBRIDGE
+	bool "Intel Ivybridge platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN7
+	help
+	  Include support for Intel Ivybridge platforms.
+
+config DRM_I915_PLATFORM_INTEL_VALLEYVIEW
+	bool "Intel Valleyview platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN7
+	help
+	  Include support for Intel Valleyview platforms.
+
+config DRM_I915_PLATFORM_INTEL_HASWELL
+	bool "Intel Haswell platform support"
+	default y
+	depends on DRM_I915
+	select DRM_I915_GEN7
+	help
+	  Include support for Intel Haswell platforms.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 311ddb8009b4..9025658bada7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2599,12 +2599,12 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_G33(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_G33)
 #define IS_IRONLAKE_M(dev_priv)	(IS_OPT_PLATFORM(dev_priv, INTEL_IRONLAKE) && \
 				 (INTEL_DEVID(dev_priv) == 0x0046))
-#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
+#define IS_IVYBRIDGE(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 #define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
 				 (dev_priv)->info.gt == 1)
-#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
+#define IS_VALLEYVIEW(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
 #define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
-#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
+#define IS_HASWELL(dev_priv)	IS_OPT_PLATFORM(dev_priv, INTEL_HASWELL)
 #define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
 #define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
 #define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
@@ -2732,7 +2732,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN6(dev_priv) \
 	(IS_ENABLED(CONFIG_DRM_I915_GEN6) && \
 	 ((dev_priv)->info.gen_mask & BIT(5)))
-#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
+#define IS_GEN7(dev_priv) \
+	(IS_ENABLED(CONFIG_DRM_I915_GEN7) && \
+	 ((dev_priv)->info.gen_mask & BIT(6)))
 #define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
 #define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
 #define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8a7399787f4b..205a8fc5e8be 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -322,6 +322,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.platform = INTEL_IVYBRIDGE, \
 	.has_l3_dpf = 1
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_IVYBRIDGE
 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
 	IVB_D_PLATFORM,
 	.gt = 1,
@@ -331,6 +332,7 @@ static const struct intel_device_info intel_ivybridge_d_gt2_info = {
 	IVB_D_PLATFORM,
 	.gt = 2,
 };
+#endif
 
 #define IVB_M_PLATFORM \
 	GEN7_FEATURES, \
@@ -338,6 +340,7 @@ static const struct intel_device_info intel_ivybridge_d_gt2_info = {
 	.is_mobile = 1, \
 	.has_l3_dpf = 1
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_IVYBRIDGE
 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
 	IVB_M_PLATFORM,
 	.gt = 1,
@@ -355,7 +358,9 @@ static const struct intel_device_info intel_ivybridge_q_info = {
 	.num_pipes = 0, /* legal, last one wins */
 	.has_l3_dpf = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_VALLEYVIEW
 static const struct intel_device_info intel_valleyview_info = {
 	.platform = INTEL_VALLEYVIEW,
 	.gen = 7,
@@ -375,6 +380,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	GEN_DEFAULT_PIPEOFFSETS,
 	CURSOR_OFFSETS
 };
+#endif
 
 #define G75_FEATURES  \
 	GEN7_FEATURES, \
@@ -392,6 +398,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.platform = INTEL_HASWELL, \
 	.has_l3_dpf = 1
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_HASWELL
 static const struct intel_device_info intel_haswell_gt1_info = {
 	HSW_PLATFORM,
 	.gt = 1,
@@ -406,6 +413,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	HSW_PLATFORM,
 	.gt = 3,
 };
+#endif
 
 #define GEN8_FEATURES \
 	G75_FEATURES, \
@@ -685,15 +693,21 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 	INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
 #endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_IVYBRIDGE
 	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 	INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 	INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
 	INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
 	INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_HASWELL
 	INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
 	INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
 	INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_VALLEYVIEW
 	INTEL_VLV_IDS(&intel_valleyview_info),
+#endif
 	INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
 	INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
 	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
-- 
2.14.1

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[RFC 11/15] drm/i915: Use INTEL_GEN everywhere

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Coccinelle patch:

 @@
 identifier p;
 @@
 -INTEL_INFO(p)->gen
 +INTEL_GEN(p)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c         |  4 ++--
 drivers/gpu/drm/i915/i915_gem_gtt.c     |  2 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c  |  2 +-
 drivers/gpu/drm/i915/intel_audio.c      |  2 +-
 drivers/gpu/drm/i915/intel_bios.c       |  2 +-
 drivers/gpu/drm/i915/intel_cdclk.c      |  2 +-
 drivers/gpu/drm/i915/intel_ddi.c        |  2 +-
 drivers/gpu/drm/i915/intel_display.c    | 12 ++++++------
 drivers/gpu/drm/i915/intel_dp.c         |  4 ++--
 drivers/gpu/drm/i915/intel_lvds.c       |  2 +-
 drivers/gpu/drm/i915/intel_mocs.c       |  2 +-
 drivers/gpu/drm/i915/intel_panel.c      |  2 +-
 drivers/gpu/drm/i915/intel_pm.c         |  8 ++++----
 drivers/gpu/drm/i915/intel_psr.c        |  4 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.c |  2 +-
 drivers/gpu/drm/i915/intel_uncore.c     |  6 +++---
 16 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c1b80cd52f9e..1d5208f24b60 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5420,10 +5420,10 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
 {
 	int i;
 
-	if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
+	if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) &&
 	    !IS_CHERRYVIEW(dev_priv))
 		dev_priv->num_fence_regs = 32;
-	else if (INTEL_INFO(dev_priv)->gen >= 4 ||
+	else if (INTEL_GEN(dev_priv) >= 4 ||
 		 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
 		 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
 		dev_priv->num_fence_regs = 16;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 955ce7bee448..0c0f1affddad 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2109,7 +2109,7 @@ static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
 	ppgtt->base.i915 = dev_priv;
 	ppgtt->base.dma = &dev_priv->drm.pdev->dev;
 
-	if (INTEL_INFO(dev_priv)->gen < 8)
+	if (INTEL_GEN(dev_priv) < 8)
 		return gen6_ppgtt_init(ppgtt);
 	else
 		return gen8_ppgtt_init(ppgtt);
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index d3f222fa6356..f18da9e2be8e 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -356,7 +356,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
 	reserved_base = 0;
 	reserved_size = 0;
 
-	switch (INTEL_INFO(dev_priv)->gen) {
+	switch (INTEL_GEN(dev_priv)) {
 	case 2:
 	case 3:
 		break;
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 522d54fecb53..ff455c724775 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -704,7 +704,7 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
-	} else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
+	} else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
 		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 4e74aa2f16bc..aa4df6548771 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -391,7 +391,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
 static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
 				    bool alternate)
 {
-	switch (INTEL_INFO(dev_priv)->gen) {
+	switch (INTEL_GEN(dev_priv)) {
 	case 2:
 		return alternate ? 66667 : 48000;
 	case 3:
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index ee788d5be5e3..aab6d1538fff 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2233,7 +2233,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 		return max_cdclk_freq;
 	else if (IS_CHERRYVIEW(dev_priv))
 		return max_cdclk_freq*95/100;
-	else if (INTEL_INFO(dev_priv)->gen < 4)
+	else if (INTEL_GEN(dev_priv) < 4)
 		return 2*max_cdclk_freq*90/100;
 	else
 		return max_cdclk_freq*90/100;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cfcd9cb37d5d..8ca376aca8bd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2152,7 +2152,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 
 		I915_WRITE(DPLL_CTRL2, val);
 
-	} else if (INTEL_INFO(dev_priv)->gen < 9) {
+	} else if (INTEL_GEN(dev_priv) < 9) {
 		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 60ba5bb3f34c..0d5207dbfdac 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2029,12 +2029,12 @@ static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_pr
 
 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
 {
-	if (INTEL_INFO(dev_priv)->gen >= 9)
+	if (INTEL_GEN(dev_priv) >= 9)
 		return 256 * 1024;
 	else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
 		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return 128 * 1024;
-	else if (INTEL_INFO(dev_priv)->gen >= 4)
+	else if (INTEL_GEN(dev_priv) >= 4)
 		return 4 * 1024;
 	else
 		return 0;
@@ -6307,7 +6307,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
 	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	/* GDG double wide on either pipe, otherwise pipe A only */
-	return INTEL_INFO(dev_priv)->gen < 4 &&
+	return INTEL_GEN(dev_priv) < 4 &&
 		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
 }
 
@@ -8194,7 +8194,7 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_crtc_state *config = intel_crtc->config;
 
-	if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
+	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
 		u32 val = 0;
 
 		switch (intel_crtc->config->pipe_bpp) {
@@ -13947,7 +13947,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 	 * gen2/3 display engine uses the fence if present,
 	 * so the tiling mode must match the fb modifier exactly.
 	 */
-	if (INTEL_INFO(dev_priv)->gen < 4 &&
+	if (INTEL_GEN(dev_priv) < 4 &&
 	    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
 		DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
 		goto err;
@@ -14162,7 +14162,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
 {
 	intel_init_cdclk_hooks(dev_priv);
 
-	if (INTEL_INFO(dev_priv)->gen >= 9) {
+	if (INTEL_GEN(dev_priv) >= 9) {
 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			skylake_get_initial_plane_config;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f10a14330e7c..abbe1e4e0af5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1467,7 +1467,7 @@ static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
 				    enum port port)
 {
-	if (INTEL_INFO(dev_priv)->gen >= 9)
+	if (INTEL_GEN(dev_priv) >= 9)
 		return skl_aux_ctl_reg(dev_priv, port);
 	else if (HAS_PCH_SPLIT(dev_priv))
 		return ilk_aux_ctl_reg(dev_priv, port);
@@ -1478,7 +1478,7 @@ static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
 				     enum port port, int index)
 {
-	if (INTEL_INFO(dev_priv)->gen >= 9)
+	if (INTEL_GEN(dev_priv) >= 9)
 		return skl_aux_data_reg(dev_priv, port, index);
 	else if (HAS_PCH_SPLIT(dev_priv))
 		return ilk_aux_data_reg(dev_priv, port, index);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index ef80499113ee..4677ac0b10d7 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -189,7 +189,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 	/* Convert from 100ms to 100us units */
 	pps->t4 = val * 1000;
 
-	if (INTEL_INFO(dev_priv)->gen <= 4 &&
+	if (INTEL_GEN(dev_priv) <= 4 &&
 	    pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 		DRM_DEBUG_KMS("Panel power timings uninitialized, "
 			      "setting defaults\n");
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index f4c46b0b8f0a..abb7a8c1e340 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -187,7 +187,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 		table->table = broxton_mocs_table;
 		result = true;
 	} else {
-		WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
+		WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
 			  "Platform that should have a MOCS table does not.\n");
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index e702a6487aa9..78a53c8b1789 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -497,7 +497,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector)
 	u32 val;
 
 	val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
-	if (INTEL_INFO(dev_priv)->gen < 4)
+	if (INTEL_GEN(dev_priv) < 4)
 		val >>= 1;
 
 	if (panel->backlight.combination_mode) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 063c885175e7..7a112d075c24 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6940,7 +6940,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 			 * No floor required for ring frequency on SKL.
 			 */
 			ring_freq = gpu_freq;
-		} else if (INTEL_INFO(dev_priv)->gen >= 8) {
+		} else if (INTEL_GEN(dev_priv) >= 8) {
 			/* max(2 * GT, DDR). NB: GT is 50MHz units */
 			ring_freq = max(min_ring_freq, gpu_freq);
 		} else if (IS_HASWELL(dev_priv)) {
@@ -7551,7 +7551,7 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
 {
 	unsigned long val;
 
-	if (INTEL_INFO(dev_priv)->gen != 5)
+	if (INTEL_GEN(dev_priv) != 5)
 		return 0;
 
 	spin_lock_irq(&mchdev_lock);
@@ -7635,7 +7635,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
 
 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_INFO(dev_priv)->gen != 5)
+	if (INTEL_GEN(dev_priv) != 5)
 		return;
 
 	spin_lock_irq(&mchdev_lock);
@@ -7686,7 +7686,7 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
 {
 	unsigned long val;
 
-	if (INTEL_INFO(dev_priv)->gen != 5)
+	if (INTEL_GEN(dev_priv) != 5)
 		return 0;
 
 	spin_lock_irq(&mchdev_lock);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index e9feffdea899..2ef374f936b9 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -126,7 +126,7 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
 				       enum port port)
 {
-	if (INTEL_INFO(dev_priv)->gen >= 9)
+	if (INTEL_GEN(dev_priv) >= 9)
 		return DP_AUX_CH_CTL(port);
 	else
 		return EDP_PSR_AUX_CTL;
@@ -135,7 +135,7 @@ static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
 					enum port port, int index)
 {
-	if (INTEL_INFO(dev_priv)->gen >= 9)
+	if (INTEL_GEN(dev_priv) >= 9)
 		return DP_AUX_CH_DATA(port, index);
 	else
 		return EDP_PSR_AUX_DATA(index);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f93e4532371a..c91d7106fbcf 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -655,7 +655,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
 	if (IS_GEN(dev_priv, 6, 7))
 		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
-	if (INTEL_INFO(dev_priv)->gen >= 6)
+	if (INTEL_GEN(dev_priv) >= 6)
 		I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 
 	return init_workarounds_ring(engine);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 164dbb8cfa36..73959ae56241 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1874,9 +1874,9 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
 	if (!i915_modparams.reset)
 		return NULL;
 
-	if (INTEL_INFO(dev_priv)->gen >= 8)
+	if (INTEL_GEN(dev_priv) >= 8)
 		return gen8_reset_engines;
-	else if (INTEL_INFO(dev_priv)->gen >= 6)
+	else if (INTEL_GEN(dev_priv) >= 6)
 		return gen6_reset_engines;
 	else if (IS_GEN5(dev_priv))
 		return ironlake_do_reset;
@@ -1884,7 +1884,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
 		return g4x_do_reset;
 	else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
 		return g33_do_reset;
-	else if (INTEL_INFO(dev_priv)->gen >= 3)
+	else if (INTEL_GEN(dev_priv) >= 3)
 		return i915_do_reset;
 	else
 		return NULL;
-- 
2.14.1

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Re: [RFC 11/15] drm/i915: Use INTEL_GEN everywhere

[Jani Nikula]

On Thu, 08 Feb 2018, Tvrtko Ursulin <tursulin@ursulin.net> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Coccinelle patch:
>
>  @@
>  identifier p;
>  @@
>  -INTEL_INFO(p)->gen
>  +INTEL_GEN(p)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

I think you should get this merged outside of this series. Please rename
->gen to ->__gen or something to discourage its direct use while at it.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/i915_gem.c         |  4 ++--
>  drivers/gpu/drm/i915/i915_gem_gtt.c     |  2 +-
>  drivers/gpu/drm/i915/i915_gem_stolen.c  |  2 +-
>  drivers/gpu/drm/i915/intel_audio.c      |  2 +-
>  drivers/gpu/drm/i915/intel_bios.c       |  2 +-
>  drivers/gpu/drm/i915/intel_cdclk.c      |  2 +-
>  drivers/gpu/drm/i915/intel_ddi.c        |  2 +-
>  drivers/gpu/drm/i915/intel_display.c    | 12 ++++++------
>  drivers/gpu/drm/i915/intel_dp.c         |  4 ++--
>  drivers/gpu/drm/i915/intel_lvds.c       |  2 +-
>  drivers/gpu/drm/i915/intel_mocs.c       |  2 +-
>  drivers/gpu/drm/i915/intel_panel.c      |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c         |  8 ++++----
>  drivers/gpu/drm/i915/intel_psr.c        |  4 ++--
>  drivers/gpu/drm/i915/intel_ringbuffer.c |  2 +-
>  drivers/gpu/drm/i915/intel_uncore.c     |  6 +++---
>  16 files changed, 29 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index c1b80cd52f9e..1d5208f24b60 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5420,10 +5420,10 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
>  {
>  	int i;
>  
> -	if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
> +	if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) &&
>  	    !IS_CHERRYVIEW(dev_priv))
>  		dev_priv->num_fence_regs = 32;
> -	else if (INTEL_INFO(dev_priv)->gen >= 4 ||
> +	else if (INTEL_GEN(dev_priv) >= 4 ||
>  		 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
>  		 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
>  		dev_priv->num_fence_regs = 16;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 955ce7bee448..0c0f1affddad 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2109,7 +2109,7 @@ static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
>  	ppgtt->base.i915 = dev_priv;
>  	ppgtt->base.dma = &dev_priv->drm.pdev->dev;
>  
> -	if (INTEL_INFO(dev_priv)->gen < 8)
> +	if (INTEL_GEN(dev_priv) < 8)
>  		return gen6_ppgtt_init(ppgtt);
>  	else
>  		return gen8_ppgtt_init(ppgtt);
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index d3f222fa6356..f18da9e2be8e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -356,7 +356,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
>  	reserved_base = 0;
>  	reserved_size = 0;
>  
> -	switch (INTEL_INFO(dev_priv)->gen) {
> +	switch (INTEL_GEN(dev_priv)) {
>  	case 2:
>  	case 3:
>  		break;
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 522d54fecb53..ff455c724775 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -704,7 +704,7 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
>  		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
> -	} else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
> +	} else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
>  		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
>  		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 4e74aa2f16bc..aa4df6548771 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -391,7 +391,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
>  static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>  				    bool alternate)
>  {
> -	switch (INTEL_INFO(dev_priv)->gen) {
> +	switch (INTEL_GEN(dev_priv)) {
>  	case 2:
>  		return alternate ? 66667 : 48000;
>  	case 3:
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index ee788d5be5e3..aab6d1538fff 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2233,7 +2233,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>  		return max_cdclk_freq;
>  	else if (IS_CHERRYVIEW(dev_priv))
>  		return max_cdclk_freq*95/100;
> -	else if (INTEL_INFO(dev_priv)->gen < 4)
> +	else if (INTEL_GEN(dev_priv) < 4)
>  		return 2*max_cdclk_freq*90/100;
>  	else
>  		return max_cdclk_freq*90/100;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cfcd9cb37d5d..8ca376aca8bd 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2152,7 +2152,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  
>  		I915_WRITE(DPLL_CTRL2, val);
>  
> -	} else if (INTEL_INFO(dev_priv)->gen < 9) {
> +	} else if (INTEL_GEN(dev_priv) < 9) {
>  		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 60ba5bb3f34c..0d5207dbfdac 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2029,12 +2029,12 @@ static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_pr
>  
>  static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_INFO(dev_priv)->gen >= 9)
> +	if (INTEL_GEN(dev_priv) >= 9)
>  		return 256 * 1024;
>  	else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
>  		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return 128 * 1024;
> -	else if (INTEL_INFO(dev_priv)->gen >= 4)
> +	else if (INTEL_GEN(dev_priv) >= 4)
>  		return 4 * 1024;
>  	else
>  		return 0;
> @@ -6307,7 +6307,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
>  	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	/* GDG double wide on either pipe, otherwise pipe A only */
> -	return INTEL_INFO(dev_priv)->gen < 4 &&
> +	return INTEL_GEN(dev_priv) < 4 &&
>  		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
>  }
>  
> @@ -8194,7 +8194,7 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_crtc_state *config = intel_crtc->config;
>  
> -	if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
> +	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
>  		u32 val = 0;
>  
>  		switch (intel_crtc->config->pipe_bpp) {
> @@ -13947,7 +13947,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  	 * gen2/3 display engine uses the fence if present,
>  	 * so the tiling mode must match the fb modifier exactly.
>  	 */
> -	if (INTEL_INFO(dev_priv)->gen < 4 &&
> +	if (INTEL_GEN(dev_priv) < 4 &&
>  	    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
>  		DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
>  		goto err;
> @@ -14162,7 +14162,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>  {
>  	intel_init_cdclk_hooks(dev_priv);
>  
> -	if (INTEL_INFO(dev_priv)->gen >= 9) {
> +	if (INTEL_GEN(dev_priv) >= 9) {
>  		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
>  		dev_priv->display.get_initial_plane_config =
>  			skylake_get_initial_plane_config;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f10a14330e7c..abbe1e4e0af5 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1467,7 +1467,7 @@ static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
>  static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  				    enum port port)
>  {
> -	if (INTEL_INFO(dev_priv)->gen >= 9)
> +	if (INTEL_GEN(dev_priv) >= 9)
>  		return skl_aux_ctl_reg(dev_priv, port);
>  	else if (HAS_PCH_SPLIT(dev_priv))
>  		return ilk_aux_ctl_reg(dev_priv, port);
> @@ -1478,7 +1478,7 @@ static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
>  				     enum port port, int index)
>  {
> -	if (INTEL_INFO(dev_priv)->gen >= 9)
> +	if (INTEL_GEN(dev_priv) >= 9)
>  		return skl_aux_data_reg(dev_priv, port, index);
>  	else if (HAS_PCH_SPLIT(dev_priv))
>  		return ilk_aux_data_reg(dev_priv, port, index);
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index ef80499113ee..4677ac0b10d7 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -189,7 +189,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
>  	/* Convert from 100ms to 100us units */
>  	pps->t4 = val * 1000;
>  
> -	if (INTEL_INFO(dev_priv)->gen <= 4 &&
> +	if (INTEL_GEN(dev_priv) <= 4 &&
>  	    pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
>  		DRM_DEBUG_KMS("Panel power timings uninitialized, "
>  			      "setting defaults\n");
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index f4c46b0b8f0a..abb7a8c1e340 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -187,7 +187,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
>  		table->table = broxton_mocs_table;
>  		result = true;
>  	} else {
> -		WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
> +		WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
>  			  "Platform that should have a MOCS table does not.\n");
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index e702a6487aa9..78a53c8b1789 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -497,7 +497,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector)
>  	u32 val;
>  
>  	val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
> -	if (INTEL_INFO(dev_priv)->gen < 4)
> +	if (INTEL_GEN(dev_priv) < 4)
>  		val >>= 1;
>  
>  	if (panel->backlight.combination_mode) {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 063c885175e7..7a112d075c24 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6940,7 +6940,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
>  			 * No floor required for ring frequency on SKL.
>  			 */
>  			ring_freq = gpu_freq;
> -		} else if (INTEL_INFO(dev_priv)->gen >= 8) {
> +		} else if (INTEL_GEN(dev_priv) >= 8) {
>  			/* max(2 * GT, DDR). NB: GT is 50MHz units */
>  			ring_freq = max(min_ring_freq, gpu_freq);
>  		} else if (IS_HASWELL(dev_priv)) {
> @@ -7551,7 +7551,7 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
>  {
>  	unsigned long val;
>  
> -	if (INTEL_INFO(dev_priv)->gen != 5)
> +	if (INTEL_GEN(dev_priv) != 5)
>  		return 0;
>  
>  	spin_lock_irq(&mchdev_lock);
> @@ -7635,7 +7635,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
>  
>  void i915_update_gfx_val(struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_INFO(dev_priv)->gen != 5)
> +	if (INTEL_GEN(dev_priv) != 5)
>  		return;
>  
>  	spin_lock_irq(&mchdev_lock);
> @@ -7686,7 +7686,7 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
>  {
>  	unsigned long val;
>  
> -	if (INTEL_INFO(dev_priv)->gen != 5)
> +	if (INTEL_GEN(dev_priv) != 5)
>  		return 0;
>  
>  	spin_lock_irq(&mchdev_lock);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index e9feffdea899..2ef374f936b9 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -126,7 +126,7 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
>  static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  				       enum port port)
>  {
> -	if (INTEL_INFO(dev_priv)->gen >= 9)
> +	if (INTEL_GEN(dev_priv) >= 9)
>  		return DP_AUX_CH_CTL(port);
>  	else
>  		return EDP_PSR_AUX_CTL;
> @@ -135,7 +135,7 @@ static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
>  					enum port port, int index)
>  {
> -	if (INTEL_INFO(dev_priv)->gen >= 9)
> +	if (INTEL_GEN(dev_priv) >= 9)
>  		return DP_AUX_CH_DATA(port, index);
>  	else
>  		return EDP_PSR_AUX_DATA(index);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index f93e4532371a..c91d7106fbcf 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -655,7 +655,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
>  	if (IS_GEN(dev_priv, 6, 7))
>  		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>  
> -	if (INTEL_INFO(dev_priv)->gen >= 6)
> +	if (INTEL_GEN(dev_priv) >= 6)
>  		I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
>  
>  	return init_workarounds_ring(engine);
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 164dbb8cfa36..73959ae56241 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1874,9 +1874,9 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
>  	if (!i915_modparams.reset)
>  		return NULL;
>  
> -	if (INTEL_INFO(dev_priv)->gen >= 8)
> +	if (INTEL_GEN(dev_priv) >= 8)
>  		return gen8_reset_engines;
> -	else if (INTEL_INFO(dev_priv)->gen >= 6)
> +	else if (INTEL_GEN(dev_priv) >= 6)
>  		return gen6_reset_engines;
>  	else if (IS_GEN5(dev_priv))
>  		return ironlake_do_reset;
> @@ -1884,7 +1884,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
>  		return g4x_do_reset;
>  	else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
>  		return g33_do_reset;
> -	else if (INTEL_INFO(dev_priv)->gen >= 3)
> +	else if (INTEL_GEN(dev_priv) >= 3)
>  		return i915_do_reset;
>  	else
>  		return NULL;

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] __gen__

[Chris Wilson]

---
 drivers/gpu/drm/i915/i915_drv.c                  |  6 ++---
 drivers/gpu/drm/i915/i915_drv.h                  |  2 +-
 drivers/gpu/drm/i915/i915_pci.c                  | 30 ++++++++++++------------
 drivers/gpu/drm/i915/intel_device_info.c         |  2 +-
 drivers/gpu/drm/i915/intel_device_info.h         |  2 +-
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 +-
 6 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index daa9060bdfcb..35fc3f59fa8b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -901,8 +901,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 		     sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 	device_info->platform_mask = BIT(device_info->platform);
 
-	BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
-	device_info->gen_mask = BIT(device_info->gen - 1);
+	BUG_ON(device_info->__gen__ > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
+	device_info->gen_mask = BIT(device_info->__gen__ - 1);
 
 	spin_lock_init(&dev_priv->irq_lock);
 	spin_lock_init(&dev_priv->gpu_error.lock);
@@ -1334,7 +1334,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 	int ret;
 
 	/* Enable nuclear pageflip on ILK+ */
-	if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
+	if (!i915_modparams.nuclear_pageflip && match_info->__gen__ < 5)
 		driver.driver_features &= ~DRIVER_ATOMIC;
 
 	ret = -ENOMEM;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a3a02acfc345..141acb0a5840 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2542,7 +2542,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define INTEL_INFO(dev_priv)	intel_info((dev_priv))
 
-#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
+#define INTEL_GEN(dev_priv)	((dev_priv)->info.__gen__)
 #define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
 
 #define REVID_FOREVER		0xff
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4e7a10c89782..c94447b1a15a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -63,7 +63,7 @@
 	.page_sizes = I915_GTT_PAGE_SIZE_4K
 
 #define GEN2_FEATURES \
-	.gen = 2, .num_pipes = 1, \
+	.__gen__ = 2, .num_pipes = 1, \
 	.has_overlay = 1, .overlay_needs_physical = 1, \
 	.has_gmch_display = 1, \
 	.hws_needs_physical = 1, \
@@ -100,7 +100,7 @@ static const struct intel_device_info intel_i865g_info = {
 };
 
 #define GEN3_FEATURES \
-	.gen = 3, .num_pipes = 2, \
+	.__gen__ = 3, .num_pipes = 2, \
 	.has_gmch_display = 1, \
 	.ring_mask = RENDER_RING, \
 	.has_snoop = true, \
@@ -163,7 +163,7 @@ static const struct intel_device_info intel_pineview_info = {
 };
 
 #define GEN4_FEATURES \
-	.gen = 4, .num_pipes = 2, \
+	.__gen__ = 4, .num_pipes = 2, \
 	.has_hotplug = 1, \
 	.has_gmch_display = 1, \
 	.ring_mask = RENDER_RING, \
@@ -205,7 +205,7 @@ static const struct intel_device_info intel_gm45_info = {
 };
 
 #define GEN5_FEATURES \
-	.gen = 5, .num_pipes = 2, \
+	.__gen__ = 5, .num_pipes = 2, \
 	.has_hotplug = 1, \
 	.ring_mask = RENDER_RING | BSD_RING, \
 	.has_snoop = true, \
@@ -227,7 +227,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 };
 
 #define GEN6_FEATURES \
-	.gen = 6, .num_pipes = 2, \
+	.__gen__ = 6, .num_pipes = 2, \
 	.has_hotplug = 1, \
 	.has_fbc = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
@@ -270,7 +270,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 };
 
 #define GEN7_FEATURES  \
-	.gen = 7, .num_pipes = 3, \
+	.__gen__ = 7, .num_pipes = 3, \
 	.has_hotplug = 1, \
 	.has_fbc = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
@@ -324,7 +324,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
 
 static const struct intel_device_info intel_valleyview_info = {
 	.platform = INTEL_VALLEYVIEW,
-	.gen = 7,
+	.__gen__ = 7,
 	.is_lp = 1,
 	.num_pipes = 2,
 	.has_psr = 1,
@@ -385,7 +385,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 
 #define BDW_PLATFORM \
 	GEN8_FEATURES, \
-	.gen = 8, \
+	.__gen__ = 8, \
 	.platform = INTEL_BROADWELL
 
 static const struct intel_device_info intel_broadwell_gt1_info = {
@@ -413,7 +413,7 @@ static const struct intel_device_info intel_broadwell_gt3_info = {
 };
 
 static const struct intel_device_info intel_cherryview_info = {
-	.gen = 8, .num_pipes = 3,
+	.__gen__ = 8, .num_pipes = 3,
 	.has_hotplug = 1,
 	.is_lp = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
@@ -452,7 +452,7 @@ static const struct intel_device_info intel_cherryview_info = {
 
 #define SKL_PLATFORM \
 	GEN9_FEATURES, \
-	.gen = 9, \
+	.__gen__ = 9, \
 	.platform = INTEL_SKYLAKE
 
 static const struct intel_device_info intel_skylake_gt1_info = {
@@ -481,7 +481,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 };
 
 #define GEN9_LP_FEATURES \
-	.gen = 9, \
+	.__gen__ = 9, \
 	.is_lp = 1, \
 	.has_hotplug = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
@@ -526,7 +526,7 @@ static const struct intel_device_info intel_geminilake_info = {
 
 #define KBL_PLATFORM \
 	GEN9_FEATURES, \
-	.gen = 9, \
+	.__gen__ = 9, \
 	.platform = INTEL_KABYLAKE
 
 static const struct intel_device_info intel_kabylake_gt1_info = {
@@ -547,7 +547,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
 
 #define CFL_PLATFORM \
 	GEN9_FEATURES, \
-	.gen = 9, \
+	.__gen__ = 9, \
 	.platform = INTEL_COFFEELAKE
 
 static const struct intel_device_info intel_coffeelake_gt1_info = {
@@ -575,13 +575,13 @@ static const struct intel_device_info intel_cannonlake_info = {
 	GEN10_FEATURES,
 	.is_alpha_support = 1,
 	.platform = INTEL_CANNONLAKE,
-	.gen = 10,
+	.__gen__ = 10,
 	.gt = 2,
 };
 
 #define GEN11_FEATURES \
 	GEN10_FEATURES, \
-	.gen = 11, \
+	.__gen__ = 11, \
 	.ddb_size = 2048, \
 	.has_csr = 0
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 298f8996cc54..2e79abff081b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -115,7 +115,7 @@ void intel_device_info_dump(const struct intel_device_info *info,
 		   INTEL_DEVID(dev_priv),
 		   INTEL_REVID(dev_priv),
 		   intel_platform_name(info->platform),
-		   info->gen);
+		   info->__gen__);
 
 	intel_device_info_dump_flags(info, p);
 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 71fdfb0451ef..927bf6c0122f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -129,7 +129,7 @@ struct intel_device_info {
 	u16 device_id;
 	u16 gen_mask;
 
-	u8 gen;
+	u8 __gen__; /* Do not use directly, use INTEL_GEN */
 	u8 gt; /* GT number, 0 if undefined */
 	u8 num_rings;
 	u8 ring_mask; /* Rings supported by the HW */
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 3175db70cc6e..bf2280f28766 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -174,7 +174,7 @@ struct drm_i915_private *mock_gem_device(void)
 	/* Using the global GTT may ask questions about KMS users, so prepare */
 	drm_mode_config_init(&i915->drm);
 
-	mkwrite_device_info(i915)->gen = -1;
+	mkwrite_device_info(i915)->__gen__ = -1;
 
 	mkwrite_device_info(i915)->page_sizes =
 		I915_GTT_PAGE_SIZE_4K |
-- 
2.16.1

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Re: [RFC 11/15] drm/i915: Use INTEL_GEN everywhere

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-08 13:06:02)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Coccinelle patch:
> 
>  @@
>  identifier p;
>  @@
>  -INTEL_INFO(p)->gen
>  +INTEL_GEN(p)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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[RFC 12/15] drm/i915: Favour IS_GENx

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Replace INTEL_GEN equals with IS_GENx for more optimisation opportunities.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
 drivers/gpu/drm/i915/intel_fbc.c         | 2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index a2c16140169f..ae6f5b7b7978 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -483,7 +483,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 	if (INTEL_GEN(dev_priv) >= 10) {
 		for_each_pipe(dev_priv, pipe)
 			info->num_scalers[pipe] = 2;
-	} else if (INTEL_GEN(dev_priv) == 9) {
+	} else if (IS_GEN9(dev_priv)) {
 		info->num_scalers[PIPE_A] = 2;
 		info->num_scalers[PIPE_B] = 2;
 		info->num_scalers[PIPE_C] = 1;
@@ -578,7 +578,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 		cherryview_sseu_info_init(dev_priv);
 	else if (IS_BROADWELL(dev_priv))
 		broadwell_sseu_info_init(dev_priv);
-	else if (INTEL_GEN(dev_priv) == 9)
+	else if (IS_GEN9(dev_priv))
 		gen9_sseu_info_init(dev_priv);
 	else if (INTEL_GEN(dev_priv) >= 10)
 		gen10_sseu_info_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index d7d1ac79c38a..0ad854095c38 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -94,7 +94,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
 	int lines;
 
 	intel_fbc_get_plane_source_size(cache, NULL, &lines);
-	if (INTEL_GEN(dev_priv) == 7)
+	if (IS_GEN7(dev_priv))
 		lines = min(lines, 2048);
 	else if (INTEL_GEN(dev_priv) >= 8)
 		lines = min(lines, 2560);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index a0e7a6c2a57c..6944c75193c3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -85,11 +85,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
 #define I915_MAX_SUBSLICES 3
 
 #define instdone_slice_mask(dev_priv__) \
-	(INTEL_GEN(dev_priv__) == 7 ? \
+	(IS_GEN7(dev_priv__) ? \
 	 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
 
 #define instdone_subslice_mask(dev_priv__) \
-	(INTEL_GEN(dev_priv__) == 7 ? \
+	(IS_GEN7(dev_priv__) ? \
 	 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask)
 
 #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
-- 
2.14.1

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[RFC 13/15] drm/i915: IS_GEN range helpers

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Add IS_GEN_GT(E) and IS_GEN_LT(E) helpers.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 49 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9025658bada7..b66f288bde7d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2740,6 +2740,55 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
 #define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
 
+#define __test_mask(s, e) \
+({ \
+	u16 m__ = (u16)INTEL_GEN_MASK((s), (e)); \
+\
+	m__ &= ~BIT(0); \
+	if (!IS_ENABLED(CONFIG_DRM_I915_GEN2)) \
+		m__ &= ~BIT(1); \
+	if (!IS_ENABLED(CONFIG_DRM_I915_GEN3)) \
+		m__ &= ~BIT(2); \
+	if (!IS_ENABLED(CONFIG_DRM_I915_GEN4)) \
+		m__ &= ~BIT(3); \
+	if (!IS_ENABLED(CONFIG_DRM_I915_GEN5)) \
+		m__ &= ~BIT(4); \
+	if (!IS_ENABLED(CONFIG_DRM_I915_GEN6)) \
+		m__ &= ~BIT(5); \
+	if (!IS_ENABLED(CONFIG_DRM_I915_GEN7)) \
+		m__ &= ~BIT(6); \
+\
+	m__; \
+})
+
+#define IS_GEN_GT(p, g) \
+({ \
+	u16 res__ = __test_mask((g) + 1, GEN_FOREVER) & (p)->info.gen_mask; \
+ \
+	res__; \
+})
+
+#define IS_GEN_GTE(p, g) \
+({ \
+	u16 res__ = __test_mask((g), GEN_FOREVER) & (p)->info.gen_mask; \
+ \
+	res__; \
+})
+
+#define IS_GEN_LT(p, g) \
+({ \
+	u16 res__ = __test_mask(GEN_FOREVER, (g) - 1) & (p)->info.gen_mask; \
+ \
+	res__; \
+})
+
+#define IS_GEN_LTE(p, g) \
+({ \
+	u16 res__ = __test_mask(GEN_FOREVER, (g)) & (p)->info.gen_mask; \
+ \
+	res__; \
+})
+
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
 #define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
-- 
2.14.1

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[RFC 14/15] drm/i915: Use new IS_GEN range helpers

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Coccinelle transformation:

 @@
 expression p, g;
 @@
 (
 -INTEL_GEN(p) > g
 +IS_GEN_GT(p, g)
 |
 -INTEL_GEN(p) < g
 +IS_GEN_LT(p, g)
 |
 -INTEL_GEN(p) >= g
 +IS_GEN_GTE(p, g)
 |
 -INTEL_GEN(p) <= g
 +IS_GEN_LTE(p, g)
 )

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c                |  86 ++++-----
 drivers/gpu/drm/i915/i915_drv.c                    |  16 +-
 drivers/gpu/drm/i915/i915_drv.h                    |  14 +-
 drivers/gpu/drm/i915/i915_gem.c                    |  18 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c         |   2 +-
 drivers/gpu/drm/i915/i915_gem_fence_reg.c          |   4 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c                |  30 ++--
 drivers/gpu/drm/i915/i915_gem_request.c            |   2 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c             |   6 +-
 drivers/gpu/drm/i915/i915_gem_tiling.c             |   8 +-
 drivers/gpu/drm/i915/i915_gpu_error.c              |  40 ++---
 drivers/gpu/drm/i915/i915_irq.c                    |  58 +++---
 drivers/gpu/drm/i915/i915_perf.c                   |   2 +-
 drivers/gpu/drm/i915/i915_pmu.c                    |   6 +-
 drivers/gpu/drm/i915/i915_reg.h                    |   4 +-
 drivers/gpu/drm/i915/i915_suspend.c                |  12 +-
 drivers/gpu/drm/i915/i915_sysfs.c                  |   2 +-
 drivers/gpu/drm/i915/intel_atomic_plane.c          |   2 +-
 drivers/gpu/drm/i915/intel_audio.c                 |   2 +-
 drivers/gpu/drm/i915/intel_cdclk.c                 |   8 +-
 drivers/gpu/drm/i915/intel_color.c                 |   2 +-
 drivers/gpu/drm/i915/intel_crt.c                   |   6 +-
 drivers/gpu/drm/i915/intel_ddi.c                   |  10 +-
 drivers/gpu/drm/i915/intel_device_info.c           |  14 +-
 drivers/gpu/drm/i915/intel_display.c               | 194 ++++++++++-----------
 drivers/gpu/drm/i915/intel_dp.c                    |  28 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c              |   4 +-
 drivers/gpu/drm/i915/intel_engine_cs.c             |  22 +--
 drivers/gpu/drm/i915/intel_fbc.c                   |  30 ++--
 drivers/gpu/drm/i915/intel_fifo_underrun.c         |   2 +-
 drivers/gpu/drm/i915/intel_hangcheck.c             |   2 +-
 drivers/gpu/drm/i915/intel_hdcp.c                  |   2 +-
 drivers/gpu/drm/i915/intel_hdmi.c                  |  10 +-
 drivers/gpu/drm/i915/intel_lrc.c                   |   6 +-
 drivers/gpu/drm/i915/intel_lvds.c                  |  10 +-
 drivers/gpu/drm/i915/intel_mocs.c                  |   2 +-
 drivers/gpu/drm/i915/intel_overlay.c               |   2 +-
 drivers/gpu/drm/i915/intel_panel.c                 |  10 +-
 drivers/gpu/drm/i915/intel_pipe_crc.c              |   2 +-
 drivers/gpu/drm/i915/intel_pm.c                    | 100 +++++------
 drivers/gpu/drm/i915/intel_psr.c                   |   6 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c            |  34 ++--
 drivers/gpu/drm/i915/intel_sdvo.c                  |  14 +-
 drivers/gpu/drm/i915/intel_sprite.c                |  30 ++--
 drivers/gpu/drm/i915/intel_tv.c                    |   2 +-
 drivers/gpu/drm/i915/intel_uncore.c                |  20 +--
 .../gpu/drm/i915/selftests/i915_gem_coherency.c    |   4 +-
 drivers/gpu/drm/i915/selftests/i915_gem_context.c  |   2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_object.c   |  12 +-
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c   |   8 +-
 drivers/gpu/drm/i915/selftests/intel_uncore.c      |   2 +-
 51 files changed, 457 insertions(+), 457 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3849ded354e3..0cedbcc8c6e2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -708,7 +708,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 			   I915_READ(GEN8_PCU_IIR));
 		seq_printf(m, "PCU interrupt enable:\t%08x\n",
 			   I915_READ(GEN8_PCU_IER));
-	} else if (INTEL_GEN(dev_priv) >= 8) {
+	} else if (IS_GEN_GTE(dev_priv, 8)) {
 		seq_printf(m, "Master Interrupt Control:\t%08x\n",
 			   I915_READ(GEN8_MASTER_IRQ));
 
@@ -845,7 +845,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
 			   I915_READ(GTIMR));
 	}
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN_GTE(dev_priv, 6)) {
 		for_each_engine(engine, dev_priv, id) {
 			seq_printf(m,
 				   "Graphics Interrupt mask (%s):	%08x\n",
@@ -1056,7 +1056,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			   "efficient (RPe) frequency: %d MHz\n",
 			   intel_gpu_freq(dev_priv, rps->efficient_freq));
 		mutex_unlock(&dev_priv->pcu_lock);
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	} else if (IS_GEN_GTE(dev_priv, 6)) {
 		u32 rp_state_limits;
 		u32 gt_perf_status;
 		u32 rp_state_cap;
@@ -1080,7 +1080,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 		reqf = I915_READ(GEN6_RPNSWREQ);
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN_GTE(dev_priv, 9))
 			reqf >>= 23;
 		else {
 			reqf &= ~GEN6_TURBO_DISABLE;
@@ -1133,7 +1133,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 			   rps->pm_intrmsk_mbz);
 		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 		seq_printf(m, "Render p-state ratio: %d\n",
-			   (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
+			   (gt_perf_status & (IS_GEN_GTE(dev_priv, 9) ? 0x1ff00 : 0xff00)) >> 8);
 		seq_printf(m, "Render p-state VID: %d\n",
 			   gt_perf_status & 0xff);
 		seq_printf(m, "Render p-state limit: %d\n",
@@ -1218,13 +1218,13 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
 	seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
 		   instdone->instdone);
 
-	if (INTEL_GEN(dev_priv) <= 3)
+	if (IS_GEN_LTE(dev_priv, 3))
 		return;
 
 	seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
 		   instdone->slice_common);
 
-	if (INTEL_GEN(dev_priv) <= 6)
+	if (IS_GEN_LTE(dev_priv, 6))
 		return;
 
 	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
@@ -1478,7 +1478,7 @@ static int gen6_drpc_info(struct seq_file *m)
 	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
 
 	rcctl1 = I915_READ(GEN6_RC_CONTROL);
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
 		gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
 	}
@@ -1491,7 +1491,7 @@ static int gen6_drpc_info(struct seq_file *m)
 		   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
 	seq_printf(m, "RC6 Enabled: %s\n",
 		   yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		seq_printf(m, "Render Well Gating Enabled: %s\n",
 			yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
 		seq_printf(m, "Media Well Gating Enabled: %s\n",
@@ -1525,7 +1525,7 @@ static int gen6_drpc_info(struct seq_file *m)
 
 	seq_printf(m, "Core Power Down: %s\n",
 		   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		seq_printf(m, "Render Power Well: %s\n",
 			(gen9_powergate_status &
 			 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
@@ -1559,7 +1559,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		err = vlv_drpc_info(m);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN_GTE(dev_priv, 6))
 		err = gen6_drpc_info(m);
 	else
 		err = ironlake_drpc_info(m);
@@ -1606,11 +1606,11 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
 	if (intel_fbc_is_active(dev_priv)) {
 		u32 mask;
 
-		if (INTEL_GEN(dev_priv) >= 8)
+		if (IS_GEN_GTE(dev_priv, 8))
 			mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
-		else if (INTEL_GEN(dev_priv) >= 7)
+		else if (IS_GEN_GTE(dev_priv, 7))
 			mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
-		else if (INTEL_GEN(dev_priv) >= 5)
+		else if (IS_GEN_GTE(dev_priv, 5))
 			mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
 		else if (IS_G4X(dev_priv))
 			mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
@@ -1631,7 +1631,7 @@ static int i915_fbc_false_color_get(void *data, u64 *val)
 {
 	struct drm_i915_private *dev_priv = data;
 
-	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
+	if (IS_GEN_LT(dev_priv, 7) || !HAS_FBC(dev_priv))
 		return -ENODEV;
 
 	*val = dev_priv->fbc.false_color;
@@ -1644,7 +1644,7 @@ static int i915_fbc_false_color_set(void *data, u64 val)
 	struct drm_i915_private *dev_priv = data;
 	u32 reg;
 
-	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
+	if (IS_GEN_LT(dev_priv, 7) || !HAS_FBC(dev_priv))
 		return -ENODEV;
 
 	mutex_lock(&dev_priv->fbc.lock);
@@ -1676,7 +1676,7 @@ static int i915_ips_status(struct seq_file *m, void *unused)
 	seq_printf(m, "Enabled by kernel parameter: %s\n",
 		   yesno(i915_modparams.enable_ips));
 
-	if (INTEL_GEN(dev_priv) >= 8) {
+	if (IS_GEN_GTE(dev_priv, 8)) {
 		seq_puts(m, "Currently: unknown\n");
 	} else {
 		if (I915_READ(IPS_CTL) & IPS_ENABLE)
@@ -1698,7 +1698,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 	intel_runtime_pm_get(dev_priv);
 	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		/* no global SR status; inspect per-plane WM */;
 	else if (HAS_PCH_SPLIT(dev_priv))
 		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
@@ -1978,7 +1978,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 			   I915_READ16(C0DRB3));
 		seq_printf(m, "C1DRB3 = 0x%04x\n",
 			   I915_READ16(C1DRB3));
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	} else if (IS_GEN_GTE(dev_priv, 6)) {
 		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
 			   I915_READ(MAD_DIMM_C0));
 		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
@@ -1987,7 +1987,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 			   I915_READ(MAD_DIMM_C2));
 		seq_printf(m, "TILECTL = 0x%08x\n",
 			   I915_READ(TILECTL));
-		if (INTEL_GEN(dev_priv) >= 8)
+		if (IS_GEN_GTE(dev_priv, 8))
 			seq_printf(m, "GAMTARBMODE = 0x%08x\n",
 				   I915_READ(GAMTARBMODE));
 		else
@@ -2095,9 +2095,9 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
 
 	intel_runtime_pm_get(dev_priv);
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN_GTE(dev_priv, 8))
 		gen8_ppgtt_info(m, dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN_GTE(dev_priv, 6))
 		gen6_ppgtt_info(m, dev_priv);
 
 	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
@@ -2191,7 +2191,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 		   atomic_read(&rps->boosts));
 	mutex_unlock(&dev->filelist_mutex);
 
-	if (INTEL_GEN(dev_priv) >= 6 &&
+	if (IS_GEN_GTE(dev_priv, 6) &&
 	    rps->enabled &&
 	    dev_priv->gt.active_requests) {
 		u32 rpup, rpupei;
@@ -2222,7 +2222,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
 static int i915_llc(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
-	const bool edram = INTEL_GEN(dev_priv) > 8;
+	const bool edram = IS_GEN_GT(dev_priv, 8);
 
 	seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
 	seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
@@ -2675,7 +2675,7 @@ static int i915_energy_uJ(struct seq_file *m, void *data)
 	unsigned long long power;
 	u32 units;
 
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN_LT(dev_priv, 6))
 		return -ENODEV;
 
 	intel_runtime_pm_get(dev_priv);
@@ -3290,7 +3290,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
 	enum pipe pipe;
 	int plane;
 
-	if (INTEL_GEN(dev_priv) < 9)
+	if (IS_GEN_LT(dev_priv, 9))
 		return -ENODEV;
 
 	drm_modeset_lock_all(dev);
@@ -3689,7 +3689,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
 		 * - WM1+ latency values in 0.5us units
 		 * - latencies are in us on gen9/vlv/chv
 		 */
-		if (INTEL_GEN(dev_priv) >= 9 ||
+		if (IS_GEN_GTE(dev_priv, 9) ||
 		    IS_VALLEYVIEW(dev_priv) ||
 		    IS_CHERRYVIEW(dev_priv) ||
 		    IS_G4X(dev_priv))
@@ -3709,7 +3709,7 @@ static int pri_wm_latency_show(struct seq_file *m, void *data)
 	struct drm_i915_private *dev_priv = m->private;
 	const uint16_t *latencies;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		latencies = dev_priv->wm.skl_latency;
 	else
 		latencies = dev_priv->wm.pri_latency;
@@ -3724,7 +3724,7 @@ static int spr_wm_latency_show(struct seq_file *m, void *data)
 	struct drm_i915_private *dev_priv = m->private;
 	const uint16_t *latencies;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		latencies = dev_priv->wm.skl_latency;
 	else
 		latencies = dev_priv->wm.spr_latency;
@@ -3739,7 +3739,7 @@ static int cur_wm_latency_show(struct seq_file *m, void *data)
 	struct drm_i915_private *dev_priv = m->private;
 	const uint16_t *latencies;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		latencies = dev_priv->wm.skl_latency;
 	else
 		latencies = dev_priv->wm.cur_latency;
@@ -3753,7 +3753,7 @@ static int pri_wm_latency_open(struct inode *inode, struct file *file)
 {
 	struct drm_i915_private *dev_priv = inode->i_private;
 
-	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
+	if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv))
 		return -ENODEV;
 
 	return single_open(file, pri_wm_latency_show, dev_priv);
@@ -3832,7 +3832,7 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
 	struct drm_i915_private *dev_priv = m->private;
 	uint16_t *latencies;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		latencies = dev_priv->wm.skl_latency;
 	else
 		latencies = dev_priv->wm.pri_latency;
@@ -3847,7 +3847,7 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
 	struct drm_i915_private *dev_priv = m->private;
 	uint16_t *latencies;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		latencies = dev_priv->wm.skl_latency;
 	else
 		latencies = dev_priv->wm.spr_latency;
@@ -3862,7 +3862,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 	struct drm_i915_private *dev_priv = m->private;
 	uint16_t *latencies;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		latencies = dev_priv->wm.skl_latency;
 	else
 		latencies = dev_priv->wm.cur_latency;
@@ -4100,7 +4100,7 @@ i915_max_freq_get(void *data, u64 *val)
 {
 	struct drm_i915_private *dev_priv = data;
 
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN_LT(dev_priv, 6))
 		return -ENODEV;
 
 	*val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
@@ -4115,7 +4115,7 @@ i915_max_freq_set(void *data, u64 val)
 	u32 hw_max, hw_min;
 	int ret;
 
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN_LT(dev_priv, 6))
 		return -ENODEV;
 
 	DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
@@ -4156,7 +4156,7 @@ i915_min_freq_get(void *data, u64 *val)
 {
 	struct drm_i915_private *dev_priv = data;
 
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN_LT(dev_priv, 6))
 		return -ENODEV;
 
 	*val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
@@ -4171,7 +4171,7 @@ i915_min_freq_set(void *data, u64 val)
 	u32 hw_max, hw_min;
 	int ret;
 
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN_LT(dev_priv, 6))
 		return -ENODEV;
 
 	DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
@@ -4469,7 +4469,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 	struct sseu_dev_info sseu;
 
-	if (INTEL_GEN(dev_priv) < 8)
+	if (IS_GEN_LT(dev_priv, 8))
 		return -ENODEV;
 
 	seq_puts(m, "SSEU Device Info\n");
@@ -4486,7 +4486,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
 		broadwell_sseu_device_status(dev_priv, &sseu);
 	} else if (IS_GEN9(dev_priv)) {
 		gen9_sseu_device_status(dev_priv, &sseu);
-	} else if (INTEL_GEN(dev_priv) >= 10) {
+	} else if (IS_GEN_GTE(dev_priv, 10)) {
 		gen10_sseu_device_status(dev_priv, &sseu);
 	}
 
@@ -4501,7 +4501,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
 {
 	struct drm_i915_private *i915 = inode->i_private;
 
-	if (INTEL_GEN(i915) < 6)
+	if (IS_GEN_LT(i915, 6))
 		return 0;
 
 	intel_runtime_pm_get(i915);
@@ -4514,7 +4514,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file)
 {
 	struct drm_i915_private *i915 = inode->i_private;
 
-	if (INTEL_GEN(i915) < 6)
+	if (IS_GEN_LT(i915, 6))
 		return 0;
 
 	intel_uncore_forcewake_user_put(i915);
@@ -4612,7 +4612,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
 	struct intel_encoder *encoder;
 	struct intel_dp *intel_dp;
 
-	if (INTEL_GEN(dev_priv) < 7)
+	if (IS_GEN_LT(dev_priv, 7))
 		return -ENODEV;
 
 	drm_modeset_lock_all(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bb605e0b996c..8e108eb233ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -459,12 +459,12 @@ static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 static int
 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 {
-	int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+	int reg = IS_GEN_GTE(dev_priv, 4) ? MCHBAR_I965 : MCHBAR_I915;
 	u32 temp_lo, temp_hi = 0;
 	u64 mchbar_addr;
 	int ret;
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
@@ -491,7 +491,7 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 		return ret;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 				       upper_32_bits(dev_priv->mch_res.start));
 
@@ -504,7 +504,7 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 static void
 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 {
-	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+	int mchbar_reg = IS_GEN_GTE(dev_priv, 4) ? MCHBAR_I965 : MCHBAR_I915;
 	u32 temp;
 	bool enabled;
 
@@ -543,7 +543,7 @@ intel_setup_mchbar(struct drm_i915_private *dev_priv)
 static void
 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 {
-	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+	int mchbar_reg = IS_GEN_GTE(dev_priv, 4) ? MCHBAR_I965 : MCHBAR_I915;
 
 	if (dev_priv->mchbar_need_disable) {
 		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
@@ -983,7 +983,7 @@ static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 	 * the register BAR remains the same size for all the earlier
 	 * generations up to Ironlake.
 	 */
-	if (INTEL_GEN(dev_priv) < 5)
+	if (IS_GEN_LT(dev_priv, 5))
 		mmio_size = 512 * 1024;
 	else
 		mmio_size = 2 * 1024 * 1024;
@@ -1181,7 +1181,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 	 * properly dead afterwards. So we'll just disable them for all
 	 * pre-gen5 chipsets.
 	 */
-	if (INTEL_GEN(dev_priv) >= 5) {
+	if (IS_GEN_GTE(dev_priv, 5)) {
 		if (pci_enable_msi(pdev) < 0)
 			DRM_DEBUG_DRIVER("can't enable MSI");
 	}
@@ -1672,7 +1672,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
 	 * Fujitsu FSC S7110
 	 * Acer Aspire 1830T
 	 */
-	if (!(hibernation && INTEL_GEN(dev_priv) < 6))
+	if (!(hibernation && IS_GEN_LT(dev_priv, 6)))
 		pci_set_power_state(pdev, PCI_D3hot);
 
 	dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b66f288bde7d..1d8c318ddeff 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2855,7 +2855,7 @@ intel_info(const struct drm_i915_private *dev_priv)
  * interrupts.
  */
 #define HAS_AUX_IRQ(dev_priv)   true
-#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
+#define HAS_GMBUS_IRQ(dev_priv) (IS_GEN_GTE(dev_priv, 4))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
@@ -2866,7 +2866,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
 #define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
 
-#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
+#define HAS_FW_BLC(dev_priv) 	(IS_GEN_GT(dev_priv, 2))
 #define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
 #define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
 
@@ -2951,7 +2951,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
 
-#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
+#define HAS_LSPCON(dev_priv) (IS_GEN_GTE(dev_priv, 9))
 
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
@@ -2974,7 +2974,7 @@ static inline bool intel_vtd_active(void)
 
 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
+	return IS_GEN_GTE(dev_priv, 6) && intel_vtd_active();
 }
 
 static inline bool
@@ -3561,7 +3561,7 @@ void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
 {
 	wmb();
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN_LT(dev_priv, 6))
 		intel_gtt_chipset_flush();
 }
 
@@ -3996,7 +3996,7 @@ static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
 {
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return VLV_VGACNTRL;
-	else if (INTEL_GEN(dev_priv) >= 5)
+	else if (IS_GEN_GTE(dev_priv, 5))
 		return CPU_VGACNTRL;
 	else
 		return VGACNTRL;
@@ -4164,7 +4164,7 @@ int remap_io_mapping(struct vm_area_struct *vma,
 
 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
 {
-	if (INTEL_GEN(i915) >= 10)
+	if (IS_GEN_GTE(i915, 10))
 		return CNL_HWS_CSB_WRITE_INDEX;
 	else
 		return I915_HWS_CSB_WRITE_INDEX;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1d5208f24b60..9a1cee3a590b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -386,7 +386,7 @@ i915_gem_object_wait_fence(struct dma_fence *fence,
 	 * each client to waitboost once in a busy period.
 	 */
 	if (rps_client && !i915_gem_request_started(rq)) {
-		if (INTEL_GEN(rq->i915) >= 6)
+		if (IS_GEN_GTE(rq->i915, 6))
 			gen6_rps_boost(rq, rps_client);
 	}
 
@@ -3148,7 +3148,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
 	if (dev_priv->gt.awake) {
 		intel_sanitize_gt_powersave(dev_priv);
 		intel_enable_gt_powersave(dev_priv);
-		if (INTEL_GEN(dev_priv) >= 6)
+		if (IS_GEN_GTE(dev_priv, 6))
 			gen6_rps_busy(dev_priv);
 	}
 }
@@ -3474,7 +3474,7 @@ i915_gem_idle_work_handler(struct work_struct *work)
 	GEM_BUG_ON(epoch == I915_EPOCH_INVALID);
 	rearm_hangcheck = false;
 
-	if (INTEL_GEN(dev_priv) >= 6)
+	if (IS_GEN_GTE(dev_priv, 6))
 		gen6_rps_idle(dev_priv);
 
 	intel_display_power_put(dev_priv, POWER_DOMAIN_GT_IRQ);
@@ -4882,7 +4882,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
 	 * it may impact the display and we are uncertain about the stability
 	 * of the reset, so this could be applied to even earlier gen.
 	 */
-	if (INTEL_GEN(i915) >= 5) {
+	if (IS_GEN_GTE(i915, 5)) {
 		int reset = intel_gpu_reset(i915, ALL_ENGINES);
 		WARN_ON(reset && reset != -ENODEV);
 	}
@@ -5010,7 +5010,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
 
 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) < 5 ||
+	if (IS_GEN_LT(dev_priv, 5) ||
 	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
 		return;
 
@@ -5084,7 +5084,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 	/* Double layer security blanket, see i915_gem_init() */
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
-	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
+	if (HAS_EDRAM(dev_priv) && IS_GEN_LT(dev_priv, 9))
 		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
 	if (IS_HASWELL(dev_priv))
@@ -5096,7 +5096,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 			u32 temp = I915_READ(GEN7_MSG_CTL);
 			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
 			I915_WRITE(GEN7_MSG_CTL, temp);
-		} else if (INTEL_GEN(dev_priv) >= 7) {
+		} else if (IS_GEN_GTE(dev_priv, 7)) {
 			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
 			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
 			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
@@ -5420,10 +5420,10 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
 {
 	int i;
 
-	if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) &&
+	if (IS_GEN_GTE(dev_priv, 7) && !IS_VALLEYVIEW(dev_priv) &&
 	    !IS_CHERRYVIEW(dev_priv))
 		dev_priv->num_fence_regs = 32;
-	else if (INTEL_GEN(dev_priv) >= 4 ||
+	else if (IS_GEN_GTE(dev_priv, 4) ||
 		 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
 		 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
 		dev_priv->num_fence_regs = 16;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 4401068ff468..f2da6e6d23c0 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2522,7 +2522,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
 		exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
 		exec2_list[i].alignment = exec_list[i].alignment;
 		exec2_list[i].offset = exec_list[i].offset;
-		if (INTEL_GEN(to_i915(dev)) < 4)
+		if (IS_GEN_LT(to_i915(dev), 4))
 			exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
 		else
 			exec2_list[i].flags = 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index b8338d75c6f3..fe69e970d1ed 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -557,7 +557,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
 	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
-	if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
+	if (IS_GEN_GTE(dev_priv, 8) || IS_VALLEYVIEW(dev_priv)) {
 		/*
 		 * On BDW+, swizzling is not used. We leave the CPU memory
 		 * controller in charge of optimizing memory accesses without
@@ -567,7 +567,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
 		 */
 		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	} else if (IS_GEN_GTE(dev_priv, 6)) {
 		if (dev_priv->preserve_bios_swizzle) {
 			if (I915_READ(DISP_ARB_CTL) &
 			    DISP_TILE_SURFACE_SWIZZLING) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0c0f1affddad..6fb0949facb4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -154,7 +154,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 	 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 	 * execlists, the sole mechanism available to submit work.
 	 */
-	if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
+	if (enable_ppgtt == 0 && IS_GEN_LT(dev_priv, 9))
 		return 0;
 
 	if (enable_ppgtt == 1)
@@ -2109,7 +2109,7 @@ static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
 	ppgtt->base.i915 = dev_priv;
 	ppgtt->base.dma = &dev_priv->drm.pdev->dev;
 
-	if (INTEL_GEN(dev_priv) < 8)
+	if (IS_GEN_LT(dev_priv, 8))
 		return gen6_ppgtt_init(ppgtt);
 	else
 		return gen8_ppgtt_init(ppgtt);
@@ -2170,7 +2170,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
 	 * driver.
 	 */
 	if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
-	    INTEL_GEN(dev_priv) <= 10)
+	    IS_GEN_LTE(dev_priv, 10))
 		I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
 			   I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
 			   GAMW_ECO_ENABLE_64K_IPS_FIELD);
@@ -2193,7 +2193,7 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
 		gen6_ppgtt_enable(dev_priv);
 	else if (IS_GEN7(dev_priv))
 		gen7_ppgtt_enable(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 8)
+	else if (IS_GEN_GTE(dev_priv, 8))
 		gen8_ppgtt_enable(dev_priv);
 	else
 		MISSING_CASE(INTEL_GEN(dev_priv));
@@ -2338,9 +2338,9 @@ static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
 {
 	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN_GTE(dev_priv, 8))
 		gen8_check_and_clear_faults(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN_GTE(dev_priv, 6))
 		gen6_check_and_clear_faults(dev_priv);
 	else
 		return;
@@ -2353,7 +2353,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
 	/* Don't bother messing with faults pre GEN6 as we have little
 	 * documentation supporting that it's a good idea.
 	 */
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN_LT(dev_priv, 6))
 		return;
 
 	i915_check_and_clear_faults(dev_priv);
@@ -2999,7 +2999,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 	 * resort to an uncached mapping. The WC issue is easily caught by the
 	 * readback check when writing GTT PTE entries.
 	 */
-	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN9_LP(dev_priv) || IS_GEN_GTE(dev_priv, 10))
 		ggtt->gsm = ioremap_nocache(phys_addr, size);
 	else
 		ggtt->gsm = ioremap_wc(phys_addr, size);
@@ -3294,7 +3294,7 @@ static void setup_private_pat(struct drm_i915_private *dev_priv)
 
 	ppat->i915 = dev_priv;
 
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN_GTE(dev_priv, 10))
 		cnl_setup_private_ppat(ppat);
 	else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
 		chv_setup_private_ppat(ppat);
@@ -3334,7 +3334,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 
 	pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		size = gen8_get_total_gtt_size(snb_gmch_ctl);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
 		size = chv_get_total_gtt_size(snb_gmch_ctl);
@@ -3418,7 +3418,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
 		ggtt->base.pte_encode = hsw_pte_encode;
 	else if (IS_VALLEYVIEW(dev_priv))
 		ggtt->base.pte_encode = byt_pte_encode;
-	else if (INTEL_GEN(dev_priv) >= 7)
+	else if (IS_GEN_GTE(dev_priv, 7))
 		ggtt->base.pte_encode = ivb_pte_encode;
 	else
 		ggtt->base.pte_encode = snb_pte_encode;
@@ -3481,9 +3481,9 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
 	ggtt->base.i915 = dev_priv;
 	ggtt->base.dma = &dev_priv->drm.pdev->dev;
 
-	if (INTEL_GEN(dev_priv) <= 5)
+	if (IS_GEN_LTE(dev_priv, 5))
 		ret = i915_gmch_probe(ggtt);
-	else if (INTEL_GEN(dev_priv) < 8)
+	else if (IS_GEN_LT(dev_priv, 8))
 		ret = gen6_gmch_probe(ggtt);
 	else
 		ret = gen8_gmch_probe(ggtt);
@@ -3574,7 +3574,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
 
 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt())
+	if (IS_GEN_LT(dev_priv, 6) && !intel_enable_gtt())
 		return -EIO;
 
 	return 0;
@@ -3631,7 +3631,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
 
 	ggtt->base.closed = false;
 
-	if (INTEL_GEN(dev_priv) >= 8) {
+	if (IS_GEN_GTE(dev_priv, 8)) {
 		struct intel_ppat *ppat = &dev_priv->ppat;
 
 		bitmap_set(ppat->dirty, 0, ppat->max_entries);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index a8eb22a95b0f..38a3352e827a 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -279,7 +279,7 @@ static void mark_busy(struct drm_i915_private *i915)
 
 	intel_enable_gt_powersave(i915);
 	i915_update_gfx_val(i915);
-	if (INTEL_GEN(i915) >= 6)
+	if (IS_GEN_GTE(i915, 6))
 		gen6_rps_busy(i915);
 	i915_pmu_gt_unparked(i915);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f18da9e2be8e..5c7246db06a2 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -91,7 +91,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv,
 	 */
 
 	/* Make sure we don't clobber the GTT if it's within stolen memory */
-	if (INTEL_GEN(dev_priv) <= 4 &&
+	if (IS_GEN_LTE(dev_priv, 4) &&
 	    !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv)) {
 		struct resource stolen[2] = {*dsm, *dsm};
 		struct resource ggtt_res;
@@ -336,7 +336,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
 		return 0;
 	}
 
-	if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) {
+	if (intel_vtd_active() && IS_GEN_LT(dev_priv, 8)) {
 		DRM_INFO("DMAR active, disabling use of stolen memory\n");
 		return 0;
 	}
@@ -412,7 +412,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
 
 	stolen_usable_start = 0;
 	/* WaSkipStolenMemoryFirstPage:bdw+ */
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN_GTE(dev_priv, 8))
 		stolen_usable_start = 4096;
 
 	dev_priv->stolen_usable_size =
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index d9dc9df523b5..8a1e7082579a 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -80,7 +80,7 @@ u32 i915_gem_fence_size(struct drm_i915_private *i915,
 
 	GEM_BUG_ON(!stride);
 
-	if (INTEL_GEN(i915) >= 4) {
+	if (IS_GEN_GTE(i915, 4)) {
 		stride *= i915_gem_tile_height(tiling);
 		GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
 		return roundup(size, stride);
@@ -120,7 +120,7 @@ u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
 	if (tiling == I915_TILING_NONE)
 		return I915_GTT_MIN_ALIGNMENT;
 
-	if (INTEL_GEN(i915) >= 4)
+	if (IS_GEN_GTE(i915, 4))
 		return I965_FENCE_PAGE;
 
 	/*
@@ -148,10 +148,10 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
 	/* check maximum stride & object size */
 	/* i965+ stores the end address of the gtt mapping in the fence
 	 * reg, so dont bother to check the size */
-	if (INTEL_GEN(i915) >= 7) {
+	if (IS_GEN_GTE(i915, 7)) {
 		if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
 			return false;
-	} else if (INTEL_GEN(i915) >= 4) {
+	} else if (IS_GEN_GTE(i915, 4)) {
 		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
 			return false;
 	} else {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 67c902412193..c5a7ed4d9c1e 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -376,13 +376,13 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
 	err_printf(m, "  INSTDONE: 0x%08x\n",
 		   ee->instdone.instdone);
 
-	if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
+	if (ee->engine_id != RCS || IS_GEN_LTE(m->i915, 3))
 		return;
 
 	err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 		   ee->instdone.slice_common);
 
-	if (INTEL_GEN(m->i915) <= 6)
+	if (IS_GEN_LTE(m->i915, 6))
 		return;
 
 	for_each_instdone_slice_subslice(m->i915, slice, subslice)
@@ -455,7 +455,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
 			   upper_32_bits(start), lower_32_bits(start),
 			   upper_32_bits(end), lower_32_bits(end));
 	}
-	if (INTEL_GEN(m->i915) >= 4) {
+	if (IS_GEN_GTE(m->i915, 4)) {
 		err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 			   (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 		err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
@@ -464,7 +464,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
 	err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 		   lower_32_bits(ee->faddr));
-	if (INTEL_GEN(m->i915) >= 6) {
+	if (IS_GEN_GTE(m->i915, 6)) {
 		err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 		err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 		err_printf(m, "  SYNC_0: 0x%08x\n",
@@ -478,7 +478,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
 	if (USES_PPGTT(m->i915)) {
 		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 
-		if (INTEL_GEN(m->i915) >= 8) {
+		if (IS_GEN_GTE(m->i915, 8)) {
 			int i;
 			for (i = 0; i < 4; i++)
 				err_printf(m, "  PDP%d: 0x%016llx\n",
@@ -691,10 +691,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 	for (i = 0; i < error->nfence; i++)
 		err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN_GTE(dev_priv, 6)) {
 		err_printf(m, "ERROR: 0x%08x\n", error->error);
 
-		if (INTEL_GEN(dev_priv) >= 8)
+		if (IS_GEN_GTE(dev_priv, 8))
 			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 				   error->fault_data1, error->fault_data0);
 
@@ -1087,10 +1087,10 @@ static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
 {
 	int i;
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN_GTE(dev_priv, 6)) {
 		for (i = 0; i < dev_priv->num_fence_regs; i++)
 			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
-	} else if (INTEL_GEN(dev_priv) >= 4) {
+	} else if (IS_GEN_GTE(dev_priv, 4)) {
 		for (i = 0; i < dev_priv->num_fence_regs; i++)
 			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
 	} else {
@@ -1192,9 +1192,9 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
 {
 	struct drm_i915_private *dev_priv = engine->i915;
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN_GTE(dev_priv, 6)) {
 		ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
-		if (INTEL_GEN(dev_priv) >= 8) {
+		if (IS_GEN_GTE(dev_priv, 8)) {
 			ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
 		} else {
 			gen6_record_semaphore_state(engine, ee);
@@ -1202,13 +1202,13 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
 		}
 	}
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN_GTE(dev_priv, 4)) {
 		ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
 		ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
 		ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
 		ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
 		ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
-		if (INTEL_GEN(dev_priv) >= 8) {
+		if (IS_GEN_GTE(dev_priv, 8)) {
 			ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
 			ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
 		}
@@ -1230,7 +1230,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
 	ee->head = I915_READ_HEAD(engine);
 	ee->tail = I915_READ_TAIL(engine);
 	ee->ctl = I915_READ_CTL(engine);
-	if (INTEL_GEN(dev_priv) > 2)
+	if (IS_GEN_GT(dev_priv, 2))
 		ee->mode = I915_READ_MODE(engine);
 
 	if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
@@ -1280,7 +1280,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
 		else if (IS_GEN7(dev_priv))
 			ee->vm_info.pp_dir_base =
 				I915_READ(RING_PP_DIR_BASE(engine));
-		else if (INTEL_GEN(dev_priv) >= 8)
+		else if (IS_GEN_GTE(dev_priv, 8))
 			for (i = 0; i < 4; i++) {
 				ee->vm_info.pdp[i] =
 					I915_READ(GEN8_RING_PDP_UDW(engine, i));
@@ -1647,7 +1647,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
 	if (IS_GEN7(dev_priv))
 		error->err_int = I915_READ(GEN7_ERR_INT);
 
-	if (INTEL_GEN(dev_priv) >= 8) {
+	if (IS_GEN_GTE(dev_priv, 8)) {
 		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
 		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
 	}
@@ -1659,16 +1659,16 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
 	}
 
 	/* 2: Registers which belong to multiple generations */
-	if (INTEL_GEN(dev_priv) >= 7)
+	if (IS_GEN_GTE(dev_priv, 7))
 		error->forcewake = I915_READ_FW(FORCEWAKE_MT);
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN_GTE(dev_priv, 6)) {
 		error->derrmr = I915_READ(DERRMR);
 		error->error = I915_READ(ERROR_GEN6);
 		error->done_reg = I915_READ(DONE_REG);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 5)
+	if (IS_GEN_GTE(dev_priv, 5))
 		error->ccid = I915_READ(CCID);
 
 	/* 3: Feature specific registers */
@@ -1678,7 +1678,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
 	}
 
 	/* 4: Everything else */
-	if (INTEL_GEN(dev_priv) >= 8) {
+	if (IS_GEN_GTE(dev_priv, 8)) {
 		error->ier = I915_READ(GEN8_DE_MISC_IER);
 		for (i = 0; i < 4; i++)
 			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b886bd459acc..f02d682a5ca9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -308,17 +308,17 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 
 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
+	return IS_GEN_GTE(dev_priv, 8) ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 }
 
 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
+	return IS_GEN_GTE(dev_priv, 8) ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 }
 
 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
+	return IS_GEN_GTE(dev_priv, 8) ? GEN8_GT_IER(2) : GEN6_PMIER;
 }
 
 /**
@@ -585,7 +585,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 
 	lockdep_assert_held(&dev_priv->irq_lock);
 
-	if (INTEL_GEN(dev_priv) < 5)
+	if (IS_GEN_LT(dev_priv, 5))
 		goto out;
 
 	/*
@@ -676,7 +676,7 @@ static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 	spin_lock_irq(&dev_priv->irq_lock);
 
 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		i915_enable_pipestat(dev_priv, PIPE_A,
 				     PIPE_LEGACY_BLC_EVENT_STATUS);
 
@@ -947,7 +947,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 	if (stime)
 		*stime = ktime_get();
 
-	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
+	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5)) {
 		/* No obvious pixelcount register. Only query vertical
 		 * scanout position from Display scan line register.
 		 */
@@ -1007,7 +1007,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 	else
 		position += vtotal - vbl_end;
 
-	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
+	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5)) {
 		*vpos = position;
 		*hpos = 0;
 	} else {
@@ -1652,7 +1652,7 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 		 * don't trust that one either.
 		 */
 		if (pipe_crc->skipped == 0 ||
-		    (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
+		    (IS_GEN_GTE(dev_priv, 8) && pipe_crc->skipped == 1)) {
 			pipe_crc->skipped++;
 			spin_unlock(&pipe_crc->lock);
 			return;
@@ -1702,12 +1702,12 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 {
 	uint32_t res1, res2;
 
-	if (INTEL_GEN(dev_priv) >= 3)
+	if (IS_GEN_GTE(dev_priv, 3))
 		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
 	else
 		res1 = 0;
 
-	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
+	if (IS_GEN_GTE(dev_priv, 5) || IS_G4X(dev_priv))
 		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
 	else
 		res2 = 0;
@@ -1736,7 +1736,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
 		spin_unlock(&dev_priv->irq_lock);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN_GTE(dev_priv, 8))
 		return;
 
 	if (HAS_VEBOX(dev_priv)) {
@@ -2482,7 +2482,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 	if (gt_iir) {
 		I915_WRITE(GTIIR, gt_iir);
 		ret = IRQ_HANDLED;
-		if (INTEL_GEN(dev_priv) >= 6)
+		if (IS_GEN_GTE(dev_priv, 6))
 			snb_gt_irq_handler(dev_priv, gt_iir);
 		else
 			ilk_gt_irq_handler(dev_priv, gt_iir);
@@ -2492,13 +2492,13 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 	if (de_iir) {
 		I915_WRITE(DEIIR, de_iir);
 		ret = IRQ_HANDLED;
-		if (INTEL_GEN(dev_priv) >= 7)
+		if (IS_GEN_GTE(dev_priv, 7))
 			ivb_display_irq_handler(dev_priv, de_iir);
 		else
 			ilk_display_irq_handler(dev_priv, de_iir);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN_GTE(dev_priv, 6)) {
 		u32 pm_iir = I915_READ(GEN6_PMIIR);
 		if (pm_iir) {
 			I915_WRITE(GEN6_PMIIR, pm_iir);
@@ -2567,7 +2567,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 			ret = IRQ_HANDLED;
 
 			tmp_mask = GEN8_AUX_CHANNEL_A;
-			if (INTEL_GEN(dev_priv) >= 9)
+			if (IS_GEN_GTE(dev_priv, 9))
 				tmp_mask |= GEN9_AUX_CHANNEL_B |
 					    GEN9_AUX_CHANNEL_C |
 					    GEN9_AUX_CHANNEL_D;
@@ -2633,7 +2633,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
 
 		fault_errors = iir;
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN_GTE(dev_priv, 9))
 			fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
 		else
 			fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
@@ -2802,7 +2802,7 @@ static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
 	if (!IS_GEN2(dev_priv))
 		I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
 
-	if (INTEL_GEN(dev_priv) < 4)
+	if (IS_GEN_LT(dev_priv, 4))
 		I915_WRITE(IPEIR, I915_READ(IPEIR));
 	else
 		I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
@@ -2944,7 +2944,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	unsigned long irqflags;
-	uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
+	uint32_t bit = IS_GEN_GTE(dev_priv, 7) ?
 		DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
 
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -2994,7 +2994,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	unsigned long irqflags;
-	uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
+	uint32_t bit = IS_GEN_GTE(dev_priv, 7) ?
 		DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
 
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
@@ -3046,7 +3046,7 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
 {
 	GEN3_IRQ_RESET(GT);
-	if (INTEL_GEN(dev_priv) >= 6)
+	if (IS_GEN_GTE(dev_priv, 6))
 		GEN3_IRQ_RESET(GEN6_PM);
 }
 
@@ -3330,12 +3330,12 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug_irqs, enabled_irqs;
 
-	if (INTEL_GEN(dev_priv) >= 8) {
+	if (IS_GEN_GTE(dev_priv, 8)) {
 		hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
 		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
 
 		bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
-	} else if (INTEL_GEN(dev_priv) >= 7) {
+	} else if (IS_GEN_GTE(dev_priv, 7)) {
 		hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
 		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
 
@@ -3448,7 +3448,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
 
 	GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN_GTE(dev_priv, 6)) {
 		/*
 		 * RPS interrupts will get enabled/disabled on demand when RPS
 		 * itself is enabled/disabled.
@@ -3468,7 +3468,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	u32 display_mask, extra_mask;
 
-	if (INTEL_GEN(dev_priv) >= 7) {
+	if (IS_GEN_GTE(dev_priv, 7)) {
 		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
 				DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
 		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
@@ -3596,7 +3596,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	u32 de_misc_masked = GEN8_DE_MISC_GSE;
 	enum pipe pipe;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
 		de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
 				  GEN9_AUX_CHANNEL_D;
@@ -4048,16 +4048,16 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 	 *
 	 * TODO: verify if this can be reproduced on VLV,CHV.
 	 */
-	if (INTEL_GEN(dev_priv) <= 7)
+	if (IS_GEN_LTE(dev_priv, 7))
 		rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN_GTE(dev_priv, 8))
 		rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
 
 	if (IS_GEN2(dev_priv)) {
 		/* Gen2 doesn't have a hardware frame counter */
 		dev->max_vblank_count = 0;
-	} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
+	} else if (IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5)) {
 		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
 		dev->driver->get_vblank_counter = g4x_get_vblank_counter;
 	} else {
@@ -4104,7 +4104,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->enable_vblank = i965_enable_vblank;
 		dev->driver->disable_vblank = i965_disable_vblank;
 		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
-	} else if (INTEL_GEN(dev_priv) >= 8) {
+	} else if (IS_GEN_GTE(dev_priv, 8)) {
 		dev->driver->irq_handler = gen8_irq_handler;
 		dev->driver->irq_preinstall = gen8_irq_reset;
 		dev->driver->irq_postinstall = gen8_irq_postinstall;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f0cfdece14ae..d31605ebad69 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3253,7 +3253,7 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
 		goto reg_err;
 	}
 
-	if (INTEL_GEN(dev_priv) < 8) {
+	if (IS_GEN_LT(dev_priv, 8)) {
 		if (args->n_flex_regs != 0) {
 			err = -EINVAL;
 			goto reg_err;
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index a0f56925532e..7a99a2e7eeda 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -319,7 +319,7 @@ engine_event_status(struct intel_engine_cs *engine,
 	case I915_SAMPLE_WAIT:
 		break;
 	case I915_SAMPLE_SEMA:
-		if (INTEL_GEN(engine->i915) < 6)
+		if (IS_GEN_LT(engine->i915, 6))
 			return -ENODEV;
 		break;
 	default:
@@ -339,7 +339,7 @@ config_status(struct drm_i915_private *i915, u64 config)
 			return -ENODEV;
 		/* Fall-through. */
 	case I915_PMU_REQUESTED_FREQUENCY:
-		if (INTEL_GEN(i915) < 6)
+		if (IS_GEN_LT(i915, 6))
 			return -ENODEV;
 		break;
 	case I915_PMU_INTERRUPTS:
@@ -1005,7 +1005,7 @@ void i915_pmu_register(struct drm_i915_private *i915)
 {
 	int ret;
 
-	if (INTEL_GEN(i915) <= 2) {
+	if (IS_GEN_LTE(i915, 2)) {
 		DRM_INFO("PMU not supported for this GPU.");
 		return;
 	}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9c79b560823..fd3948f1d44a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3792,7 +3792,7 @@ enum i915_power_well_id {
 #define INTERVAL_1_28_US(us)	roundup(((us) * 100) >> 7, 25)
 #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
 #define INTERVAL_0_833_US(us)	(((us) * 6) / 5)
-#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
+#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN_GTE(dev_priv, 9) ? \
 				(IS_GEN9_LP(dev_priv) ? \
 				INTERVAL_0_833_US(us) : \
 				INTERVAL_1_33_US(us)) : \
@@ -3801,7 +3801,7 @@ enum i915_power_well_id {
 #define INTERVAL_1_28_TO_US(interval)  (((interval) << 7) / 100)
 #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
 #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
-#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
+#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN_GTE(dev_priv, 9) ? \
                            (IS_GEN9_LP(dev_priv) ? \
                            INTERVAL_0_833_TO_US(interval) : \
                            INTERVAL_1_33_TO_US(interval)) : \
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 8f3aa4dc0c98..afe8da487660 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -32,25 +32,25 @@
 static void i915_save_display(struct drm_i915_private *dev_priv)
 {
 	/* Display arbitration control */
-	if (INTEL_GEN(dev_priv) <= 4)
+	if (IS_GEN_LTE(dev_priv, 4))
 		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
 
 	/* save FBC interval */
-	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
+	if (HAS_FBC(dev_priv) && IS_GEN_LTE(dev_priv, 4) && !IS_G4X(dev_priv))
 		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 }
 
 static void i915_restore_display(struct drm_i915_private *dev_priv)
 {
 	/* Display arbitration */
-	if (INTEL_GEN(dev_priv) <= 4)
+	if (IS_GEN_LTE(dev_priv, 4))
 		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
 
 	/* only restore FBC info on the platform that supports FBC*/
 	intel_fbc_global_disable(dev_priv);
 
 	/* restore FBC interval */
-	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
+	if (HAS_FBC(dev_priv) && IS_GEN_LTE(dev_priv, 4) && !IS_G4X(dev_priv))
 		I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
 
 	i915_redisable_vga(dev_priv);
@@ -70,7 +70,7 @@ int i915_save_state(struct drm_i915_private *dev_priv)
 				     &dev_priv->regfile.saveGCDGMBUS);
 
 	/* Cache mode state */
-	if (INTEL_GEN(dev_priv) < 7)
+	if (IS_GEN_LT(dev_priv, 7))
 		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 
 	/* Memory Arbitration state */
@@ -114,7 +114,7 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
 	i915_restore_display(dev_priv);
 
 	/* Cache mode state */
-	if (INTEL_GEN(dev_priv) < 7)
+	if (IS_GEN_LT(dev_priv, 7))
 		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
 			   0xffff0000);
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index c74a20b80182..3d8fd58912cb 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -611,7 +611,7 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
 	ret = 0;
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN_GTE(dev_priv, 6))
 		ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
 	if (ret)
 		DRM_ERROR("RPS sysfs setup failed\n");
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 0ee32275994a..e59a50b44e85 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -172,7 +172,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	 * Y-tiling is not supported in IF-ID Interlace mode in
 	 * GEN9 and above.
 	 */
-	if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
+	if (state->fb && IS_GEN_GTE(dev_priv, 9) && crtc_state->base.enable &&
 	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		if (state->fb->modifier == I915_FORMAT_MOD_Y_TILED ||
 		    state->fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index ff455c724775..f8705138bf4a 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -704,7 +704,7 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
-	} else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
+	} else if (IS_HASWELL(dev_priv) || IS_GEN_GTE(dev_priv, 8)) {
 		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
 		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index aab6d1538fff..b13fb999340c 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1895,7 +1895,7 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
 				     int pixel_rate)
 {
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN_GTE(dev_priv, 10))
 		return DIV_ROUND_UP(pixel_rate, 2);
 	else if (IS_GEMINILAKE(dev_priv))
 		/*
@@ -1950,7 +1950,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	/* According to BSpec, "The CD clock frequency must be at least twice
 	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
 	 */
-	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
+	if (crtc_state->has_audio && IS_GEN_GTE(dev_priv, 9))
 		min_cdclk = max(2 * 96000, min_cdclk);
 
 	/*
@@ -2220,7 +2220,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 {
 	int max_cdclk_freq = dev_priv->max_cdclk_freq;
 
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN_GTE(dev_priv, 10))
 		return 2 * max_cdclk_freq;
 	else if (IS_GEMINILAKE(dev_priv))
 		/*
@@ -2233,7 +2233,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 		return max_cdclk_freq;
 	else if (IS_CHERRYVIEW(dev_priv))
 		return max_cdclk_freq*95/100;
-	else if (INTEL_GEN(dev_priv) < 4)
+	else if (IS_GEN_LT(dev_priv, 4))
 		return 2*max_cdclk_freq*90/100;
 	else
 		return max_cdclk_freq*90/100;
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index aa66e952a95d..31c9a5b62297 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -222,7 +222,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
 	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
 	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
 
-	if (INTEL_GEN(dev_priv) > 6) {
+	if (IS_GEN_GT(dev_priv, 6)) {
 		uint16_t postoff = 0;
 
 		if (intel_crtc_state->limited_color_range)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 1cd4a7c22bd5..871576790668 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -154,7 +154,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
 	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 	u32 adpa;
 
-	if (INTEL_GEN(dev_priv) >= 5)
+	if (IS_GEN_GTE(dev_priv, 5))
 		adpa = ADPA_HOTPLUG_BITS;
 	else
 		adpa = 0;
@@ -799,7 +799,7 @@ intel_crt_detect(struct drm_connector *connector,
 	if (ret > 0) {
 		if (intel_crt_detect_ddc(connector))
 			status = connector_status_connected;
-		else if (INTEL_GEN(dev_priv) < 4)
+		else if (IS_GEN_LT(dev_priv, 4))
 			status = intel_crt_load_detect(crt,
 				to_intel_crtc(connector->state->crtc)->pipe);
 		else if (i915_modparams.load_detect_test)
@@ -854,7 +854,7 @@ void intel_crt_reset(struct drm_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 	struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 
-	if (INTEL_GEN(dev_priv) >= 5) {
+	if (IS_GEN_GTE(dev_priv, 5)) {
 		u32 adpa;
 
 		adpa = I915_READ(crt->adpa_reg);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8ca376aca8bd..5ae9cd02cd39 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1458,7 +1458,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	if (INTEL_GEN(dev_priv) <= 8)
+	if (IS_GEN_LTE(dev_priv, 8))
 		hsw_ddi_clock_get(encoder, pipe_config);
 	else if (IS_GEN9_BC(dev_priv))
 		skl_ddi_clock_get(encoder, pipe_config);
@@ -2152,7 +2152,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 
 		I915_WRITE(DPLL_CTRL2, val);
 
-	} else if (INTEL_GEN(dev_priv) < 9) {
+	} else if (IS_GEN_LT(dev_priv, 9)) {
 		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
 	}
 
@@ -2170,7 +2170,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 	else if (IS_GEN9_BC(dev_priv))
 		I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
 			   DPLL_CTRL2_DDI_CLK_OFF(port));
-	else if (INTEL_GEN(dev_priv) < 9)
+	else if (IS_GEN_LT(dev_priv, 9))
 		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
 }
 
@@ -2207,7 +2207,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	if (!is_mst)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	intel_dp_start_link_train(intel_dp);
-	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
+	if (port != PORT_A || IS_GEN_GTE(dev_priv, 9))
 		intel_dp_stop_link_train(intel_dp);
 }
 
@@ -2409,7 +2409,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	enum port port = encoder->port;
 
-	if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
+	if (port == PORT_A && IS_GEN_LT(dev_priv, 9))
 		intel_dp_stop_link_train(intel_dp);
 
 	intel_edp_backlight_on(crtc_state, conn_state);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index ae6f5b7b7978..068705c91332 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -380,7 +380,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 	u32 f19_2_mhz = 19200;
 	u32 f24_mhz = 24000;
 
-	if (INTEL_GEN(dev_priv) <= 4) {
+	if (IS_GEN_LTE(dev_priv, 4)) {
 		/* PRMs say:
 		 *
 		 *     "The value in this register increments once every 16
@@ -388,7 +388,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 		 *      (“CLKCFG”) MCHBAR register)
 		 */
 		return dev_priv->rawclk_freq / 16;
-	} else if (INTEL_GEN(dev_priv) <= 8) {
+	} else if (IS_GEN_LTE(dev_priv, 8)) {
 		/* PRMs say:
 		 *
 		 *     "The PCU TSC counts 10ns increments; this timestamp
@@ -396,7 +396,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 		 *      rolling over every 1.5 hours).
 		 */
 		return f12_5_mhz;
-	} else if (INTEL_GEN(dev_priv) <= 9) {
+	} else if (IS_GEN_LTE(dev_priv, 9)) {
 		u32 ctc_reg = I915_READ(CTC_MODE);
 		u32 freq = 0;
 
@@ -414,7 +414,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 		}
 
 		return freq;
-	} else if (INTEL_GEN(dev_priv) <= 10) {
+	} else if (IS_GEN_LTE(dev_priv, 10)) {
 		u32 ctc_reg = I915_READ(CTC_MODE);
 		u32 freq = 0;
 		u32 rpm_config_reg = 0;
@@ -480,7 +480,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 		container_of(info, struct drm_i915_private, info);
 	enum pipe pipe;
 
-	if (INTEL_GEN(dev_priv) >= 10) {
+	if (IS_GEN_GTE(dev_priv, 10)) {
 		for_each_pipe(dev_priv, pipe)
 			info->num_scalers[pipe] = 2;
 	} else if (IS_GEN9(dev_priv)) {
@@ -507,7 +507,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		for_each_pipe(dev_priv, pipe)
 			info->num_sprites[pipe] = 2;
-	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
+	} else if (IS_GEN_GTE(dev_priv, 5) || IS_G4X(dev_priv)) {
 		for_each_pipe(dev_priv, pipe)
 			info->num_sprites[pipe] = 1;
 	}
@@ -580,7 +580,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 		broadwell_sseu_info_init(dev_priv);
 	else if (IS_GEN9(dev_priv))
 		gen9_sseu_info_init(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 10)
+	else if (IS_GEN_GTE(dev_priv, 10))
 		gen10_sseu_info_init(dev_priv);
 
 	/* Initialize command stream timestamp frequency */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0d5207dbfdac..00efc4e6b7ce 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1044,7 +1044,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN_GTE(dev_priv, 4)) {
 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 		i915_reg_t reg = PIPECONF(cpu_transcoder);
 
@@ -1542,7 +1542,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
 	POSTING_READ(reg);
 	udelay(150);
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN_GTE(dev_priv, 4)) {
 		I915_WRITE(DPLL_MD(crtc->pipe),
 			   crtc_state->dpll_hw_state.dpll_md);
 	} else {
@@ -2029,12 +2029,12 @@ static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_pr
 
 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		return 256 * 1024;
 	else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
 		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return 128 * 1024;
-	else if (INTEL_GEN(dev_priv) >= 4)
+	else if (IS_GEN_GTE(dev_priv, 4))
 		return 4 * 1024;
 	else
 		return 0;
@@ -2053,7 +2053,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 	case DRM_FORMAT_MOD_LINEAR:
 		return intel_linear_alignment(dev_priv);
 	case I915_FORMAT_MOD_X_TILED:
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN_GTE(dev_priv, 9))
 			return 256 * 1024;
 		return 0;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
@@ -3163,7 +3163,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
 
-	if (INTEL_GEN(dev_priv) < 4)
+	if (IS_GEN_LT(dev_priv, 4))
 		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
 
 	switch (fb->format->format) {
@@ -3193,7 +3193,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
 		return 0;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 4 &&
+	if (IS_GEN_GTE(dev_priv, 4) &&
 	    fb->modifier == I915_FORMAT_MOD_X_TILED)
 		dspcntr |= DISPPLANE_TILED;
 
@@ -3216,7 +3216,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
 
 	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		offset = intel_compute_tile_offset(&src_x, &src_y,
 						   plane_state, 0);
 	else
@@ -3260,14 +3260,14 @@ static void i9xx_update_plane(struct intel_plane *plane,
 
 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		dspaddr_offset = plane_state->main.offset;
 	else
 		dspaddr_offset = linear_offset;
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	if (INTEL_GEN(dev_priv) < 4) {
+	if (IS_GEN_LT(dev_priv, 4)) {
 		/* pipesrc and dspsize control the size that is scaled from,
 		 * which should always be the user's requested size.
 		 */
@@ -3291,7 +3291,7 @@ static void i9xx_update_plane(struct intel_plane *plane,
 			      intel_plane_ggtt_offset(plane_state) +
 			      dspaddr_offset);
 		I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
-	} else if (INTEL_GEN(dev_priv) >= 4) {
+	} else if (IS_GEN_GTE(dev_priv, 4)) {
 		I915_WRITE_FW(DSPSURF(i9xx_plane),
 			      intel_plane_ggtt_offset(plane_state) +
 			      dspaddr_offset);
@@ -3317,7 +3317,7 @@ static void i9xx_disable_plane(struct intel_plane *plane,
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
 	I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
 	else
 		I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
@@ -3538,7 +3538,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 
 	plane_ctl = PLANE_CTL_ENABLE;
 
-	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
+	if (IS_GEN_LT(dev_priv, 10) && !IS_GEMINILAKE(dev_priv)) {
 		plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
 		plane_ctl |=
 			PLANE_CTL_PIPE_GAMMA_ENABLE |
@@ -3550,7 +3550,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 	plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
 	plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
 
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN_GTE(dev_priv, 10))
 		plane_ctl |= cnl_plane_ctl_flip(rotation &
 						DRM_MODE_REFLECT_MASK);
 
@@ -3618,7 +3618,7 @@ __intel_display_resume(struct drm_device *dev,
 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
 {
 	return intel_has_gpu_reset(dev_priv) &&
-		INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
+		IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv);
 }
 
 void intel_prepare_reset(struct drm_i915_private *dev_priv)
@@ -3757,7 +3757,7 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
 		   (new_crtc_state->pipe_src_h - 1));
 
 	/* on skylake this is done by detaching scalers */
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		skl_detach_scalers(crtc);
 
 		if (new_crtc_state->pch_pfit.enabled)
@@ -4683,7 +4683,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 	 * Once NV12 is enabled, handle it here while allocating scaler
 	 * for NV12.
 	 */
-	if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
+	if (IS_GEN_GTE(dev_priv, 9) && crtc_state->base.enable &&
 	    need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
 		return -EINVAL;
@@ -5477,7 +5477,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (psl_clkgate_wa)
 		glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		skylake_pfit_enable(intel_crtc);
 	else
 		ironlake_pfit_enable(intel_crtc);
@@ -5623,7 +5623,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		skylake_scaler_disable(intel_crtc);
 	else
 		ironlake_pfit_disable(intel_crtc, false);
@@ -6307,7 +6307,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
 	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	/* GDG double wide on either pipe, otherwise pipe A only */
-	return INTEL_GEN(dev_priv) < 4 &&
+	return IS_GEN_LT(dev_priv, 4) &&
 		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
 }
 
@@ -6367,7 +6367,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	int clock_limit = dev_priv->max_dotclk_freq;
 
-	if (INTEL_GEN(dev_priv) < 4) {
+	if (IS_GEN_LT(dev_priv, 4)) {
 		clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
 
 		/*
@@ -6420,7 +6420,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
 	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
 	 */
-	if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
+	if ((IS_GEN_GT(dev_priv, 4) || IS_G4X(dev_priv)) &&
 		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
 		return -EINVAL;
 
@@ -6577,7 +6577,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 	int pipe = crtc->pipe;
 	enum transcoder transcoder = crtc->config->cpu_transcoder;
 
-	if (INTEL_GEN(dev_priv) >= 5) {
+	if (IS_GEN_GTE(dev_priv, 5)) {
 		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
 		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
 		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
@@ -6587,7 +6587,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 		 * registers are not unnecessarily accessed).
 		 */
 		if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
-		    INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
+		    IS_GEN_LT(dev_priv, 8)) && crtc->config->has_drrs) {
 			I915_WRITE(PIPE_DATA_M2(transcoder),
 					TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
 			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
@@ -6971,7 +6971,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
 		break;
 	}
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
 
 	if (crtc_state->sdvo_tv_clock)
@@ -6985,7 +6985,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
 	dpll |= DPLL_VCO_ENABLE;
 	crtc_state->dpll_hw_state.dpll = dpll;
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN_GTE(dev_priv, 4)) {
 		u32 dpll_md = (crtc_state->pixel_multiplier - 1)
 			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
 		crtc_state->dpll_hw_state.dpll_md = dpll_md;
@@ -7058,7 +7058,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
 			vsyncshift += adjusted_mode->crtc_htotal;
 	}
 
-	if (INTEL_GEN(dev_priv) > 3)
+	if (IS_GEN_GT(dev_priv, 3))
 		I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
 
 	I915_WRITE(HTOTAL(cpu_transcoder),
@@ -7217,7 +7217,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 	}
 
 	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
-		if (INTEL_GEN(dev_priv) < 4 ||
+		if (IS_GEN_LT(dev_priv, 4) ||
 		    intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
 			pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
 		else
@@ -7428,7 +7428,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	uint32_t tmp;
 
-	if (INTEL_GEN(dev_priv) <= 3 &&
+	if (IS_GEN_LTE(dev_priv, 3) &&
 	    (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
 		return;
 
@@ -7437,7 +7437,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
 		return;
 
 	/* Check whether the pfit is attached to our pipe. */
-	if (INTEL_GEN(dev_priv) < 4) {
+	if (IS_GEN_LT(dev_priv, 4)) {
 		if (crtc->pipe != PIPE_B)
 			return;
 	} else {
@@ -7506,7 +7506,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(DSPCNTR(i9xx_plane));
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN_GTE(dev_priv, 4)) {
 		if (val & DISPPLANE_TILED) {
 			plane_config->tiling = I915_TILING_X;
 			fb->modifier = I915_FORMAT_MOD_X_TILED;
@@ -7520,7 +7520,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		offset = I915_READ(DSPOFFSET(i9xx_plane));
 		base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
-	} else if (INTEL_GEN(dev_priv) >= 4) {
+	} else if (IS_GEN_GTE(dev_priv, 4)) {
 		if (plane_config->tiling)
 			offset = I915_READ(DSPTILEOFF(i9xx_plane));
 		else
@@ -7626,7 +7626,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
 		pipe_config->limited_color_range = true;
 
-	if (INTEL_GEN(dev_priv) < 4)
+	if (IS_GEN_LT(dev_priv, 4))
 		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
 
 	intel_get_pipe_timings(crtc, pipe_config);
@@ -7634,7 +7634,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 
 	i9xx_get_pfit_config(crtc, pipe_config);
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN_GTE(dev_priv, 4)) {
 		/* No way to read it out on pipes B and C */
 		if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
 			tmp = dev_priv->chv_dpll_md[crtc->pipe];
@@ -8194,7 +8194,7 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_crtc_state *config = intel_crtc->config;
 
-	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
+	if (IS_BROADWELL(dev_priv) || IS_GEN_GTE(dev_priv, 9)) {
 		u32 val = 0;
 
 		switch (intel_crtc->config->pipe_bpp) {
@@ -8425,7 +8425,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
-	if (INTEL_GEN(dev_priv) >= 5) {
+	if (IS_GEN_GTE(dev_priv, 5)) {
 		m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
 		m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
 		m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
@@ -8437,7 +8437,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
 		 * gen < 8) and if DRRS is supported (to make sure the
 		 * registers are not unnecessarily read).
 		 */
-		if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
+		if (m2_n2 && IS_GEN_LT(dev_priv, 8) &&
 			crtc->config->has_drrs) {
 			m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
 			m2_n2->link_n =	I915_READ(PIPE_LINK_N2(transcoder));
@@ -8536,12 +8536,12 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(PLANE_CTL(pipe, plane_id));
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_GEN_GTE(dev_priv, 11))
 		pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
 	else
 		pixel_format = val & PLANE_CTL_FORMAT_MASK;
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) {
 		alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
 		alpha &= PLANE_COLOR_ALPHA_MASK;
 	} else {
@@ -9188,7 +9188,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 	 * DDI E. So just check whether this pipe is wired to DDI E and whether
 	 * the PCH transcoder is on.
 	 */
-	if (INTEL_GEN(dev_priv) < 9 &&
+	if (IS_GEN_LT(dev_priv, 9) &&
 	    (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
 		pipe_config->has_pch_encoder = true;
 
@@ -9238,11 +9238,11 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->gamma_mode =
 		I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
 
-	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
+	if (IS_BROADWELL(dev_priv) || IS_GEN_GTE(dev_priv, 9)) {
 		u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
 		bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
 
-		if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
+		if (IS_GEMINILAKE(dev_priv) || IS_GEN_GTE(dev_priv, 10)) {
 			bool blend_mode_420 = tmp &
 					      PIPEMISC_YUV420_MODE_FULL_BLEND;
 
@@ -9258,7 +9258,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
 	if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
 		power_domain_mask |= BIT_ULL(power_domain);
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN_GTE(dev_priv, 9))
 			skylake_get_pfit_config(crtc, pipe_config);
 		else
 			ironlake_get_pfit_config(crtc, pipe_config);
@@ -10227,7 +10227,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
 	struct drm_framebuffer *fb = plane_state->fb;
 	int ret;
 
-	if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
+	if (IS_GEN_GTE(dev_priv, 9) && plane->id != PLANE_CURSOR) {
 		ret = skl_update_scaler_plane(
 			to_intel_crtc_state(crtc_state),
 			to_intel_plane_state(plane_state));
@@ -10276,21 +10276,21 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
 			 turn_off, turn_on, mode_changed);
 
 	if (turn_on) {
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
+		if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv))
 			pipe_config->update_wm_pre = true;
 
 		/* must disable cxsr around plane enable/disable */
 		if (plane->id != PLANE_CURSOR)
 			pipe_config->disable_cxsr = true;
 	} else if (turn_off) {
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
+		if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv))
 			pipe_config->update_wm_post = true;
 
 		/* must disable cxsr around plane enable/disable */
 		if (plane->id != PLANE_CURSOR)
 			pipe_config->disable_cxsr = true;
 	} else if (intel_wm_need_update(&plane->base, plane_state)) {
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
+		if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv)) {
 			/* FIXME bollocks */
 			pipe_config->update_wm_pre = true;
 			pipe_config->update_wm_post = true;
@@ -10407,11 +10407,11 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
 			return ret;
 		}
 	} else if (dev_priv->display.compute_intermediate_wm) {
-		if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
+		if (HAS_PCH_SPLIT(dev_priv) && IS_GEN_LT(dev_priv, 9))
 			pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		if (mode_changed)
 			ret = skl_update_scaler_crtc(pipe_config);
 
@@ -10499,7 +10499,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
 	if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
 	    IS_CHERRYVIEW(dev_priv)))
 		bpp = 10*3;
-	else if (INTEL_GEN(dev_priv) >= 5)
+	else if (IS_GEN_GTE(dev_priv, 5))
 		bpp = 12*3;
 	else
 		bpp = 8*3;
@@ -10641,7 +10641,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
 		      pipe_config->pipe_src_w, pipe_config->pipe_src_h,
 		      pipe_config->pixel_rate);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
 			      crtc->num_scalers,
 			      pipe_config->scaler_state.scaler_users,
@@ -10682,7 +10682,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
 			      plane->base.id, plane->name,
 			      fb->base.id, fb->width, fb->height,
 			      drm_get_format_name(fb->format->format, &format_name));
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN_GTE(dev_priv, 9))
 			DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
 				      state->scaler_id,
 				      state->base.src.x1 >> 16,
@@ -11167,7 +11167,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 	PIPE_CONF_CHECK_I(lane_count);
 	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
 
-	if (INTEL_GEN(dev_priv) < 8) {
+	if (IS_GEN_LT(dev_priv, 8)) {
 		PIPE_CONF_CHECK_M_N(dp_m_n);
 
 		if (current_config->has_drrs)
@@ -11193,7 +11193,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 
 	PIPE_CONF_CHECK_I(pixel_multiplier);
 	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
-	if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
+	if ((IS_GEN_LT(dev_priv, 8) && !IS_HASWELL(dev_priv)) ||
 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		PIPE_CONF_CHECK_BOOL(limited_color_range);
 
@@ -11220,7 +11220,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 
 	PIPE_CONF_CHECK_X(gmch_pfit.control);
 	/* pfit ratios are autocomputed by the hw on gen4+ */
-	if (INTEL_GEN(dev_priv) < 4)
+	if (IS_GEN_LT(dev_priv, 4))
 		PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
 	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
 
@@ -11266,7 +11266,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
 	PIPE_CONF_CHECK_X(dsi_pll.div);
 
-	if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
+	if (IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5))
 		PIPE_CONF_CHECK_I(pipe_bpp);
 
 	PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
@@ -11316,7 +11316,7 @@ static void verify_wm_state(struct drm_crtc *crtc,
 	const enum pipe pipe = intel_crtc->pipe;
 	int plane, level, max_level = ilk_wm_max_level(dev_priv);
 
-	if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
+	if (IS_GEN_LT(dev_priv, 9) || !new_state->active)
 		return;
 
 	skl_pipe_wm_get_hw_state(crtc, &hw_wm);
@@ -12293,7 +12293,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 				 *
 				 * No clue what this is supposed to achieve.
 				 */
-				if (INTEL_GEN(dev_priv) >= 9)
+				if (IS_GEN_GTE(dev_priv, 9))
 					dev_priv->display.initial_watermarks(intel_state,
 									     to_intel_crtc_state(new_crtc_state));
 			}
@@ -12485,7 +12485,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 	 * FIXME doing watermarks and fb cleanup from a vblank worker
 	 * (assuming we had any) would solve these problems.
 	 */
-	if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
+	if (IS_GEN_LT(dev_priv, 9) && state->legacy_cursor_update) {
 		struct intel_crtc_state *new_crtc_state;
 		struct intel_crtc *crtc;
 		int i;
@@ -12592,7 +12592,7 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
 	if (!dma_fence_is_i915(fence))
 		return;
 
-	if (INTEL_GEN(to_i915(crtc->dev)) < 6)
+	if (IS_GEN_LT(to_i915(crtc->dev), 6))
 		return;
 
 	if (drm_crtc_vblank_get(crtc))
@@ -12770,7 +12770,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
 	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
 	max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
 
-	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEMINILAKE(dev_priv) || IS_GEN_GTE(dev_priv, 10))
 		max_dotclk *= 2;
 
 	if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
@@ -12801,7 +12801,7 @@ intel_check_primary_plane(struct intel_plane *plane,
 	struct drm_rect clip = {};
 	int ret;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		/* use scaler when colorkey is not required */
 		if (!state->ckey.flags) {
 			min_scale = 1;
@@ -12825,7 +12825,7 @@ intel_check_primary_plane(struct intel_plane *plane,
 	if (!state->base.fb)
 		return 0;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		ret = skl_check_plane_surface(crtc_state, state);
 		if (ret)
 			return ret;
@@ -12839,7 +12839,7 @@ intel_check_primary_plane(struct intel_plane *plane,
 		state->ctl = i9xx_plane_ctl(crtc_state, state);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
 		state->color_ctl = glk_plane_color_ctl(crtc_state, state);
 
 	return 0;
@@ -12874,7 +12874,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
 
 	if (intel_cstate->update_pipe)
 		intel_update_pipe_config(old_intel_cstate, intel_cstate);
-	else if (INTEL_GEN(dev_priv) >= 9)
+	else if (IS_GEN_GTE(dev_priv, 9))
 		skl_detach_scalers(intel_crtc);
 
 out:
@@ -12998,9 +12998,9 @@ static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
 	    modifier != DRM_FORMAT_MOD_LINEAR)
 		return false;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		return skl_mod_supported(format, modifier);
-	else if (INTEL_GEN(dev_priv) >= 4)
+	else if (IS_GEN_GTE(dev_priv, 4))
 		return i965_mod_supported(format, modifier);
 	else
 		return i8xx_mod_supported(format, modifier);
@@ -13197,7 +13197,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 	primary->can_scale = false;
 	primary->max_downscale = 1;
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		primary->can_scale = true;
 		state->scaler_id = -1;
 	}
@@ -13206,7 +13206,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 	 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
 	 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
 	 */
-	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
+	if (HAS_FBC(dev_priv) && IS_GEN_LT(dev_priv, 4))
 		primary->i9xx_plane = (enum i9xx_plane_id) !pipe;
 	else
 		primary->i9xx_plane = (enum i9xx_plane_id) pipe;
@@ -13214,7 +13214,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 	primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
 	primary->check_plane = intel_check_primary_plane;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		intel_primary_formats = skl_primary_formats;
 		num_formats = ARRAY_SIZE(skl_primary_formats);
 
@@ -13226,7 +13226,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		primary->update_plane = skl_update_plane;
 		primary->disable_plane = skl_disable_plane;
 		primary->get_hw_state = skl_plane_get_hw_state;
-	} else if (INTEL_GEN(dev_priv) >= 4) {
+	} else if (IS_GEN_GTE(dev_priv, 4)) {
 		intel_primary_formats = i965_primary_formats;
 		num_formats = ARRAY_SIZE(i965_primary_formats);
 		modifiers = i9xx_format_modifiers;
@@ -13244,14 +13244,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		primary->get_hw_state = i9xx_plane_get_hw_state;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
 					       0, &intel_plane_funcs,
 					       intel_primary_formats, num_formats,
 					       modifiers,
 					       DRM_PLANE_TYPE_PRIMARY,
 					       "plane 1%c", pipe_name(pipe));
-	else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
+	else if (IS_GEN_GTE(dev_priv, 5) || IS_G4X(dev_priv))
 		ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
 					       0, &intel_plane_funcs,
 					       intel_primary_formats, num_formats,
@@ -13269,12 +13269,12 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 	if (ret)
 		goto fail;
 
-	if (INTEL_GEN(dev_priv) >= 10) {
+	if (IS_GEN_GTE(dev_priv, 10)) {
 		supported_rotations =
 			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
 			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
 			DRM_MODE_REFLECT_X;
-	} else if (INTEL_GEN(dev_priv) >= 9) {
+	} else if (IS_GEN_GTE(dev_priv, 9)) {
 		supported_rotations =
 			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
 			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
@@ -13282,14 +13282,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		supported_rotations =
 			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
 			DRM_MODE_REFLECT_X;
-	} else if (INTEL_GEN(dev_priv) >= 4) {
+	} else if (IS_GEN_GTE(dev_priv, 4)) {
 		supported_rotations =
 			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
 	} else {
 		supported_rotations = DRM_MODE_ROTATE_0;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		drm_plane_create_rotation_property(&primary->base,
 						   DRM_MODE_ROTATE_0,
 						   supported_rotations);
@@ -13362,13 +13362,13 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
 	if (ret)
 		goto fail;
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		drm_plane_create_rotation_property(&cursor->base,
 						   DRM_MODE_ROTATE_0,
 						   DRM_MODE_ROTATE_0 |
 						   DRM_MODE_ROTATE_180);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		state->scaler_id = -1;
 
 	drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
@@ -13548,7 +13548,7 @@ static bool has_edp_a(struct drm_i915_private *dev_priv)
 
 static bool intel_crt_present(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		return false;
 
 	if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
@@ -13929,7 +13929,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 		/* fall through */
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Yf_TILED:
-		if (INTEL_GEN(dev_priv) < 9) {
+		if (IS_GEN_LT(dev_priv, 9)) {
 			DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
 				      mode_cmd->modifier[0]);
 			goto err;
@@ -13947,7 +13947,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 	 * gen2/3 display engine uses the fence if present,
 	 * so the tiling mode must match the fb modifier exactly.
 	 */
-	if (INTEL_GEN(dev_priv) < 4 &&
+	if (IS_GEN_LT(dev_priv, 4) &&
 	    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
 		DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
 		goto err;
@@ -13981,7 +13981,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 	case DRM_FORMAT_ARGB8888:
 		break;
 	case DRM_FORMAT_XRGB1555:
-		if (INTEL_GEN(dev_priv) > 3) {
+		if (IS_GEN_GT(dev_priv, 3)) {
 			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 			goto err;
@@ -13989,7 +13989,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 		break;
 	case DRM_FORMAT_ABGR8888:
 		if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
-		    INTEL_GEN(dev_priv) < 9) {
+		    IS_GEN_LT(dev_priv, 9)) {
 			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 			goto err;
@@ -13998,7 +13998,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_XBGR2101010:
-		if (INTEL_GEN(dev_priv) < 4) {
+		if (IS_GEN_LT(dev_priv, 4)) {
 			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 			goto err;
@@ -14015,7 +14015,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_VYUY:
-		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
+		if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv)) {
 			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
 			goto err;
@@ -14162,7 +14162,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
 {
 	intel_init_cdclk_hooks(dev_priv);
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			skylake_get_initial_plane_config;
@@ -14241,7 +14241,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		dev_priv->display.update_crtcs = skl_update_crtcs;
 	else
 		dev_priv->display.update_crtcs = intel_update_crtcs;
@@ -14774,7 +14774,7 @@ intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
 {
 	struct intel_crtc *crtc;
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		return;
 
 	for_each_intel_crtc(&dev_priv->drm, crtc) {
@@ -15210,7 +15210,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		vlv_wm_get_hw_state(dev);
 		vlv_wm_sanitize(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 9) {
+	} else if (IS_GEN_GTE(dev_priv, 9)) {
 		skl_wm_get_hw_state(dev);
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		ilk_wm_get_hw_state(dev);
@@ -15361,7 +15361,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
  */
 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
 {
-	unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
+	unsigned reg = IS_GEN_GTE(dev_priv, 6) ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
 	u16 gmch_ctrl;
 
 	if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
@@ -15467,13 +15467,13 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
 
 		error->plane[i].control = I915_READ(DSPCNTR(i));
 		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
-		if (INTEL_GEN(dev_priv) <= 3) {
+		if (IS_GEN_LTE(dev_priv, 3)) {
 			error->plane[i].size = I915_READ(DSPSIZE(i));
 			error->plane[i].pos = I915_READ(DSPPOS(i));
 		}
-		if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
+		if (IS_GEN_LTE(dev_priv, 7) && !IS_HASWELL(dev_priv))
 			error->plane[i].addr = I915_READ(DSPADDR(i));
-		if (INTEL_GEN(dev_priv) >= 4) {
+		if (IS_GEN_GTE(dev_priv, 4)) {
 			error->plane[i].surface = I915_READ(DSPSURF(i));
 			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
 		}
@@ -15538,13 +15538,13 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
 		err_printf(m, "Plane [%d]:\n", i);
 		err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
 		err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
-		if (INTEL_GEN(dev_priv) <= 3) {
+		if (IS_GEN_LTE(dev_priv, 3)) {
 			err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
 			err_printf(m, "  POS: %08x\n", error->plane[i].pos);
 		}
-		if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
+		if (IS_GEN_LTE(dev_priv, 7) && !IS_HASWELL(dev_priv))
 			err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
-		if (INTEL_GEN(dev_priv) >= 4) {
+		if (IS_GEN_GTE(dev_priv, 4)) {
 			err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
 			err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
 		}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index abbe1e4e0af5..319d0d00f4ca 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1467,7 +1467,7 @@ static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
 				    enum port port)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		return skl_aux_ctl_reg(dev_priv, port);
 	else if (HAS_PCH_SPLIT(dev_priv))
 		return ilk_aux_ctl_reg(dev_priv, port);
@@ -1478,7 +1478,7 @@ static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
 				     enum port port, int index)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		return skl_aux_data_reg(dev_priv, port, index);
 	else if (HAS_PCH_SPLIT(dev_priv))
 		return ilk_aux_data_reg(dev_priv, port, index);
@@ -1726,7 +1726,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 		intel_fixed_panel_mode(panel_mode, adjusted_mode);
 
-		if (INTEL_GEN(dev_priv) >= 9) {
+		if (IS_GEN_GTE(dev_priv, 9)) {
 			int ret;
 			ret = skl_update_scaler_crtc(pipe_config);
 			if (ret)
@@ -3208,7 +3208,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 	enum port port = dp_to_dig_port(intel_dp)->base.port;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 		return intel_ddi_dp_voltage_max(encoder);
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
@@ -3227,7 +3227,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 	enum port port = dp_to_dig_port(intel_dp)->base.port;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
 			return DP_TRAIN_PRE_EMPH_LEVEL_3;
@@ -3760,7 +3760,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
 		DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9 &&
+	if (IS_GEN_GTE(dev_priv, 9) &&
 	    (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
 		uint8_t frame_sync_cap;
 
@@ -5468,10 +5468,10 @@ bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
 	 * eDP not supported on g4x. so bail out early just
 	 * for a bit extra safety in case the VBT is bonkers.
 	 */
-	if (INTEL_GEN(dev_priv) < 5)
+	if (IS_GEN_LT(dev_priv, 5))
 		return false;
 
-	if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
+	if (IS_GEN_LT(dev_priv, 9) && port == PORT_A)
 		return true;
 
 	return intel_bios_is_port_edp(dev_priv, port);
@@ -5830,7 +5830,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
 		return;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
+	if (IS_GEN_GTE(dev_priv, 8) && !IS_CHERRYVIEW(dev_priv)) {
 		switch (index) {
 		case DRRS_HIGH_RR:
 			intel_dp_set_m_n(intel_crtc, M1_N1);
@@ -5842,7 +5842,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
 		default:
 			DRM_ERROR("Unsupported refreshrate type\n");
 		}
-	} else if (INTEL_GEN(dev_priv) > 6) {
+	} else if (IS_GEN_GT(dev_priv, 6)) {
 		i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
 		u32 val;
 
@@ -6115,7 +6115,7 @@ intel_dp_drrs_init(struct intel_connector *connector,
 	INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
 	mutex_init(&dev_priv->drrs.mutex);
 
-	if (INTEL_GEN(dev_priv) <= 6) {
+	if (IS_GEN_LTE(dev_priv, 6)) {
 		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
 		return NULL;
 	}
@@ -6353,7 +6353,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	intel_dp->active_pipe = INVALID_PIPE;
 
 	/* intel_dp vfuncs */
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
@@ -6362,7 +6362,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	else
 		intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
 	else
 		intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
@@ -6501,7 +6501,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
 		intel_encoder->enable = vlv_enable_dp;
 		intel_encoder->disable = vlv_disable_dp;
 		intel_encoder->post_disable = vlv_post_disable_dp;
-	} else if (INTEL_GEN(dev_priv) >= 5) {
+	} else if (IS_GEN_GTE(dev_priv, 5)) {
 		intel_encoder->pre_enable = g4x_pre_enable_dp;
 		intel_encoder->enable = g4x_enable_dp;
 		intel_encoder->disable = ilk_disable_dp;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 51c5ae4e9116..7bde6b9853e3 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -210,7 +210,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
 	unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
 
 	/* PCH only available on ILK+ */
-	if (INTEL_GEN(dev_priv) < 5)
+	if (IS_GEN_LT(dev_priv, 5))
 		return;
 
 	if (pll == NULL)
@@ -1860,7 +1860,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (INTEL_GEN(dev_priv) < 9) {
+	if (IS_GEN_LT(dev_priv, 9)) {
 		uint32_t val = I915_READ(LCPLL_CTL);
 
 		/*
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 7eebfbb95e89..9706bd8d9e77 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -193,7 +193,7 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
 	case VIDEO_DECODE_CLASS:
 	case VIDEO_ENHANCEMENT_CLASS:
 	case COPY_ENGINE_CLASS:
-		if (INTEL_GEN(dev_priv) < 8)
+		if (IS_GEN_LT(dev_priv, 8))
 			return 0;
 		return GEN8_LR_CONTEXT_OTHER_SIZE;
 	}
@@ -696,10 +696,10 @@ u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	u64 acthd;
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN_GTE(dev_priv, 8))
 		acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 					 RING_ACTHD_UDW(engine->mmio_base));
-	else if (INTEL_GEN(dev_priv) >= 4)
+	else if (IS_GEN_GTE(dev_priv, 4))
 		acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 	else
 		acthd = I915_READ(ACTHD);
@@ -712,7 +712,7 @@ u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine)
 	struct drm_i915_private *dev_priv = engine->i915;
 	u64 bbaddr;
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN_GTE(dev_priv, 8))
 		bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
 					  RING_BBADDR_UDW(engine->mmio_base));
 	else
@@ -1472,7 +1472,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
 		idle = false;
 
 	/* No bit for gen2, so assume the CS parser is idle */
-	if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE))
+	if (IS_GEN_GT(dev_priv, 2) && !(I915_READ_MODE(engine) & MODE_IDLE))
 		idle = false;
 
 	intel_runtime_pm_put(dev_priv);
@@ -1777,7 +1777,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
 	drm_printf(m, "\tRING_CTL:   0x%08x%s\n",
 		   I915_READ(RING_CTL(engine->mmio_base)),
 		   I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
-	if (INTEL_GEN(engine->i915) > 2) {
+	if (IS_GEN_GT(engine->i915, 2)) {
 		drm_printf(m, "\tRING_MODE:  0x%08x%s\n",
 			   I915_READ(RING_MI_MODE(engine->mmio_base)),
 			   I915_READ(RING_MI_MODE(engine->mmio_base)) & (MODE_IDLE) ? " [idle]" : "");
@@ -1800,16 +1800,16 @@ void intel_engine_dump(struct intel_engine_cs *engine,
 	addr = intel_engine_get_last_batch_head(engine);
 	drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
 		   upper_32_bits(addr), lower_32_bits(addr));
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN_GTE(dev_priv, 8))
 		addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
 					RING_DMA_FADD_UDW(engine->mmio_base));
-	else if (INTEL_GEN(dev_priv) >= 4)
+	else if (IS_GEN_GTE(dev_priv, 4))
 		addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
 	else
 		addr = I915_READ(DMA_FADD_I8XX);
 	drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
 		   upper_32_bits(addr), lower_32_bits(addr));
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN_GTE(dev_priv, 4)) {
 		drm_printf(m, "\tIPEIR: 0x%08x\n",
 			   I915_READ(RING_IPEIR(engine->mmio_base)));
 		drm_printf(m, "\tIPEHR: 0x%08x\n",
@@ -1869,7 +1869,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
 		}
 		drm_printf(m, "\t\tHW active? 0x%x\n", execlists->active);
 		rcu_read_unlock();
-	} else if (INTEL_GEN(dev_priv) > 6) {
+	} else if (IS_GEN_GT(dev_priv, 6)) {
 		drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
 			   I915_READ(RING_PP_DIR_BASE(engine)));
 		drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
@@ -1899,7 +1899,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
 	}
 	spin_unlock_irq(&b->rb_lock);
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN_GTE(dev_priv, 6)) {
 		drm_printf(m, "\tRING_IMR: %08x\n", I915_READ_IMR(engine));
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 0ad854095c38..30da6085f84e 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -48,17 +48,17 @@ static inline bool fbc_supported(struct drm_i915_private *dev_priv)
 
 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
 {
-	return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
+	return IS_HASWELL(dev_priv) || IS_GEN_GTE(dev_priv, 8);
 }
 
 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) < 4;
+	return IS_GEN_LT(dev_priv, 4);
 }
 
 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) <= 3;
+	return IS_GEN_LTE(dev_priv, 3);
 }
 
 /*
@@ -96,7 +96,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
 	intel_fbc_get_plane_source_size(cache, NULL, &lines);
 	if (IS_GEN7(dev_priv))
 		lines = min(lines, 2048);
-	else if (INTEL_GEN(dev_priv) >= 8)
+	else if (IS_GEN_GTE(dev_priv, 8))
 		lines = min(lines, 2560);
 
 	/* Hardware needs the full buffer stride, not just the active area. */
@@ -357,7 +357,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 
 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 5)
+	if (IS_GEN_GTE(dev_priv, 5))
 		return ilk_fbc_is_active(dev_priv);
 	else if (IS_GM45(dev_priv))
 		return g4x_fbc_is_active(dev_priv);
@@ -371,9 +371,9 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 
 	fbc->active = true;
 
-	if (INTEL_GEN(dev_priv) >= 7)
+	if (IS_GEN_GTE(dev_priv, 7))
 		gen7_fbc_activate(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 5)
+	else if (IS_GEN_GTE(dev_priv, 5))
 		ilk_fbc_activate(dev_priv);
 	else if (IS_GM45(dev_priv))
 		g4x_fbc_activate(dev_priv);
@@ -387,7 +387,7 @@ static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 
 	fbc->active = false;
 
-	if (INTEL_GEN(dev_priv) >= 5)
+	if (IS_GEN_GTE(dev_priv, 5))
 		ilk_fbc_deactivate(dev_priv);
 	else if (IS_GM45(dev_priv))
 		g4x_fbc_deactivate(dev_priv);
@@ -568,7 +568,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
 
 	ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 						   4096, 0, end);
-	if (ret && INTEL_GEN(dev_priv) <= 4) {
+	if (ret && IS_GEN_LTE(dev_priv, 4)) {
 		return 0;
 	} else if (ret) {
 		compression_threshold <<= 1;
@@ -601,7 +601,7 @@ static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 
 	fbc->threshold = ret;
 
-	if (INTEL_GEN(dev_priv) >= 5)
+	if (IS_GEN_GTE(dev_priv, 5))
 		I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 	else if (IS_GM45(dev_priv)) {
 		I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
@@ -724,10 +724,10 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 	struct intel_fbc *fbc = &dev_priv->fbc;
 	unsigned int effective_w, effective_h, max_w, max_h;
 
-	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
+	if (IS_GEN_GTE(dev_priv, 8) || IS_HASWELL(dev_priv)) {
 		max_w = 4096;
 		max_h = 4096;
-	} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
+	} else if (IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5)) {
 		max_w = 4096;
 		max_h = 2048;
 	} else {
@@ -820,7 +820,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 		fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 		return false;
 	}
-	if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
+	if (IS_GEN_LTE(dev_priv, 4) && !IS_G4X(dev_priv) &&
 	    cache->plane.rotation != DRM_MODE_ROTATE_0) {
 		fbc->no_fbc_reason = "rotation unsupported";
 		return false;
@@ -1325,7 +1325,7 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
 	if (!HAS_FBC(dev_priv))
 		return 0;
 
-	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
+	if (IS_BROADWELL(dev_priv) || IS_GEN_GTE(dev_priv, 9))
 		return 1;
 
 	return 0;
@@ -1382,7 +1382,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
 	}
 
 	/* This value was pulled out of someone's hat */
-	if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
+	if (IS_GEN_LTE(dev_priv, 4) && !IS_GM45(dev_priv))
 		I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
 
 	/* We still don't have any sort of hardware state readout for FBC, so
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index 77c123cc8817..0521208041ab 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -264,7 +264,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 	else if (IS_GEN7(dev_priv))
 		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
-	else if (INTEL_GEN(dev_priv) >= 8)
+	else if (IS_GEN_GTE(dev_priv, 8))
 		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 
 	return old;
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
index 42e45ae87393..3e4db1c0329d 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -97,7 +97,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
 	 * ringbuffer itself.
 	 */
 	head = I915_READ_HEAD(engine) & HEAD_ADDR;
-	backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
+	backwards = (IS_GEN_GTE(dev_priv, 8)) ? 5 : 4;
 	vaddr = (void __iomem *)engine->buffer->vaddr;
 
 	for (i = backwards; i; --i) {
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 14ca5d3057a7..9c5ee2dae9fa 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -651,7 +651,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
 {
 	/* PORT E doesn't have HDCP, and PORT F is disabled */
-	return ((INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
+	return ((IS_GEN_GTE(dev_priv, 8) || IS_HASWELL(dev_priv)) &&
 		!IS_CHERRYVIEW(dev_priv) && port < PORT_E);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f5d7bfb43006..ea64df508052 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1481,11 +1481,11 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
 		&dev_priv->vbt.ddi_port_info[encoder->port];
 	int max_tmds_clock;
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
 		max_tmds_clock = 594000;
-	else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
+	else if (IS_GEN_GTE(dev_priv, 8) || IS_HASWELL(dev_priv))
 		max_tmds_clock = 300000;
-	else if (INTEL_GEN(dev_priv) >= 5)
+	else if (IS_GEN_GTE(dev_priv, 5))
 		max_tmds_clock = 225000;
 	else
 		max_tmds_clock = 165000;
@@ -1754,7 +1754,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 
 	pipe_config->lane_count = 4;
 
-	if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
+	if (scdc->scrambling.supported && (IS_GEN_GTE(dev_priv, 10) ||
 					   IS_GEMINILAKE(dev_priv))) {
 		if (scdc->scrambling.low_rates)
 			pipe_config->hdmi_scrambling = true;
@@ -2324,7 +2324,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 	connector->doublescan_allowed = 0;
 	connector->stereo_allowed = 1;
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
 		connector->ycbcr_420_allowed = true;
 
 	intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 380c0838d8b3..1a08f6bdaf50 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1488,7 +1488,7 @@ static void enable_execlists(struct intel_engine_cs *engine)
 	 * deeper FIFO it's not needed and it's not worth adding
 	 * more statements to the irq handler to support it.
 	 */
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_GEN_GTE(dev_priv, 11))
 		I915_WRITE(RING_MODE_GEN7(engine),
 			   _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
 	else
@@ -2057,7 +2057,7 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
 		engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
 	/* Override some for render ring. */
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		engine->init_hw = gen9_init_render_ring;
 	else
 		engine->init_hw = gen8_init_render_ring;
@@ -2100,7 +2100,7 @@ make_rpcs(struct drm_i915_private *dev_priv)
 	 * No explicit RPCS request is needed to ensure full
 	 * slice/subslice/EU enablement prior to Gen9.
 	*/
-	if (INTEL_GEN(dev_priv) < 9)
+	if (IS_GEN_LT(dev_priv, 9))
 		return 0;
 
 	/*
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 4677ac0b10d7..577385cb3c8d 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -139,12 +139,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
 
 	pipe_config->base.adjusted_mode.flags |= flags;
 
-	if (INTEL_GEN(dev_priv) < 5)
+	if (IS_GEN_LT(dev_priv, 5))
 		pipe_config->gmch_pfit.lvds_border_bits =
 			tmp & LVDS_BORDER_ENABLE;
 
 	/* gen2/3 store dither state in pfit control, needs to match */
-	if (INTEL_GEN(dev_priv) < 4) {
+	if (IS_GEN_LT(dev_priv, 4)) {
 		tmp = I915_READ(PFIT_CONTROL);
 
 		pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
@@ -189,7 +189,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 	/* Convert from 100ms to 100us units */
 	pps->t4 = val * 1000;
 
-	if (INTEL_GEN(dev_priv) <= 4 &&
+	if (IS_GEN_LTE(dev_priv, 4) &&
 	    pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 		DRM_DEBUG_KMS("Panel power timings uninitialized, "
 			      "setting defaults\n");
@@ -396,7 +396,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 	unsigned int lvds_bpp;
 
 	/* Should never happen!! */
-	if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
+	if (IS_GEN_LT(dev_priv, 4) && intel_crtc->pipe == 0) {
 		DRM_ERROR("Can't support LVDS on pipe A\n");
 		return false;
 	}
@@ -914,7 +914,7 @@ static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
 
 	/* Otherwise LVDS was only attached to mobile products,
 	 * except for the inglorious 830gm */
-	if (INTEL_GEN(dev_priv) <= 4 &&
+	if (IS_GEN_LTE(dev_priv, 4) &&
 	    IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
 		return true;
 
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index abb7a8c1e340..02b2768b556e 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -187,7 +187,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 		table->table = broxton_mocs_table;
 		result = true;
 	} else {
-		WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
+		WARN_ONCE(IS_GEN_GTE(dev_priv, 9),
 			  "Platform that should have a MOCS table does not.\n");
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 41e9465d44a8..752085a2a2d0 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -945,7 +945,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 	/* XXX: This is not the same logic as in the xorg driver, but more in
 	 * line with the intel documentation for the i965
 	 */
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN_GTE(dev_priv, 4)) {
 		/* on i965 use the PGM reg to read out the autoscaler values */
 		ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 	} else {
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 78a53c8b1789..557249583f8e 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -326,7 +326,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
 		break;
 	case DRM_MODE_SCALE_ASPECT:
 		/* Scale but preserve the aspect ratio */
-		if (INTEL_GEN(dev_priv) >= 4)
+		if (IS_GEN_GTE(dev_priv, 4))
 			i965_scale_aspect(pipe_config, &pfit_control);
 		else
 			i9xx_scale_aspect(pipe_config, &pfit_control,
@@ -340,7 +340,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
 		if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay ||
 		    pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
 			pfit_control |= PFIT_ENABLE;
-			if (INTEL_GEN(dev_priv) >= 4)
+			if (IS_GEN_GTE(dev_priv, 4))
 				pfit_control |= PFIT_SCALING_AUTO;
 			else
 				pfit_control |= (VERT_AUTO_SCALE |
@@ -356,7 +356,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
 
 	/* 965+ wants fuzzy fitting */
 	/* FIXME: handle multiple panels by failing gracefully */
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
 				 PFIT_FILTER_FUZZY);
 
@@ -367,7 +367,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
 	}
 
 	/* Make sure pre-965 set dither correctly for 18bpp panels. */
-	if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18)
+	if (IS_GEN_LT(dev_priv, 4) && pipe_config->pipe_bpp == 18)
 		pfit_control |= PANEL_8TO6_DITHER_ENABLE;
 
 	pipe_config->gmch_pfit.control = pfit_control;
@@ -497,7 +497,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector)
 	u32 val;
 
 	val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
-	if (INTEL_GEN(dev_priv) < 4)
+	if (IS_GEN_LT(dev_priv, 4))
 		val >>= 1;
 
 	if (panel->backlight.combination_mode) {
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 1f5cd572a7ff..017bd2602c99 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -604,7 +604,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
 {
 	if (IS_GEN2(dev_priv))
 		return i8xx_pipe_crc_ctl_reg(source, val);
-	else if (INTEL_GEN(dev_priv) < 5)
+	else if (IS_GEN_LT(dev_priv, 5))
 		return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7a112d075c24..37421fe4c0a3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2571,9 +2571,9 @@ static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
 static unsigned int
 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN_GTE(dev_priv, 8))
 		return 3072;
-	else if (INTEL_GEN(dev_priv) >= 7)
+	else if (IS_GEN_GTE(dev_priv, 7))
 		return 768;
 	else
 		return 512;
@@ -2583,10 +2583,10 @@ static unsigned int
 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
 		     int level, bool is_sprite)
 {
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN_GTE(dev_priv, 8))
 		/* BDW primary/sprite plane watermarks */
 		return level == 0 ? 255 : 2047;
-	else if (INTEL_GEN(dev_priv) >= 7)
+	else if (IS_GEN_GTE(dev_priv, 7))
 		/* IVB/HSW primary/sprite plane watermarks */
 		return level == 0 ? 127 : 1023;
 	else if (!is_sprite)
@@ -2600,7 +2600,7 @@ ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
 static unsigned int
 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
 {
-	if (INTEL_GEN(dev_priv) >= 7)
+	if (IS_GEN_GTE(dev_priv, 7))
 		return level == 0 ? 63 : 255;
 	else
 		return level == 0 ? 31 : 63;
@@ -2608,7 +2608,7 @@ ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
 
 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN_GTE(dev_priv, 8))
 		return 31;
 	else
 		return 15;
@@ -2637,7 +2637,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
 		 * FIFO size is only half of the self
 		 * refresh FIFO size on ILK/SNB.
 		 */
-		if (INTEL_GEN(dev_priv) <= 6)
+		if (IS_GEN_LTE(dev_priv, 6))
 			fifo_size /= 2;
 	}
 
@@ -2798,7 +2798,7 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 				  uint16_t wm[8])
 {
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		uint32_t val;
 		int ret, i;
 		int level, max_level = ilk_wm_max_level(dev_priv);
@@ -2883,14 +2883,14 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 		wm[2] = (sskpd >> 12) & 0xFF;
 		wm[3] = (sskpd >> 20) & 0x1FF;
 		wm[4] = (sskpd >> 32) & 0x1FF;
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	} else if (IS_GEN_GTE(dev_priv, 6)) {
 		uint32_t sskpd = I915_READ(MCH_SSKPD);
 
 		wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
 		wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
 		wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
 		wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
-	} else if (INTEL_GEN(dev_priv) >= 5) {
+	} else if (IS_GEN_GTE(dev_priv, 5)) {
 		uint32_t mltr = I915_READ(MLTR_ILK);
 
 		/* ILK primary LP0 latency is 700 ns */
@@ -2925,11 +2925,11 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
 {
 	/* how many WM levels are we expecting */
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		return 7;
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		return 4;
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN_GTE(dev_priv, 6))
 		return 3;
 	else
 		return 2;
@@ -2954,7 +2954,7 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
 		 * - latencies are in us on gen9.
 		 * - before then, WM1+ latency values are in 0.5us units
 		 */
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN_GTE(dev_priv, 9))
 			latency *= 10;
 		else if (level > 0)
 			latency *= 5;
@@ -3090,7 +3090,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
 	usable_level = max_level;
 
 	/* ILK/SNB: LP2+ watermarks only w/o sprites */
-	if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
+	if (IS_GEN_LTE(dev_priv, 6) && pipe_wm->sprites_enabled)
 		usable_level = 1;
 
 	/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
@@ -3235,12 +3235,12 @@ static void ilk_wm_merge(struct drm_device *dev,
 	int last_enabled_level = max_level;
 
 	/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
-	if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
+	if ((IS_GEN_LTE(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) &&
 	    config->num_pipes_active > 1)
 		last_enabled_level = 0;
 
 	/* ILK: FBC WM must be disabled always */
-	merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
+	merged->fbc_wm_enabled = IS_GEN_GTE(dev_priv, 6);
 
 	/* merge each WM1+ level */
 	for (level = 1; level <= max_level; level++) {
@@ -3330,7 +3330,7 @@ static void ilk_compute_wm_results(struct drm_device *dev,
 		if (r->enable)
 			results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
 
-		if (INTEL_GEN(dev_priv) >= 8)
+		if (IS_GEN_GTE(dev_priv, 8))
 			results->wm_lp[wm_lp - 1] |=
 				r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
 		else
@@ -3341,7 +3341,7 @@ static void ilk_compute_wm_results(struct drm_device *dev,
 		 * Always set WM1S_LP_EN when spr_val != 0, even if the
 		 * level is disabled. Doing otherwise could cause underruns.
 		 */
-		if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
+		if (IS_GEN_LTE(dev_priv, 6) && r->spr_val) {
 			WARN_ON(wm_lp != 1);
 			results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
 		} else
@@ -3546,7 +3546,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
 	    previous->wm_lp_spr[0] != results->wm_lp_spr[0])
 		I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
 
-	if (INTEL_GEN(dev_priv) >= 7) {
+	if (IS_GEN_GTE(dev_priv, 7)) {
 		if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
 			I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
 		if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
@@ -3785,7 +3785,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 	ddb_size = INTEL_INFO(dev_priv)->ddb_size;
 	WARN_ON(ddb_size == 0);
 
-	if (INTEL_GEN(dev_priv) < 11)
+	if (IS_GEN_LT(dev_priv, 11))
 		ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
 	/*
@@ -3996,7 +3996,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 	crtc_clock = crtc_state->adjusted_mode.crtc_clock;
 	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
 
-	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEMINILAKE(dev_priv) || IS_GEN_GTE(dev_priv, 10))
 		dotclk *= 2;
 
 	pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
@@ -4330,7 +4330,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
 	wm_intermediate_val = latency * pixel_rate * cpp;
 	ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
 
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN_GTE(dev_priv, 10))
 		ret = add_fixed16_u32(ret, 1);
 
 	return ret;
@@ -4438,7 +4438,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 	wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 							     intel_pstate);
 
-	if (INTEL_GEN(dev_priv) >= 11 &&
+	if (IS_GEN_GTE(dev_priv, 11) &&
 	    fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
 		wp->dbuf_block_size = 256;
 	else
@@ -4473,7 +4473,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 					   wp->y_min_scanlines,
 					   wp->dbuf_block_size);
 
-		if (INTEL_GEN(dev_priv) >= 10)
+		if (IS_GEN_GTE(dev_priv, 10))
 			interm_pbpl++;
 
 		wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
@@ -4573,7 +4573,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		}
 	}
 
-	if (INTEL_GEN(dev_priv) >= 11) {
+	if (IS_GEN_GTE(dev_priv, 11)) {
 		if (wp->y_tiled) {
 			uint32_t extra_lines;
 			uint_fixed_16_16_t fp_min_disp_buf_needed;
@@ -4705,14 +4705,14 @@ static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
 		goto exit;
 
 	/* Transition WM are not recommended by HW team for GEN9 */
-	if (INTEL_GEN(dev_priv) <= 9)
+	if (IS_GEN_LTE(dev_priv, 9))
 		goto exit;
 
 	/* Transition WM don't make any sense if ipc is disabled */
 	if (!dev_priv->ipc_enabled)
 		goto exit;
 
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN_GTE(dev_priv, 10))
 		trans_min = 4;
 
 	trans_offset_b = trans_min + trans_amount;
@@ -4835,7 +4835,7 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 
 	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
 			    &ddb->plane[pipe][plane_id]);
-	if (INTEL_GEN(dev_priv) < 11)
+	if (IS_GEN_LT(dev_priv, 11))
 		skl_ddb_entry_write(dev_priv,
 				    PLANE_NV12_BUF_CFG(pipe, plane_id),
 				    &ddb->y_plane[pipe][plane_id]);
@@ -5249,7 +5249,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
 	ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
 
 	/* 5/6 split only in single pipe config on IVB+ */
-	if (INTEL_GEN(dev_priv) >= 7 &&
+	if (IS_GEN_GTE(dev_priv, 7) &&
 	    config.num_pipes_active == 1 && config.sprites_enabled) {
 		ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
 		ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
@@ -5848,7 +5848,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
 	hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
 
 	hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
-	if (INTEL_GEN(dev_priv) >= 7) {
+	if (IS_GEN_GTE(dev_priv, 7)) {
 		hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
 		hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
 	}
@@ -6076,7 +6076,7 @@ static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 	 * the hw runs at the minimal clock before selecting the desired
 	 * frequency, if the down threshold expires in that window we will not
 	 * receive a down interrupt. */
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		limits = (rps->max_freq_softlimit) << 23;
 		if (val <= rps->min_freq_softlimit)
 			limits |= (rps->min_freq_softlimit) << 14;
@@ -6222,7 +6222,7 @@ static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
 	if (val != rps->cur_freq) {
 		gen6_set_rps_thresholds(dev_priv, val);
 
-		if (INTEL_GEN(dev_priv) >= 9)
+		if (IS_GEN_GTE(dev_priv, 9))
 			I915_WRITE(GEN6_RPNSWREQ,
 				   GEN9_FREQUENCY(val));
 		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
@@ -6650,7 +6650,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
 	/* 2b: Program RC6 thresholds.*/
-	if (INTEL_GEN(dev_priv) >= 10) {
+	if (IS_GEN_GTE(dev_priv, 10)) {
 		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
 		I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
 	} else if (IS_SKYLAKE(dev_priv)) {
@@ -6940,7 +6940,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 			 * No floor required for ring frequency on SKL.
 			 */
 			ring_freq = gpu_freq;
-		} else if (INTEL_GEN(dev_priv) >= 8) {
+		} else if (IS_GEN_GTE(dev_priv, 8)) {
 			/* max(2 * GT, DDR). NB: GT is 50MHz units */
 			ring_freq = max(min_ring_freq, gpu_freq);
 		} else if (IS_HASWELL(dev_priv)) {
@@ -7957,7 +7957,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 		cherryview_init_gt_powersave(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_init_gt_powersave(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN_GTE(dev_priv, 6))
 		gen6_init_rps_frequencies(dev_priv);
 
 	/* Derive initial user preferences/limits from the hardware limits */
@@ -8012,7 +8012,7 @@ void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
  */
 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) < 6)
+	if (IS_GEN_LT(dev_priv, 6))
 		return;
 
 	/* gen6_rps_idle() will be called later to disable interrupts */
@@ -8046,13 +8046,13 @@ static void intel_disable_rc6(struct drm_i915_private *dev_priv)
 	if (!dev_priv->gt_pm.rc6.enabled)
 		return;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		gen9_disable_rc6(dev_priv);
 	else if (IS_CHERRYVIEW(dev_priv))
 		cherryview_disable_rc6(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_disable_rc6(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN_GTE(dev_priv, 6))
 		gen6_disable_rc6(dev_priv);
 
 	dev_priv->gt_pm.rc6.enabled = false;
@@ -8065,13 +8065,13 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv)
 	if (!dev_priv->gt_pm.rps.enabled)
 		return;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		gen9_disable_rps(dev_priv);
 	else if (IS_CHERRYVIEW(dev_priv))
 		cherryview_disable_rps(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_disable_rps(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN_GTE(dev_priv, 6))
 		gen6_disable_rps(dev_priv);
 	else if (IS_IRONLAKE_M(dev_priv))
 		ironlake_disable_drps(dev_priv);
@@ -8114,11 +8114,11 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv)
 		cherryview_enable_rc6(dev_priv);
 	else if (IS_VALLEYVIEW(dev_priv))
 		valleyview_enable_rc6(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 9)
+	else if (IS_GEN_GTE(dev_priv, 9))
 		gen9_enable_rc6(dev_priv);
 	else if (IS_BROADWELL(dev_priv))
 		gen8_enable_rc6(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN_GTE(dev_priv, 6))
 		gen6_enable_rc6(dev_priv);
 
 	dev_priv->gt_pm.rc6.enabled = true;
@@ -8137,11 +8137,11 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
 		cherryview_enable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		valleyview_enable_rps(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 9) {
+	} else if (IS_GEN_GTE(dev_priv, 9)) {
 		gen9_enable_rps(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
 		gen8_enable_rps(dev_priv);
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	} else if (IS_GEN_GTE(dev_priv, 6)) {
 		gen6_enable_rps(dev_priv);
 	} else if (IS_IRONLAKE_M(dev_priv)) {
 		ironlake_enable_drps(dev_priv);
@@ -9056,7 +9056,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 		i915_ironlake_get_mem_freq(dev_priv);
 
 	/* For FIFO watermark updates */
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		skl_setup_wm_latency(dev_priv);
 		dev_priv->display.initial_watermarks = skl_initial_wm;
 		dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
@@ -9202,7 +9202,7 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val
 	*val = I915_READ_FW(GEN6_PCODE_DATA);
 	I915_WRITE_FW(GEN6_PCODE_DATA, 0);
 
-	if (INTEL_GEN(dev_priv) > 6)
+	if (IS_GEN_GT(dev_priv, 6))
 		status = gen7_check_mailbox_status(dev_priv);
 	else
 		status = gen6_check_mailbox_status(dev_priv);
@@ -9250,7 +9250,7 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
 
 	I915_WRITE_FW(GEN6_PCODE_DATA, 0);
 
-	if (INTEL_GEN(dev_priv) > 6)
+	if (IS_GEN_GT(dev_priv, 6))
 		status = gen7_check_mailbox_status(dev_priv);
 	else
 		status = gen6_check_mailbox_status(dev_priv);
@@ -9379,7 +9379,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
 					 GEN9_FREQ_SCALER);
 	else if (IS_CHERRYVIEW(dev_priv))
@@ -9392,7 +9392,7 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
 
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
 					 GT_FREQUENCY_MULTIPLIER);
 	else if (IS_CHERRYVIEW(dev_priv))
@@ -9537,7 +9537,7 @@ u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
 {
 	u32 cagf;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2ef374f936b9..116cce194ac9 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -126,7 +126,7 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
 				       enum port port)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		return DP_AUX_CH_CTL(port);
 	else
 		return EDP_PSR_AUX_CTL;
@@ -135,7 +135,7 @@ static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
 					enum port port, int index)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		return DP_AUX_CH_DATA(port, index);
 	else
 		return EDP_PSR_AUX_DATA(index);
@@ -521,7 +521,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
 	dev_priv->psr.enable_source(intel_dp, crtc_state);
 	dev_priv->psr.enabled = intel_dp;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		intel_psr_activate(intel_dp);
 	} else {
 		/*
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c91d7106fbcf..2c4ad89d9d57 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -346,7 +346,7 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 	u32 addr;
 
 	addr = dev_priv->status_page_dmah->busaddr;
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 	I915_WRITE(HWS_PGA, addr);
 }
@@ -386,7 +386,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 		mmio = RING_HWS_PGA(engine->mmio_base);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 6)
+	if (IS_GEN_GTE(dev_priv, 6))
 		I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
 
 	I915_WRITE(mmio, engine->status_page.ggtt_offset);
@@ -414,7 +414,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
 
-	if (INTEL_GEN(dev_priv) > 2) {
+	if (IS_GEN_GT(dev_priv, 2)) {
 		I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 		if (intel_wait_for_register(dev_priv,
 					    RING_MI_MODE(engine->mmio_base),
@@ -521,7 +521,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
 
 	intel_engine_init_hangcheck(engine);
 
-	if (INTEL_GEN(dev_priv) > 2)
+	if (IS_GEN_GT(dev_priv, 2))
 		I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 
 out:
@@ -655,7 +655,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
 	if (IS_GEN(dev_priv, 6, 7))
 		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
-	if (INTEL_GEN(dev_priv) >= 6)
+	if (IS_GEN_GTE(dev_priv, 6))
 		I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 
 	return init_workarounds_ring(engine);
@@ -1360,7 +1360,7 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
 
-	WARN_ON(INTEL_GEN(dev_priv) > 2 &&
+	WARN_ON(IS_GEN_GT(dev_priv, 2) &&
 		(I915_READ_MODE(engine) & MODE_IDLE) == 0);
 
 	intel_ring_unpin(engine->buffer);
@@ -1900,7 +1900,7 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
 	if (!HAS_LEGACY_SEMAPHORES(dev_priv))
 		return;
 
-	GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
+	GEM_BUG_ON(IS_GEN_LT(dev_priv, 6));
 	engine->semaphore.sync_to = gen6_ring_sync_to;
 	engine->semaphore.signal = gen6_signal;
 
@@ -1957,15 +1957,15 @@ static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
 {
 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN_GTE(dev_priv, 6)) {
 		engine->irq_enable = gen6_irq_enable;
 		engine->irq_disable = gen6_irq_disable;
 		engine->irq_seqno_barrier = gen6_seqno_barrier;
-	} else if (INTEL_GEN(dev_priv) >= 5) {
+	} else if (IS_GEN_GTE(dev_priv, 5)) {
 		engine->irq_enable = gen5_irq_enable;
 		engine->irq_disable = gen5_irq_disable;
 		engine->irq_seqno_barrier = gen5_seqno_barrier;
-	} else if (INTEL_GEN(dev_priv) >= 3) {
+	} else if (IS_GEN_GTE(dev_priv, 3)) {
 		engine->irq_enable = i9xx_irq_enable;
 		engine->irq_disable = i9xx_irq_disable;
 	} else {
@@ -1993,7 +1993,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
 				      struct intel_engine_cs *engine)
 {
 	/* gen8+ are only supported with execlists */
-	GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
+	GEM_BUG_ON(IS_GEN_GTE(dev_priv, 8));
 
 	intel_ring_init_irq(dev_priv, engine);
 	intel_ring_init_semaphores(dev_priv, engine);
@@ -2021,9 +2021,9 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
 
 	engine->set_default_submission = i9xx_set_default_submission;
 
-	if (INTEL_GEN(dev_priv) >= 6)
+	if (IS_GEN_GTE(dev_priv, 6))
 		engine->emit_bb_start = gen6_emit_bb_start;
-	else if (INTEL_GEN(dev_priv) >= 4)
+	else if (IS_GEN_GTE(dev_priv, 4))
 		engine->emit_bb_start = i965_emit_bb_start;
 	else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
 		engine->emit_bb_start = i830_emit_bb_start;
@@ -2041,7 +2041,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
 	if (HAS_L3_DPF(dev_priv))
 		engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN_GTE(dev_priv, 6)) {
 		engine->init_context = intel_rcs_ctx_init;
 		engine->emit_flush = gen7_render_ring_flush;
 		if (IS_GEN6(dev_priv))
@@ -2049,7 +2049,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
 	} else if (IS_GEN5(dev_priv)) {
 		engine->emit_flush = gen4_render_ring_flush;
 	} else {
-		if (INTEL_GEN(dev_priv) < 4)
+		if (IS_GEN_LT(dev_priv, 4))
 			engine->emit_flush = gen2_render_ring_flush;
 		else
 			engine->emit_flush = gen4_render_ring_flush;
@@ -2065,7 +2065,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
 	if (ret)
 		return ret;
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN_GTE(dev_priv, 6)) {
 		ret = intel_engine_create_scratch(engine, PAGE_SIZE);
 		if (ret)
 			return ret;
@@ -2084,7 +2084,7 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
 
 	intel_ring_default_vfuncs(dev_priv, engine);
 
-	if (INTEL_GEN(dev_priv) >= 6) {
+	if (IS_GEN_GTE(dev_priv, 6)) {
 		/* gen6 bsd needs a special wa for tail updates */
 		if (IS_GEN6(dev_priv))
 			engine->set_default_submission = gen6_bsd_set_default_submission;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 0bf97ed5ffac..3dd5f2c244d9 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1335,13 +1335,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
 		return;
 
 	/* Set the SDVO control regs. */
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN_GTE(dev_priv, 4)) {
 		/* The real mode polarity is set by the SDVO commands, using
 		 * struct intel_sdvo_dtd. */
 		sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
 		if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
 			sdvox |= HDMI_COLOR_RANGE_16_235;
-		if (INTEL_GEN(dev_priv) < 5)
+		if (IS_GEN_LT(dev_priv, 5))
 			sdvox |= SDVO_BORDER_ENABLE;
 	} else {
 		sdvox = I915_READ(intel_sdvo->sdvo_reg);
@@ -1358,11 +1358,11 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
 		sdvox |= SDVO_PIPE_SEL(crtc->pipe);
 
 	if (crtc_state->has_audio) {
-		WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4);
+		WARN_ON_ONCE(IS_GEN_LT(dev_priv, 4));
 		sdvox |= SDVO_AUDIO_ENABLE;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_GEN_GTE(dev_priv, 4)) {
 		/* done in crtc_mode_set as the dpll_md reg must be written early */
 	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
 		   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
@@ -1373,7 +1373,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
 	}
 
 	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
-	    INTEL_GEN(dev_priv) < 5)
+	    IS_GEN_LT(dev_priv, 5))
 		sdvox |= SDVO_STALL_SELECT;
 	intel_sdvo_write_sdvox(intel_sdvo, sdvox);
 }
@@ -2433,7 +2433,7 @@ intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
 	struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
 
 	intel_attach_force_audio_property(&connector->base.base);
-	if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
+	if (IS_GEN_GTE(dev_priv, 4) && IS_MOBILE(dev_priv)) {
 		intel_attach_broadcast_rgb_property(&connector->base.base);
 	}
 	intel_attach_aspect_ratio_property(&connector->base.base);
@@ -2502,7 +2502,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
 	connector->connector_type = DRM_MODE_CONNECTOR_DVID;
 
 	/* gen3 doesn't do the hdmi bits in the SDVO register */
-	if (INTEL_GEN(dev_priv) >= 4 &&
+	if (IS_GEN_GTE(dev_priv, 4) &&
 	    intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
 		connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
 		intel_sdvo->is_hdmi = true;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 3be22c0fcfb5..a28c5f83fa02 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -263,7 +263,7 @@ skl_update_plane(struct intel_plane *plane,
 
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
 		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
 			      plane_state->color_ctl);
 	if (key->flags) {
@@ -865,7 +865,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
 	struct drm_rect *src = &state->base.src;
 	struct drm_rect *dst = &state->base.dst;
 	struct drm_rect clip = {};
-	int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
+	int max_stride = IS_GEN_GTE(dev_priv, 9) ? 32768 : 16384;
 	int hscale, vscale;
 	int max_scale, min_scale;
 	bool can_scale;
@@ -892,7 +892,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
 	}
 
 	/* setup can_scale, min_scale, max_scale */
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		/* use scaler when colorkey is not required */
 		if (!state->ckey.flags) {
 			can_scale = 1;
@@ -1012,8 +1012,8 @@ intel_check_sprite_plane(struct intel_plane *plane,
 
 		width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 
-		if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
-		    width_bytes > 4096 || fb->pitches[0] > 4096)) {
+		if (IS_GEN_LT(dev_priv, 9) && (src_w > 2048 || src_h > 2048 ||
+					       width_bytes > 4096 || fb->pitches[0] > 4096)) {
 			DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 			return -EINVAL;
 		}
@@ -1031,7 +1031,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
 	dst->y1 = crtc_y;
 	dst->y2 = crtc_y + crtc_h;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		ret = skl_check_plane_surface(crtc_state, state);
 		if (ret)
 			return ret;
@@ -1043,7 +1043,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
 			return ret;
 
 		state->ctl = vlv_sprite_ctl(crtc_state, state);
-	} else if (INTEL_GEN(dev_priv) >= 7) {
+	} else if (IS_GEN_GTE(dev_priv, 7)) {
 		ret = i9xx_check_plane_surface(state);
 		if (ret)
 			return ret;
@@ -1057,7 +1057,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
 		state->ctl = g4x_sprite_ctl(crtc_state, state);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
+	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
 		state->color_ctl = glk_plane_color_ctl(crtc_state, state);
 
 	return 0;
@@ -1290,11 +1290,11 @@ static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
 	    modifier != DRM_FORMAT_MOD_LINEAR)
 		return false;
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		return skl_mod_supported(format, modifier);
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		return vlv_mod_supported(format, modifier);
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN_GTE(dev_priv, 6))
 		return snb_mod_supported(format, modifier);
 	else
 		return g4x_mod_supported(format, modifier);
@@ -1317,7 +1317,7 @@ bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
 	if (plane_id == PLANE_CURSOR)
 		return false;
 
-	if (INTEL_GEN(dev_priv) >= 10)
+	if (IS_GEN_GTE(dev_priv, 10))
 		return true;
 
 	if (IS_GEMINILAKE(dev_priv))
@@ -1354,7 +1354,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 	}
 	intel_plane->base.state = &state->base;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		intel_plane->can_scale = true;
 		state->scaler_id = -1;
 
@@ -1380,7 +1380,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 		plane_formats = vlv_plane_formats;
 		num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
 		modifiers = i9xx_plane_format_modifiers;
-	} else if (INTEL_GEN(dev_priv) >= 7) {
+	} else if (IS_GEN_GTE(dev_priv, 7)) {
 		if (IS_IVYBRIDGE(dev_priv)) {
 			intel_plane->can_scale = true;
 			intel_plane->max_downscale = 2;
@@ -1414,7 +1414,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 		}
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		supported_rotations =
 			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
 			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
@@ -1435,7 +1435,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 
 	possible_crtcs = (1 << pipe);
 
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_GEN_GTE(dev_priv, 9))
 		ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
 					       possible_crtcs, &intel_sprite_plane_funcs,
 					       plane_formats, num_plane_formats,
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index b3dabc219e6a..e9bed89cc1f7 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1067,7 +1067,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
 
 	set_color_conversion(dev_priv, color_conversion);
 
-	if (INTEL_GEN(dev_priv) >= 4)
+	if (IS_GEN_GTE(dev_priv, 4))
 		I915_WRITE(TV_CLR_KNOBS, 0x00404000);
 	else
 		I915_WRITE(TV_CLR_KNOBS, 0x00606000);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 73959ae56241..4ae72c2f1921 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -435,7 +435,7 @@ u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
 	/* The needed capability bits for size calculation
 	 * are not there with pre gen9 so return 128MB always.
 	 */
-	if (INTEL_GEN(dev_priv) < 9)
+	if (IS_GEN_LT(dev_priv, 9))
 		return 128 * 1024 * 1024;
 
 	return gen9_edram_size(dev_priv);
@@ -445,7 +445,7 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
 {
 	if (IS_HASWELL(dev_priv) ||
 	    IS_BROADWELL(dev_priv) ||
-	    INTEL_GEN(dev_priv) >= 9) {
+	    IS_GEN_GTE(dev_priv, 9)) {
 		dev_priv->edram_cap = __raw_i915_read32(dev_priv,
 							HSW_EDRAM_CAP);
 
@@ -837,7 +837,7 @@ find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
 	{ .start = (s), .end = (e), .domains = (d) }
 
 #define HAS_FWTABLE(dev_priv) \
-	(INTEL_GEN(dev_priv) >= 9 || \
+	(IS_GEN_GTE(dev_priv, 9) || \
 	 IS_CHERRYVIEW(dev_priv) || \
 	 IS_VALLEYVIEW(dev_priv))
 
@@ -1253,7 +1253,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
 
 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
+	if (IS_GEN_LTE(dev_priv, 5) || intel_vgpu_active(dev_priv))
 		return;
 
 	if (IS_GEN6(dev_priv)) {
@@ -1267,7 +1267,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
 		dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (IS_GEN_GTE(dev_priv, 9)) {
 		dev_priv->uncore.funcs.force_wake_get =
 			fw_domains_get_with_fallback;
 		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
@@ -1541,7 +1541,7 @@ static void i915_stop_engines(struct drm_i915_private *dev_priv,
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
 
-	if (INTEL_GEN(dev_priv) < 3)
+	if (IS_GEN_LT(dev_priv, 3))
 		return;
 
 	for_each_engine_masked(engine, dev_priv, engine_mask, id)
@@ -1874,9 +1874,9 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
 	if (!i915_modparams.reset)
 		return NULL;
 
-	if (INTEL_GEN(dev_priv) >= 8)
+	if (IS_GEN_GTE(dev_priv, 8))
 		return gen8_reset_engines;
-	else if (INTEL_GEN(dev_priv) >= 6)
+	else if (IS_GEN_GTE(dev_priv, 6))
 		return gen6_reset_engines;
 	else if (IS_GEN5(dev_priv))
 		return ironlake_do_reset;
@@ -1884,7 +1884,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
 		return g4x_do_reset;
 	else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
 		return g33_do_reset;
-	else if (INTEL_GEN(dev_priv) >= 3)
+	else if (IS_GEN_GTE(dev_priv, 3))
 		return i915_do_reset;
 	else
 		return NULL;
@@ -1987,7 +1987,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
 
 	if (HAS_FWTABLE(dev_priv)) {
 		fw_domains = __fwtable_reg_read_fw_domains(offset);
-	} else if (INTEL_GEN(dev_priv) >= 6) {
+	} else if (IS_GEN_GTE(dev_priv, 6)) {
 		fw_domains = __gen6_reg_read_fw_domains(offset);
 	} else {
 		WARN_ON(!IS_GEN(dev_priv, 2, 5));
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
index 7a0d1e17c1ad..8deed5569b7a 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
@@ -204,12 +204,12 @@ static int gpu_set(struct drm_i915_gem_object *obj,
 		return PTR_ERR(cs);
 	}
 
-	if (INTEL_GEN(i915) >= 8) {
+	if (IS_GEN_GTE(i915, 8)) {
 		*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
 		*cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset);
 		*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
 		*cs++ = v;
-	} else if (INTEL_GEN(i915) >= 4) {
+	} else if (IS_GEN_GTE(i915, 4)) {
 		*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
 		*cs++ = 0;
 		*cs++ = i915_ggtt_offset(vma) + offset;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 56a803d11916..12ec7b39ce77 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -159,7 +159,7 @@ static int gpu_fill(struct drm_i915_gem_object *obj,
 	}
 
 	flags = 0;
-	if (INTEL_GEN(vm->i915) <= 5)
+	if (IS_GEN_LTE(vm->i915, 5))
 		flags |= I915_DISPATCH_SECURE;
 
 	err = engine->emit_bb_start(rq,
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
index f32aa6bb79e2..2c8f500ed7f7 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
@@ -355,7 +355,7 @@ static int igt_partial_tiling(void *arg)
 		    tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)
 			continue;
 
-		if (INTEL_GEN(i915) <= 2) {
+		if (IS_GEN_LTE(i915, 2)) {
 			tile.height = 16;
 			tile.width = 128;
 			tile.size = 11;
@@ -370,9 +370,9 @@ static int igt_partial_tiling(void *arg)
 			tile.size = 12;
 		}
 
-		if (INTEL_GEN(i915) < 4)
+		if (IS_GEN_LT(i915, 4))
 			max_pitch = 8192 / tile.width;
-		else if (INTEL_GEN(i915) < 7)
+		else if (IS_GEN_LT(i915, 7))
 			max_pitch = 128 * I965_FENCE_MAX_PITCH_VAL / tile.width;
 		else
 			max_pitch = 128 * GEN7_FENCE_MAX_PITCH_VAL / tile.width;
@@ -385,7 +385,7 @@ static int igt_partial_tiling(void *arg)
 			if (err)
 				goto out_unlock;
 
-			if (pitch > 2 && INTEL_GEN(i915) >= 4) {
+			if (pitch > 2 && IS_GEN_GTE(i915, 4)) {
 				tile.stride = tile.width * (pitch - 1);
 				err = check_partial_mapping(obj, &tile, end);
 				if (err == -EINTR)
@@ -394,7 +394,7 @@ static int igt_partial_tiling(void *arg)
 					goto out_unlock;
 			}
 
-			if (pitch < max_pitch && INTEL_GEN(i915) >= 4) {
+			if (pitch < max_pitch && IS_GEN_GTE(i915, 4)) {
 				tile.stride = tile.width * (pitch + 1);
 				err = check_partial_mapping(obj, &tile, end);
 				if (err == -EINTR)
@@ -404,7 +404,7 @@ static int igt_partial_tiling(void *arg)
 			}
 		}
 
-		if (INTEL_GEN(i915) >= 4) {
+		if (IS_GEN_GTE(i915, 4)) {
 			for_each_prime_number(pitch, max_pitch) {
 				tile.stride = tile.width * pitch;
 				err = check_partial_mapping(obj, &tile, end);
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index d1d2c2456f69..92bc059a78f4 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -136,7 +136,7 @@ static int emit_recurse_batch(struct hang *h,
 	}
 
 	batch = h->batch;
-	if (INTEL_GEN(i915) >= 8) {
+	if (IS_GEN_GTE(i915, 8)) {
 		*batch++ = MI_STORE_DWORD_IMM_GEN4;
 		*batch++ = lower_32_bits(hws_address(hws, rq));
 		*batch++ = upper_32_bits(hws_address(hws, rq));
@@ -150,7 +150,7 @@ static int emit_recurse_batch(struct hang *h,
 		*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
 		*batch++ = lower_32_bits(vma->node.start);
 		*batch++ = upper_32_bits(vma->node.start);
-	} else if (INTEL_GEN(i915) >= 6) {
+	} else if (IS_GEN_GTE(i915, 6)) {
 		*batch++ = MI_STORE_DWORD_IMM_GEN4;
 		*batch++ = 0;
 		*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -163,7 +163,7 @@ static int emit_recurse_batch(struct hang *h,
 		*batch++ = MI_ARB_CHECK;
 		*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
 		*batch++ = lower_32_bits(vma->node.start);
-	} else if (INTEL_GEN(i915) >= 4) {
+	} else if (IS_GEN_GTE(i915, 4)) {
 		*batch++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
 		*batch++ = 0;
 		*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -193,7 +193,7 @@ static int emit_recurse_batch(struct hang *h,
 	i915_gem_chipset_flush(h->i915);
 
 	flags = 0;
-	if (INTEL_GEN(vm->i915) <= 5)
+	if (IS_GEN_LTE(vm->i915, 5))
 		flags |= I915_DISPATCH_SECURE;
 
 	err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 2f6367643171..7177f97e72ef 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -173,7 +173,7 @@ int intel_uncore_live_selftests(struct drm_i915_private *i915)
 	/* Confirm the table we load is still valid */
 	err = intel_fw_table_check(i915->uncore.fw_domains_table,
 				   i915->uncore.fw_domains_table_entries,
-				   INTEL_GEN(i915) >= 9);
+				   IS_GEN_GTE(i915, 9));
 	if (err)
 		return err;
 
-- 
2.14.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [RFC 14/15] drm/i915: Use new IS_GEN range helpers

[Ville Syrjälä]

On Thu, Feb 08, 2018 at 01:06:05PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Coccinelle transformation:
> 
>  @@
>  expression p, g;
>  @@
>  (
>  -INTEL_GEN(p) > g
>  +IS_GEN_GT(p, g)

I think this stuff makes the code pretty close to illegible.
In this particular case even more so because "GT" actually
means something very different to us.

>  |
>  -INTEL_GEN(p) < g
>  +IS_GEN_LT(p, g)
>  |
>  -INTEL_GEN(p) >= g
>  +IS_GEN_GTE(p, g)
>  |
>  -INTEL_GEN(p) <= g
>  +IS_GEN_LTE(p, g)
>  )
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c                |  86 ++++-----
>  drivers/gpu/drm/i915/i915_drv.c                    |  16 +-
>  drivers/gpu/drm/i915/i915_drv.h                    |  14 +-
>  drivers/gpu/drm/i915/i915_gem.c                    |  18 +-
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c         |   2 +-
>  drivers/gpu/drm/i915/i915_gem_fence_reg.c          |   4 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c                |  30 ++--
>  drivers/gpu/drm/i915/i915_gem_request.c            |   2 +-
>  drivers/gpu/drm/i915/i915_gem_stolen.c             |   6 +-
>  drivers/gpu/drm/i915/i915_gem_tiling.c             |   8 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c              |  40 ++---
>  drivers/gpu/drm/i915/i915_irq.c                    |  58 +++---
>  drivers/gpu/drm/i915/i915_perf.c                   |   2 +-
>  drivers/gpu/drm/i915/i915_pmu.c                    |   6 +-
>  drivers/gpu/drm/i915/i915_reg.h                    |   4 +-
>  drivers/gpu/drm/i915/i915_suspend.c                |  12 +-
>  drivers/gpu/drm/i915/i915_sysfs.c                  |   2 +-
>  drivers/gpu/drm/i915/intel_atomic_plane.c          |   2 +-
>  drivers/gpu/drm/i915/intel_audio.c                 |   2 +-
>  drivers/gpu/drm/i915/intel_cdclk.c                 |   8 +-
>  drivers/gpu/drm/i915/intel_color.c                 |   2 +-
>  drivers/gpu/drm/i915/intel_crt.c                   |   6 +-
>  drivers/gpu/drm/i915/intel_ddi.c                   |  10 +-
>  drivers/gpu/drm/i915/intel_device_info.c           |  14 +-
>  drivers/gpu/drm/i915/intel_display.c               | 194 ++++++++++-----------
>  drivers/gpu/drm/i915/intel_dp.c                    |  28 +--
>  drivers/gpu/drm/i915/intel_dpll_mgr.c              |   4 +-
>  drivers/gpu/drm/i915/intel_engine_cs.c             |  22 +--
>  drivers/gpu/drm/i915/intel_fbc.c                   |  30 ++--
>  drivers/gpu/drm/i915/intel_fifo_underrun.c         |   2 +-
>  drivers/gpu/drm/i915/intel_hangcheck.c             |   2 +-
>  drivers/gpu/drm/i915/intel_hdcp.c                  |   2 +-
>  drivers/gpu/drm/i915/intel_hdmi.c                  |  10 +-
>  drivers/gpu/drm/i915/intel_lrc.c                   |   6 +-
>  drivers/gpu/drm/i915/intel_lvds.c                  |  10 +-
>  drivers/gpu/drm/i915/intel_mocs.c                  |   2 +-
>  drivers/gpu/drm/i915/intel_overlay.c               |   2 +-
>  drivers/gpu/drm/i915/intel_panel.c                 |  10 +-
>  drivers/gpu/drm/i915/intel_pipe_crc.c              |   2 +-
>  drivers/gpu/drm/i915/intel_pm.c                    | 100 +++++------
>  drivers/gpu/drm/i915/intel_psr.c                   |   6 +-
>  drivers/gpu/drm/i915/intel_ringbuffer.c            |  34 ++--
>  drivers/gpu/drm/i915/intel_sdvo.c                  |  14 +-
>  drivers/gpu/drm/i915/intel_sprite.c                |  30 ++--
>  drivers/gpu/drm/i915/intel_tv.c                    |   2 +-
>  drivers/gpu/drm/i915/intel_uncore.c                |  20 +--
>  .../gpu/drm/i915/selftests/i915_gem_coherency.c    |   4 +-
>  drivers/gpu/drm/i915/selftests/i915_gem_context.c  |   2 +-
>  drivers/gpu/drm/i915/selftests/i915_gem_object.c   |  12 +-
>  drivers/gpu/drm/i915/selftests/intel_hangcheck.c   |   8 +-
>  drivers/gpu/drm/i915/selftests/intel_uncore.c      |   2 +-
>  51 files changed, 457 insertions(+), 457 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 3849ded354e3..0cedbcc8c6e2 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -708,7 +708,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>  			   I915_READ(GEN8_PCU_IIR));
>  		seq_printf(m, "PCU interrupt enable:\t%08x\n",
>  			   I915_READ(GEN8_PCU_IER));
> -	} else if (INTEL_GEN(dev_priv) >= 8) {
> +	} else if (IS_GEN_GTE(dev_priv, 8)) {
>  		seq_printf(m, "Master Interrupt Control:\t%08x\n",
>  			   I915_READ(GEN8_MASTER_IRQ));
>  
> @@ -845,7 +845,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>  		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
>  			   I915_READ(GTIMR));
>  	}
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (IS_GEN_GTE(dev_priv, 6)) {
>  		for_each_engine(engine, dev_priv, id) {
>  			seq_printf(m,
>  				   "Graphics Interrupt mask (%s):	%08x\n",
> @@ -1056,7 +1056,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  			   "efficient (RPe) frequency: %d MHz\n",
>  			   intel_gpu_freq(dev_priv, rps->efficient_freq));
>  		mutex_unlock(&dev_priv->pcu_lock);
> -	} else if (INTEL_GEN(dev_priv) >= 6) {
> +	} else if (IS_GEN_GTE(dev_priv, 6)) {
>  		u32 rp_state_limits;
>  		u32 gt_perf_status;
>  		u32 rp_state_cap;
> @@ -1080,7 +1080,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  		reqf = I915_READ(GEN6_RPNSWREQ);
> -		if (INTEL_GEN(dev_priv) >= 9)
> +		if (IS_GEN_GTE(dev_priv, 9))
>  			reqf >>= 23;
>  		else {
>  			reqf &= ~GEN6_TURBO_DISABLE;
> @@ -1133,7 +1133,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  			   rps->pm_intrmsk_mbz);
>  		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
>  		seq_printf(m, "Render p-state ratio: %d\n",
> -			   (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> +			   (gt_perf_status & (IS_GEN_GTE(dev_priv, 9) ? 0x1ff00 : 0xff00)) >> 8);
>  		seq_printf(m, "Render p-state VID: %d\n",
>  			   gt_perf_status & 0xff);
>  		seq_printf(m, "Render p-state limit: %d\n",
> @@ -1218,13 +1218,13 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
>  	seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
>  		   instdone->instdone);
>  
> -	if (INTEL_GEN(dev_priv) <= 3)
> +	if (IS_GEN_LTE(dev_priv, 3))
>  		return;
>  
>  	seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
>  		   instdone->slice_common);
>  
> -	if (INTEL_GEN(dev_priv) <= 6)
> +	if (IS_GEN_LTE(dev_priv, 6))
>  		return;
>  
>  	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
> @@ -1478,7 +1478,7 @@ static int gen6_drpc_info(struct seq_file *m)
>  	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
>  
>  	rcctl1 = I915_READ(GEN6_RC_CONTROL);
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
>  		gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
>  	}
> @@ -1491,7 +1491,7 @@ static int gen6_drpc_info(struct seq_file *m)
>  		   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
>  	seq_printf(m, "RC6 Enabled: %s\n",
>  		   yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		seq_printf(m, "Render Well Gating Enabled: %s\n",
>  			yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
>  		seq_printf(m, "Media Well Gating Enabled: %s\n",
> @@ -1525,7 +1525,7 @@ static int gen6_drpc_info(struct seq_file *m)
>  
>  	seq_printf(m, "Core Power Down: %s\n",
>  		   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		seq_printf(m, "Render Power Well: %s\n",
>  			(gen9_powergate_status &
>  			 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
> @@ -1559,7 +1559,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
>  
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		err = vlv_drpc_info(m);
> -	else if (INTEL_GEN(dev_priv) >= 6)
> +	else if (IS_GEN_GTE(dev_priv, 6))
>  		err = gen6_drpc_info(m);
>  	else
>  		err = ironlake_drpc_info(m);
> @@ -1606,11 +1606,11 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
>  	if (intel_fbc_is_active(dev_priv)) {
>  		u32 mask;
>  
> -		if (INTEL_GEN(dev_priv) >= 8)
> +		if (IS_GEN_GTE(dev_priv, 8))
>  			mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
> -		else if (INTEL_GEN(dev_priv) >= 7)
> +		else if (IS_GEN_GTE(dev_priv, 7))
>  			mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
> -		else if (INTEL_GEN(dev_priv) >= 5)
> +		else if (IS_GEN_GTE(dev_priv, 5))
>  			mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
>  		else if (IS_G4X(dev_priv))
>  			mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
> @@ -1631,7 +1631,7 @@ static int i915_fbc_false_color_get(void *data, u64 *val)
>  {
>  	struct drm_i915_private *dev_priv = data;
>  
> -	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
> +	if (IS_GEN_LT(dev_priv, 7) || !HAS_FBC(dev_priv))
>  		return -ENODEV;
>  
>  	*val = dev_priv->fbc.false_color;
> @@ -1644,7 +1644,7 @@ static int i915_fbc_false_color_set(void *data, u64 val)
>  	struct drm_i915_private *dev_priv = data;
>  	u32 reg;
>  
> -	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
> +	if (IS_GEN_LT(dev_priv, 7) || !HAS_FBC(dev_priv))
>  		return -ENODEV;
>  
>  	mutex_lock(&dev_priv->fbc.lock);
> @@ -1676,7 +1676,7 @@ static int i915_ips_status(struct seq_file *m, void *unused)
>  	seq_printf(m, "Enabled by kernel parameter: %s\n",
>  		   yesno(i915_modparams.enable_ips));
>  
> -	if (INTEL_GEN(dev_priv) >= 8) {
> +	if (IS_GEN_GTE(dev_priv, 8)) {
>  		seq_puts(m, "Currently: unknown\n");
>  	} else {
>  		if (I915_READ(IPS_CTL) & IPS_ENABLE)
> @@ -1698,7 +1698,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>  	intel_runtime_pm_get(dev_priv);
>  	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		/* no global SR status; inspect per-plane WM */;
>  	else if (HAS_PCH_SPLIT(dev_priv))
>  		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
> @@ -1978,7 +1978,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
>  			   I915_READ16(C0DRB3));
>  		seq_printf(m, "C1DRB3 = 0x%04x\n",
>  			   I915_READ16(C1DRB3));
> -	} else if (INTEL_GEN(dev_priv) >= 6) {
> +	} else if (IS_GEN_GTE(dev_priv, 6)) {
>  		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
>  			   I915_READ(MAD_DIMM_C0));
>  		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
> @@ -1987,7 +1987,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
>  			   I915_READ(MAD_DIMM_C2));
>  		seq_printf(m, "TILECTL = 0x%08x\n",
>  			   I915_READ(TILECTL));
> -		if (INTEL_GEN(dev_priv) >= 8)
> +		if (IS_GEN_GTE(dev_priv, 8))
>  			seq_printf(m, "GAMTARBMODE = 0x%08x\n",
>  				   I915_READ(GAMTARBMODE));
>  		else
> @@ -2095,9 +2095,9 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
>  
>  	intel_runtime_pm_get(dev_priv);
>  
> -	if (INTEL_GEN(dev_priv) >= 8)
> +	if (IS_GEN_GTE(dev_priv, 8))
>  		gen8_ppgtt_info(m, dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 6)
> +	else if (IS_GEN_GTE(dev_priv, 6))
>  		gen6_ppgtt_info(m, dev_priv);
>  
>  	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
> @@ -2191,7 +2191,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
>  		   atomic_read(&rps->boosts));
>  	mutex_unlock(&dev->filelist_mutex);
>  
> -	if (INTEL_GEN(dev_priv) >= 6 &&
> +	if (IS_GEN_GTE(dev_priv, 6) &&
>  	    rps->enabled &&
>  	    dev_priv->gt.active_requests) {
>  		u32 rpup, rpupei;
> @@ -2222,7 +2222,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
>  static int i915_llc(struct seq_file *m, void *data)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> -	const bool edram = INTEL_GEN(dev_priv) > 8;
> +	const bool edram = IS_GEN_GT(dev_priv, 8);
>  
>  	seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
>  	seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
> @@ -2675,7 +2675,7 @@ static int i915_energy_uJ(struct seq_file *m, void *data)
>  	unsigned long long power;
>  	u32 units;
>  
> -	if (INTEL_GEN(dev_priv) < 6)
> +	if (IS_GEN_LT(dev_priv, 6))
>  		return -ENODEV;
>  
>  	intel_runtime_pm_get(dev_priv);
> @@ -3290,7 +3290,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
>  	enum pipe pipe;
>  	int plane;
>  
> -	if (INTEL_GEN(dev_priv) < 9)
> +	if (IS_GEN_LT(dev_priv, 9))
>  		return -ENODEV;
>  
>  	drm_modeset_lock_all(dev);
> @@ -3689,7 +3689,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
>  		 * - WM1+ latency values in 0.5us units
>  		 * - latencies are in us on gen9/vlv/chv
>  		 */
> -		if (INTEL_GEN(dev_priv) >= 9 ||
> +		if (IS_GEN_GTE(dev_priv, 9) ||
>  		    IS_VALLEYVIEW(dev_priv) ||
>  		    IS_CHERRYVIEW(dev_priv) ||
>  		    IS_G4X(dev_priv))
> @@ -3709,7 +3709,7 @@ static int pri_wm_latency_show(struct seq_file *m, void *data)
>  	struct drm_i915_private *dev_priv = m->private;
>  	const uint16_t *latencies;
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		latencies = dev_priv->wm.skl_latency;
>  	else
>  		latencies = dev_priv->wm.pri_latency;
> @@ -3724,7 +3724,7 @@ static int spr_wm_latency_show(struct seq_file *m, void *data)
>  	struct drm_i915_private *dev_priv = m->private;
>  	const uint16_t *latencies;
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		latencies = dev_priv->wm.skl_latency;
>  	else
>  		latencies = dev_priv->wm.spr_latency;
> @@ -3739,7 +3739,7 @@ static int cur_wm_latency_show(struct seq_file *m, void *data)
>  	struct drm_i915_private *dev_priv = m->private;
>  	const uint16_t *latencies;
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		latencies = dev_priv->wm.skl_latency;
>  	else
>  		latencies = dev_priv->wm.cur_latency;
> @@ -3753,7 +3753,7 @@ static int pri_wm_latency_open(struct inode *inode, struct file *file)
>  {
>  	struct drm_i915_private *dev_priv = inode->i_private;
>  
> -	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
> +	if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv))
>  		return -ENODEV;
>  
>  	return single_open(file, pri_wm_latency_show, dev_priv);
> @@ -3832,7 +3832,7 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
>  	struct drm_i915_private *dev_priv = m->private;
>  	uint16_t *latencies;
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		latencies = dev_priv->wm.skl_latency;
>  	else
>  		latencies = dev_priv->wm.pri_latency;
> @@ -3847,7 +3847,7 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
>  	struct drm_i915_private *dev_priv = m->private;
>  	uint16_t *latencies;
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		latencies = dev_priv->wm.skl_latency;
>  	else
>  		latencies = dev_priv->wm.spr_latency;
> @@ -3862,7 +3862,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
>  	struct drm_i915_private *dev_priv = m->private;
>  	uint16_t *latencies;
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		latencies = dev_priv->wm.skl_latency;
>  	else
>  		latencies = dev_priv->wm.cur_latency;
> @@ -4100,7 +4100,7 @@ i915_max_freq_get(void *data, u64 *val)
>  {
>  	struct drm_i915_private *dev_priv = data;
>  
> -	if (INTEL_GEN(dev_priv) < 6)
> +	if (IS_GEN_LT(dev_priv, 6))
>  		return -ENODEV;
>  
>  	*val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
> @@ -4115,7 +4115,7 @@ i915_max_freq_set(void *data, u64 val)
>  	u32 hw_max, hw_min;
>  	int ret;
>  
> -	if (INTEL_GEN(dev_priv) < 6)
> +	if (IS_GEN_LT(dev_priv, 6))
>  		return -ENODEV;
>  
>  	DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
> @@ -4156,7 +4156,7 @@ i915_min_freq_get(void *data, u64 *val)
>  {
>  	struct drm_i915_private *dev_priv = data;
>  
> -	if (INTEL_GEN(dev_priv) < 6)
> +	if (IS_GEN_LT(dev_priv, 6))
>  		return -ENODEV;
>  
>  	*val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
> @@ -4171,7 +4171,7 @@ i915_min_freq_set(void *data, u64 val)
>  	u32 hw_max, hw_min;
>  	int ret;
>  
> -	if (INTEL_GEN(dev_priv) < 6)
> +	if (IS_GEN_LT(dev_priv, 6))
>  		return -ENODEV;
>  
>  	DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
> @@ -4469,7 +4469,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>  	struct sseu_dev_info sseu;
>  
> -	if (INTEL_GEN(dev_priv) < 8)
> +	if (IS_GEN_LT(dev_priv, 8))
>  		return -ENODEV;
>  
>  	seq_puts(m, "SSEU Device Info\n");
> @@ -4486,7 +4486,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>  		broadwell_sseu_device_status(dev_priv, &sseu);
>  	} else if (IS_GEN9(dev_priv)) {
>  		gen9_sseu_device_status(dev_priv, &sseu);
> -	} else if (INTEL_GEN(dev_priv) >= 10) {
> +	} else if (IS_GEN_GTE(dev_priv, 10)) {
>  		gen10_sseu_device_status(dev_priv, &sseu);
>  	}
>  
> @@ -4501,7 +4501,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
>  {
>  	struct drm_i915_private *i915 = inode->i_private;
>  
> -	if (INTEL_GEN(i915) < 6)
> +	if (IS_GEN_LT(i915, 6))
>  		return 0;
>  
>  	intel_runtime_pm_get(i915);
> @@ -4514,7 +4514,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file)
>  {
>  	struct drm_i915_private *i915 = inode->i_private;
>  
> -	if (INTEL_GEN(i915) < 6)
> +	if (IS_GEN_LT(i915, 6))
>  		return 0;
>  
>  	intel_uncore_forcewake_user_put(i915);
> @@ -4612,7 +4612,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
>  	struct intel_encoder *encoder;
>  	struct intel_dp *intel_dp;
>  
> -	if (INTEL_GEN(dev_priv) < 7)
> +	if (IS_GEN_LT(dev_priv, 7))
>  		return -ENODEV;
>  
>  	drm_modeset_lock_all(dev);
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index bb605e0b996c..8e108eb233ee 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -459,12 +459,12 @@ static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
>  static int
>  intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
>  {
> -	int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
> +	int reg = IS_GEN_GTE(dev_priv, 4) ? MCHBAR_I965 : MCHBAR_I915;
>  	u32 temp_lo, temp_hi = 0;
>  	u64 mchbar_addr;
>  	int ret;
>  
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
>  	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
>  	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
> @@ -491,7 +491,7 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
>  		return ret;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
>  				       upper_32_bits(dev_priv->mch_res.start));
>  
> @@ -504,7 +504,7 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
>  static void
>  intel_setup_mchbar(struct drm_i915_private *dev_priv)
>  {
> -	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
> +	int mchbar_reg = IS_GEN_GTE(dev_priv, 4) ? MCHBAR_I965 : MCHBAR_I915;
>  	u32 temp;
>  	bool enabled;
>  
> @@ -543,7 +543,7 @@ intel_setup_mchbar(struct drm_i915_private *dev_priv)
>  static void
>  intel_teardown_mchbar(struct drm_i915_private *dev_priv)
>  {
> -	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
> +	int mchbar_reg = IS_GEN_GTE(dev_priv, 4) ? MCHBAR_I965 : MCHBAR_I915;
>  
>  	if (dev_priv->mchbar_need_disable) {
>  		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
> @@ -983,7 +983,7 @@ static int i915_mmio_setup(struct drm_i915_private *dev_priv)
>  	 * the register BAR remains the same size for all the earlier
>  	 * generations up to Ironlake.
>  	 */
> -	if (INTEL_GEN(dev_priv) < 5)
> +	if (IS_GEN_LT(dev_priv, 5))
>  		mmio_size = 512 * 1024;
>  	else
>  		mmio_size = 2 * 1024 * 1024;
> @@ -1181,7 +1181,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>  	 * properly dead afterwards. So we'll just disable them for all
>  	 * pre-gen5 chipsets.
>  	 */
> -	if (INTEL_GEN(dev_priv) >= 5) {
> +	if (IS_GEN_GTE(dev_priv, 5)) {
>  		if (pci_enable_msi(pdev) < 0)
>  			DRM_DEBUG_DRIVER("can't enable MSI");
>  	}
> @@ -1672,7 +1672,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
>  	 * Fujitsu FSC S7110
>  	 * Acer Aspire 1830T
>  	 */
> -	if (!(hibernation && INTEL_GEN(dev_priv) < 6))
> +	if (!(hibernation && IS_GEN_LT(dev_priv, 6)))
>  		pci_set_power_state(pdev, PCI_D3hot);
>  
>  	dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b66f288bde7d..1d8c318ddeff 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2855,7 +2855,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>   * interrupts.
>   */
>  #define HAS_AUX_IRQ(dev_priv)   true
> -#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
> +#define HAS_GMBUS_IRQ(dev_priv) (IS_GEN_GTE(dev_priv, 4))
>  
>  /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
>   * rows, which changed the alignment requirements and fence programming.
> @@ -2866,7 +2866,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  #define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
>  #define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
>  
> -#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
> +#define HAS_FW_BLC(dev_priv) 	(IS_GEN_GT(dev_priv, 2))
>  #define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
>  #define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
>  
> @@ -2951,7 +2951,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
>  
> -#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
> +#define HAS_LSPCON(dev_priv) (IS_GEN_GTE(dev_priv, 9))
>  
>  /* DPF == dynamic parity feature */
>  #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
> @@ -2974,7 +2974,7 @@ static inline bool intel_vtd_active(void)
>  
>  static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
>  {
> -	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
> +	return IS_GEN_GTE(dev_priv, 6) && intel_vtd_active();
>  }
>  
>  static inline bool
> @@ -3561,7 +3561,7 @@ void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
>  static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
>  {
>  	wmb();
> -	if (INTEL_GEN(dev_priv) < 6)
> +	if (IS_GEN_LT(dev_priv, 6))
>  		intel_gtt_chipset_flush();
>  }
>  
> @@ -3996,7 +3996,7 @@ static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return VLV_VGACNTRL;
> -	else if (INTEL_GEN(dev_priv) >= 5)
> +	else if (IS_GEN_GTE(dev_priv, 5))
>  		return CPU_VGACNTRL;
>  	else
>  		return VGACNTRL;
> @@ -4164,7 +4164,7 @@ int remap_io_mapping(struct vm_area_struct *vma,
>  
>  static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
>  {
> -	if (INTEL_GEN(i915) >= 10)
> +	if (IS_GEN_GTE(i915, 10))
>  		return CNL_HWS_CSB_WRITE_INDEX;
>  	else
>  		return I915_HWS_CSB_WRITE_INDEX;
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 1d5208f24b60..9a1cee3a590b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -386,7 +386,7 @@ i915_gem_object_wait_fence(struct dma_fence *fence,
>  	 * each client to waitboost once in a busy period.
>  	 */
>  	if (rps_client && !i915_gem_request_started(rq)) {
> -		if (INTEL_GEN(rq->i915) >= 6)
> +		if (IS_GEN_GTE(rq->i915, 6))
>  			gen6_rps_boost(rq, rps_client);
>  	}
>  
> @@ -3148,7 +3148,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
>  	if (dev_priv->gt.awake) {
>  		intel_sanitize_gt_powersave(dev_priv);
>  		intel_enable_gt_powersave(dev_priv);
> -		if (INTEL_GEN(dev_priv) >= 6)
> +		if (IS_GEN_GTE(dev_priv, 6))
>  			gen6_rps_busy(dev_priv);
>  	}
>  }
> @@ -3474,7 +3474,7 @@ i915_gem_idle_work_handler(struct work_struct *work)
>  	GEM_BUG_ON(epoch == I915_EPOCH_INVALID);
>  	rearm_hangcheck = false;
>  
> -	if (INTEL_GEN(dev_priv) >= 6)
> +	if (IS_GEN_GTE(dev_priv, 6))
>  		gen6_rps_idle(dev_priv);
>  
>  	intel_display_power_put(dev_priv, POWER_DOMAIN_GT_IRQ);
> @@ -4882,7 +4882,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
>  	 * it may impact the display and we are uncertain about the stability
>  	 * of the reset, so this could be applied to even earlier gen.
>  	 */
> -	if (INTEL_GEN(i915) >= 5) {
> +	if (IS_GEN_GTE(i915, 5)) {
>  		int reset = intel_gpu_reset(i915, ALL_ENGINES);
>  		WARN_ON(reset && reset != -ENODEV);
>  	}
> @@ -5010,7 +5010,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
>  
>  void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_GEN(dev_priv) < 5 ||
> +	if (IS_GEN_LT(dev_priv, 5) ||
>  	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
>  		return;
>  
> @@ -5084,7 +5084,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>  	/* Double layer security blanket, see i915_gem_init() */
>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
> -	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
> +	if (HAS_EDRAM(dev_priv) && IS_GEN_LT(dev_priv, 9))
>  		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
>  
>  	if (IS_HASWELL(dev_priv))
> @@ -5096,7 +5096,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>  			u32 temp = I915_READ(GEN7_MSG_CTL);
>  			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
>  			I915_WRITE(GEN7_MSG_CTL, temp);
> -		} else if (INTEL_GEN(dev_priv) >= 7) {
> +		} else if (IS_GEN_GTE(dev_priv, 7)) {
>  			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
>  			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
>  			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
> @@ -5420,10 +5420,10 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
>  {
>  	int i;
>  
> -	if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) &&
> +	if (IS_GEN_GTE(dev_priv, 7) && !IS_VALLEYVIEW(dev_priv) &&
>  	    !IS_CHERRYVIEW(dev_priv))
>  		dev_priv->num_fence_regs = 32;
> -	else if (INTEL_GEN(dev_priv) >= 4 ||
> +	else if (IS_GEN_GTE(dev_priv, 4) ||
>  		 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
>  		 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
>  		dev_priv->num_fence_regs = 16;
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 4401068ff468..f2da6e6d23c0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -2522,7 +2522,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
>  		exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
>  		exec2_list[i].alignment = exec_list[i].alignment;
>  		exec2_list[i].offset = exec_list[i].offset;
> -		if (INTEL_GEN(to_i915(dev)) < 4)
> +		if (IS_GEN_LT(to_i915(dev), 4))
>  			exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
>  		else
>  			exec2_list[i].flags = 0;
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> index b8338d75c6f3..fe69e970d1ed 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> @@ -557,7 +557,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
>  	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>  	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>  
> -	if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
> +	if (IS_GEN_GTE(dev_priv, 8) || IS_VALLEYVIEW(dev_priv)) {
>  		/*
>  		 * On BDW+, swizzling is not used. We leave the CPU memory
>  		 * controller in charge of optimizing memory accesses without
> @@ -567,7 +567,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
>  		 */
>  		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
>  		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> -	} else if (INTEL_GEN(dev_priv) >= 6) {
> +	} else if (IS_GEN_GTE(dev_priv, 6)) {
>  		if (dev_priv->preserve_bios_swizzle) {
>  			if (I915_READ(DISP_ARB_CTL) &
>  			    DISP_TILE_SURFACE_SWIZZLING) {
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0c0f1affddad..6fb0949facb4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -154,7 +154,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>  	 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
>  	 * execlists, the sole mechanism available to submit work.
>  	 */
> -	if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
> +	if (enable_ppgtt == 0 && IS_GEN_LT(dev_priv, 9))
>  		return 0;
>  
>  	if (enable_ppgtt == 1)
> @@ -2109,7 +2109,7 @@ static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
>  	ppgtt->base.i915 = dev_priv;
>  	ppgtt->base.dma = &dev_priv->drm.pdev->dev;
>  
> -	if (INTEL_GEN(dev_priv) < 8)
> +	if (IS_GEN_LT(dev_priv, 8))
>  		return gen6_ppgtt_init(ppgtt);
>  	else
>  		return gen8_ppgtt_init(ppgtt);
> @@ -2170,7 +2170,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
>  	 * driver.
>  	 */
>  	if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
> -	    INTEL_GEN(dev_priv) <= 10)
> +	    IS_GEN_LTE(dev_priv, 10))
>  		I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
>  			   I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
>  			   GAMW_ECO_ENABLE_64K_IPS_FIELD);
> @@ -2193,7 +2193,7 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
>  		gen6_ppgtt_enable(dev_priv);
>  	else if (IS_GEN7(dev_priv))
>  		gen7_ppgtt_enable(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 8)
> +	else if (IS_GEN_GTE(dev_priv, 8))
>  		gen8_ppgtt_enable(dev_priv);
>  	else
>  		MISSING_CASE(INTEL_GEN(dev_priv));
> @@ -2338,9 +2338,9 @@ static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
>  void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
>  {
>  	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
> -	if (INTEL_GEN(dev_priv) >= 8)
> +	if (IS_GEN_GTE(dev_priv, 8))
>  		gen8_check_and_clear_faults(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 6)
> +	else if (IS_GEN_GTE(dev_priv, 6))
>  		gen6_check_and_clear_faults(dev_priv);
>  	else
>  		return;
> @@ -2353,7 +2353,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
>  	/* Don't bother messing with faults pre GEN6 as we have little
>  	 * documentation supporting that it's a good idea.
>  	 */
> -	if (INTEL_GEN(dev_priv) < 6)
> +	if (IS_GEN_LT(dev_priv, 6))
>  		return;
>  
>  	i915_check_and_clear_faults(dev_priv);
> @@ -2999,7 +2999,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
>  	 * resort to an uncached mapping. The WC issue is easily caught by the
>  	 * readback check when writing GTT PTE entries.
>  	 */
> -	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> +	if (IS_GEN9_LP(dev_priv) || IS_GEN_GTE(dev_priv, 10))
>  		ggtt->gsm = ioremap_nocache(phys_addr, size);
>  	else
>  		ggtt->gsm = ioremap_wc(phys_addr, size);
> @@ -3294,7 +3294,7 @@ static void setup_private_pat(struct drm_i915_private *dev_priv)
>  
>  	ppat->i915 = dev_priv;
>  
> -	if (INTEL_GEN(dev_priv) >= 10)
> +	if (IS_GEN_GTE(dev_priv, 10))
>  		cnl_setup_private_ppat(ppat);
>  	else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
>  		chv_setup_private_ppat(ppat);
> @@ -3334,7 +3334,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>  
>  	pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		size = gen8_get_total_gtt_size(snb_gmch_ctl);
>  	} else if (IS_CHERRYVIEW(dev_priv)) {
>  		size = chv_get_total_gtt_size(snb_gmch_ctl);
> @@ -3418,7 +3418,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
>  		ggtt->base.pte_encode = hsw_pte_encode;
>  	else if (IS_VALLEYVIEW(dev_priv))
>  		ggtt->base.pte_encode = byt_pte_encode;
> -	else if (INTEL_GEN(dev_priv) >= 7)
> +	else if (IS_GEN_GTE(dev_priv, 7))
>  		ggtt->base.pte_encode = ivb_pte_encode;
>  	else
>  		ggtt->base.pte_encode = snb_pte_encode;
> @@ -3481,9 +3481,9 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
>  	ggtt->base.i915 = dev_priv;
>  	ggtt->base.dma = &dev_priv->drm.pdev->dev;
>  
> -	if (INTEL_GEN(dev_priv) <= 5)
> +	if (IS_GEN_LTE(dev_priv, 5))
>  		ret = i915_gmch_probe(ggtt);
> -	else if (INTEL_GEN(dev_priv) < 8)
> +	else if (IS_GEN_LT(dev_priv, 8))
>  		ret = gen6_gmch_probe(ggtt);
>  	else
>  		ret = gen8_gmch_probe(ggtt);
> @@ -3574,7 +3574,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
>  
>  int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt())
> +	if (IS_GEN_LT(dev_priv, 6) && !intel_enable_gtt())
>  		return -EIO;
>  
>  	return 0;
> @@ -3631,7 +3631,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
>  
>  	ggtt->base.closed = false;
>  
> -	if (INTEL_GEN(dev_priv) >= 8) {
> +	if (IS_GEN_GTE(dev_priv, 8)) {
>  		struct intel_ppat *ppat = &dev_priv->ppat;
>  
>  		bitmap_set(ppat->dirty, 0, ppat->max_entries);
> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
> index a8eb22a95b0f..38a3352e827a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_request.c
> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
> @@ -279,7 +279,7 @@ static void mark_busy(struct drm_i915_private *i915)
>  
>  	intel_enable_gt_powersave(i915);
>  	i915_update_gfx_val(i915);
> -	if (INTEL_GEN(i915) >= 6)
> +	if (IS_GEN_GTE(i915, 6))
>  		gen6_rps_busy(i915);
>  	i915_pmu_gt_unparked(i915);
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index f18da9e2be8e..5c7246db06a2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -91,7 +91,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv,
>  	 */
>  
>  	/* Make sure we don't clobber the GTT if it's within stolen memory */
> -	if (INTEL_GEN(dev_priv) <= 4 &&
> +	if (IS_GEN_LTE(dev_priv, 4) &&
>  	    !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv)) {
>  		struct resource stolen[2] = {*dsm, *dsm};
>  		struct resource ggtt_res;
> @@ -336,7 +336,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
>  		return 0;
>  	}
>  
> -	if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) {
> +	if (intel_vtd_active() && IS_GEN_LT(dev_priv, 8)) {
>  		DRM_INFO("DMAR active, disabling use of stolen memory\n");
>  		return 0;
>  	}
> @@ -412,7 +412,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
>  
>  	stolen_usable_start = 0;
>  	/* WaSkipStolenMemoryFirstPage:bdw+ */
> -	if (INTEL_GEN(dev_priv) >= 8)
> +	if (IS_GEN_GTE(dev_priv, 8))
>  		stolen_usable_start = 4096;
>  
>  	dev_priv->stolen_usable_size =
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index d9dc9df523b5..8a1e7082579a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -80,7 +80,7 @@ u32 i915_gem_fence_size(struct drm_i915_private *i915,
>  
>  	GEM_BUG_ON(!stride);
>  
> -	if (INTEL_GEN(i915) >= 4) {
> +	if (IS_GEN_GTE(i915, 4)) {
>  		stride *= i915_gem_tile_height(tiling);
>  		GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
>  		return roundup(size, stride);
> @@ -120,7 +120,7 @@ u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
>  	if (tiling == I915_TILING_NONE)
>  		return I915_GTT_MIN_ALIGNMENT;
>  
> -	if (INTEL_GEN(i915) >= 4)
> +	if (IS_GEN_GTE(i915, 4))
>  		return I965_FENCE_PAGE;
>  
>  	/*
> @@ -148,10 +148,10 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
>  	/* check maximum stride & object size */
>  	/* i965+ stores the end address of the gtt mapping in the fence
>  	 * reg, so dont bother to check the size */
> -	if (INTEL_GEN(i915) >= 7) {
> +	if (IS_GEN_GTE(i915, 7)) {
>  		if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
>  			return false;
> -	} else if (INTEL_GEN(i915) >= 4) {
> +	} else if (IS_GEN_GTE(i915, 4)) {
>  		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
>  			return false;
>  	} else {
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 67c902412193..c5a7ed4d9c1e 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -376,13 +376,13 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
>  	err_printf(m, "  INSTDONE: 0x%08x\n",
>  		   ee->instdone.instdone);
>  
> -	if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
> +	if (ee->engine_id != RCS || IS_GEN_LTE(m->i915, 3))
>  		return;
>  
>  	err_printf(m, "  SC_INSTDONE: 0x%08x\n",
>  		   ee->instdone.slice_common);
>  
> -	if (INTEL_GEN(m->i915) <= 6)
> +	if (IS_GEN_LTE(m->i915, 6))
>  		return;
>  
>  	for_each_instdone_slice_subslice(m->i915, slice, subslice)
> @@ -455,7 +455,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
>  			   upper_32_bits(start), lower_32_bits(start),
>  			   upper_32_bits(end), lower_32_bits(end));
>  	}
> -	if (INTEL_GEN(m->i915) >= 4) {
> +	if (IS_GEN_GTE(m->i915, 4)) {
>  		err_printf(m, "  BBADDR: 0x%08x_%08x\n",
>  			   (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
>  		err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
> @@ -464,7 +464,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
>  	err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
>  	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
>  		   lower_32_bits(ee->faddr));
> -	if (INTEL_GEN(m->i915) >= 6) {
> +	if (IS_GEN_GTE(m->i915, 6)) {
>  		err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
>  		err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
>  		err_printf(m, "  SYNC_0: 0x%08x\n",
> @@ -478,7 +478,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
>  	if (USES_PPGTT(m->i915)) {
>  		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
>  
> -		if (INTEL_GEN(m->i915) >= 8) {
> +		if (IS_GEN_GTE(m->i915, 8)) {
>  			int i;
>  			for (i = 0; i < 4; i++)
>  				err_printf(m, "  PDP%d: 0x%016llx\n",
> @@ -691,10 +691,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>  	for (i = 0; i < error->nfence; i++)
>  		err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (IS_GEN_GTE(dev_priv, 6)) {
>  		err_printf(m, "ERROR: 0x%08x\n", error->error);
>  
> -		if (INTEL_GEN(dev_priv) >= 8)
> +		if (IS_GEN_GTE(dev_priv, 8))
>  			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
>  				   error->fault_data1, error->fault_data0);
>  
> @@ -1087,10 +1087,10 @@ static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
>  {
>  	int i;
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (IS_GEN_GTE(dev_priv, 6)) {
>  		for (i = 0; i < dev_priv->num_fence_regs; i++)
>  			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
> -	} else if (INTEL_GEN(dev_priv) >= 4) {
> +	} else if (IS_GEN_GTE(dev_priv, 4)) {
>  		for (i = 0; i < dev_priv->num_fence_regs; i++)
>  			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
>  	} else {
> @@ -1192,9 +1192,9 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (IS_GEN_GTE(dev_priv, 6)) {
>  		ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
> -		if (INTEL_GEN(dev_priv) >= 8) {
> +		if (IS_GEN_GTE(dev_priv, 8)) {
>  			ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
>  		} else {
>  			gen6_record_semaphore_state(engine, ee);
> @@ -1202,13 +1202,13 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>  		}
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 4) {
> +	if (IS_GEN_GTE(dev_priv, 4)) {
>  		ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
>  		ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
>  		ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
>  		ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
>  		ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
> -		if (INTEL_GEN(dev_priv) >= 8) {
> +		if (IS_GEN_GTE(dev_priv, 8)) {
>  			ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
>  			ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
>  		}
> @@ -1230,7 +1230,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>  	ee->head = I915_READ_HEAD(engine);
>  	ee->tail = I915_READ_TAIL(engine);
>  	ee->ctl = I915_READ_CTL(engine);
> -	if (INTEL_GEN(dev_priv) > 2)
> +	if (IS_GEN_GT(dev_priv, 2))
>  		ee->mode = I915_READ_MODE(engine);
>  
>  	if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
> @@ -1280,7 +1280,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>  		else if (IS_GEN7(dev_priv))
>  			ee->vm_info.pp_dir_base =
>  				I915_READ(RING_PP_DIR_BASE(engine));
> -		else if (INTEL_GEN(dev_priv) >= 8)
> +		else if (IS_GEN_GTE(dev_priv, 8))
>  			for (i = 0; i < 4; i++) {
>  				ee->vm_info.pdp[i] =
>  					I915_READ(GEN8_RING_PDP_UDW(engine, i));
> @@ -1647,7 +1647,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
>  	if (IS_GEN7(dev_priv))
>  		error->err_int = I915_READ(GEN7_ERR_INT);
>  
> -	if (INTEL_GEN(dev_priv) >= 8) {
> +	if (IS_GEN_GTE(dev_priv, 8)) {
>  		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
>  		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
>  	}
> @@ -1659,16 +1659,16 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
>  	}
>  
>  	/* 2: Registers which belong to multiple generations */
> -	if (INTEL_GEN(dev_priv) >= 7)
> +	if (IS_GEN_GTE(dev_priv, 7))
>  		error->forcewake = I915_READ_FW(FORCEWAKE_MT);
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (IS_GEN_GTE(dev_priv, 6)) {
>  		error->derrmr = I915_READ(DERRMR);
>  		error->error = I915_READ(ERROR_GEN6);
>  		error->done_reg = I915_READ(DONE_REG);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 5)
> +	if (IS_GEN_GTE(dev_priv, 5))
>  		error->ccid = I915_READ(CCID);
>  
>  	/* 3: Feature specific registers */
> @@ -1678,7 +1678,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
>  	}
>  
>  	/* 4: Everything else */
> -	if (INTEL_GEN(dev_priv) >= 8) {
> +	if (IS_GEN_GTE(dev_priv, 8)) {
>  		error->ier = I915_READ(GEN8_DE_MISC_IER);
>  		for (i = 0; i < 4; i++)
>  			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b886bd459acc..f02d682a5ca9 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -308,17 +308,17 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
>  
>  static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
>  {
> -	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
> +	return IS_GEN_GTE(dev_priv, 8) ? GEN8_GT_IIR(2) : GEN6_PMIIR;
>  }
>  
>  static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
>  {
> -	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
> +	return IS_GEN_GTE(dev_priv, 8) ? GEN8_GT_IMR(2) : GEN6_PMIMR;
>  }
>  
>  static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
>  {
> -	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
> +	return IS_GEN_GTE(dev_priv, 8) ? GEN8_GT_IER(2) : GEN6_PMIER;
>  }
>  
>  /**
> @@ -585,7 +585,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
>  
>  	lockdep_assert_held(&dev_priv->irq_lock);
>  
> -	if (INTEL_GEN(dev_priv) < 5)
> +	if (IS_GEN_LT(dev_priv, 5))
>  		goto out;
>  
>  	/*
> @@ -676,7 +676,7 @@ static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
>  	spin_lock_irq(&dev_priv->irq_lock);
>  
>  	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		i915_enable_pipestat(dev_priv, PIPE_A,
>  				     PIPE_LEGACY_BLC_EVENT_STATUS);
>  
> @@ -947,7 +947,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
>  	if (stime)
>  		*stime = ktime_get();
>  
> -	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
> +	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5)) {
>  		/* No obvious pixelcount register. Only query vertical
>  		 * scanout position from Display scan line register.
>  		 */
> @@ -1007,7 +1007,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
>  	else
>  		position += vtotal - vbl_end;
>  
> -	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
> +	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5)) {
>  		*vpos = position;
>  		*hpos = 0;
>  	} else {
> @@ -1652,7 +1652,7 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>  		 * don't trust that one either.
>  		 */
>  		if (pipe_crc->skipped == 0 ||
> -		    (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
> +		    (IS_GEN_GTE(dev_priv, 8) && pipe_crc->skipped == 1)) {
>  			pipe_crc->skipped++;
>  			spin_unlock(&pipe_crc->lock);
>  			return;
> @@ -1702,12 +1702,12 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>  {
>  	uint32_t res1, res2;
>  
> -	if (INTEL_GEN(dev_priv) >= 3)
> +	if (IS_GEN_GTE(dev_priv, 3))
>  		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
>  	else
>  		res1 = 0;
>  
> -	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> +	if (IS_GEN_GTE(dev_priv, 5) || IS_G4X(dev_priv))
>  		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
>  	else
>  		res2 = 0;
> @@ -1736,7 +1736,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
>  		spin_unlock(&dev_priv->irq_lock);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 8)
> +	if (IS_GEN_GTE(dev_priv, 8))
>  		return;
>  
>  	if (HAS_VEBOX(dev_priv)) {
> @@ -2482,7 +2482,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
>  	if (gt_iir) {
>  		I915_WRITE(GTIIR, gt_iir);
>  		ret = IRQ_HANDLED;
> -		if (INTEL_GEN(dev_priv) >= 6)
> +		if (IS_GEN_GTE(dev_priv, 6))
>  			snb_gt_irq_handler(dev_priv, gt_iir);
>  		else
>  			ilk_gt_irq_handler(dev_priv, gt_iir);
> @@ -2492,13 +2492,13 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
>  	if (de_iir) {
>  		I915_WRITE(DEIIR, de_iir);
>  		ret = IRQ_HANDLED;
> -		if (INTEL_GEN(dev_priv) >= 7)
> +		if (IS_GEN_GTE(dev_priv, 7))
>  			ivb_display_irq_handler(dev_priv, de_iir);
>  		else
>  			ilk_display_irq_handler(dev_priv, de_iir);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (IS_GEN_GTE(dev_priv, 6)) {
>  		u32 pm_iir = I915_READ(GEN6_PMIIR);
>  		if (pm_iir) {
>  			I915_WRITE(GEN6_PMIIR, pm_iir);
> @@ -2567,7 +2567,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  			ret = IRQ_HANDLED;
>  
>  			tmp_mask = GEN8_AUX_CHANNEL_A;
> -			if (INTEL_GEN(dev_priv) >= 9)
> +			if (IS_GEN_GTE(dev_priv, 9))
>  				tmp_mask |= GEN9_AUX_CHANNEL_B |
>  					    GEN9_AUX_CHANNEL_C |
>  					    GEN9_AUX_CHANNEL_D;
> @@ -2633,7 +2633,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
>  
>  		fault_errors = iir;
> -		if (INTEL_GEN(dev_priv) >= 9)
> +		if (IS_GEN_GTE(dev_priv, 9))
>  			fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
>  		else
>  			fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> @@ -2802,7 +2802,7 @@ static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
>  	if (!IS_GEN2(dev_priv))
>  		I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
>  
> -	if (INTEL_GEN(dev_priv) < 4)
> +	if (IS_GEN_LT(dev_priv, 4))
>  		I915_WRITE(IPEIR, I915_READ(IPEIR));
>  	else
>  		I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
> @@ -2944,7 +2944,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	unsigned long irqflags;
> -	uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
> +	uint32_t bit = IS_GEN_GTE(dev_priv, 7) ?
>  		DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
>  
>  	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> @@ -2994,7 +2994,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	unsigned long irqflags;
> -	uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
> +	uint32_t bit = IS_GEN_GTE(dev_priv, 7) ?
>  		DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
>  
>  	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> @@ -3046,7 +3046,7 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
>  static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
>  {
>  	GEN3_IRQ_RESET(GT);
> -	if (INTEL_GEN(dev_priv) >= 6)
> +	if (IS_GEN_GTE(dev_priv, 6))
>  		GEN3_IRQ_RESET(GEN6_PM);
>  }
>  
> @@ -3330,12 +3330,12 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
>  {
>  	u32 hotplug_irqs, enabled_irqs;
>  
> -	if (INTEL_GEN(dev_priv) >= 8) {
> +	if (IS_GEN_GTE(dev_priv, 8)) {
>  		hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
>  		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
>  
>  		bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
> -	} else if (INTEL_GEN(dev_priv) >= 7) {
> +	} else if (IS_GEN_GTE(dev_priv, 7)) {
>  		hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
>  		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
>  
> @@ -3448,7 +3448,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
>  
>  	GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (IS_GEN_GTE(dev_priv, 6)) {
>  		/*
>  		 * RPS interrupts will get enabled/disabled on demand when RPS
>  		 * itself is enabled/disabled.
> @@ -3468,7 +3468,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	u32 display_mask, extra_mask;
>  
> -	if (INTEL_GEN(dev_priv) >= 7) {
> +	if (IS_GEN_GTE(dev_priv, 7)) {
>  		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
>  				DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
>  		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
> @@ -3596,7 +3596,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	u32 de_misc_masked = GEN8_DE_MISC_GSE;
>  	enum pipe pipe;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
>  		de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
>  				  GEN9_AUX_CHANNEL_D;
> @@ -4048,16 +4048,16 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  	 *
>  	 * TODO: verify if this can be reproduced on VLV,CHV.
>  	 */
> -	if (INTEL_GEN(dev_priv) <= 7)
> +	if (IS_GEN_LTE(dev_priv, 7))
>  		rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
>  
> -	if (INTEL_GEN(dev_priv) >= 8)
> +	if (IS_GEN_GTE(dev_priv, 8))
>  		rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
>  
>  	if (IS_GEN2(dev_priv)) {
>  		/* Gen2 doesn't have a hardware frame counter */
>  		dev->max_vblank_count = 0;
> -	} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
> +	} else if (IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5)) {
>  		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
>  		dev->driver->get_vblank_counter = g4x_get_vblank_counter;
>  	} else {
> @@ -4104,7 +4104,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		dev->driver->enable_vblank = i965_enable_vblank;
>  		dev->driver->disable_vblank = i965_disable_vblank;
>  		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> -	} else if (INTEL_GEN(dev_priv) >= 8) {
> +	} else if (IS_GEN_GTE(dev_priv, 8)) {
>  		dev->driver->irq_handler = gen8_irq_handler;
>  		dev->driver->irq_preinstall = gen8_irq_reset;
>  		dev->driver->irq_postinstall = gen8_irq_postinstall;
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index f0cfdece14ae..d31605ebad69 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -3253,7 +3253,7 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
>  		goto reg_err;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) < 8) {
> +	if (IS_GEN_LT(dev_priv, 8)) {
>  		if (args->n_flex_regs != 0) {
>  			err = -EINVAL;
>  			goto reg_err;
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index a0f56925532e..7a99a2e7eeda 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -319,7 +319,7 @@ engine_event_status(struct intel_engine_cs *engine,
>  	case I915_SAMPLE_WAIT:
>  		break;
>  	case I915_SAMPLE_SEMA:
> -		if (INTEL_GEN(engine->i915) < 6)
> +		if (IS_GEN_LT(engine->i915, 6))
>  			return -ENODEV;
>  		break;
>  	default:
> @@ -339,7 +339,7 @@ config_status(struct drm_i915_private *i915, u64 config)
>  			return -ENODEV;
>  		/* Fall-through. */
>  	case I915_PMU_REQUESTED_FREQUENCY:
> -		if (INTEL_GEN(i915) < 6)
> +		if (IS_GEN_LT(i915, 6))
>  			return -ENODEV;
>  		break;
>  	case I915_PMU_INTERRUPTS:
> @@ -1005,7 +1005,7 @@ void i915_pmu_register(struct drm_i915_private *i915)
>  {
>  	int ret;
>  
> -	if (INTEL_GEN(i915) <= 2) {
> +	if (IS_GEN_LTE(i915, 2)) {
>  		DRM_INFO("PMU not supported for this GPU.");
>  		return;
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e9c79b560823..fd3948f1d44a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3792,7 +3792,7 @@ enum i915_power_well_id {
>  #define INTERVAL_1_28_US(us)	roundup(((us) * 100) >> 7, 25)
>  #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
>  #define INTERVAL_0_833_US(us)	(((us) * 6) / 5)
> -#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
> +#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN_GTE(dev_priv, 9) ? \
>  				(IS_GEN9_LP(dev_priv) ? \
>  				INTERVAL_0_833_US(us) : \
>  				INTERVAL_1_33_US(us)) : \
> @@ -3801,7 +3801,7 @@ enum i915_power_well_id {
>  #define INTERVAL_1_28_TO_US(interval)  (((interval) << 7) / 100)
>  #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
>  #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
> -#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
> +#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN_GTE(dev_priv, 9) ? \
>                             (IS_GEN9_LP(dev_priv) ? \
>                             INTERVAL_0_833_TO_US(interval) : \
>                             INTERVAL_1_33_TO_US(interval)) : \
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 8f3aa4dc0c98..afe8da487660 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -32,25 +32,25 @@
>  static void i915_save_display(struct drm_i915_private *dev_priv)
>  {
>  	/* Display arbitration control */
> -	if (INTEL_GEN(dev_priv) <= 4)
> +	if (IS_GEN_LTE(dev_priv, 4))
>  		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
>  
>  	/* save FBC interval */
> -	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
> +	if (HAS_FBC(dev_priv) && IS_GEN_LTE(dev_priv, 4) && !IS_G4X(dev_priv))
>  		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
>  }
>  
>  static void i915_restore_display(struct drm_i915_private *dev_priv)
>  {
>  	/* Display arbitration */
> -	if (INTEL_GEN(dev_priv) <= 4)
> +	if (IS_GEN_LTE(dev_priv, 4))
>  		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
>  
>  	/* only restore FBC info on the platform that supports FBC*/
>  	intel_fbc_global_disable(dev_priv);
>  
>  	/* restore FBC interval */
> -	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
> +	if (HAS_FBC(dev_priv) && IS_GEN_LTE(dev_priv, 4) && !IS_G4X(dev_priv))
>  		I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
>  
>  	i915_redisable_vga(dev_priv);
> @@ -70,7 +70,7 @@ int i915_save_state(struct drm_i915_private *dev_priv)
>  				     &dev_priv->regfile.saveGCDGMBUS);
>  
>  	/* Cache mode state */
> -	if (INTEL_GEN(dev_priv) < 7)
> +	if (IS_GEN_LT(dev_priv, 7))
>  		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
>  
>  	/* Memory Arbitration state */
> @@ -114,7 +114,7 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
>  	i915_restore_display(dev_priv);
>  
>  	/* Cache mode state */
> -	if (INTEL_GEN(dev_priv) < 7)
> +	if (IS_GEN_LT(dev_priv, 7))
>  		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
>  			   0xffff0000);
>  
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index c74a20b80182..3d8fd58912cb 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -611,7 +611,7 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
>  	ret = 0;
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
> -	else if (INTEL_GEN(dev_priv) >= 6)
> +	else if (IS_GEN_GTE(dev_priv, 6))
>  		ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
>  	if (ret)
>  		DRM_ERROR("RPS sysfs setup failed\n");
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 0ee32275994a..e59a50b44e85 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -172,7 +172,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  	 * Y-tiling is not supported in IF-ID Interlace mode in
>  	 * GEN9 and above.
>  	 */
> -	if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
> +	if (state->fb && IS_GEN_GTE(dev_priv, 9) && crtc_state->base.enable &&
>  	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
>  		if (state->fb->modifier == I915_FORMAT_MOD_Y_TILED ||
>  		    state->fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index ff455c724775..f8705138bf4a 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -704,7 +704,7 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
>  		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
> -	} else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
> +	} else if (IS_HASWELL(dev_priv) || IS_GEN_GTE(dev_priv, 8)) {
>  		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
>  		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index aab6d1538fff..b13fb999340c 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1895,7 +1895,7 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
>  static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
>  				     int pixel_rate)
>  {
> -	if (INTEL_GEN(dev_priv) >= 10)
> +	if (IS_GEN_GTE(dev_priv, 10))
>  		return DIV_ROUND_UP(pixel_rate, 2);
>  	else if (IS_GEMINILAKE(dev_priv))
>  		/*
> @@ -1950,7 +1950,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	/* According to BSpec, "The CD clock frequency must be at least twice
>  	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
>  	 */
> -	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
> +	if (crtc_state->has_audio && IS_GEN_GTE(dev_priv, 9))
>  		min_cdclk = max(2 * 96000, min_cdclk);
>  
>  	/*
> @@ -2220,7 +2220,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>  {
>  	int max_cdclk_freq = dev_priv->max_cdclk_freq;
>  
> -	if (INTEL_GEN(dev_priv) >= 10)
> +	if (IS_GEN_GTE(dev_priv, 10))
>  		return 2 * max_cdclk_freq;
>  	else if (IS_GEMINILAKE(dev_priv))
>  		/*
> @@ -2233,7 +2233,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>  		return max_cdclk_freq;
>  	else if (IS_CHERRYVIEW(dev_priv))
>  		return max_cdclk_freq*95/100;
> -	else if (INTEL_GEN(dev_priv) < 4)
> +	else if (IS_GEN_LT(dev_priv, 4))
>  		return 2*max_cdclk_freq*90/100;
>  	else
>  		return max_cdclk_freq*90/100;
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index aa66e952a95d..31c9a5b62297 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -222,7 +222,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
>  	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
>  	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
>  
> -	if (INTEL_GEN(dev_priv) > 6) {
> +	if (IS_GEN_GT(dev_priv, 6)) {
>  		uint16_t postoff = 0;
>  
>  		if (intel_crtc_state->limited_color_range)
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 1cd4a7c22bd5..871576790668 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -154,7 +154,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
>  	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
>  	u32 adpa;
>  
> -	if (INTEL_GEN(dev_priv) >= 5)
> +	if (IS_GEN_GTE(dev_priv, 5))
>  		adpa = ADPA_HOTPLUG_BITS;
>  	else
>  		adpa = 0;
> @@ -799,7 +799,7 @@ intel_crt_detect(struct drm_connector *connector,
>  	if (ret > 0) {
>  		if (intel_crt_detect_ddc(connector))
>  			status = connector_status_connected;
> -		else if (INTEL_GEN(dev_priv) < 4)
> +		else if (IS_GEN_LT(dev_priv, 4))
>  			status = intel_crt_load_detect(crt,
>  				to_intel_crtc(connector->state->crtc)->pipe);
>  		else if (i915_modparams.load_detect_test)
> @@ -854,7 +854,7 @@ void intel_crt_reset(struct drm_encoder *encoder)
>  	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
>  	struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
>  
> -	if (INTEL_GEN(dev_priv) >= 5) {
> +	if (IS_GEN_GTE(dev_priv, 5)) {
>  		u32 adpa;
>  
>  		adpa = I915_READ(crt->adpa_reg);
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 8ca376aca8bd..5ae9cd02cd39 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1458,7 +1458,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  
> -	if (INTEL_GEN(dev_priv) <= 8)
> +	if (IS_GEN_LTE(dev_priv, 8))
>  		hsw_ddi_clock_get(encoder, pipe_config);
>  	else if (IS_GEN9_BC(dev_priv))
>  		skl_ddi_clock_get(encoder, pipe_config);
> @@ -2152,7 +2152,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  
>  		I915_WRITE(DPLL_CTRL2, val);
>  
> -	} else if (INTEL_GEN(dev_priv) < 9) {
> +	} else if (IS_GEN_LT(dev_priv, 9)) {
>  		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
>  	}
>  
> @@ -2170,7 +2170,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
>  	else if (IS_GEN9_BC(dev_priv))
>  		I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
>  			   DPLL_CTRL2_DDI_CLK_OFF(port));
> -	else if (INTEL_GEN(dev_priv) < 9)
> +	else if (IS_GEN_LT(dev_priv, 9))
>  		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
>  }
>  
> @@ -2207,7 +2207,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>  	if (!is_mst)
>  		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>  	intel_dp_start_link_train(intel_dp);
> -	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> +	if (port != PORT_A || IS_GEN_GTE(dev_priv, 9))
>  		intel_dp_stop_link_train(intel_dp);
>  }
>  
> @@ -2409,7 +2409,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	enum port port = encoder->port;
>  
> -	if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
> +	if (port == PORT_A && IS_GEN_LT(dev_priv, 9))
>  		intel_dp_stop_link_train(intel_dp);
>  
>  	intel_edp_backlight_on(crtc_state, conn_state);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index ae6f5b7b7978..068705c91332 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -380,7 +380,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>  	u32 f19_2_mhz = 19200;
>  	u32 f24_mhz = 24000;
>  
> -	if (INTEL_GEN(dev_priv) <= 4) {
> +	if (IS_GEN_LTE(dev_priv, 4)) {
>  		/* PRMs say:
>  		 *
>  		 *     "The value in this register increments once every 16
> @@ -388,7 +388,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>  		 *      (“CLKCFG”) MCHBAR register)
>  		 */
>  		return dev_priv->rawclk_freq / 16;
> -	} else if (INTEL_GEN(dev_priv) <= 8) {
> +	} else if (IS_GEN_LTE(dev_priv, 8)) {
>  		/* PRMs say:
>  		 *
>  		 *     "The PCU TSC counts 10ns increments; this timestamp
> @@ -396,7 +396,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>  		 *      rolling over every 1.5 hours).
>  		 */
>  		return f12_5_mhz;
> -	} else if (INTEL_GEN(dev_priv) <= 9) {
> +	} else if (IS_GEN_LTE(dev_priv, 9)) {
>  		u32 ctc_reg = I915_READ(CTC_MODE);
>  		u32 freq = 0;
>  
> @@ -414,7 +414,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>  		}
>  
>  		return freq;
> -	} else if (INTEL_GEN(dev_priv) <= 10) {
> +	} else if (IS_GEN_LTE(dev_priv, 10)) {
>  		u32 ctc_reg = I915_READ(CTC_MODE);
>  		u32 freq = 0;
>  		u32 rpm_config_reg = 0;
> @@ -480,7 +480,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>  		container_of(info, struct drm_i915_private, info);
>  	enum pipe pipe;
>  
> -	if (INTEL_GEN(dev_priv) >= 10) {
> +	if (IS_GEN_GTE(dev_priv, 10)) {
>  		for_each_pipe(dev_priv, pipe)
>  			info->num_scalers[pipe] = 2;
>  	} else if (IS_GEN9(dev_priv)) {
> @@ -507,7 +507,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		for_each_pipe(dev_priv, pipe)
>  			info->num_sprites[pipe] = 2;
> -	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> +	} else if (IS_GEN_GTE(dev_priv, 5) || IS_G4X(dev_priv)) {
>  		for_each_pipe(dev_priv, pipe)
>  			info->num_sprites[pipe] = 1;
>  	}
> @@ -580,7 +580,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>  		broadwell_sseu_info_init(dev_priv);
>  	else if (IS_GEN9(dev_priv))
>  		gen9_sseu_info_init(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 10)
> +	else if (IS_GEN_GTE(dev_priv, 10))
>  		gen10_sseu_info_init(dev_priv);
>  
>  	/* Initialize command stream timestamp frequency */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0d5207dbfdac..00efc4e6b7ce 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1044,7 +1044,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
>  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -	if (INTEL_GEN(dev_priv) >= 4) {
> +	if (IS_GEN_GTE(dev_priv, 4)) {
>  		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>  		i915_reg_t reg = PIPECONF(cpu_transcoder);
>  
> @@ -1542,7 +1542,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
>  	POSTING_READ(reg);
>  	udelay(150);
>  
> -	if (INTEL_GEN(dev_priv) >= 4) {
> +	if (IS_GEN_GTE(dev_priv, 4)) {
>  		I915_WRITE(DPLL_MD(crtc->pipe),
>  			   crtc_state->dpll_hw_state.dpll_md);
>  	} else {
> @@ -2029,12 +2029,12 @@ static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_pr
>  
>  static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		return 256 * 1024;
>  	else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
>  		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return 128 * 1024;
> -	else if (INTEL_GEN(dev_priv) >= 4)
> +	else if (IS_GEN_GTE(dev_priv, 4))
>  		return 4 * 1024;
>  	else
>  		return 0;
> @@ -2053,7 +2053,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>  	case DRM_FORMAT_MOD_LINEAR:
>  		return intel_linear_alignment(dev_priv);
>  	case I915_FORMAT_MOD_X_TILED:
> -		if (INTEL_GEN(dev_priv) >= 9)
> +		if (IS_GEN_GTE(dev_priv, 9))
>  			return 256 * 1024;
>  		return 0;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
> @@ -3163,7 +3163,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>  
> -	if (INTEL_GEN(dev_priv) < 4)
> +	if (IS_GEN_LT(dev_priv, 4))
>  		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
>  
>  	switch (fb->format->format) {
> @@ -3193,7 +3193,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
>  		return 0;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 4 &&
> +	if (IS_GEN_GTE(dev_priv, 4) &&
>  	    fb->modifier == I915_FORMAT_MOD_X_TILED)
>  		dspcntr |= DISPPLANE_TILED;
>  
> @@ -3216,7 +3216,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
>  
>  	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
>  
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		offset = intel_compute_tile_offset(&src_x, &src_y,
>  						   plane_state, 0);
>  	else
> @@ -3260,14 +3260,14 @@ static void i9xx_update_plane(struct intel_plane *plane,
>  
>  	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>  
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		dspaddr_offset = plane_state->main.offset;
>  	else
>  		dspaddr_offset = linear_offset;
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> -	if (INTEL_GEN(dev_priv) < 4) {
> +	if (IS_GEN_LT(dev_priv, 4)) {
>  		/* pipesrc and dspsize control the size that is scaled from,
>  		 * which should always be the user's requested size.
>  		 */
> @@ -3291,7 +3291,7 @@ static void i9xx_update_plane(struct intel_plane *plane,
>  			      intel_plane_ggtt_offset(plane_state) +
>  			      dspaddr_offset);
>  		I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
> -	} else if (INTEL_GEN(dev_priv) >= 4) {
> +	} else if (IS_GEN_GTE(dev_priv, 4)) {
>  		I915_WRITE_FW(DSPSURF(i9xx_plane),
>  			      intel_plane_ggtt_offset(plane_state) +
>  			      dspaddr_offset);
> @@ -3317,7 +3317,7 @@ static void i9xx_disable_plane(struct intel_plane *plane,
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
>  	I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
>  	else
>  		I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
> @@ -3538,7 +3538,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  
>  	plane_ctl = PLANE_CTL_ENABLE;
>  
> -	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
> +	if (IS_GEN_LT(dev_priv, 10) && !IS_GEMINILAKE(dev_priv)) {
>  		plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
>  		plane_ctl |=
>  			PLANE_CTL_PIPE_GAMMA_ENABLE |
> @@ -3550,7 +3550,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  	plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
>  	plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
>  
> -	if (INTEL_GEN(dev_priv) >= 10)
> +	if (IS_GEN_GTE(dev_priv, 10))
>  		plane_ctl |= cnl_plane_ctl_flip(rotation &
>  						DRM_MODE_REFLECT_MASK);
>  
> @@ -3618,7 +3618,7 @@ __intel_display_resume(struct drm_device *dev,
>  static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
>  {
>  	return intel_has_gpu_reset(dev_priv) &&
> -		INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
> +		IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv);
>  }
>  
>  void intel_prepare_reset(struct drm_i915_private *dev_priv)
> @@ -3757,7 +3757,7 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
>  		   (new_crtc_state->pipe_src_h - 1));
>  
>  	/* on skylake this is done by detaching scalers */
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		skl_detach_scalers(crtc);
>  
>  		if (new_crtc_state->pch_pfit.enabled)
> @@ -4683,7 +4683,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  	 * Once NV12 is enabled, handle it here while allocating scaler
>  	 * for NV12.
>  	 */
> -	if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
> +	if (IS_GEN_GTE(dev_priv, 9) && crtc_state->base.enable &&
>  	    need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
>  		DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
>  		return -EINVAL;
> @@ -5477,7 +5477,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  	if (psl_clkgate_wa)
>  		glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		skylake_pfit_enable(intel_crtc);
>  	else
>  		ironlake_pfit_enable(intel_crtc);
> @@ -5623,7 +5623,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
>  	if (!transcoder_is_dsi(cpu_transcoder))
>  		intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		skylake_scaler_disable(intel_crtc);
>  	else
>  		ironlake_pfit_disable(intel_crtc, false);
> @@ -6307,7 +6307,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
>  	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	/* GDG double wide on either pipe, otherwise pipe A only */
> -	return INTEL_GEN(dev_priv) < 4 &&
> +	return IS_GEN_LT(dev_priv, 4) &&
>  		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
>  }
>  
> @@ -6367,7 +6367,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>  	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
>  	int clock_limit = dev_priv->max_dotclk_freq;
>  
> -	if (INTEL_GEN(dev_priv) < 4) {
> +	if (IS_GEN_LT(dev_priv, 4)) {
>  		clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
>  
>  		/*
> @@ -6420,7 +6420,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>  	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
>  	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
>  	 */
> -	if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
> +	if ((IS_GEN_GT(dev_priv, 4) || IS_G4X(dev_priv)) &&
>  		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
>  		return -EINVAL;
>  
> @@ -6577,7 +6577,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>  	int pipe = crtc->pipe;
>  	enum transcoder transcoder = crtc->config->cpu_transcoder;
>  
> -	if (INTEL_GEN(dev_priv) >= 5) {
> +	if (IS_GEN_GTE(dev_priv, 5)) {
>  		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
>  		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
>  		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
> @@ -6587,7 +6587,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>  		 * registers are not unnecessarily accessed).
>  		 */
>  		if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
> -		    INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
> +		    IS_GEN_LT(dev_priv, 8)) && crtc->config->has_drrs) {
>  			I915_WRITE(PIPE_DATA_M2(transcoder),
>  					TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
>  			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
> @@ -6971,7 +6971,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
>  		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
>  		break;
>  	}
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
>  
>  	if (crtc_state->sdvo_tv_clock)
> @@ -6985,7 +6985,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
>  	dpll |= DPLL_VCO_ENABLE;
>  	crtc_state->dpll_hw_state.dpll = dpll;
>  
> -	if (INTEL_GEN(dev_priv) >= 4) {
> +	if (IS_GEN_GTE(dev_priv, 4)) {
>  		u32 dpll_md = (crtc_state->pixel_multiplier - 1)
>  			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
>  		crtc_state->dpll_hw_state.dpll_md = dpll_md;
> @@ -7058,7 +7058,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
>  			vsyncshift += adjusted_mode->crtc_htotal;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) > 3)
> +	if (IS_GEN_GT(dev_priv, 3))
>  		I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
>  
>  	I915_WRITE(HTOTAL(cpu_transcoder),
> @@ -7217,7 +7217,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>  	}
>  
>  	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> -		if (INTEL_GEN(dev_priv) < 4 ||
> +		if (IS_GEN_LT(dev_priv, 4) ||
>  		    intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
>  			pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
>  		else
> @@ -7428,7 +7428,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	uint32_t tmp;
>  
> -	if (INTEL_GEN(dev_priv) <= 3 &&
> +	if (IS_GEN_LTE(dev_priv, 3) &&
>  	    (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
>  		return;
>  
> @@ -7437,7 +7437,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
>  		return;
>  
>  	/* Check whether the pfit is attached to our pipe. */
> -	if (INTEL_GEN(dev_priv) < 4) {
> +	if (IS_GEN_LT(dev_priv, 4)) {
>  		if (crtc->pipe != PIPE_B)
>  			return;
>  	} else {
> @@ -7506,7 +7506,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>  
>  	val = I915_READ(DSPCNTR(i9xx_plane));
>  
> -	if (INTEL_GEN(dev_priv) >= 4) {
> +	if (IS_GEN_GTE(dev_priv, 4)) {
>  		if (val & DISPPLANE_TILED) {
>  			plane_config->tiling = I915_TILING_X;
>  			fb->modifier = I915_FORMAT_MOD_X_TILED;
> @@ -7520,7 +7520,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>  		offset = I915_READ(DSPOFFSET(i9xx_plane));
>  		base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
> -	} else if (INTEL_GEN(dev_priv) >= 4) {
> +	} else if (IS_GEN_GTE(dev_priv, 4)) {
>  		if (plane_config->tiling)
>  			offset = I915_READ(DSPTILEOFF(i9xx_plane));
>  		else
> @@ -7626,7 +7626,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
>  		pipe_config->limited_color_range = true;
>  
> -	if (INTEL_GEN(dev_priv) < 4)
> +	if (IS_GEN_LT(dev_priv, 4))
>  		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
>  
>  	intel_get_pipe_timings(crtc, pipe_config);
> @@ -7634,7 +7634,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  
>  	i9xx_get_pfit_config(crtc, pipe_config);
>  
> -	if (INTEL_GEN(dev_priv) >= 4) {
> +	if (IS_GEN_GTE(dev_priv, 4)) {
>  		/* No way to read it out on pipes B and C */
>  		if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
>  			tmp = dev_priv->chv_dpll_md[crtc->pipe];
> @@ -8194,7 +8194,7 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_crtc_state *config = intel_crtc->config;
>  
> -	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_BROADWELL(dev_priv) || IS_GEN_GTE(dev_priv, 9)) {
>  		u32 val = 0;
>  
>  		switch (intel_crtc->config->pipe_bpp) {
> @@ -8425,7 +8425,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  
> -	if (INTEL_GEN(dev_priv) >= 5) {
> +	if (IS_GEN_GTE(dev_priv, 5)) {
>  		m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
>  		m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
>  		m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
> @@ -8437,7 +8437,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
>  		 * gen < 8) and if DRRS is supported (to make sure the
>  		 * registers are not unnecessarily read).
>  		 */
> -		if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
> +		if (m2_n2 && IS_GEN_LT(dev_priv, 8) &&
>  			crtc->config->has_drrs) {
>  			m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
>  			m2_n2->link_n =	I915_READ(PIPE_LINK_N2(transcoder));
> @@ -8536,12 +8536,12 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  
>  	val = I915_READ(PLANE_CTL(pipe, plane_id));
>  
> -	if (INTEL_GEN(dev_priv) >= 11)
> +	if (IS_GEN_GTE(dev_priv, 11))
>  		pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
>  	else
>  		pixel_format = val & PLANE_CTL_FORMAT_MASK;
>  
> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> +	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) {
>  		alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
>  		alpha &= PLANE_COLOR_ALPHA_MASK;
>  	} else {
> @@ -9188,7 +9188,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>  	 * DDI E. So just check whether this pipe is wired to DDI E and whether
>  	 * the PCH transcoder is on.
>  	 */
> -	if (INTEL_GEN(dev_priv) < 9 &&
> +	if (IS_GEN_LT(dev_priv, 9) &&
>  	    (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
>  		pipe_config->has_pch_encoder = true;
>  
> @@ -9238,11 +9238,11 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  	pipe_config->gamma_mode =
>  		I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
>  
> -	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_BROADWELL(dev_priv) || IS_GEN_GTE(dev_priv, 9)) {
>  		u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
>  		bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
>  
> -		if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
> +		if (IS_GEMINILAKE(dev_priv) || IS_GEN_GTE(dev_priv, 10)) {
>  			bool blend_mode_420 = tmp &
>  					      PIPEMISC_YUV420_MODE_FULL_BLEND;
>  
> @@ -9258,7 +9258,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  	power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
>  	if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
>  		power_domain_mask |= BIT_ULL(power_domain);
> -		if (INTEL_GEN(dev_priv) >= 9)
> +		if (IS_GEN_GTE(dev_priv, 9))
>  			skylake_get_pfit_config(crtc, pipe_config);
>  		else
>  			ironlake_get_pfit_config(crtc, pipe_config);
> @@ -10227,7 +10227,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
>  	struct drm_framebuffer *fb = plane_state->fb;
>  	int ret;
>  
> -	if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
> +	if (IS_GEN_GTE(dev_priv, 9) && plane->id != PLANE_CURSOR) {
>  		ret = skl_update_scaler_plane(
>  			to_intel_crtc_state(crtc_state),
>  			to_intel_plane_state(plane_state));
> @@ -10276,21 +10276,21 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
>  			 turn_off, turn_on, mode_changed);
>  
>  	if (turn_on) {
> -		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
> +		if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv))
>  			pipe_config->update_wm_pre = true;
>  
>  		/* must disable cxsr around plane enable/disable */
>  		if (plane->id != PLANE_CURSOR)
>  			pipe_config->disable_cxsr = true;
>  	} else if (turn_off) {
> -		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
> +		if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv))
>  			pipe_config->update_wm_post = true;
>  
>  		/* must disable cxsr around plane enable/disable */
>  		if (plane->id != PLANE_CURSOR)
>  			pipe_config->disable_cxsr = true;
>  	} else if (intel_wm_need_update(&plane->base, plane_state)) {
> -		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
> +		if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv)) {
>  			/* FIXME bollocks */
>  			pipe_config->update_wm_pre = true;
>  			pipe_config->update_wm_post = true;
> @@ -10407,11 +10407,11 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
>  			return ret;
>  		}
>  	} else if (dev_priv->display.compute_intermediate_wm) {
> -		if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
> +		if (HAS_PCH_SPLIT(dev_priv) && IS_GEN_LT(dev_priv, 9))
>  			pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		if (mode_changed)
>  			ret = skl_update_scaler_crtc(pipe_config);
>  
> @@ -10499,7 +10499,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
>  	if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
>  	    IS_CHERRYVIEW(dev_priv)))
>  		bpp = 10*3;
> -	else if (INTEL_GEN(dev_priv) >= 5)
> +	else if (IS_GEN_GTE(dev_priv, 5))
>  		bpp = 12*3;
>  	else
>  		bpp = 8*3;
> @@ -10641,7 +10641,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
>  		      pipe_config->pipe_src_w, pipe_config->pipe_src_h,
>  		      pipe_config->pixel_rate);
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
>  			      crtc->num_scalers,
>  			      pipe_config->scaler_state.scaler_users,
> @@ -10682,7 +10682,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
>  			      plane->base.id, plane->name,
>  			      fb->base.id, fb->width, fb->height,
>  			      drm_get_format_name(fb->format->format, &format_name));
> -		if (INTEL_GEN(dev_priv) >= 9)
> +		if (IS_GEN_GTE(dev_priv, 9))
>  			DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
>  				      state->scaler_id,
>  				      state->base.src.x1 >> 16,
> @@ -11167,7 +11167,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>  	PIPE_CONF_CHECK_I(lane_count);
>  	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
>  
> -	if (INTEL_GEN(dev_priv) < 8) {
> +	if (IS_GEN_LT(dev_priv, 8)) {
>  		PIPE_CONF_CHECK_M_N(dp_m_n);
>  
>  		if (current_config->has_drrs)
> @@ -11193,7 +11193,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>  
>  	PIPE_CONF_CHECK_I(pixel_multiplier);
>  	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
> -	if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
> +	if ((IS_GEN_LT(dev_priv, 8) && !IS_HASWELL(dev_priv)) ||
>  	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		PIPE_CONF_CHECK_BOOL(limited_color_range);
>  
> @@ -11220,7 +11220,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>  
>  	PIPE_CONF_CHECK_X(gmch_pfit.control);
>  	/* pfit ratios are autocomputed by the hw on gen4+ */
> -	if (INTEL_GEN(dev_priv) < 4)
> +	if (IS_GEN_LT(dev_priv, 4))
>  		PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
>  	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
>  
> @@ -11266,7 +11266,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>  	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
>  	PIPE_CONF_CHECK_X(dsi_pll.div);
>  
> -	if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> +	if (IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5))
>  		PIPE_CONF_CHECK_I(pipe_bpp);
>  
>  	PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
> @@ -11316,7 +11316,7 @@ static void verify_wm_state(struct drm_crtc *crtc,
>  	const enum pipe pipe = intel_crtc->pipe;
>  	int plane, level, max_level = ilk_wm_max_level(dev_priv);
>  
> -	if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
> +	if (IS_GEN_LT(dev_priv, 9) || !new_state->active)
>  		return;
>  
>  	skl_pipe_wm_get_hw_state(crtc, &hw_wm);
> @@ -12293,7 +12293,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
>  				 *
>  				 * No clue what this is supposed to achieve.
>  				 */
> -				if (INTEL_GEN(dev_priv) >= 9)
> +				if (IS_GEN_GTE(dev_priv, 9))
>  					dev_priv->display.initial_watermarks(intel_state,
>  									     to_intel_crtc_state(new_crtc_state));
>  			}
> @@ -12485,7 +12485,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>  	 * FIXME doing watermarks and fb cleanup from a vblank worker
>  	 * (assuming we had any) would solve these problems.
>  	 */
> -	if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
> +	if (IS_GEN_LT(dev_priv, 9) && state->legacy_cursor_update) {
>  		struct intel_crtc_state *new_crtc_state;
>  		struct intel_crtc *crtc;
>  		int i;
> @@ -12592,7 +12592,7 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
>  	if (!dma_fence_is_i915(fence))
>  		return;
>  
> -	if (INTEL_GEN(to_i915(crtc->dev)) < 6)
> +	if (IS_GEN_LT(to_i915(crtc->dev), 6))
>  		return;
>  
>  	if (drm_crtc_vblank_get(crtc))
> @@ -12770,7 +12770,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
>  	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
>  	max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
>  
> -	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> +	if (IS_GEMINILAKE(dev_priv) || IS_GEN_GTE(dev_priv, 10))
>  		max_dotclk *= 2;
>  
>  	if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
> @@ -12801,7 +12801,7 @@ intel_check_primary_plane(struct intel_plane *plane,
>  	struct drm_rect clip = {};
>  	int ret;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		/* use scaler when colorkey is not required */
>  		if (!state->ckey.flags) {
>  			min_scale = 1;
> @@ -12825,7 +12825,7 @@ intel_check_primary_plane(struct intel_plane *plane,
>  	if (!state->base.fb)
>  		return 0;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		ret = skl_check_plane_surface(crtc_state, state);
>  		if (ret)
>  			return ret;
> @@ -12839,7 +12839,7 @@ intel_check_primary_plane(struct intel_plane *plane,
>  		state->ctl = i9xx_plane_ctl(crtc_state, state);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> +	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
>  		state->color_ctl = glk_plane_color_ctl(crtc_state, state);
>  
>  	return 0;
> @@ -12874,7 +12874,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
>  
>  	if (intel_cstate->update_pipe)
>  		intel_update_pipe_config(old_intel_cstate, intel_cstate);
> -	else if (INTEL_GEN(dev_priv) >= 9)
> +	else if (IS_GEN_GTE(dev_priv, 9))
>  		skl_detach_scalers(intel_crtc);
>  
>  out:
> @@ -12998,9 +12998,9 @@ static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
>  	    modifier != DRM_FORMAT_MOD_LINEAR)
>  		return false;
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		return skl_mod_supported(format, modifier);
> -	else if (INTEL_GEN(dev_priv) >= 4)
> +	else if (IS_GEN_GTE(dev_priv, 4))
>  		return i965_mod_supported(format, modifier);
>  	else
>  		return i8xx_mod_supported(format, modifier);
> @@ -13197,7 +13197,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  
>  	primary->can_scale = false;
>  	primary->max_downscale = 1;
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		primary->can_scale = true;
>  		state->scaler_id = -1;
>  	}
> @@ -13206,7 +13206,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
>  	 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
>  	 */
> -	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
> +	if (HAS_FBC(dev_priv) && IS_GEN_LT(dev_priv, 4))
>  		primary->i9xx_plane = (enum i9xx_plane_id) !pipe;
>  	else
>  		primary->i9xx_plane = (enum i9xx_plane_id) pipe;
> @@ -13214,7 +13214,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
>  	primary->check_plane = intel_check_primary_plane;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		intel_primary_formats = skl_primary_formats;
>  		num_formats = ARRAY_SIZE(skl_primary_formats);
>  
> @@ -13226,7 +13226,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		primary->update_plane = skl_update_plane;
>  		primary->disable_plane = skl_disable_plane;
>  		primary->get_hw_state = skl_plane_get_hw_state;
> -	} else if (INTEL_GEN(dev_priv) >= 4) {
> +	} else if (IS_GEN_GTE(dev_priv, 4)) {
>  		intel_primary_formats = i965_primary_formats;
>  		num_formats = ARRAY_SIZE(i965_primary_formats);
>  		modifiers = i9xx_format_modifiers;
> @@ -13244,14 +13244,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		primary->get_hw_state = i9xx_plane_get_hw_state;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
>  					       0, &intel_plane_funcs,
>  					       intel_primary_formats, num_formats,
>  					       modifiers,
>  					       DRM_PLANE_TYPE_PRIMARY,
>  					       "plane 1%c", pipe_name(pipe));
> -	else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> +	else if (IS_GEN_GTE(dev_priv, 5) || IS_G4X(dev_priv))
>  		ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
>  					       0, &intel_plane_funcs,
>  					       intel_primary_formats, num_formats,
> @@ -13269,12 +13269,12 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	if (ret)
>  		goto fail;
>  
> -	if (INTEL_GEN(dev_priv) >= 10) {
> +	if (IS_GEN_GTE(dev_priv, 10)) {
>  		supported_rotations =
>  			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
>  			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
>  			DRM_MODE_REFLECT_X;
> -	} else if (INTEL_GEN(dev_priv) >= 9) {
> +	} else if (IS_GEN_GTE(dev_priv, 9)) {
>  		supported_rotations =
>  			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
>  			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
> @@ -13282,14 +13282,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		supported_rotations =
>  			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
>  			DRM_MODE_REFLECT_X;
> -	} else if (INTEL_GEN(dev_priv) >= 4) {
> +	} else if (IS_GEN_GTE(dev_priv, 4)) {
>  		supported_rotations =
>  			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
>  	} else {
>  		supported_rotations = DRM_MODE_ROTATE_0;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		drm_plane_create_rotation_property(&primary->base,
>  						   DRM_MODE_ROTATE_0,
>  						   supported_rotations);
> @@ -13362,13 +13362,13 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
>  	if (ret)
>  		goto fail;
>  
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		drm_plane_create_rotation_property(&cursor->base,
>  						   DRM_MODE_ROTATE_0,
>  						   DRM_MODE_ROTATE_0 |
>  						   DRM_MODE_ROTATE_180);
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		state->scaler_id = -1;
>  
>  	drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
> @@ -13548,7 +13548,7 @@ static bool has_edp_a(struct drm_i915_private *dev_priv)
>  
>  static bool intel_crt_present(struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		return false;
>  
>  	if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
> @@ -13929,7 +13929,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  		/* fall through */
>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Yf_TILED:
> -		if (INTEL_GEN(dev_priv) < 9) {
> +		if (IS_GEN_LT(dev_priv, 9)) {
>  			DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
>  				      mode_cmd->modifier[0]);
>  			goto err;
> @@ -13947,7 +13947,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  	 * gen2/3 display engine uses the fence if present,
>  	 * so the tiling mode must match the fb modifier exactly.
>  	 */
> -	if (INTEL_GEN(dev_priv) < 4 &&
> +	if (IS_GEN_LT(dev_priv, 4) &&
>  	    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
>  		DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
>  		goto err;
> @@ -13981,7 +13981,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  	case DRM_FORMAT_ARGB8888:
>  		break;
>  	case DRM_FORMAT_XRGB1555:
> -		if (INTEL_GEN(dev_priv) > 3) {
> +		if (IS_GEN_GT(dev_priv, 3)) {
>  			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>  				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
>  			goto err;
> @@ -13989,7 +13989,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  		break;
>  	case DRM_FORMAT_ABGR8888:
>  		if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> -		    INTEL_GEN(dev_priv) < 9) {
> +		    IS_GEN_LT(dev_priv, 9)) {
>  			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>  				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
>  			goto err;
> @@ -13998,7 +13998,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  	case DRM_FORMAT_XBGR8888:
>  	case DRM_FORMAT_XRGB2101010:
>  	case DRM_FORMAT_XBGR2101010:
> -		if (INTEL_GEN(dev_priv) < 4) {
> +		if (IS_GEN_LT(dev_priv, 4)) {
>  			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>  				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
>  			goto err;
> @@ -14015,7 +14015,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_YVYU:
>  	case DRM_FORMAT_VYUY:
> -		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
> +		if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv)) {
>  			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>  				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
>  			goto err;
> @@ -14162,7 +14162,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>  {
>  	intel_init_cdclk_hooks(dev_priv);
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
>  		dev_priv->display.get_initial_plane_config =
>  			skylake_get_initial_plane_config;
> @@ -14241,7 +14241,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		dev_priv->display.update_crtcs = skl_update_crtcs;
>  	else
>  		dev_priv->display.update_crtcs = intel_update_crtcs;
> @@ -14774,7 +14774,7 @@ intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_crtc *crtc;
>  
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		return;
>  
>  	for_each_intel_crtc(&dev_priv->drm, crtc) {
> @@ -15210,7 +15210,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		vlv_wm_get_hw_state(dev);
>  		vlv_wm_sanitize(dev_priv);
> -	} else if (INTEL_GEN(dev_priv) >= 9) {
> +	} else if (IS_GEN_GTE(dev_priv, 9)) {
>  		skl_wm_get_hw_state(dev);
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		ilk_wm_get_hw_state(dev);
> @@ -15361,7 +15361,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
>   */
>  int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
>  {
> -	unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
> +	unsigned reg = IS_GEN_GTE(dev_priv, 6) ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
>  	u16 gmch_ctrl;
>  
>  	if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
> @@ -15467,13 +15467,13 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
>  
>  		error->plane[i].control = I915_READ(DSPCNTR(i));
>  		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
> -		if (INTEL_GEN(dev_priv) <= 3) {
> +		if (IS_GEN_LTE(dev_priv, 3)) {
>  			error->plane[i].size = I915_READ(DSPSIZE(i));
>  			error->plane[i].pos = I915_READ(DSPPOS(i));
>  		}
> -		if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
> +		if (IS_GEN_LTE(dev_priv, 7) && !IS_HASWELL(dev_priv))
>  			error->plane[i].addr = I915_READ(DSPADDR(i));
> -		if (INTEL_GEN(dev_priv) >= 4) {
> +		if (IS_GEN_GTE(dev_priv, 4)) {
>  			error->plane[i].surface = I915_READ(DSPSURF(i));
>  			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
>  		}
> @@ -15538,13 +15538,13 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
>  		err_printf(m, "Plane [%d]:\n", i);
>  		err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
>  		err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
> -		if (INTEL_GEN(dev_priv) <= 3) {
> +		if (IS_GEN_LTE(dev_priv, 3)) {
>  			err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
>  			err_printf(m, "  POS: %08x\n", error->plane[i].pos);
>  		}
> -		if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
> +		if (IS_GEN_LTE(dev_priv, 7) && !IS_HASWELL(dev_priv))
>  			err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
> -		if (INTEL_GEN(dev_priv) >= 4) {
> +		if (IS_GEN_GTE(dev_priv, 4)) {
>  			err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
>  			err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
>  		}
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index abbe1e4e0af5..319d0d00f4ca 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1467,7 +1467,7 @@ static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
>  static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  				    enum port port)
>  {
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		return skl_aux_ctl_reg(dev_priv, port);
>  	else if (HAS_PCH_SPLIT(dev_priv))
>  		return ilk_aux_ctl_reg(dev_priv, port);
> @@ -1478,7 +1478,7 @@ static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
>  				     enum port port, int index)
>  {
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		return skl_aux_data_reg(dev_priv, port, index);
>  	else if (HAS_PCH_SPLIT(dev_priv))
>  		return ilk_aux_data_reg(dev_priv, port, index);
> @@ -1726,7 +1726,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  
>  		intel_fixed_panel_mode(panel_mode, adjusted_mode);
>  
> -		if (INTEL_GEN(dev_priv) >= 9) {
> +		if (IS_GEN_GTE(dev_priv, 9)) {
>  			int ret;
>  			ret = skl_update_scaler_crtc(pipe_config);
>  			if (ret)
> @@ -3208,7 +3208,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>  	enum port port = dp_to_dig_port(intel_dp)->base.port;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>  		return intel_ddi_dp_voltage_max(encoder);
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> @@ -3227,7 +3227,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>  	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>  	enum port port = dp_to_dig_port(intel_dp)->base.port;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>  		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>  			return DP_TRAIN_PRE_EMPH_LEVEL_3;
> @@ -3760,7 +3760,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>  		DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 9 &&
> +	if (IS_GEN_GTE(dev_priv, 9) &&
>  	    (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
>  		uint8_t frame_sync_cap;
>  
> @@ -5468,10 +5468,10 @@ bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
>  	 * eDP not supported on g4x. so bail out early just
>  	 * for a bit extra safety in case the VBT is bonkers.
>  	 */
> -	if (INTEL_GEN(dev_priv) < 5)
> +	if (IS_GEN_LT(dev_priv, 5))
>  		return false;
>  
> -	if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
> +	if (IS_GEN_LT(dev_priv, 9) && port == PORT_A)
>  		return true;
>  
>  	return intel_bios_is_port_edp(dev_priv, port);
> @@ -5830,7 +5830,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
>  		return;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
> +	if (IS_GEN_GTE(dev_priv, 8) && !IS_CHERRYVIEW(dev_priv)) {
>  		switch (index) {
>  		case DRRS_HIGH_RR:
>  			intel_dp_set_m_n(intel_crtc, M1_N1);
> @@ -5842,7 +5842,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
>  		default:
>  			DRM_ERROR("Unsupported refreshrate type\n");
>  		}
> -	} else if (INTEL_GEN(dev_priv) > 6) {
> +	} else if (IS_GEN_GT(dev_priv, 6)) {
>  		i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
>  		u32 val;
>  
> @@ -6115,7 +6115,7 @@ intel_dp_drrs_init(struct intel_connector *connector,
>  	INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
>  	mutex_init(&dev_priv->drrs.mutex);
>  
> -	if (INTEL_GEN(dev_priv) <= 6) {
> +	if (IS_GEN_LTE(dev_priv, 6)) {
>  		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
>  		return NULL;
>  	}
> @@ -6353,7 +6353,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  	intel_dp->active_pipe = INVALID_PIPE;
>  
>  	/* intel_dp vfuncs */
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
>  	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
> @@ -6362,7 +6362,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  	else
>  		intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
>  	else
>  		intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
> @@ -6501,7 +6501,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
>  		intel_encoder->enable = vlv_enable_dp;
>  		intel_encoder->disable = vlv_disable_dp;
>  		intel_encoder->post_disable = vlv_post_disable_dp;
> -	} else if (INTEL_GEN(dev_priv) >= 5) {
> +	} else if (IS_GEN_GTE(dev_priv, 5)) {
>  		intel_encoder->pre_enable = g4x_pre_enable_dp;
>  		intel_encoder->enable = g4x_enable_dp;
>  		intel_encoder->disable = ilk_disable_dp;
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 51c5ae4e9116..7bde6b9853e3 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -210,7 +210,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
>  	unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
>  
>  	/* PCH only available on ILK+ */
> -	if (INTEL_GEN(dev_priv) < 5)
> +	if (IS_GEN_LT(dev_priv, 5))
>  		return;
>  
>  	if (pll == NULL)
> @@ -1860,7 +1860,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	if (INTEL_GEN(dev_priv) < 9) {
> +	if (IS_GEN_LT(dev_priv, 9)) {
>  		uint32_t val = I915_READ(LCPLL_CTL);
>  
>  		/*
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 7eebfbb95e89..9706bd8d9e77 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -193,7 +193,7 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
>  	case VIDEO_DECODE_CLASS:
>  	case VIDEO_ENHANCEMENT_CLASS:
>  	case COPY_ENGINE_CLASS:
> -		if (INTEL_GEN(dev_priv) < 8)
> +		if (IS_GEN_LT(dev_priv, 8))
>  			return 0;
>  		return GEN8_LR_CONTEXT_OTHER_SIZE;
>  	}
> @@ -696,10 +696,10 @@ u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  	u64 acthd;
>  
> -	if (INTEL_GEN(dev_priv) >= 8)
> +	if (IS_GEN_GTE(dev_priv, 8))
>  		acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
>  					 RING_ACTHD_UDW(engine->mmio_base));
> -	else if (INTEL_GEN(dev_priv) >= 4)
> +	else if (IS_GEN_GTE(dev_priv, 4))
>  		acthd = I915_READ(RING_ACTHD(engine->mmio_base));
>  	else
>  		acthd = I915_READ(ACTHD);
> @@ -712,7 +712,7 @@ u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  	u64 bbaddr;
>  
> -	if (INTEL_GEN(dev_priv) >= 8)
> +	if (IS_GEN_GTE(dev_priv, 8))
>  		bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
>  					  RING_BBADDR_UDW(engine->mmio_base));
>  	else
> @@ -1472,7 +1472,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
>  		idle = false;
>  
>  	/* No bit for gen2, so assume the CS parser is idle */
> -	if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE))
> +	if (IS_GEN_GT(dev_priv, 2) && !(I915_READ_MODE(engine) & MODE_IDLE))
>  		idle = false;
>  
>  	intel_runtime_pm_put(dev_priv);
> @@ -1777,7 +1777,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>  	drm_printf(m, "\tRING_CTL:   0x%08x%s\n",
>  		   I915_READ(RING_CTL(engine->mmio_base)),
>  		   I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
> -	if (INTEL_GEN(engine->i915) > 2) {
> +	if (IS_GEN_GT(engine->i915, 2)) {
>  		drm_printf(m, "\tRING_MODE:  0x%08x%s\n",
>  			   I915_READ(RING_MI_MODE(engine->mmio_base)),
>  			   I915_READ(RING_MI_MODE(engine->mmio_base)) & (MODE_IDLE) ? " [idle]" : "");
> @@ -1800,16 +1800,16 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>  	addr = intel_engine_get_last_batch_head(engine);
>  	drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
>  		   upper_32_bits(addr), lower_32_bits(addr));
> -	if (INTEL_GEN(dev_priv) >= 8)
> +	if (IS_GEN_GTE(dev_priv, 8))
>  		addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
>  					RING_DMA_FADD_UDW(engine->mmio_base));
> -	else if (INTEL_GEN(dev_priv) >= 4)
> +	else if (IS_GEN_GTE(dev_priv, 4))
>  		addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
>  	else
>  		addr = I915_READ(DMA_FADD_I8XX);
>  	drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
>  		   upper_32_bits(addr), lower_32_bits(addr));
> -	if (INTEL_GEN(dev_priv) >= 4) {
> +	if (IS_GEN_GTE(dev_priv, 4)) {
>  		drm_printf(m, "\tIPEIR: 0x%08x\n",
>  			   I915_READ(RING_IPEIR(engine->mmio_base)));
>  		drm_printf(m, "\tIPEHR: 0x%08x\n",
> @@ -1869,7 +1869,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>  		}
>  		drm_printf(m, "\t\tHW active? 0x%x\n", execlists->active);
>  		rcu_read_unlock();
> -	} else if (INTEL_GEN(dev_priv) > 6) {
> +	} else if (IS_GEN_GT(dev_priv, 6)) {
>  		drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
>  			   I915_READ(RING_PP_DIR_BASE(engine)));
>  		drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
> @@ -1899,7 +1899,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>  	}
>  	spin_unlock_irq(&b->rb_lock);
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (IS_GEN_GTE(dev_priv, 6)) {
>  		drm_printf(m, "\tRING_IMR: %08x\n", I915_READ_IMR(engine));
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 0ad854095c38..30da6085f84e 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -48,17 +48,17 @@ static inline bool fbc_supported(struct drm_i915_private *dev_priv)
>  
>  static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
>  {
> -	return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
> +	return IS_HASWELL(dev_priv) || IS_GEN_GTE(dev_priv, 8);
>  }
>  
>  static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
>  {
> -	return INTEL_GEN(dev_priv) < 4;
> +	return IS_GEN_LT(dev_priv, 4);
>  }
>  
>  static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
>  {
> -	return INTEL_GEN(dev_priv) <= 3;
> +	return IS_GEN_LTE(dev_priv, 3);
>  }
>  
>  /*
> @@ -96,7 +96,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
>  	intel_fbc_get_plane_source_size(cache, NULL, &lines);
>  	if (IS_GEN7(dev_priv))
>  		lines = min(lines, 2048);
> -	else if (INTEL_GEN(dev_priv) >= 8)
> +	else if (IS_GEN_GTE(dev_priv, 8))
>  		lines = min(lines, 2560);
>  
>  	/* Hardware needs the full buffer stride, not just the active area. */
> @@ -357,7 +357,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>  
>  static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_GEN(dev_priv) >= 5)
> +	if (IS_GEN_GTE(dev_priv, 5))
>  		return ilk_fbc_is_active(dev_priv);
>  	else if (IS_GM45(dev_priv))
>  		return g4x_fbc_is_active(dev_priv);
> @@ -371,9 +371,9 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
>  
>  	fbc->active = true;
>  
> -	if (INTEL_GEN(dev_priv) >= 7)
> +	if (IS_GEN_GTE(dev_priv, 7))
>  		gen7_fbc_activate(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 5)
> +	else if (IS_GEN_GTE(dev_priv, 5))
>  		ilk_fbc_activate(dev_priv);
>  	else if (IS_GM45(dev_priv))
>  		g4x_fbc_activate(dev_priv);
> @@ -387,7 +387,7 @@ static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
>  
>  	fbc->active = false;
>  
> -	if (INTEL_GEN(dev_priv) >= 5)
> +	if (IS_GEN_GTE(dev_priv, 5))
>  		ilk_fbc_deactivate(dev_priv);
>  	else if (IS_GM45(dev_priv))
>  		g4x_fbc_deactivate(dev_priv);
> @@ -568,7 +568,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
>  
>  	ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
>  						   4096, 0, end);
> -	if (ret && INTEL_GEN(dev_priv) <= 4) {
> +	if (ret && IS_GEN_LTE(dev_priv, 4)) {
>  		return 0;
>  	} else if (ret) {
>  		compression_threshold <<= 1;
> @@ -601,7 +601,7 @@ static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
>  
>  	fbc->threshold = ret;
>  
> -	if (INTEL_GEN(dev_priv) >= 5)
> +	if (IS_GEN_GTE(dev_priv, 5))
>  		I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
>  	else if (IS_GM45(dev_priv)) {
>  		I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
> @@ -724,10 +724,10 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
>  	struct intel_fbc *fbc = &dev_priv->fbc;
>  	unsigned int effective_w, effective_h, max_w, max_h;
>  
> -	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
> +	if (IS_GEN_GTE(dev_priv, 8) || IS_HASWELL(dev_priv)) {
>  		max_w = 4096;
>  		max_h = 4096;
> -	} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
> +	} else if (IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5)) {
>  		max_w = 4096;
>  		max_h = 2048;
>  	} else {
> @@ -820,7 +820,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
>  		fbc->no_fbc_reason = "framebuffer not tiled or fenced";
>  		return false;
>  	}
> -	if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
> +	if (IS_GEN_LTE(dev_priv, 4) && !IS_G4X(dev_priv) &&
>  	    cache->plane.rotation != DRM_MODE_ROTATE_0) {
>  		fbc->no_fbc_reason = "rotation unsupported";
>  		return false;
> @@ -1325,7 +1325,7 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
>  	if (!HAS_FBC(dev_priv))
>  		return 0;
>  
> -	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
> +	if (IS_BROADWELL(dev_priv) || IS_GEN_GTE(dev_priv, 9))
>  		return 1;
>  
>  	return 0;
> @@ -1382,7 +1382,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
>  	}
>  
>  	/* This value was pulled out of someone's hat */
> -	if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
> +	if (IS_GEN_LTE(dev_priv, 4) && !IS_GM45(dev_priv))
>  		I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
>  
>  	/* We still don't have any sort of hardware state readout for FBC, so
> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> index 77c123cc8817..0521208041ab 100644
> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> @@ -264,7 +264,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
>  		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
>  	else if (IS_GEN7(dev_priv))
>  		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
> -	else if (INTEL_GEN(dev_priv) >= 8)
> +	else if (IS_GEN_GTE(dev_priv, 8))
>  		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
>  
>  	return old;
> diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
> index 42e45ae87393..3e4db1c0329d 100644
> --- a/drivers/gpu/drm/i915/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
> @@ -97,7 +97,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
>  	 * ringbuffer itself.
>  	 */
>  	head = I915_READ_HEAD(engine) & HEAD_ADDR;
> -	backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
> +	backwards = (IS_GEN_GTE(dev_priv, 8)) ? 5 : 4;
>  	vaddr = (void __iomem *)engine->buffer->vaddr;
>  
>  	for (i = backwards; i; --i) {
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
> index 14ca5d3057a7..9c5ee2dae9fa 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -651,7 +651,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
>  bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
>  {
>  	/* PORT E doesn't have HDCP, and PORT F is disabled */
> -	return ((INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
> +	return ((IS_GEN_GTE(dev_priv, 8) || IS_HASWELL(dev_priv)) &&
>  		!IS_CHERRYVIEW(dev_priv) && port < PORT_E);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index f5d7bfb43006..ea64df508052 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1481,11 +1481,11 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
>  		&dev_priv->vbt.ddi_port_info[encoder->port];
>  	int max_tmds_clock;
>  
> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> +	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
>  		max_tmds_clock = 594000;
> -	else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> +	else if (IS_GEN_GTE(dev_priv, 8) || IS_HASWELL(dev_priv))
>  		max_tmds_clock = 300000;
> -	else if (INTEL_GEN(dev_priv) >= 5)
> +	else if (IS_GEN_GTE(dev_priv, 5))
>  		max_tmds_clock = 225000;
>  	else
>  		max_tmds_clock = 165000;
> @@ -1754,7 +1754,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
>  
>  	pipe_config->lane_count = 4;
>  
> -	if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
> +	if (scdc->scrambling.supported && (IS_GEN_GTE(dev_priv, 10) ||
>  					   IS_GEMINILAKE(dev_priv))) {
>  		if (scdc->scrambling.low_rates)
>  			pipe_config->hdmi_scrambling = true;
> @@ -2324,7 +2324,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>  	connector->doublescan_allowed = 0;
>  	connector->stereo_allowed = 1;
>  
> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> +	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
>  		connector->ycbcr_420_allowed = true;
>  
>  	intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 380c0838d8b3..1a08f6bdaf50 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1488,7 +1488,7 @@ static void enable_execlists(struct intel_engine_cs *engine)
>  	 * deeper FIFO it's not needed and it's not worth adding
>  	 * more statements to the irq handler to support it.
>  	 */
> -	if (INTEL_GEN(dev_priv) >= 11)
> +	if (IS_GEN_GTE(dev_priv, 11))
>  		I915_WRITE(RING_MODE_GEN7(engine),
>  			   _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
>  	else
> @@ -2057,7 +2057,7 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
>  		engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
>  
>  	/* Override some for render ring. */
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		engine->init_hw = gen9_init_render_ring;
>  	else
>  		engine->init_hw = gen8_init_render_ring;
> @@ -2100,7 +2100,7 @@ make_rpcs(struct drm_i915_private *dev_priv)
>  	 * No explicit RPCS request is needed to ensure full
>  	 * slice/subslice/EU enablement prior to Gen9.
>  	*/
> -	if (INTEL_GEN(dev_priv) < 9)
> +	if (IS_GEN_LT(dev_priv, 9))
>  		return 0;
>  
>  	/*
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 4677ac0b10d7..577385cb3c8d 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -139,12 +139,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
>  
>  	pipe_config->base.adjusted_mode.flags |= flags;
>  
> -	if (INTEL_GEN(dev_priv) < 5)
> +	if (IS_GEN_LT(dev_priv, 5))
>  		pipe_config->gmch_pfit.lvds_border_bits =
>  			tmp & LVDS_BORDER_ENABLE;
>  
>  	/* gen2/3 store dither state in pfit control, needs to match */
> -	if (INTEL_GEN(dev_priv) < 4) {
> +	if (IS_GEN_LT(dev_priv, 4)) {
>  		tmp = I915_READ(PFIT_CONTROL);
>  
>  		pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
> @@ -189,7 +189,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
>  	/* Convert from 100ms to 100us units */
>  	pps->t4 = val * 1000;
>  
> -	if (INTEL_GEN(dev_priv) <= 4 &&
> +	if (IS_GEN_LTE(dev_priv, 4) &&
>  	    pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
>  		DRM_DEBUG_KMS("Panel power timings uninitialized, "
>  			      "setting defaults\n");
> @@ -396,7 +396,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
>  	unsigned int lvds_bpp;
>  
>  	/* Should never happen!! */
> -	if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
> +	if (IS_GEN_LT(dev_priv, 4) && intel_crtc->pipe == 0) {
>  		DRM_ERROR("Can't support LVDS on pipe A\n");
>  		return false;
>  	}
> @@ -914,7 +914,7 @@ static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
>  
>  	/* Otherwise LVDS was only attached to mobile products,
>  	 * except for the inglorious 830gm */
> -	if (INTEL_GEN(dev_priv) <= 4 &&
> +	if (IS_GEN_LTE(dev_priv, 4) &&
>  	    IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
>  		return true;
>  
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index abb7a8c1e340..02b2768b556e 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -187,7 +187,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
>  		table->table = broxton_mocs_table;
>  		result = true;
>  	} else {
> -		WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
> +		WARN_ONCE(IS_GEN_GTE(dev_priv, 9),
>  			  "Platform that should have a MOCS table does not.\n");
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index 41e9465d44a8..752085a2a2d0 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -945,7 +945,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
>  	/* XXX: This is not the same logic as in the xorg driver, but more in
>  	 * line with the intel documentation for the i965
>  	 */
> -	if (INTEL_GEN(dev_priv) >= 4) {
> +	if (IS_GEN_GTE(dev_priv, 4)) {
>  		/* on i965 use the PGM reg to read out the autoscaler values */
>  		ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
>  	} else {
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 78a53c8b1789..557249583f8e 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -326,7 +326,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
>  		break;
>  	case DRM_MODE_SCALE_ASPECT:
>  		/* Scale but preserve the aspect ratio */
> -		if (INTEL_GEN(dev_priv) >= 4)
> +		if (IS_GEN_GTE(dev_priv, 4))
>  			i965_scale_aspect(pipe_config, &pfit_control);
>  		else
>  			i9xx_scale_aspect(pipe_config, &pfit_control,
> @@ -340,7 +340,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
>  		if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay ||
>  		    pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
>  			pfit_control |= PFIT_ENABLE;
> -			if (INTEL_GEN(dev_priv) >= 4)
> +			if (IS_GEN_GTE(dev_priv, 4))
>  				pfit_control |= PFIT_SCALING_AUTO;
>  			else
>  				pfit_control |= (VERT_AUTO_SCALE |
> @@ -356,7 +356,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
>  
>  	/* 965+ wants fuzzy fitting */
>  	/* FIXME: handle multiple panels by failing gracefully */
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
>  				 PFIT_FILTER_FUZZY);
>  
> @@ -367,7 +367,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
>  	}
>  
>  	/* Make sure pre-965 set dither correctly for 18bpp panels. */
> -	if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18)
> +	if (IS_GEN_LT(dev_priv, 4) && pipe_config->pipe_bpp == 18)
>  		pfit_control |= PANEL_8TO6_DITHER_ENABLE;
>  
>  	pipe_config->gmch_pfit.control = pfit_control;
> @@ -497,7 +497,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector)
>  	u32 val;
>  
>  	val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
> -	if (INTEL_GEN(dev_priv) < 4)
> +	if (IS_GEN_LT(dev_priv, 4))
>  		val >>= 1;
>  
>  	if (panel->backlight.combination_mode) {
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index 1f5cd572a7ff..017bd2602c99 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -604,7 +604,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
>  {
>  	if (IS_GEN2(dev_priv))
>  		return i8xx_pipe_crc_ctl_reg(source, val);
> -	else if (INTEL_GEN(dev_priv) < 5)
> +	else if (IS_GEN_LT(dev_priv, 5))
>  		return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7a112d075c24..37421fe4c0a3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2571,9 +2571,9 @@ static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
>  static unsigned int
>  ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_GEN(dev_priv) >= 8)
> +	if (IS_GEN_GTE(dev_priv, 8))
>  		return 3072;
> -	else if (INTEL_GEN(dev_priv) >= 7)
> +	else if (IS_GEN_GTE(dev_priv, 7))
>  		return 768;
>  	else
>  		return 512;
> @@ -2583,10 +2583,10 @@ static unsigned int
>  ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
>  		     int level, bool is_sprite)
>  {
> -	if (INTEL_GEN(dev_priv) >= 8)
> +	if (IS_GEN_GTE(dev_priv, 8))
>  		/* BDW primary/sprite plane watermarks */
>  		return level == 0 ? 255 : 2047;
> -	else if (INTEL_GEN(dev_priv) >= 7)
> +	else if (IS_GEN_GTE(dev_priv, 7))
>  		/* IVB/HSW primary/sprite plane watermarks */
>  		return level == 0 ? 127 : 1023;
>  	else if (!is_sprite)
> @@ -2600,7 +2600,7 @@ ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
>  static unsigned int
>  ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
>  {
> -	if (INTEL_GEN(dev_priv) >= 7)
> +	if (IS_GEN_GTE(dev_priv, 7))
>  		return level == 0 ? 63 : 255;
>  	else
>  		return level == 0 ? 31 : 63;
> @@ -2608,7 +2608,7 @@ ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
>  
>  static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_GEN(dev_priv) >= 8)
> +	if (IS_GEN_GTE(dev_priv, 8))
>  		return 31;
>  	else
>  		return 15;
> @@ -2637,7 +2637,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
>  		 * FIFO size is only half of the self
>  		 * refresh FIFO size on ILK/SNB.
>  		 */
> -		if (INTEL_GEN(dev_priv) <= 6)
> +		if (IS_GEN_LTE(dev_priv, 6))
>  			fifo_size /= 2;
>  	}
>  
> @@ -2798,7 +2798,7 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
>  static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>  				  uint16_t wm[8])
>  {
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		uint32_t val;
>  		int ret, i;
>  		int level, max_level = ilk_wm_max_level(dev_priv);
> @@ -2883,14 +2883,14 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>  		wm[2] = (sskpd >> 12) & 0xFF;
>  		wm[3] = (sskpd >> 20) & 0x1FF;
>  		wm[4] = (sskpd >> 32) & 0x1FF;
> -	} else if (INTEL_GEN(dev_priv) >= 6) {
> +	} else if (IS_GEN_GTE(dev_priv, 6)) {
>  		uint32_t sskpd = I915_READ(MCH_SSKPD);
>  
>  		wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
>  		wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
>  		wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
>  		wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
> -	} else if (INTEL_GEN(dev_priv) >= 5) {
> +	} else if (IS_GEN_GTE(dev_priv, 5)) {
>  		uint32_t mltr = I915_READ(MLTR_ILK);
>  
>  		/* ILK primary LP0 latency is 700 ns */
> @@ -2925,11 +2925,11 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
>  int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
>  {
>  	/* how many WM levels are we expecting */
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		return 7;
>  	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		return 4;
> -	else if (INTEL_GEN(dev_priv) >= 6)
> +	else if (IS_GEN_GTE(dev_priv, 6))
>  		return 3;
>  	else
>  		return 2;
> @@ -2954,7 +2954,7 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
>  		 * - latencies are in us on gen9.
>  		 * - before then, WM1+ latency values are in 0.5us units
>  		 */
> -		if (INTEL_GEN(dev_priv) >= 9)
> +		if (IS_GEN_GTE(dev_priv, 9))
>  			latency *= 10;
>  		else if (level > 0)
>  			latency *= 5;
> @@ -3090,7 +3090,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
>  	usable_level = max_level;
>  
>  	/* ILK/SNB: LP2+ watermarks only w/o sprites */
> -	if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
> +	if (IS_GEN_LTE(dev_priv, 6) && pipe_wm->sprites_enabled)
>  		usable_level = 1;
>  
>  	/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
> @@ -3235,12 +3235,12 @@ static void ilk_wm_merge(struct drm_device *dev,
>  	int last_enabled_level = max_level;
>  
>  	/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
> -	if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
> +	if ((IS_GEN_LTE(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) &&
>  	    config->num_pipes_active > 1)
>  		last_enabled_level = 0;
>  
>  	/* ILK: FBC WM must be disabled always */
> -	merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
> +	merged->fbc_wm_enabled = IS_GEN_GTE(dev_priv, 6);
>  
>  	/* merge each WM1+ level */
>  	for (level = 1; level <= max_level; level++) {
> @@ -3330,7 +3330,7 @@ static void ilk_compute_wm_results(struct drm_device *dev,
>  		if (r->enable)
>  			results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
>  
> -		if (INTEL_GEN(dev_priv) >= 8)
> +		if (IS_GEN_GTE(dev_priv, 8))
>  			results->wm_lp[wm_lp - 1] |=
>  				r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
>  		else
> @@ -3341,7 +3341,7 @@ static void ilk_compute_wm_results(struct drm_device *dev,
>  		 * Always set WM1S_LP_EN when spr_val != 0, even if the
>  		 * level is disabled. Doing otherwise could cause underruns.
>  		 */
> -		if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
> +		if (IS_GEN_LTE(dev_priv, 6) && r->spr_val) {
>  			WARN_ON(wm_lp != 1);
>  			results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
>  		} else
> @@ -3546,7 +3546,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
>  	    previous->wm_lp_spr[0] != results->wm_lp_spr[0])
>  		I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
>  
> -	if (INTEL_GEN(dev_priv) >= 7) {
> +	if (IS_GEN_GTE(dev_priv, 7)) {
>  		if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
>  			I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
>  		if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
> @@ -3785,7 +3785,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
>  	ddb_size = INTEL_INFO(dev_priv)->ddb_size;
>  	WARN_ON(ddb_size == 0);
>  
> -	if (INTEL_GEN(dev_priv) < 11)
> +	if (IS_GEN_LT(dev_priv, 11))
>  		ddb_size -= 4; /* 4 blocks for bypass path allocation */
>  
>  	/*
> @@ -3996,7 +3996,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>  	crtc_clock = crtc_state->adjusted_mode.crtc_clock;
>  	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
>  
> -	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> +	if (IS_GEMINILAKE(dev_priv) || IS_GEN_GTE(dev_priv, 10))
>  		dotclk *= 2;
>  
>  	pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
> @@ -4330,7 +4330,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
>  	wm_intermediate_val = latency * pixel_rate * cpp;
>  	ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
>  
> -	if (INTEL_GEN(dev_priv) >= 10)
> +	if (IS_GEN_GTE(dev_priv, 10))
>  		ret = add_fixed16_u32(ret, 1);
>  
>  	return ret;
> @@ -4438,7 +4438,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>  	wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
>  							     intel_pstate);
>  
> -	if (INTEL_GEN(dev_priv) >= 11 &&
> +	if (IS_GEN_GTE(dev_priv, 11) &&
>  	    fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
>  		wp->dbuf_block_size = 256;
>  	else
> @@ -4473,7 +4473,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>  					   wp->y_min_scanlines,
>  					   wp->dbuf_block_size);
>  
> -		if (INTEL_GEN(dev_priv) >= 10)
> +		if (IS_GEN_GTE(dev_priv, 10))
>  			interm_pbpl++;
>  
>  		wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
> @@ -4573,7 +4573,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  		}
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 11) {
> +	if (IS_GEN_GTE(dev_priv, 11)) {
>  		if (wp->y_tiled) {
>  			uint32_t extra_lines;
>  			uint_fixed_16_16_t fp_min_disp_buf_needed;
> @@ -4705,14 +4705,14 @@ static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
>  		goto exit;
>  
>  	/* Transition WM are not recommended by HW team for GEN9 */
> -	if (INTEL_GEN(dev_priv) <= 9)
> +	if (IS_GEN_LTE(dev_priv, 9))
>  		goto exit;
>  
>  	/* Transition WM don't make any sense if ipc is disabled */
>  	if (!dev_priv->ipc_enabled)
>  		goto exit;
>  
> -	if (INTEL_GEN(dev_priv) >= 10)
> +	if (IS_GEN_GTE(dev_priv, 10))
>  		trans_min = 4;
>  
>  	trans_offset_b = trans_min + trans_amount;
> @@ -4835,7 +4835,7 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
>  
>  	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
>  			    &ddb->plane[pipe][plane_id]);
> -	if (INTEL_GEN(dev_priv) < 11)
> +	if (IS_GEN_LT(dev_priv, 11))
>  		skl_ddb_entry_write(dev_priv,
>  				    PLANE_NV12_BUF_CFG(pipe, plane_id),
>  				    &ddb->y_plane[pipe][plane_id]);
> @@ -5249,7 +5249,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
>  	ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
>  
>  	/* 5/6 split only in single pipe config on IVB+ */
> -	if (INTEL_GEN(dev_priv) >= 7 &&
> +	if (IS_GEN_GTE(dev_priv, 7) &&
>  	    config.num_pipes_active == 1 && config.sprites_enabled) {
>  		ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
>  		ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
> @@ -5848,7 +5848,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
>  	hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
>  
>  	hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
> -	if (INTEL_GEN(dev_priv) >= 7) {
> +	if (IS_GEN_GTE(dev_priv, 7)) {
>  		hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
>  		hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
>  	}
> @@ -6076,7 +6076,7 @@ static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
>  	 * the hw runs at the minimal clock before selecting the desired
>  	 * frequency, if the down threshold expires in that window we will not
>  	 * receive a down interrupt. */
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		limits = (rps->max_freq_softlimit) << 23;
>  		if (val <= rps->min_freq_softlimit)
>  			limits |= (rps->min_freq_softlimit) << 14;
> @@ -6222,7 +6222,7 @@ static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
>  	if (val != rps->cur_freq) {
>  		gen6_set_rps_thresholds(dev_priv, val);
>  
> -		if (INTEL_GEN(dev_priv) >= 9)
> +		if (IS_GEN_GTE(dev_priv, 9))
>  			I915_WRITE(GEN6_RPNSWREQ,
>  				   GEN9_FREQUENCY(val));
>  		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> @@ -6650,7 +6650,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN6_RC_CONTROL, 0);
>  
>  	/* 2b: Program RC6 thresholds.*/
> -	if (INTEL_GEN(dev_priv) >= 10) {
> +	if (IS_GEN_GTE(dev_priv, 10)) {
>  		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
>  		I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>  	} else if (IS_SKYLAKE(dev_priv)) {
> @@ -6940,7 +6940,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
>  			 * No floor required for ring frequency on SKL.
>  			 */
>  			ring_freq = gpu_freq;
> -		} else if (INTEL_GEN(dev_priv) >= 8) {
> +		} else if (IS_GEN_GTE(dev_priv, 8)) {
>  			/* max(2 * GT, DDR). NB: GT is 50MHz units */
>  			ring_freq = max(min_ring_freq, gpu_freq);
>  		} else if (IS_HASWELL(dev_priv)) {
> @@ -7957,7 +7957,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>  		cherryview_init_gt_powersave(dev_priv);
>  	else if (IS_VALLEYVIEW(dev_priv))
>  		valleyview_init_gt_powersave(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 6)
> +	else if (IS_GEN_GTE(dev_priv, 6))
>  		gen6_init_rps_frequencies(dev_priv);
>  
>  	/* Derive initial user preferences/limits from the hardware limits */
> @@ -8012,7 +8012,7 @@ void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
>   */
>  void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_GEN(dev_priv) < 6)
> +	if (IS_GEN_LT(dev_priv, 6))
>  		return;
>  
>  	/* gen6_rps_idle() will be called later to disable interrupts */
> @@ -8046,13 +8046,13 @@ static void intel_disable_rc6(struct drm_i915_private *dev_priv)
>  	if (!dev_priv->gt_pm.rc6.enabled)
>  		return;
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		gen9_disable_rc6(dev_priv);
>  	else if (IS_CHERRYVIEW(dev_priv))
>  		cherryview_disable_rc6(dev_priv);
>  	else if (IS_VALLEYVIEW(dev_priv))
>  		valleyview_disable_rc6(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 6)
> +	else if (IS_GEN_GTE(dev_priv, 6))
>  		gen6_disable_rc6(dev_priv);
>  
>  	dev_priv->gt_pm.rc6.enabled = false;
> @@ -8065,13 +8065,13 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv)
>  	if (!dev_priv->gt_pm.rps.enabled)
>  		return;
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		gen9_disable_rps(dev_priv);
>  	else if (IS_CHERRYVIEW(dev_priv))
>  		cherryview_disable_rps(dev_priv);
>  	else if (IS_VALLEYVIEW(dev_priv))
>  		valleyview_disable_rps(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 6)
> +	else if (IS_GEN_GTE(dev_priv, 6))
>  		gen6_disable_rps(dev_priv);
>  	else if (IS_IRONLAKE_M(dev_priv))
>  		ironlake_disable_drps(dev_priv);
> @@ -8114,11 +8114,11 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv)
>  		cherryview_enable_rc6(dev_priv);
>  	else if (IS_VALLEYVIEW(dev_priv))
>  		valleyview_enable_rc6(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 9)
> +	else if (IS_GEN_GTE(dev_priv, 9))
>  		gen9_enable_rc6(dev_priv);
>  	else if (IS_BROADWELL(dev_priv))
>  		gen8_enable_rc6(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 6)
> +	else if (IS_GEN_GTE(dev_priv, 6))
>  		gen6_enable_rc6(dev_priv);
>  
>  	dev_priv->gt_pm.rc6.enabled = true;
> @@ -8137,11 +8137,11 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
>  		cherryview_enable_rps(dev_priv);
>  	} else if (IS_VALLEYVIEW(dev_priv)) {
>  		valleyview_enable_rps(dev_priv);
> -	} else if (INTEL_GEN(dev_priv) >= 9) {
> +	} else if (IS_GEN_GTE(dev_priv, 9)) {
>  		gen9_enable_rps(dev_priv);
>  	} else if (IS_BROADWELL(dev_priv)) {
>  		gen8_enable_rps(dev_priv);
> -	} else if (INTEL_GEN(dev_priv) >= 6) {
> +	} else if (IS_GEN_GTE(dev_priv, 6)) {
>  		gen6_enable_rps(dev_priv);
>  	} else if (IS_IRONLAKE_M(dev_priv)) {
>  		ironlake_enable_drps(dev_priv);
> @@ -9056,7 +9056,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  		i915_ironlake_get_mem_freq(dev_priv);
>  
>  	/* For FIFO watermark updates */
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		skl_setup_wm_latency(dev_priv);
>  		dev_priv->display.initial_watermarks = skl_initial_wm;
>  		dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
> @@ -9202,7 +9202,7 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val
>  	*val = I915_READ_FW(GEN6_PCODE_DATA);
>  	I915_WRITE_FW(GEN6_PCODE_DATA, 0);
>  
> -	if (INTEL_GEN(dev_priv) > 6)
> +	if (IS_GEN_GT(dev_priv, 6))
>  		status = gen7_check_mailbox_status(dev_priv);
>  	else
>  		status = gen6_check_mailbox_status(dev_priv);
> @@ -9250,7 +9250,7 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
>  
>  	I915_WRITE_FW(GEN6_PCODE_DATA, 0);
>  
> -	if (INTEL_GEN(dev_priv) > 6)
> +	if (IS_GEN_GT(dev_priv, 6))
>  		status = gen7_check_mailbox_status(dev_priv);
>  	else
>  		status = gen6_check_mailbox_status(dev_priv);
> @@ -9379,7 +9379,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
>  {
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
>  					 GEN9_FREQ_SCALER);
>  	else if (IS_CHERRYVIEW(dev_priv))
> @@ -9392,7 +9392,7 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
>  
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
>  {
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
>  					 GT_FREQUENCY_MULTIPLIER);
>  	else if (IS_CHERRYVIEW(dev_priv))
> @@ -9537,7 +9537,7 @@ u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
>  {
>  	u32 cagf;
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
>  	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 2ef374f936b9..116cce194ac9 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -126,7 +126,7 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
>  static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  				       enum port port)
>  {
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		return DP_AUX_CH_CTL(port);
>  	else
>  		return EDP_PSR_AUX_CTL;
> @@ -135,7 +135,7 @@ static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
>  					enum port port, int index)
>  {
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		return DP_AUX_CH_DATA(port, index);
>  	else
>  		return EDP_PSR_AUX_DATA(index);
> @@ -521,7 +521,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>  	dev_priv->psr.enable_source(intel_dp, crtc_state);
>  	dev_priv->psr.enabled = intel_dp;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		intel_psr_activate(intel_dp);
>  	} else {
>  		/*
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index c91d7106fbcf..2c4ad89d9d57 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -346,7 +346,7 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
>  	u32 addr;
>  
>  	addr = dev_priv->status_page_dmah->busaddr;
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
>  	I915_WRITE(HWS_PGA, addr);
>  }
> @@ -386,7 +386,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>  		mmio = RING_HWS_PGA(engine->mmio_base);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 6)
> +	if (IS_GEN_GTE(dev_priv, 6))
>  		I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
>  
>  	I915_WRITE(mmio, engine->status_page.ggtt_offset);
> @@ -414,7 +414,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
>  
> -	if (INTEL_GEN(dev_priv) > 2) {
> +	if (IS_GEN_GT(dev_priv, 2)) {
>  		I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
>  		if (intel_wait_for_register(dev_priv,
>  					    RING_MI_MODE(engine->mmio_base),
> @@ -521,7 +521,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
>  
>  	intel_engine_init_hangcheck(engine);
>  
> -	if (INTEL_GEN(dev_priv) > 2)
> +	if (IS_GEN_GT(dev_priv, 2))
>  		I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
>  
>  out:
> @@ -655,7 +655,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
>  	if (IS_GEN(dev_priv, 6, 7))
>  		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>  
> -	if (INTEL_GEN(dev_priv) >= 6)
> +	if (IS_GEN_GTE(dev_priv, 6))
>  		I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
>  
>  	return init_workarounds_ring(engine);
> @@ -1360,7 +1360,7 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
>  
> -	WARN_ON(INTEL_GEN(dev_priv) > 2 &&
> +	WARN_ON(IS_GEN_GT(dev_priv, 2) &&
>  		(I915_READ_MODE(engine) & MODE_IDLE) == 0);
>  
>  	intel_ring_unpin(engine->buffer);
> @@ -1900,7 +1900,7 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
>  	if (!HAS_LEGACY_SEMAPHORES(dev_priv))
>  		return;
>  
> -	GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
> +	GEM_BUG_ON(IS_GEN_LT(dev_priv, 6));
>  	engine->semaphore.sync_to = gen6_ring_sync_to;
>  	engine->semaphore.signal = gen6_signal;
>  
> @@ -1957,15 +1957,15 @@ static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
>  {
>  	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (IS_GEN_GTE(dev_priv, 6)) {
>  		engine->irq_enable = gen6_irq_enable;
>  		engine->irq_disable = gen6_irq_disable;
>  		engine->irq_seqno_barrier = gen6_seqno_barrier;
> -	} else if (INTEL_GEN(dev_priv) >= 5) {
> +	} else if (IS_GEN_GTE(dev_priv, 5)) {
>  		engine->irq_enable = gen5_irq_enable;
>  		engine->irq_disable = gen5_irq_disable;
>  		engine->irq_seqno_barrier = gen5_seqno_barrier;
> -	} else if (INTEL_GEN(dev_priv) >= 3) {
> +	} else if (IS_GEN_GTE(dev_priv, 3)) {
>  		engine->irq_enable = i9xx_irq_enable;
>  		engine->irq_disable = i9xx_irq_disable;
>  	} else {
> @@ -1993,7 +1993,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
>  				      struct intel_engine_cs *engine)
>  {
>  	/* gen8+ are only supported with execlists */
> -	GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
> +	GEM_BUG_ON(IS_GEN_GTE(dev_priv, 8));
>  
>  	intel_ring_init_irq(dev_priv, engine);
>  	intel_ring_init_semaphores(dev_priv, engine);
> @@ -2021,9 +2021,9 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
>  
>  	engine->set_default_submission = i9xx_set_default_submission;
>  
> -	if (INTEL_GEN(dev_priv) >= 6)
> +	if (IS_GEN_GTE(dev_priv, 6))
>  		engine->emit_bb_start = gen6_emit_bb_start;
> -	else if (INTEL_GEN(dev_priv) >= 4)
> +	else if (IS_GEN_GTE(dev_priv, 4))
>  		engine->emit_bb_start = i965_emit_bb_start;
>  	else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
>  		engine->emit_bb_start = i830_emit_bb_start;
> @@ -2041,7 +2041,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
>  	if (HAS_L3_DPF(dev_priv))
>  		engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (IS_GEN_GTE(dev_priv, 6)) {
>  		engine->init_context = intel_rcs_ctx_init;
>  		engine->emit_flush = gen7_render_ring_flush;
>  		if (IS_GEN6(dev_priv))
> @@ -2049,7 +2049,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
>  	} else if (IS_GEN5(dev_priv)) {
>  		engine->emit_flush = gen4_render_ring_flush;
>  	} else {
> -		if (INTEL_GEN(dev_priv) < 4)
> +		if (IS_GEN_LT(dev_priv, 4))
>  			engine->emit_flush = gen2_render_ring_flush;
>  		else
>  			engine->emit_flush = gen4_render_ring_flush;
> @@ -2065,7 +2065,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
>  	if (ret)
>  		return ret;
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (IS_GEN_GTE(dev_priv, 6)) {
>  		ret = intel_engine_create_scratch(engine, PAGE_SIZE);
>  		if (ret)
>  			return ret;
> @@ -2084,7 +2084,7 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
>  
>  	intel_ring_default_vfuncs(dev_priv, engine);
>  
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (IS_GEN_GTE(dev_priv, 6)) {
>  		/* gen6 bsd needs a special wa for tail updates */
>  		if (IS_GEN6(dev_priv))
>  			engine->set_default_submission = gen6_bsd_set_default_submission;
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 0bf97ed5ffac..3dd5f2c244d9 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1335,13 +1335,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
>  		return;
>  
>  	/* Set the SDVO control regs. */
> -	if (INTEL_GEN(dev_priv) >= 4) {
> +	if (IS_GEN_GTE(dev_priv, 4)) {
>  		/* The real mode polarity is set by the SDVO commands, using
>  		 * struct intel_sdvo_dtd. */
>  		sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
>  		if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
>  			sdvox |= HDMI_COLOR_RANGE_16_235;
> -		if (INTEL_GEN(dev_priv) < 5)
> +		if (IS_GEN_LT(dev_priv, 5))
>  			sdvox |= SDVO_BORDER_ENABLE;
>  	} else {
>  		sdvox = I915_READ(intel_sdvo->sdvo_reg);
> @@ -1358,11 +1358,11 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
>  		sdvox |= SDVO_PIPE_SEL(crtc->pipe);
>  
>  	if (crtc_state->has_audio) {
> -		WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4);
> +		WARN_ON_ONCE(IS_GEN_LT(dev_priv, 4));
>  		sdvox |= SDVO_AUDIO_ENABLE;
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 4) {
> +	if (IS_GEN_GTE(dev_priv, 4)) {
>  		/* done in crtc_mode_set as the dpll_md reg must be written early */
>  	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
>  		   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
> @@ -1373,7 +1373,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
>  	}
>  
>  	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
> -	    INTEL_GEN(dev_priv) < 5)
> +	    IS_GEN_LT(dev_priv, 5))
>  		sdvox |= SDVO_STALL_SELECT;
>  	intel_sdvo_write_sdvox(intel_sdvo, sdvox);
>  }
> @@ -2433,7 +2433,7 @@ intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
>  	struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
>  
>  	intel_attach_force_audio_property(&connector->base.base);
> -	if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
> +	if (IS_GEN_GTE(dev_priv, 4) && IS_MOBILE(dev_priv)) {
>  		intel_attach_broadcast_rgb_property(&connector->base.base);
>  	}
>  	intel_attach_aspect_ratio_property(&connector->base.base);
> @@ -2502,7 +2502,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
>  	connector->connector_type = DRM_MODE_CONNECTOR_DVID;
>  
>  	/* gen3 doesn't do the hdmi bits in the SDVO register */
> -	if (INTEL_GEN(dev_priv) >= 4 &&
> +	if (IS_GEN_GTE(dev_priv, 4) &&
>  	    intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
>  		connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
>  		intel_sdvo->is_hdmi = true;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 3be22c0fcfb5..a28c5f83fa02 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -263,7 +263,7 @@ skl_update_plane(struct intel_plane *plane,
>  
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> +	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
>  		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>  			      plane_state->color_ctl);
>  	if (key->flags) {
> @@ -865,7 +865,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>  	struct drm_rect *src = &state->base.src;
>  	struct drm_rect *dst = &state->base.dst;
>  	struct drm_rect clip = {};
> -	int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
> +	int max_stride = IS_GEN_GTE(dev_priv, 9) ? 32768 : 16384;
>  	int hscale, vscale;
>  	int max_scale, min_scale;
>  	bool can_scale;
> @@ -892,7 +892,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>  	}
>  
>  	/* setup can_scale, min_scale, max_scale */
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		/* use scaler when colorkey is not required */
>  		if (!state->ckey.flags) {
>  			can_scale = 1;
> @@ -1012,8 +1012,8 @@ intel_check_sprite_plane(struct intel_plane *plane,
>  
>  		width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
>  
> -		if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
> -		    width_bytes > 4096 || fb->pitches[0] > 4096)) {
> +		if (IS_GEN_LT(dev_priv, 9) && (src_w > 2048 || src_h > 2048 ||
> +					       width_bytes > 4096 || fb->pitches[0] > 4096)) {
>  			DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
>  			return -EINVAL;
>  		}
> @@ -1031,7 +1031,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>  	dst->y1 = crtc_y;
>  	dst->y2 = crtc_y + crtc_h;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		ret = skl_check_plane_surface(crtc_state, state);
>  		if (ret)
>  			return ret;
> @@ -1043,7 +1043,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>  			return ret;
>  
>  		state->ctl = vlv_sprite_ctl(crtc_state, state);
> -	} else if (INTEL_GEN(dev_priv) >= 7) {
> +	} else if (IS_GEN_GTE(dev_priv, 7)) {
>  		ret = i9xx_check_plane_surface(state);
>  		if (ret)
>  			return ret;
> @@ -1057,7 +1057,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>  		state->ctl = g4x_sprite_ctl(crtc_state, state);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> +	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
>  		state->color_ctl = glk_plane_color_ctl(crtc_state, state);
>  
>  	return 0;
> @@ -1290,11 +1290,11 @@ static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
>  	    modifier != DRM_FORMAT_MOD_LINEAR)
>  		return false;
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		return skl_mod_supported(format, modifier);
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		return vlv_mod_supported(format, modifier);
> -	else if (INTEL_GEN(dev_priv) >= 6)
> +	else if (IS_GEN_GTE(dev_priv, 6))
>  		return snb_mod_supported(format, modifier);
>  	else
>  		return g4x_mod_supported(format, modifier);
> @@ -1317,7 +1317,7 @@ bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
>  	if (plane_id == PLANE_CURSOR)
>  		return false;
>  
> -	if (INTEL_GEN(dev_priv) >= 10)
> +	if (IS_GEN_GTE(dev_priv, 10))
>  		return true;
>  
>  	if (IS_GEMINILAKE(dev_priv))
> @@ -1354,7 +1354,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>  	}
>  	intel_plane->base.state = &state->base;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		intel_plane->can_scale = true;
>  		state->scaler_id = -1;
>  
> @@ -1380,7 +1380,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>  		plane_formats = vlv_plane_formats;
>  		num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
>  		modifiers = i9xx_plane_format_modifiers;
> -	} else if (INTEL_GEN(dev_priv) >= 7) {
> +	} else if (IS_GEN_GTE(dev_priv, 7)) {
>  		if (IS_IVYBRIDGE(dev_priv)) {
>  			intel_plane->can_scale = true;
>  			intel_plane->max_downscale = 2;
> @@ -1414,7 +1414,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>  		}
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		supported_rotations =
>  			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
>  			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
> @@ -1435,7 +1435,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>  
>  	possible_crtcs = (1 << pipe);
>  
> -	if (INTEL_GEN(dev_priv) >= 9)
> +	if (IS_GEN_GTE(dev_priv, 9))
>  		ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
>  					       possible_crtcs, &intel_sprite_plane_funcs,
>  					       plane_formats, num_plane_formats,
> diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
> index b3dabc219e6a..e9bed89cc1f7 100644
> --- a/drivers/gpu/drm/i915/intel_tv.c
> +++ b/drivers/gpu/drm/i915/intel_tv.c
> @@ -1067,7 +1067,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
>  
>  	set_color_conversion(dev_priv, color_conversion);
>  
> -	if (INTEL_GEN(dev_priv) >= 4)
> +	if (IS_GEN_GTE(dev_priv, 4))
>  		I915_WRITE(TV_CLR_KNOBS, 0x00404000);
>  	else
>  		I915_WRITE(TV_CLR_KNOBS, 0x00606000);
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 73959ae56241..4ae72c2f1921 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -435,7 +435,7 @@ u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
>  	/* The needed capability bits for size calculation
>  	 * are not there with pre gen9 so return 128MB always.
>  	 */
> -	if (INTEL_GEN(dev_priv) < 9)
> +	if (IS_GEN_LT(dev_priv, 9))
>  		return 128 * 1024 * 1024;
>  
>  	return gen9_edram_size(dev_priv);
> @@ -445,7 +445,7 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_HASWELL(dev_priv) ||
>  	    IS_BROADWELL(dev_priv) ||
> -	    INTEL_GEN(dev_priv) >= 9) {
> +	    IS_GEN_GTE(dev_priv, 9)) {
>  		dev_priv->edram_cap = __raw_i915_read32(dev_priv,
>  							HSW_EDRAM_CAP);
>  
> @@ -837,7 +837,7 @@ find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
>  	{ .start = (s), .end = (e), .domains = (d) }
>  
>  #define HAS_FWTABLE(dev_priv) \
> -	(INTEL_GEN(dev_priv) >= 9 || \
> +	(IS_GEN_GTE(dev_priv, 9) || \
>  	 IS_CHERRYVIEW(dev_priv) || \
>  	 IS_VALLEYVIEW(dev_priv))
>  
> @@ -1253,7 +1253,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
>  
>  static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
> +	if (IS_GEN_LTE(dev_priv, 5) || intel_vgpu_active(dev_priv))
>  		return;
>  
>  	if (IS_GEN6(dev_priv)) {
> @@ -1267,7 +1267,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>  		dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEN_GTE(dev_priv, 9)) {
>  		dev_priv->uncore.funcs.force_wake_get =
>  			fw_domains_get_with_fallback;
>  		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
> @@ -1541,7 +1541,7 @@ static void i915_stop_engines(struct drm_i915_private *dev_priv,
>  	struct intel_engine_cs *engine;
>  	enum intel_engine_id id;
>  
> -	if (INTEL_GEN(dev_priv) < 3)
> +	if (IS_GEN_LT(dev_priv, 3))
>  		return;
>  
>  	for_each_engine_masked(engine, dev_priv, engine_mask, id)
> @@ -1874,9 +1874,9 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
>  	if (!i915_modparams.reset)
>  		return NULL;
>  
> -	if (INTEL_GEN(dev_priv) >= 8)
> +	if (IS_GEN_GTE(dev_priv, 8))
>  		return gen8_reset_engines;
> -	else if (INTEL_GEN(dev_priv) >= 6)
> +	else if (IS_GEN_GTE(dev_priv, 6))
>  		return gen6_reset_engines;
>  	else if (IS_GEN5(dev_priv))
>  		return ironlake_do_reset;
> @@ -1884,7 +1884,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
>  		return g4x_do_reset;
>  	else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
>  		return g33_do_reset;
> -	else if (INTEL_GEN(dev_priv) >= 3)
> +	else if (IS_GEN_GTE(dev_priv, 3))
>  		return i915_do_reset;
>  	else
>  		return NULL;
> @@ -1987,7 +1987,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
>  
>  	if (HAS_FWTABLE(dev_priv)) {
>  		fw_domains = __fwtable_reg_read_fw_domains(offset);
> -	} else if (INTEL_GEN(dev_priv) >= 6) {
> +	} else if (IS_GEN_GTE(dev_priv, 6)) {
>  		fw_domains = __gen6_reg_read_fw_domains(offset);
>  	} else {
>  		WARN_ON(!IS_GEN(dev_priv, 2, 5));
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> index 7a0d1e17c1ad..8deed5569b7a 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> @@ -204,12 +204,12 @@ static int gpu_set(struct drm_i915_gem_object *obj,
>  		return PTR_ERR(cs);
>  	}
>  
> -	if (INTEL_GEN(i915) >= 8) {
> +	if (IS_GEN_GTE(i915, 8)) {
>  		*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
>  		*cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset);
>  		*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
>  		*cs++ = v;
> -	} else if (INTEL_GEN(i915) >= 4) {
> +	} else if (IS_GEN_GTE(i915, 4)) {
>  		*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
>  		*cs++ = 0;
>  		*cs++ = i915_ggtt_offset(vma) + offset;
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> index 56a803d11916..12ec7b39ce77 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> @@ -159,7 +159,7 @@ static int gpu_fill(struct drm_i915_gem_object *obj,
>  	}
>  
>  	flags = 0;
> -	if (INTEL_GEN(vm->i915) <= 5)
> +	if (IS_GEN_LTE(vm->i915, 5))
>  		flags |= I915_DISPATCH_SECURE;
>  
>  	err = engine->emit_bb_start(rq,
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
> index f32aa6bb79e2..2c8f500ed7f7 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
> @@ -355,7 +355,7 @@ static int igt_partial_tiling(void *arg)
>  		    tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)
>  			continue;
>  
> -		if (INTEL_GEN(i915) <= 2) {
> +		if (IS_GEN_LTE(i915, 2)) {
>  			tile.height = 16;
>  			tile.width = 128;
>  			tile.size = 11;
> @@ -370,9 +370,9 @@ static int igt_partial_tiling(void *arg)
>  			tile.size = 12;
>  		}
>  
> -		if (INTEL_GEN(i915) < 4)
> +		if (IS_GEN_LT(i915, 4))
>  			max_pitch = 8192 / tile.width;
> -		else if (INTEL_GEN(i915) < 7)
> +		else if (IS_GEN_LT(i915, 7))
>  			max_pitch = 128 * I965_FENCE_MAX_PITCH_VAL / tile.width;
>  		else
>  			max_pitch = 128 * GEN7_FENCE_MAX_PITCH_VAL / tile.width;
> @@ -385,7 +385,7 @@ static int igt_partial_tiling(void *arg)
>  			if (err)
>  				goto out_unlock;
>  
> -			if (pitch > 2 && INTEL_GEN(i915) >= 4) {
> +			if (pitch > 2 && IS_GEN_GTE(i915, 4)) {
>  				tile.stride = tile.width * (pitch - 1);
>  				err = check_partial_mapping(obj, &tile, end);
>  				if (err == -EINTR)
> @@ -394,7 +394,7 @@ static int igt_partial_tiling(void *arg)
>  					goto out_unlock;
>  			}
>  
> -			if (pitch < max_pitch && INTEL_GEN(i915) >= 4) {
> +			if (pitch < max_pitch && IS_GEN_GTE(i915, 4)) {
>  				tile.stride = tile.width * (pitch + 1);
>  				err = check_partial_mapping(obj, &tile, end);
>  				if (err == -EINTR)
> @@ -404,7 +404,7 @@ static int igt_partial_tiling(void *arg)
>  			}
>  		}
>  
> -		if (INTEL_GEN(i915) >= 4) {
> +		if (IS_GEN_GTE(i915, 4)) {
>  			for_each_prime_number(pitch, max_pitch) {
>  				tile.stride = tile.width * pitch;
>  				err = check_partial_mapping(obj, &tile, end);
> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> index d1d2c2456f69..92bc059a78f4 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> @@ -136,7 +136,7 @@ static int emit_recurse_batch(struct hang *h,
>  	}
>  
>  	batch = h->batch;
> -	if (INTEL_GEN(i915) >= 8) {
> +	if (IS_GEN_GTE(i915, 8)) {
>  		*batch++ = MI_STORE_DWORD_IMM_GEN4;
>  		*batch++ = lower_32_bits(hws_address(hws, rq));
>  		*batch++ = upper_32_bits(hws_address(hws, rq));
> @@ -150,7 +150,7 @@ static int emit_recurse_batch(struct hang *h,
>  		*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
>  		*batch++ = lower_32_bits(vma->node.start);
>  		*batch++ = upper_32_bits(vma->node.start);
> -	} else if (INTEL_GEN(i915) >= 6) {
> +	} else if (IS_GEN_GTE(i915, 6)) {
>  		*batch++ = MI_STORE_DWORD_IMM_GEN4;
>  		*batch++ = 0;
>  		*batch++ = lower_32_bits(hws_address(hws, rq));
> @@ -163,7 +163,7 @@ static int emit_recurse_batch(struct hang *h,
>  		*batch++ = MI_ARB_CHECK;
>  		*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
>  		*batch++ = lower_32_bits(vma->node.start);
> -	} else if (INTEL_GEN(i915) >= 4) {
> +	} else if (IS_GEN_GTE(i915, 4)) {
>  		*batch++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
>  		*batch++ = 0;
>  		*batch++ = lower_32_bits(hws_address(hws, rq));
> @@ -193,7 +193,7 @@ static int emit_recurse_batch(struct hang *h,
>  	i915_gem_chipset_flush(h->i915);
>  
>  	flags = 0;
> -	if (INTEL_GEN(vm->i915) <= 5)
> +	if (IS_GEN_LTE(vm->i915, 5))
>  		flags |= I915_DISPATCH_SECURE;
>  
>  	err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> index 2f6367643171..7177f97e72ef 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> @@ -173,7 +173,7 @@ int intel_uncore_live_selftests(struct drm_i915_private *i915)
>  	/* Confirm the table we load is still valid */
>  	err = intel_fw_table_check(i915->uncore.fw_domains_table,
>  				   i915->uncore.fw_domains_table_entries,
> -				   INTEL_GEN(i915) >= 9);
> +				   IS_GEN_GTE(i915, 9));
>  	if (err)
>  		return err;
>  
> -- 
> 2.14.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [RFC 14/15] drm/i915: Use new IS_GEN range helpers

[Tvrtko Ursulin]

On 08/02/2018 14:22, Ville Syrjälä wrote:
> On Thu, Feb 08, 2018 at 01:06:05PM +0000, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Coccinelle transformation:
>>
>>   @@
>>   expression p, g;
>>   @@
>>   (
>>   -INTEL_GEN(p) > g
>>   +IS_GEN_GT(p, g)
> 
> I think this stuff makes the code pretty close to illegible.
> In this particular case even more so because "GT" actually
> means something very different to us.

Oh how true! And I did not realize it at all while writing it! :)

Anyway, something like this, regardless of a name, is needed if people 
want this to be effective. Since the checks have to be moved to known at 
compile time. Or a completely different approach will be needed.

Regards,

Tvrtko

>>   |
>>   -INTEL_GEN(p) < g
>>   +IS_GEN_LT(p, g)
>>   |
>>   -INTEL_GEN(p) >= g
>>   +IS_GEN_GTE(p, g)
>>   |
>>   -INTEL_GEN(p) <= g
>>   +IS_GEN_LTE(p, g)
>>   )
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_debugfs.c                |  86 ++++-----
>>   drivers/gpu/drm/i915/i915_drv.c                    |  16 +-
>>   drivers/gpu/drm/i915/i915_drv.h                    |  14 +-
>>   drivers/gpu/drm/i915/i915_gem.c                    |  18 +-
>>   drivers/gpu/drm/i915/i915_gem_execbuffer.c         |   2 +-
>>   drivers/gpu/drm/i915/i915_gem_fence_reg.c          |   4 +-
>>   drivers/gpu/drm/i915/i915_gem_gtt.c                |  30 ++--
>>   drivers/gpu/drm/i915/i915_gem_request.c            |   2 +-
>>   drivers/gpu/drm/i915/i915_gem_stolen.c             |   6 +-
>>   drivers/gpu/drm/i915/i915_gem_tiling.c             |   8 +-
>>   drivers/gpu/drm/i915/i915_gpu_error.c              |  40 ++---
>>   drivers/gpu/drm/i915/i915_irq.c                    |  58 +++---
>>   drivers/gpu/drm/i915/i915_perf.c                   |   2 +-
>>   drivers/gpu/drm/i915/i915_pmu.c                    |   6 +-
>>   drivers/gpu/drm/i915/i915_reg.h                    |   4 +-
>>   drivers/gpu/drm/i915/i915_suspend.c                |  12 +-
>>   drivers/gpu/drm/i915/i915_sysfs.c                  |   2 +-
>>   drivers/gpu/drm/i915/intel_atomic_plane.c          |   2 +-
>>   drivers/gpu/drm/i915/intel_audio.c                 |   2 +-
>>   drivers/gpu/drm/i915/intel_cdclk.c                 |   8 +-
>>   drivers/gpu/drm/i915/intel_color.c                 |   2 +-
>>   drivers/gpu/drm/i915/intel_crt.c                   |   6 +-
>>   drivers/gpu/drm/i915/intel_ddi.c                   |  10 +-
>>   drivers/gpu/drm/i915/intel_device_info.c           |  14 +-
>>   drivers/gpu/drm/i915/intel_display.c               | 194 ++++++++++-----------
>>   drivers/gpu/drm/i915/intel_dp.c                    |  28 +--
>>   drivers/gpu/drm/i915/intel_dpll_mgr.c              |   4 +-
>>   drivers/gpu/drm/i915/intel_engine_cs.c             |  22 +--
>>   drivers/gpu/drm/i915/intel_fbc.c                   |  30 ++--
>>   drivers/gpu/drm/i915/intel_fifo_underrun.c         |   2 +-
>>   drivers/gpu/drm/i915/intel_hangcheck.c             |   2 +-
>>   drivers/gpu/drm/i915/intel_hdcp.c                  |   2 +-
>>   drivers/gpu/drm/i915/intel_hdmi.c                  |  10 +-
>>   drivers/gpu/drm/i915/intel_lrc.c                   |   6 +-
>>   drivers/gpu/drm/i915/intel_lvds.c                  |  10 +-
>>   drivers/gpu/drm/i915/intel_mocs.c                  |   2 +-
>>   drivers/gpu/drm/i915/intel_overlay.c               |   2 +-
>>   drivers/gpu/drm/i915/intel_panel.c                 |  10 +-
>>   drivers/gpu/drm/i915/intel_pipe_crc.c              |   2 +-
>>   drivers/gpu/drm/i915/intel_pm.c                    | 100 +++++------
>>   drivers/gpu/drm/i915/intel_psr.c                   |   6 +-
>>   drivers/gpu/drm/i915/intel_ringbuffer.c            |  34 ++--
>>   drivers/gpu/drm/i915/intel_sdvo.c                  |  14 +-
>>   drivers/gpu/drm/i915/intel_sprite.c                |  30 ++--
>>   drivers/gpu/drm/i915/intel_tv.c                    |   2 +-
>>   drivers/gpu/drm/i915/intel_uncore.c                |  20 +--
>>   .../gpu/drm/i915/selftests/i915_gem_coherency.c    |   4 +-
>>   drivers/gpu/drm/i915/selftests/i915_gem_context.c  |   2 +-
>>   drivers/gpu/drm/i915/selftests/i915_gem_object.c   |  12 +-
>>   drivers/gpu/drm/i915/selftests/intel_hangcheck.c   |   8 +-
>>   drivers/gpu/drm/i915/selftests/intel_uncore.c      |   2 +-
>>   51 files changed, 457 insertions(+), 457 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 3849ded354e3..0cedbcc8c6e2 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -708,7 +708,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>>   			   I915_READ(GEN8_PCU_IIR));
>>   		seq_printf(m, "PCU interrupt enable:\t%08x\n",
>>   			   I915_READ(GEN8_PCU_IER));
>> -	} else if (INTEL_GEN(dev_priv) >= 8) {
>> +	} else if (IS_GEN_GTE(dev_priv, 8)) {
>>   		seq_printf(m, "Master Interrupt Control:\t%08x\n",
>>   			   I915_READ(GEN8_MASTER_IRQ));
>>   
>> @@ -845,7 +845,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>>   		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
>>   			   I915_READ(GTIMR));
>>   	}
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +	if (IS_GEN_GTE(dev_priv, 6)) {
>>   		for_each_engine(engine, dev_priv, id) {
>>   			seq_printf(m,
>>   				   "Graphics Interrupt mask (%s):	%08x\n",
>> @@ -1056,7 +1056,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>   			   "efficient (RPe) frequency: %d MHz\n",
>>   			   intel_gpu_freq(dev_priv, rps->efficient_freq));
>>   		mutex_unlock(&dev_priv->pcu_lock);
>> -	} else if (INTEL_GEN(dev_priv) >= 6) {
>> +	} else if (IS_GEN_GTE(dev_priv, 6)) {
>>   		u32 rp_state_limits;
>>   		u32 gt_perf_status;
>>   		u32 rp_state_cap;
>> @@ -1080,7 +1080,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>   		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>>   
>>   		reqf = I915_READ(GEN6_RPNSWREQ);
>> -		if (INTEL_GEN(dev_priv) >= 9)
>> +		if (IS_GEN_GTE(dev_priv, 9))
>>   			reqf >>= 23;
>>   		else {
>>   			reqf &= ~GEN6_TURBO_DISABLE;
>> @@ -1133,7 +1133,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>>   			   rps->pm_intrmsk_mbz);
>>   		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
>>   		seq_printf(m, "Render p-state ratio: %d\n",
>> -			   (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
>> +			   (gt_perf_status & (IS_GEN_GTE(dev_priv, 9) ? 0x1ff00 : 0xff00)) >> 8);
>>   		seq_printf(m, "Render p-state VID: %d\n",
>>   			   gt_perf_status & 0xff);
>>   		seq_printf(m, "Render p-state limit: %d\n",
>> @@ -1218,13 +1218,13 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
>>   	seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
>>   		   instdone->instdone);
>>   
>> -	if (INTEL_GEN(dev_priv) <= 3)
>> +	if (IS_GEN_LTE(dev_priv, 3))
>>   		return;
>>   
>>   	seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
>>   		   instdone->slice_common);
>>   
>> -	if (INTEL_GEN(dev_priv) <= 6)
>> +	if (IS_GEN_LTE(dev_priv, 6))
>>   		return;
>>   
>>   	for_each_instdone_slice_subslice(dev_priv, slice, subslice)
>> @@ -1478,7 +1478,7 @@ static int gen6_drpc_info(struct seq_file *m)
>>   	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
>>   
>>   	rcctl1 = I915_READ(GEN6_RC_CONTROL);
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
>>   		gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
>>   	}
>> @@ -1491,7 +1491,7 @@ static int gen6_drpc_info(struct seq_file *m)
>>   		   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
>>   	seq_printf(m, "RC6 Enabled: %s\n",
>>   		   yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		seq_printf(m, "Render Well Gating Enabled: %s\n",
>>   			yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
>>   		seq_printf(m, "Media Well Gating Enabled: %s\n",
>> @@ -1525,7 +1525,7 @@ static int gen6_drpc_info(struct seq_file *m)
>>   
>>   	seq_printf(m, "Core Power Down: %s\n",
>>   		   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		seq_printf(m, "Render Power Well: %s\n",
>>   			(gen9_powergate_status &
>>   			 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
>> @@ -1559,7 +1559,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
>>   
>>   	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>   		err = vlv_drpc_info(m);
>> -	else if (INTEL_GEN(dev_priv) >= 6)
>> +	else if (IS_GEN_GTE(dev_priv, 6))
>>   		err = gen6_drpc_info(m);
>>   	else
>>   		err = ironlake_drpc_info(m);
>> @@ -1606,11 +1606,11 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
>>   	if (intel_fbc_is_active(dev_priv)) {
>>   		u32 mask;
>>   
>> -		if (INTEL_GEN(dev_priv) >= 8)
>> +		if (IS_GEN_GTE(dev_priv, 8))
>>   			mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
>> -		else if (INTEL_GEN(dev_priv) >= 7)
>> +		else if (IS_GEN_GTE(dev_priv, 7))
>>   			mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
>> -		else if (INTEL_GEN(dev_priv) >= 5)
>> +		else if (IS_GEN_GTE(dev_priv, 5))
>>   			mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK;
>>   		else if (IS_G4X(dev_priv))
>>   			mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK;
>> @@ -1631,7 +1631,7 @@ static int i915_fbc_false_color_get(void *data, u64 *val)
>>   {
>>   	struct drm_i915_private *dev_priv = data;
>>   
>> -	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
>> +	if (IS_GEN_LT(dev_priv, 7) || !HAS_FBC(dev_priv))
>>   		return -ENODEV;
>>   
>>   	*val = dev_priv->fbc.false_color;
>> @@ -1644,7 +1644,7 @@ static int i915_fbc_false_color_set(void *data, u64 val)
>>   	struct drm_i915_private *dev_priv = data;
>>   	u32 reg;
>>   
>> -	if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
>> +	if (IS_GEN_LT(dev_priv, 7) || !HAS_FBC(dev_priv))
>>   		return -ENODEV;
>>   
>>   	mutex_lock(&dev_priv->fbc.lock);
>> @@ -1676,7 +1676,7 @@ static int i915_ips_status(struct seq_file *m, void *unused)
>>   	seq_printf(m, "Enabled by kernel parameter: %s\n",
>>   		   yesno(i915_modparams.enable_ips));
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8) {
>> +	if (IS_GEN_GTE(dev_priv, 8)) {
>>   		seq_puts(m, "Currently: unknown\n");
>>   	} else {
>>   		if (I915_READ(IPS_CTL) & IPS_ENABLE)
>> @@ -1698,7 +1698,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>>   	intel_runtime_pm_get(dev_priv);
>>   	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		/* no global SR status; inspect per-plane WM */;
>>   	else if (HAS_PCH_SPLIT(dev_priv))
>>   		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
>> @@ -1978,7 +1978,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
>>   			   I915_READ16(C0DRB3));
>>   		seq_printf(m, "C1DRB3 = 0x%04x\n",
>>   			   I915_READ16(C1DRB3));
>> -	} else if (INTEL_GEN(dev_priv) >= 6) {
>> +	} else if (IS_GEN_GTE(dev_priv, 6)) {
>>   		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
>>   			   I915_READ(MAD_DIMM_C0));
>>   		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
>> @@ -1987,7 +1987,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
>>   			   I915_READ(MAD_DIMM_C2));
>>   		seq_printf(m, "TILECTL = 0x%08x\n",
>>   			   I915_READ(TILECTL));
>> -		if (INTEL_GEN(dev_priv) >= 8)
>> +		if (IS_GEN_GTE(dev_priv, 8))
>>   			seq_printf(m, "GAMTARBMODE = 0x%08x\n",
>>   				   I915_READ(GAMTARBMODE));
>>   		else
>> @@ -2095,9 +2095,9 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
>>   
>>   	intel_runtime_pm_get(dev_priv);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> +	if (IS_GEN_GTE(dev_priv, 8))
>>   		gen8_ppgtt_info(m, dev_priv);
>> -	else if (INTEL_GEN(dev_priv) >= 6)
>> +	else if (IS_GEN_GTE(dev_priv, 6))
>>   		gen6_ppgtt_info(m, dev_priv);
>>   
>>   	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
>> @@ -2191,7 +2191,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
>>   		   atomic_read(&rps->boosts));
>>   	mutex_unlock(&dev->filelist_mutex);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6 &&
>> +	if (IS_GEN_GTE(dev_priv, 6) &&
>>   	    rps->enabled &&
>>   	    dev_priv->gt.active_requests) {
>>   		u32 rpup, rpupei;
>> @@ -2222,7 +2222,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
>>   static int i915_llc(struct seq_file *m, void *data)
>>   {
>>   	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> -	const bool edram = INTEL_GEN(dev_priv) > 8;
>> +	const bool edram = IS_GEN_GT(dev_priv, 8);
>>   
>>   	seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
>>   	seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
>> @@ -2675,7 +2675,7 @@ static int i915_energy_uJ(struct seq_file *m, void *data)
>>   	unsigned long long power;
>>   	u32 units;
>>   
>> -	if (INTEL_GEN(dev_priv) < 6)
>> +	if (IS_GEN_LT(dev_priv, 6))
>>   		return -ENODEV;
>>   
>>   	intel_runtime_pm_get(dev_priv);
>> @@ -3290,7 +3290,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
>>   	enum pipe pipe;
>>   	int plane;
>>   
>> -	if (INTEL_GEN(dev_priv) < 9)
>> +	if (IS_GEN_LT(dev_priv, 9))
>>   		return -ENODEV;
>>   
>>   	drm_modeset_lock_all(dev);
>> @@ -3689,7 +3689,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
>>   		 * - WM1+ latency values in 0.5us units
>>   		 * - latencies are in us on gen9/vlv/chv
>>   		 */
>> -		if (INTEL_GEN(dev_priv) >= 9 ||
>> +		if (IS_GEN_GTE(dev_priv, 9) ||
>>   		    IS_VALLEYVIEW(dev_priv) ||
>>   		    IS_CHERRYVIEW(dev_priv) ||
>>   		    IS_G4X(dev_priv))
>> @@ -3709,7 +3709,7 @@ static int pri_wm_latency_show(struct seq_file *m, void *data)
>>   	struct drm_i915_private *dev_priv = m->private;
>>   	const uint16_t *latencies;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		latencies = dev_priv->wm.skl_latency;
>>   	else
>>   		latencies = dev_priv->wm.pri_latency;
>> @@ -3724,7 +3724,7 @@ static int spr_wm_latency_show(struct seq_file *m, void *data)
>>   	struct drm_i915_private *dev_priv = m->private;
>>   	const uint16_t *latencies;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		latencies = dev_priv->wm.skl_latency;
>>   	else
>>   		latencies = dev_priv->wm.spr_latency;
>> @@ -3739,7 +3739,7 @@ static int cur_wm_latency_show(struct seq_file *m, void *data)
>>   	struct drm_i915_private *dev_priv = m->private;
>>   	const uint16_t *latencies;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		latencies = dev_priv->wm.skl_latency;
>>   	else
>>   		latencies = dev_priv->wm.cur_latency;
>> @@ -3753,7 +3753,7 @@ static int pri_wm_latency_open(struct inode *inode, struct file *file)
>>   {
>>   	struct drm_i915_private *dev_priv = inode->i_private;
>>   
>> -	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
>> +	if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv))
>>   		return -ENODEV;
>>   
>>   	return single_open(file, pri_wm_latency_show, dev_priv);
>> @@ -3832,7 +3832,7 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
>>   	struct drm_i915_private *dev_priv = m->private;
>>   	uint16_t *latencies;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		latencies = dev_priv->wm.skl_latency;
>>   	else
>>   		latencies = dev_priv->wm.pri_latency;
>> @@ -3847,7 +3847,7 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
>>   	struct drm_i915_private *dev_priv = m->private;
>>   	uint16_t *latencies;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		latencies = dev_priv->wm.skl_latency;
>>   	else
>>   		latencies = dev_priv->wm.spr_latency;
>> @@ -3862,7 +3862,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
>>   	struct drm_i915_private *dev_priv = m->private;
>>   	uint16_t *latencies;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		latencies = dev_priv->wm.skl_latency;
>>   	else
>>   		latencies = dev_priv->wm.cur_latency;
>> @@ -4100,7 +4100,7 @@ i915_max_freq_get(void *data, u64 *val)
>>   {
>>   	struct drm_i915_private *dev_priv = data;
>>   
>> -	if (INTEL_GEN(dev_priv) < 6)
>> +	if (IS_GEN_LT(dev_priv, 6))
>>   		return -ENODEV;
>>   
>>   	*val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.max_freq_softlimit);
>> @@ -4115,7 +4115,7 @@ i915_max_freq_set(void *data, u64 val)
>>   	u32 hw_max, hw_min;
>>   	int ret;
>>   
>> -	if (INTEL_GEN(dev_priv) < 6)
>> +	if (IS_GEN_LT(dev_priv, 6))
>>   		return -ENODEV;
>>   
>>   	DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
>> @@ -4156,7 +4156,7 @@ i915_min_freq_get(void *data, u64 *val)
>>   {
>>   	struct drm_i915_private *dev_priv = data;
>>   
>> -	if (INTEL_GEN(dev_priv) < 6)
>> +	if (IS_GEN_LT(dev_priv, 6))
>>   		return -ENODEV;
>>   
>>   	*val = intel_gpu_freq(dev_priv, dev_priv->gt_pm.rps.min_freq_softlimit);
>> @@ -4171,7 +4171,7 @@ i915_min_freq_set(void *data, u64 val)
>>   	u32 hw_max, hw_min;
>>   	int ret;
>>   
>> -	if (INTEL_GEN(dev_priv) < 6)
>> +	if (IS_GEN_LT(dev_priv, 6))
>>   		return -ENODEV;
>>   
>>   	DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
>> @@ -4469,7 +4469,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>>   	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>>   	struct sseu_dev_info sseu;
>>   
>> -	if (INTEL_GEN(dev_priv) < 8)
>> +	if (IS_GEN_LT(dev_priv, 8))
>>   		return -ENODEV;
>>   
>>   	seq_puts(m, "SSEU Device Info\n");
>> @@ -4486,7 +4486,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>>   		broadwell_sseu_device_status(dev_priv, &sseu);
>>   	} else if (IS_GEN9(dev_priv)) {
>>   		gen9_sseu_device_status(dev_priv, &sseu);
>> -	} else if (INTEL_GEN(dev_priv) >= 10) {
>> +	} else if (IS_GEN_GTE(dev_priv, 10)) {
>>   		gen10_sseu_device_status(dev_priv, &sseu);
>>   	}
>>   
>> @@ -4501,7 +4501,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
>>   {
>>   	struct drm_i915_private *i915 = inode->i_private;
>>   
>> -	if (INTEL_GEN(i915) < 6)
>> +	if (IS_GEN_LT(i915, 6))
>>   		return 0;
>>   
>>   	intel_runtime_pm_get(i915);
>> @@ -4514,7 +4514,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file)
>>   {
>>   	struct drm_i915_private *i915 = inode->i_private;
>>   
>> -	if (INTEL_GEN(i915) < 6)
>> +	if (IS_GEN_LT(i915, 6))
>>   		return 0;
>>   
>>   	intel_uncore_forcewake_user_put(i915);
>> @@ -4612,7 +4612,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
>>   	struct intel_encoder *encoder;
>>   	struct intel_dp *intel_dp;
>>   
>> -	if (INTEL_GEN(dev_priv) < 7)
>> +	if (IS_GEN_LT(dev_priv, 7))
>>   		return -ENODEV;
>>   
>>   	drm_modeset_lock_all(dev);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index bb605e0b996c..8e108eb233ee 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -459,12 +459,12 @@ static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
>>   static int
>>   intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
>>   {
>> -	int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
>> +	int reg = IS_GEN_GTE(dev_priv, 4) ? MCHBAR_I965 : MCHBAR_I915;
>>   	u32 temp_lo, temp_hi = 0;
>>   	u64 mchbar_addr;
>>   	int ret;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
>>   	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
>>   	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
>> @@ -491,7 +491,7 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
>>   		return ret;
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
>>   				       upper_32_bits(dev_priv->mch_res.start));
>>   
>> @@ -504,7 +504,7 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
>>   static void
>>   intel_setup_mchbar(struct drm_i915_private *dev_priv)
>>   {
>> -	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
>> +	int mchbar_reg = IS_GEN_GTE(dev_priv, 4) ? MCHBAR_I965 : MCHBAR_I915;
>>   	u32 temp;
>>   	bool enabled;
>>   
>> @@ -543,7 +543,7 @@ intel_setup_mchbar(struct drm_i915_private *dev_priv)
>>   static void
>>   intel_teardown_mchbar(struct drm_i915_private *dev_priv)
>>   {
>> -	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
>> +	int mchbar_reg = IS_GEN_GTE(dev_priv, 4) ? MCHBAR_I965 : MCHBAR_I915;
>>   
>>   	if (dev_priv->mchbar_need_disable) {
>>   		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
>> @@ -983,7 +983,7 @@ static int i915_mmio_setup(struct drm_i915_private *dev_priv)
>>   	 * the register BAR remains the same size for all the earlier
>>   	 * generations up to Ironlake.
>>   	 */
>> -	if (INTEL_GEN(dev_priv) < 5)
>> +	if (IS_GEN_LT(dev_priv, 5))
>>   		mmio_size = 512 * 1024;
>>   	else
>>   		mmio_size = 2 * 1024 * 1024;
>> @@ -1181,7 +1181,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>>   	 * properly dead afterwards. So we'll just disable them for all
>>   	 * pre-gen5 chipsets.
>>   	 */
>> -	if (INTEL_GEN(dev_priv) >= 5) {
>> +	if (IS_GEN_GTE(dev_priv, 5)) {
>>   		if (pci_enable_msi(pdev) < 0)
>>   			DRM_DEBUG_DRIVER("can't enable MSI");
>>   	}
>> @@ -1672,7 +1672,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
>>   	 * Fujitsu FSC S7110
>>   	 * Acer Aspire 1830T
>>   	 */
>> -	if (!(hibernation && INTEL_GEN(dev_priv) < 6))
>> +	if (!(hibernation && IS_GEN_LT(dev_priv, 6)))
>>   		pci_set_power_state(pdev, PCI_D3hot);
>>   
>>   	dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index b66f288bde7d..1d8c318ddeff 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2855,7 +2855,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>>    * interrupts.
>>    */
>>   #define HAS_AUX_IRQ(dev_priv)   true
>> -#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
>> +#define HAS_GMBUS_IRQ(dev_priv) (IS_GEN_GTE(dev_priv, 4))
>>   
>>   /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
>>    * rows, which changed the alignment requirements and fence programming.
>> @@ -2866,7 +2866,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>>   #define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
>>   #define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
>>   
>> -#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
>> +#define HAS_FW_BLC(dev_priv) 	(IS_GEN_GT(dev_priv, 2))
>>   #define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
>>   #define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
>>   
>> @@ -2951,7 +2951,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>>   
>>   #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
>>   
>> -#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
>> +#define HAS_LSPCON(dev_priv) (IS_GEN_GTE(dev_priv, 9))
>>   
>>   /* DPF == dynamic parity feature */
>>   #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
>> @@ -2974,7 +2974,7 @@ static inline bool intel_vtd_active(void)
>>   
>>   static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
>>   {
>> -	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
>> +	return IS_GEN_GTE(dev_priv, 6) && intel_vtd_active();
>>   }
>>   
>>   static inline bool
>> @@ -3561,7 +3561,7 @@ void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
>>   static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
>>   {
>>   	wmb();
>> -	if (INTEL_GEN(dev_priv) < 6)
>> +	if (IS_GEN_LT(dev_priv, 6))
>>   		intel_gtt_chipset_flush();
>>   }
>>   
>> @@ -3996,7 +3996,7 @@ static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
>>   {
>>   	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>   		return VLV_VGACNTRL;
>> -	else if (INTEL_GEN(dev_priv) >= 5)
>> +	else if (IS_GEN_GTE(dev_priv, 5))
>>   		return CPU_VGACNTRL;
>>   	else
>>   		return VGACNTRL;
>> @@ -4164,7 +4164,7 @@ int remap_io_mapping(struct vm_area_struct *vma,
>>   
>>   static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
>>   {
>> -	if (INTEL_GEN(i915) >= 10)
>> +	if (IS_GEN_GTE(i915, 10))
>>   		return CNL_HWS_CSB_WRITE_INDEX;
>>   	else
>>   		return I915_HWS_CSB_WRITE_INDEX;
>> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>> index 1d5208f24b60..9a1cee3a590b 100644
>> --- a/drivers/gpu/drm/i915/i915_gem.c
>> +++ b/drivers/gpu/drm/i915/i915_gem.c
>> @@ -386,7 +386,7 @@ i915_gem_object_wait_fence(struct dma_fence *fence,
>>   	 * each client to waitboost once in a busy period.
>>   	 */
>>   	if (rps_client && !i915_gem_request_started(rq)) {
>> -		if (INTEL_GEN(rq->i915) >= 6)
>> +		if (IS_GEN_GTE(rq->i915, 6))
>>   			gen6_rps_boost(rq, rps_client);
>>   	}
>>   
>> @@ -3148,7 +3148,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
>>   	if (dev_priv->gt.awake) {
>>   		intel_sanitize_gt_powersave(dev_priv);
>>   		intel_enable_gt_powersave(dev_priv);
>> -		if (INTEL_GEN(dev_priv) >= 6)
>> +		if (IS_GEN_GTE(dev_priv, 6))
>>   			gen6_rps_busy(dev_priv);
>>   	}
>>   }
>> @@ -3474,7 +3474,7 @@ i915_gem_idle_work_handler(struct work_struct *work)
>>   	GEM_BUG_ON(epoch == I915_EPOCH_INVALID);
>>   	rearm_hangcheck = false;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6)
>> +	if (IS_GEN_GTE(dev_priv, 6))
>>   		gen6_rps_idle(dev_priv);
>>   
>>   	intel_display_power_put(dev_priv, POWER_DOMAIN_GT_IRQ);
>> @@ -4882,7 +4882,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
>>   	 * it may impact the display and we are uncertain about the stability
>>   	 * of the reset, so this could be applied to even earlier gen.
>>   	 */
>> -	if (INTEL_GEN(i915) >= 5) {
>> +	if (IS_GEN_GTE(i915, 5)) {
>>   		int reset = intel_gpu_reset(i915, ALL_ENGINES);
>>   		WARN_ON(reset && reset != -ENODEV);
>>   	}
>> @@ -5010,7 +5010,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
>>   
>>   void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
>>   {
>> -	if (INTEL_GEN(dev_priv) < 5 ||
>> +	if (IS_GEN_LT(dev_priv, 5) ||
>>   	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
>>   		return;
>>   
>> @@ -5084,7 +5084,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>>   	/* Double layer security blanket, see i915_gem_init() */
>>   	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>>   
>> -	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
>> +	if (HAS_EDRAM(dev_priv) && IS_GEN_LT(dev_priv, 9))
>>   		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
>>   
>>   	if (IS_HASWELL(dev_priv))
>> @@ -5096,7 +5096,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>>   			u32 temp = I915_READ(GEN7_MSG_CTL);
>>   			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
>>   			I915_WRITE(GEN7_MSG_CTL, temp);
>> -		} else if (INTEL_GEN(dev_priv) >= 7) {
>> +		} else if (IS_GEN_GTE(dev_priv, 7)) {
>>   			u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
>>   			temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
>>   			I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
>> @@ -5420,10 +5420,10 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
>>   {
>>   	int i;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) &&
>> +	if (IS_GEN_GTE(dev_priv, 7) && !IS_VALLEYVIEW(dev_priv) &&
>>   	    !IS_CHERRYVIEW(dev_priv))
>>   		dev_priv->num_fence_regs = 32;
>> -	else if (INTEL_GEN(dev_priv) >= 4 ||
>> +	else if (IS_GEN_GTE(dev_priv, 4) ||
>>   		 IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
>>   		 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
>>   		dev_priv->num_fence_regs = 16;
>> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
>> index 4401068ff468..f2da6e6d23c0 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
>> @@ -2522,7 +2522,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
>>   		exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
>>   		exec2_list[i].alignment = exec_list[i].alignment;
>>   		exec2_list[i].offset = exec_list[i].offset;
>> -		if (INTEL_GEN(to_i915(dev)) < 4)
>> +		if (IS_GEN_LT(to_i915(dev), 4))
>>   			exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
>>   		else
>>   			exec2_list[i].flags = 0;
>> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>> index b8338d75c6f3..fe69e970d1ed 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>> @@ -557,7 +557,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
>>   	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>>   	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
>> +	if (IS_GEN_GTE(dev_priv, 8) || IS_VALLEYVIEW(dev_priv)) {
>>   		/*
>>   		 * On BDW+, swizzling is not used. We leave the CPU memory
>>   		 * controller in charge of optimizing memory accesses without
>> @@ -567,7 +567,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
>>   		 */
>>   		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
>>   		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
>> -	} else if (INTEL_GEN(dev_priv) >= 6) {
>> +	} else if (IS_GEN_GTE(dev_priv, 6)) {
>>   		if (dev_priv->preserve_bios_swizzle) {
>>   			if (I915_READ(DISP_ARB_CTL) &
>>   			    DISP_TILE_SURFACE_SWIZZLING) {
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index 0c0f1affddad..6fb0949facb4 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -154,7 +154,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>>   	 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
>>   	 * execlists, the sole mechanism available to submit work.
>>   	 */
>> -	if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
>> +	if (enable_ppgtt == 0 && IS_GEN_LT(dev_priv, 9))
>>   		return 0;
>>   
>>   	if (enable_ppgtt == 1)
>> @@ -2109,7 +2109,7 @@ static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
>>   	ppgtt->base.i915 = dev_priv;
>>   	ppgtt->base.dma = &dev_priv->drm.pdev->dev;
>>   
>> -	if (INTEL_GEN(dev_priv) < 8)
>> +	if (IS_GEN_LT(dev_priv, 8))
>>   		return gen6_ppgtt_init(ppgtt);
>>   	else
>>   		return gen8_ppgtt_init(ppgtt);
>> @@ -2170,7 +2170,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
>>   	 * driver.
>>   	 */
>>   	if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
>> -	    INTEL_GEN(dev_priv) <= 10)
>> +	    IS_GEN_LTE(dev_priv, 10))
>>   		I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
>>   			   I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
>>   			   GAMW_ECO_ENABLE_64K_IPS_FIELD);
>> @@ -2193,7 +2193,7 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
>>   		gen6_ppgtt_enable(dev_priv);
>>   	else if (IS_GEN7(dev_priv))
>>   		gen7_ppgtt_enable(dev_priv);
>> -	else if (INTEL_GEN(dev_priv) >= 8)
>> +	else if (IS_GEN_GTE(dev_priv, 8))
>>   		gen8_ppgtt_enable(dev_priv);
>>   	else
>>   		MISSING_CASE(INTEL_GEN(dev_priv));
>> @@ -2338,9 +2338,9 @@ static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
>>   void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
>>   {
>>   	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> +	if (IS_GEN_GTE(dev_priv, 8))
>>   		gen8_check_and_clear_faults(dev_priv);
>> -	else if (INTEL_GEN(dev_priv) >= 6)
>> +	else if (IS_GEN_GTE(dev_priv, 6))
>>   		gen6_check_and_clear_faults(dev_priv);
>>   	else
>>   		return;
>> @@ -2353,7 +2353,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
>>   	/* Don't bother messing with faults pre GEN6 as we have little
>>   	 * documentation supporting that it's a good idea.
>>   	 */
>> -	if (INTEL_GEN(dev_priv) < 6)
>> +	if (IS_GEN_LT(dev_priv, 6))
>>   		return;
>>   
>>   	i915_check_and_clear_faults(dev_priv);
>> @@ -2999,7 +2999,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
>>   	 * resort to an uncached mapping. The WC issue is easily caught by the
>>   	 * readback check when writing GTT PTE entries.
>>   	 */
>> -	if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>> +	if (IS_GEN9_LP(dev_priv) || IS_GEN_GTE(dev_priv, 10))
>>   		ggtt->gsm = ioremap_nocache(phys_addr, size);
>>   	else
>>   		ggtt->gsm = ioremap_wc(phys_addr, size);
>> @@ -3294,7 +3294,7 @@ static void setup_private_pat(struct drm_i915_private *dev_priv)
>>   
>>   	ppat->i915 = dev_priv;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10)
>> +	if (IS_GEN_GTE(dev_priv, 10))
>>   		cnl_setup_private_ppat(ppat);
>>   	else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
>>   		chv_setup_private_ppat(ppat);
>> @@ -3334,7 +3334,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>>   
>>   	pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		size = gen8_get_total_gtt_size(snb_gmch_ctl);
>>   	} else if (IS_CHERRYVIEW(dev_priv)) {
>>   		size = chv_get_total_gtt_size(snb_gmch_ctl);
>> @@ -3418,7 +3418,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
>>   		ggtt->base.pte_encode = hsw_pte_encode;
>>   	else if (IS_VALLEYVIEW(dev_priv))
>>   		ggtt->base.pte_encode = byt_pte_encode;
>> -	else if (INTEL_GEN(dev_priv) >= 7)
>> +	else if (IS_GEN_GTE(dev_priv, 7))
>>   		ggtt->base.pte_encode = ivb_pte_encode;
>>   	else
>>   		ggtt->base.pte_encode = snb_pte_encode;
>> @@ -3481,9 +3481,9 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
>>   	ggtt->base.i915 = dev_priv;
>>   	ggtt->base.dma = &dev_priv->drm.pdev->dev;
>>   
>> -	if (INTEL_GEN(dev_priv) <= 5)
>> +	if (IS_GEN_LTE(dev_priv, 5))
>>   		ret = i915_gmch_probe(ggtt);
>> -	else if (INTEL_GEN(dev_priv) < 8)
>> +	else if (IS_GEN_LT(dev_priv, 8))
>>   		ret = gen6_gmch_probe(ggtt);
>>   	else
>>   		ret = gen8_gmch_probe(ggtt);
>> @@ -3574,7 +3574,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
>>   
>>   int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
>>   {
>> -	if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt())
>> +	if (IS_GEN_LT(dev_priv, 6) && !intel_enable_gtt())
>>   		return -EIO;
>>   
>>   	return 0;
>> @@ -3631,7 +3631,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
>>   
>>   	ggtt->base.closed = false;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8) {
>> +	if (IS_GEN_GTE(dev_priv, 8)) {
>>   		struct intel_ppat *ppat = &dev_priv->ppat;
>>   
>>   		bitmap_set(ppat->dirty, 0, ppat->max_entries);
>> diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
>> index a8eb22a95b0f..38a3352e827a 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_request.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_request.c
>> @@ -279,7 +279,7 @@ static void mark_busy(struct drm_i915_private *i915)
>>   
>>   	intel_enable_gt_powersave(i915);
>>   	i915_update_gfx_val(i915);
>> -	if (INTEL_GEN(i915) >= 6)
>> +	if (IS_GEN_GTE(i915, 6))
>>   		gen6_rps_busy(i915);
>>   	i915_pmu_gt_unparked(i915);
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
>> index f18da9e2be8e..5c7246db06a2 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
>> @@ -91,7 +91,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv,
>>   	 */
>>   
>>   	/* Make sure we don't clobber the GTT if it's within stolen memory */
>> -	if (INTEL_GEN(dev_priv) <= 4 &&
>> +	if (IS_GEN_LTE(dev_priv, 4) &&
>>   	    !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv)) {
>>   		struct resource stolen[2] = {*dsm, *dsm};
>>   		struct resource ggtt_res;
>> @@ -336,7 +336,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
>>   		return 0;
>>   	}
>>   
>> -	if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) {
>> +	if (intel_vtd_active() && IS_GEN_LT(dev_priv, 8)) {
>>   		DRM_INFO("DMAR active, disabling use of stolen memory\n");
>>   		return 0;
>>   	}
>> @@ -412,7 +412,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
>>   
>>   	stolen_usable_start = 0;
>>   	/* WaSkipStolenMemoryFirstPage:bdw+ */
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> +	if (IS_GEN_GTE(dev_priv, 8))
>>   		stolen_usable_start = 4096;
>>   
>>   	dev_priv->stolen_usable_size =
>> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
>> index d9dc9df523b5..8a1e7082579a 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
>> @@ -80,7 +80,7 @@ u32 i915_gem_fence_size(struct drm_i915_private *i915,
>>   
>>   	GEM_BUG_ON(!stride);
>>   
>> -	if (INTEL_GEN(i915) >= 4) {
>> +	if (IS_GEN_GTE(i915, 4)) {
>>   		stride *= i915_gem_tile_height(tiling);
>>   		GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
>>   		return roundup(size, stride);
>> @@ -120,7 +120,7 @@ u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
>>   	if (tiling == I915_TILING_NONE)
>>   		return I915_GTT_MIN_ALIGNMENT;
>>   
>> -	if (INTEL_GEN(i915) >= 4)
>> +	if (IS_GEN_GTE(i915, 4))
>>   		return I965_FENCE_PAGE;
>>   
>>   	/*
>> @@ -148,10 +148,10 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
>>   	/* check maximum stride & object size */
>>   	/* i965+ stores the end address of the gtt mapping in the fence
>>   	 * reg, so dont bother to check the size */
>> -	if (INTEL_GEN(i915) >= 7) {
>> +	if (IS_GEN_GTE(i915, 7)) {
>>   		if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
>>   			return false;
>> -	} else if (INTEL_GEN(i915) >= 4) {
>> +	} else if (IS_GEN_GTE(i915, 4)) {
>>   		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
>>   			return false;
>>   	} else {
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index 67c902412193..c5a7ed4d9c1e 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -376,13 +376,13 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
>>   	err_printf(m, "  INSTDONE: 0x%08x\n",
>>   		   ee->instdone.instdone);
>>   
>> -	if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
>> +	if (ee->engine_id != RCS || IS_GEN_LTE(m->i915, 3))
>>   		return;
>>   
>>   	err_printf(m, "  SC_INSTDONE: 0x%08x\n",
>>   		   ee->instdone.slice_common);
>>   
>> -	if (INTEL_GEN(m->i915) <= 6)
>> +	if (IS_GEN_LTE(m->i915, 6))
>>   		return;
>>   
>>   	for_each_instdone_slice_subslice(m->i915, slice, subslice)
>> @@ -455,7 +455,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
>>   			   upper_32_bits(start), lower_32_bits(start),
>>   			   upper_32_bits(end), lower_32_bits(end));
>>   	}
>> -	if (INTEL_GEN(m->i915) >= 4) {
>> +	if (IS_GEN_GTE(m->i915, 4)) {
>>   		err_printf(m, "  BBADDR: 0x%08x_%08x\n",
>>   			   (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
>>   		err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
>> @@ -464,7 +464,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
>>   	err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
>>   	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
>>   		   lower_32_bits(ee->faddr));
>> -	if (INTEL_GEN(m->i915) >= 6) {
>> +	if (IS_GEN_GTE(m->i915, 6)) {
>>   		err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
>>   		err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
>>   		err_printf(m, "  SYNC_0: 0x%08x\n",
>> @@ -478,7 +478,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
>>   	if (USES_PPGTT(m->i915)) {
>>   		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
>>   
>> -		if (INTEL_GEN(m->i915) >= 8) {
>> +		if (IS_GEN_GTE(m->i915, 8)) {
>>   			int i;
>>   			for (i = 0; i < 4; i++)
>>   				err_printf(m, "  PDP%d: 0x%016llx\n",
>> @@ -691,10 +691,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>>   	for (i = 0; i < error->nfence; i++)
>>   		err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +	if (IS_GEN_GTE(dev_priv, 6)) {
>>   		err_printf(m, "ERROR: 0x%08x\n", error->error);
>>   
>> -		if (INTEL_GEN(dev_priv) >= 8)
>> +		if (IS_GEN_GTE(dev_priv, 8))
>>   			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
>>   				   error->fault_data1, error->fault_data0);
>>   
>> @@ -1087,10 +1087,10 @@ static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
>>   {
>>   	int i;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +	if (IS_GEN_GTE(dev_priv, 6)) {
>>   		for (i = 0; i < dev_priv->num_fence_regs; i++)
>>   			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
>> -	} else if (INTEL_GEN(dev_priv) >= 4) {
>> +	} else if (IS_GEN_GTE(dev_priv, 4)) {
>>   		for (i = 0; i < dev_priv->num_fence_regs; i++)
>>   			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
>>   	} else {
>> @@ -1192,9 +1192,9 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>>   {
>>   	struct drm_i915_private *dev_priv = engine->i915;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +	if (IS_GEN_GTE(dev_priv, 6)) {
>>   		ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
>> -		if (INTEL_GEN(dev_priv) >= 8) {
>> +		if (IS_GEN_GTE(dev_priv, 8)) {
>>   			ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
>>   		} else {
>>   			gen6_record_semaphore_state(engine, ee);
>> @@ -1202,13 +1202,13 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>>   		}
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4) {
>> +	if (IS_GEN_GTE(dev_priv, 4)) {
>>   		ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
>>   		ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
>>   		ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
>>   		ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
>>   		ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
>> -		if (INTEL_GEN(dev_priv) >= 8) {
>> +		if (IS_GEN_GTE(dev_priv, 8)) {
>>   			ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
>>   			ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
>>   		}
>> @@ -1230,7 +1230,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>>   	ee->head = I915_READ_HEAD(engine);
>>   	ee->tail = I915_READ_TAIL(engine);
>>   	ee->ctl = I915_READ_CTL(engine);
>> -	if (INTEL_GEN(dev_priv) > 2)
>> +	if (IS_GEN_GT(dev_priv, 2))
>>   		ee->mode = I915_READ_MODE(engine);
>>   
>>   	if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
>> @@ -1280,7 +1280,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>>   		else if (IS_GEN7(dev_priv))
>>   			ee->vm_info.pp_dir_base =
>>   				I915_READ(RING_PP_DIR_BASE(engine));
>> -		else if (INTEL_GEN(dev_priv) >= 8)
>> +		else if (IS_GEN_GTE(dev_priv, 8))
>>   			for (i = 0; i < 4; i++) {
>>   				ee->vm_info.pdp[i] =
>>   					I915_READ(GEN8_RING_PDP_UDW(engine, i));
>> @@ -1647,7 +1647,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
>>   	if (IS_GEN7(dev_priv))
>>   		error->err_int = I915_READ(GEN7_ERR_INT);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8) {
>> +	if (IS_GEN_GTE(dev_priv, 8)) {
>>   		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
>>   		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
>>   	}
>> @@ -1659,16 +1659,16 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
>>   	}
>>   
>>   	/* 2: Registers which belong to multiple generations */
>> -	if (INTEL_GEN(dev_priv) >= 7)
>> +	if (IS_GEN_GTE(dev_priv, 7))
>>   		error->forcewake = I915_READ_FW(FORCEWAKE_MT);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +	if (IS_GEN_GTE(dev_priv, 6)) {
>>   		error->derrmr = I915_READ(DERRMR);
>>   		error->error = I915_READ(ERROR_GEN6);
>>   		error->done_reg = I915_READ(DONE_REG);
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 5)
>> +	if (IS_GEN_GTE(dev_priv, 5))
>>   		error->ccid = I915_READ(CCID);
>>   
>>   	/* 3: Feature specific registers */
>> @@ -1678,7 +1678,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
>>   	}
>>   
>>   	/* 4: Everything else */
>> -	if (INTEL_GEN(dev_priv) >= 8) {
>> +	if (IS_GEN_GTE(dev_priv, 8)) {
>>   		error->ier = I915_READ(GEN8_DE_MISC_IER);
>>   		for (i = 0; i < 4; i++)
>>   			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index b886bd459acc..f02d682a5ca9 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -308,17 +308,17 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
>>   
>>   static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
>>   {
>> -	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
>> +	return IS_GEN_GTE(dev_priv, 8) ? GEN8_GT_IIR(2) : GEN6_PMIIR;
>>   }
>>   
>>   static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
>>   {
>> -	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
>> +	return IS_GEN_GTE(dev_priv, 8) ? GEN8_GT_IMR(2) : GEN6_PMIMR;
>>   }
>>   
>>   static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
>>   {
>> -	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
>> +	return IS_GEN_GTE(dev_priv, 8) ? GEN8_GT_IER(2) : GEN6_PMIER;
>>   }
>>   
>>   /**
>> @@ -585,7 +585,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
>>   
>>   	lockdep_assert_held(&dev_priv->irq_lock);
>>   
>> -	if (INTEL_GEN(dev_priv) < 5)
>> +	if (IS_GEN_LT(dev_priv, 5))
>>   		goto out;
>>   
>>   	/*
>> @@ -676,7 +676,7 @@ static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
>>   	spin_lock_irq(&dev_priv->irq_lock);
>>   
>>   	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		i915_enable_pipestat(dev_priv, PIPE_A,
>>   				     PIPE_LEGACY_BLC_EVENT_STATUS);
>>   
>> @@ -947,7 +947,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
>>   	if (stime)
>>   		*stime = ktime_get();
>>   
>> -	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
>> +	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5)) {
>>   		/* No obvious pixelcount register. Only query vertical
>>   		 * scanout position from Display scan line register.
>>   		 */
>> @@ -1007,7 +1007,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
>>   	else
>>   		position += vtotal - vbl_end;
>>   
>> -	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
>> +	if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5)) {
>>   		*vpos = position;
>>   		*hpos = 0;
>>   	} else {
>> @@ -1652,7 +1652,7 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>   		 * don't trust that one either.
>>   		 */
>>   		if (pipe_crc->skipped == 0 ||
>> -		    (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
>> +		    (IS_GEN_GTE(dev_priv, 8) && pipe_crc->skipped == 1)) {
>>   			pipe_crc->skipped++;
>>   			spin_unlock(&pipe_crc->lock);
>>   			return;
>> @@ -1702,12 +1702,12 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>   {
>>   	uint32_t res1, res2;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 3)
>> +	if (IS_GEN_GTE(dev_priv, 3))
>>   		res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
>>   	else
>>   		res1 = 0;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
>> +	if (IS_GEN_GTE(dev_priv, 5) || IS_G4X(dev_priv))
>>   		res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
>>   	else
>>   		res2 = 0;
>> @@ -1736,7 +1736,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
>>   		spin_unlock(&dev_priv->irq_lock);
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> +	if (IS_GEN_GTE(dev_priv, 8))
>>   		return;
>>   
>>   	if (HAS_VEBOX(dev_priv)) {
>> @@ -2482,7 +2482,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
>>   	if (gt_iir) {
>>   		I915_WRITE(GTIIR, gt_iir);
>>   		ret = IRQ_HANDLED;
>> -		if (INTEL_GEN(dev_priv) >= 6)
>> +		if (IS_GEN_GTE(dev_priv, 6))
>>   			snb_gt_irq_handler(dev_priv, gt_iir);
>>   		else
>>   			ilk_gt_irq_handler(dev_priv, gt_iir);
>> @@ -2492,13 +2492,13 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
>>   	if (de_iir) {
>>   		I915_WRITE(DEIIR, de_iir);
>>   		ret = IRQ_HANDLED;
>> -		if (INTEL_GEN(dev_priv) >= 7)
>> +		if (IS_GEN_GTE(dev_priv, 7))
>>   			ivb_display_irq_handler(dev_priv, de_iir);
>>   		else
>>   			ilk_display_irq_handler(dev_priv, de_iir);
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +	if (IS_GEN_GTE(dev_priv, 6)) {
>>   		u32 pm_iir = I915_READ(GEN6_PMIIR);
>>   		if (pm_iir) {
>>   			I915_WRITE(GEN6_PMIIR, pm_iir);
>> @@ -2567,7 +2567,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>>   			ret = IRQ_HANDLED;
>>   
>>   			tmp_mask = GEN8_AUX_CHANNEL_A;
>> -			if (INTEL_GEN(dev_priv) >= 9)
>> +			if (IS_GEN_GTE(dev_priv, 9))
>>   				tmp_mask |= GEN9_AUX_CHANNEL_B |
>>   					    GEN9_AUX_CHANNEL_C |
>>   					    GEN9_AUX_CHANNEL_D;
>> @@ -2633,7 +2633,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>>   			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
>>   
>>   		fault_errors = iir;
>> -		if (INTEL_GEN(dev_priv) >= 9)
>> +		if (IS_GEN_GTE(dev_priv, 9))
>>   			fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
>>   		else
>>   			fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
>> @@ -2802,7 +2802,7 @@ static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
>>   	if (!IS_GEN2(dev_priv))
>>   		I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
>>   
>> -	if (INTEL_GEN(dev_priv) < 4)
>> +	if (IS_GEN_LT(dev_priv, 4))
>>   		I915_WRITE(IPEIR, I915_READ(IPEIR));
>>   	else
>>   		I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
>> @@ -2944,7 +2944,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
>>   {
>>   	struct drm_i915_private *dev_priv = to_i915(dev);
>>   	unsigned long irqflags;
>> -	uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
>> +	uint32_t bit = IS_GEN_GTE(dev_priv, 7) ?
>>   		DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
>>   
>>   	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>> @@ -2994,7 +2994,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
>>   {
>>   	struct drm_i915_private *dev_priv = to_i915(dev);
>>   	unsigned long irqflags;
>> -	uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
>> +	uint32_t bit = IS_GEN_GTE(dev_priv, 7) ?
>>   		DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
>>   
>>   	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>> @@ -3046,7 +3046,7 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
>>   static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
>>   {
>>   	GEN3_IRQ_RESET(GT);
>> -	if (INTEL_GEN(dev_priv) >= 6)
>> +	if (IS_GEN_GTE(dev_priv, 6))
>>   		GEN3_IRQ_RESET(GEN6_PM);
>>   }
>>   
>> @@ -3330,12 +3330,12 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
>>   {
>>   	u32 hotplug_irqs, enabled_irqs;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8) {
>> +	if (IS_GEN_GTE(dev_priv, 8)) {
>>   		hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
>>   		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
>>   
>>   		bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
>> -	} else if (INTEL_GEN(dev_priv) >= 7) {
>> +	} else if (IS_GEN_GTE(dev_priv, 7)) {
>>   		hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
>>   		enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
>>   
>> @@ -3448,7 +3448,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
>>   
>>   	GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +	if (IS_GEN_GTE(dev_priv, 6)) {
>>   		/*
>>   		 * RPS interrupts will get enabled/disabled on demand when RPS
>>   		 * itself is enabled/disabled.
>> @@ -3468,7 +3468,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
>>   	struct drm_i915_private *dev_priv = to_i915(dev);
>>   	u32 display_mask, extra_mask;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 7) {
>> +	if (IS_GEN_GTE(dev_priv, 7)) {
>>   		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
>>   				DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
>>   		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
>> @@ -3596,7 +3596,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>>   	u32 de_misc_masked = GEN8_DE_MISC_GSE;
>>   	enum pipe pipe;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
>>   		de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
>>   				  GEN9_AUX_CHANNEL_D;
>> @@ -4048,16 +4048,16 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>>   	 *
>>   	 * TODO: verify if this can be reproduced on VLV,CHV.
>>   	 */
>> -	if (INTEL_GEN(dev_priv) <= 7)
>> +	if (IS_GEN_LTE(dev_priv, 7))
>>   		rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> +	if (IS_GEN_GTE(dev_priv, 8))
>>   		rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
>>   
>>   	if (IS_GEN2(dev_priv)) {
>>   		/* Gen2 doesn't have a hardware frame counter */
>>   		dev->max_vblank_count = 0;
>> -	} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
>> +	} else if (IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5)) {
>>   		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
>>   		dev->driver->get_vblank_counter = g4x_get_vblank_counter;
>>   	} else {
>> @@ -4104,7 +4104,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>>   		dev->driver->enable_vblank = i965_enable_vblank;
>>   		dev->driver->disable_vblank = i965_disable_vblank;
>>   		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
>> -	} else if (INTEL_GEN(dev_priv) >= 8) {
>> +	} else if (IS_GEN_GTE(dev_priv, 8)) {
>>   		dev->driver->irq_handler = gen8_irq_handler;
>>   		dev->driver->irq_preinstall = gen8_irq_reset;
>>   		dev->driver->irq_postinstall = gen8_irq_postinstall;
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>> index f0cfdece14ae..d31605ebad69 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -3253,7 +3253,7 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
>>   		goto reg_err;
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) < 8) {
>> +	if (IS_GEN_LT(dev_priv, 8)) {
>>   		if (args->n_flex_regs != 0) {
>>   			err = -EINVAL;
>>   			goto reg_err;
>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
>> index a0f56925532e..7a99a2e7eeda 100644
>> --- a/drivers/gpu/drm/i915/i915_pmu.c
>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>> @@ -319,7 +319,7 @@ engine_event_status(struct intel_engine_cs *engine,
>>   	case I915_SAMPLE_WAIT:
>>   		break;
>>   	case I915_SAMPLE_SEMA:
>> -		if (INTEL_GEN(engine->i915) < 6)
>> +		if (IS_GEN_LT(engine->i915, 6))
>>   			return -ENODEV;
>>   		break;
>>   	default:
>> @@ -339,7 +339,7 @@ config_status(struct drm_i915_private *i915, u64 config)
>>   			return -ENODEV;
>>   		/* Fall-through. */
>>   	case I915_PMU_REQUESTED_FREQUENCY:
>> -		if (INTEL_GEN(i915) < 6)
>> +		if (IS_GEN_LT(i915, 6))
>>   			return -ENODEV;
>>   		break;
>>   	case I915_PMU_INTERRUPTS:
>> @@ -1005,7 +1005,7 @@ void i915_pmu_register(struct drm_i915_private *i915)
>>   {
>>   	int ret;
>>   
>> -	if (INTEL_GEN(i915) <= 2) {
>> +	if (IS_GEN_LTE(i915, 2)) {
>>   		DRM_INFO("PMU not supported for this GPU.");
>>   		return;
>>   	}
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index e9c79b560823..fd3948f1d44a 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3792,7 +3792,7 @@ enum i915_power_well_id {
>>   #define INTERVAL_1_28_US(us)	roundup(((us) * 100) >> 7, 25)
>>   #define INTERVAL_1_33_US(us)	(((us) * 3)   >> 2)
>>   #define INTERVAL_0_833_US(us)	(((us) * 6) / 5)
>> -#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
>> +#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN_GTE(dev_priv, 9) ? \
>>   				(IS_GEN9_LP(dev_priv) ? \
>>   				INTERVAL_0_833_US(us) : \
>>   				INTERVAL_1_33_US(us)) : \
>> @@ -3801,7 +3801,7 @@ enum i915_power_well_id {
>>   #define INTERVAL_1_28_TO_US(interval)  (((interval) << 7) / 100)
>>   #define INTERVAL_1_33_TO_US(interval)  (((interval) << 2) / 3)
>>   #define INTERVAL_0_833_TO_US(interval) (((interval) * 5)  / 6)
>> -#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
>> +#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN_GTE(dev_priv, 9) ? \
>>                              (IS_GEN9_LP(dev_priv) ? \
>>                              INTERVAL_0_833_TO_US(interval) : \
>>                              INTERVAL_1_33_TO_US(interval)) : \
>> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
>> index 8f3aa4dc0c98..afe8da487660 100644
>> --- a/drivers/gpu/drm/i915/i915_suspend.c
>> +++ b/drivers/gpu/drm/i915/i915_suspend.c
>> @@ -32,25 +32,25 @@
>>   static void i915_save_display(struct drm_i915_private *dev_priv)
>>   {
>>   	/* Display arbitration control */
>> -	if (INTEL_GEN(dev_priv) <= 4)
>> +	if (IS_GEN_LTE(dev_priv, 4))
>>   		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
>>   
>>   	/* save FBC interval */
>> -	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
>> +	if (HAS_FBC(dev_priv) && IS_GEN_LTE(dev_priv, 4) && !IS_G4X(dev_priv))
>>   		dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
>>   }
>>   
>>   static void i915_restore_display(struct drm_i915_private *dev_priv)
>>   {
>>   	/* Display arbitration */
>> -	if (INTEL_GEN(dev_priv) <= 4)
>> +	if (IS_GEN_LTE(dev_priv, 4))
>>   		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
>>   
>>   	/* only restore FBC info on the platform that supports FBC*/
>>   	intel_fbc_global_disable(dev_priv);
>>   
>>   	/* restore FBC interval */
>> -	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
>> +	if (HAS_FBC(dev_priv) && IS_GEN_LTE(dev_priv, 4) && !IS_G4X(dev_priv))
>>   		I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
>>   
>>   	i915_redisable_vga(dev_priv);
>> @@ -70,7 +70,7 @@ int i915_save_state(struct drm_i915_private *dev_priv)
>>   				     &dev_priv->regfile.saveGCDGMBUS);
>>   
>>   	/* Cache mode state */
>> -	if (INTEL_GEN(dev_priv) < 7)
>> +	if (IS_GEN_LT(dev_priv, 7))
>>   		dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
>>   
>>   	/* Memory Arbitration state */
>> @@ -114,7 +114,7 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
>>   	i915_restore_display(dev_priv);
>>   
>>   	/* Cache mode state */
>> -	if (INTEL_GEN(dev_priv) < 7)
>> +	if (IS_GEN_LT(dev_priv, 7))
>>   		I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
>>   			   0xffff0000);
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
>> index c74a20b80182..3d8fd58912cb 100644
>> --- a/drivers/gpu/drm/i915/i915_sysfs.c
>> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
>> @@ -611,7 +611,7 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
>>   	ret = 0;
>>   	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>   		ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
>> -	else if (INTEL_GEN(dev_priv) >= 6)
>> +	else if (IS_GEN_GTE(dev_priv, 6))
>>   		ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
>>   	if (ret)
>>   		DRM_ERROR("RPS sysfs setup failed\n");
>> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
>> index 0ee32275994a..e59a50b44e85 100644
>> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
>> @@ -172,7 +172,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>>   	 * Y-tiling is not supported in IF-ID Interlace mode in
>>   	 * GEN9 and above.
>>   	 */
>> -	if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
>> +	if (state->fb && IS_GEN_GTE(dev_priv, 9) && crtc_state->base.enable &&
>>   	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
>>   		if (state->fb->modifier == I915_FORMAT_MOD_Y_TILED ||
>>   		    state->fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
>> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
>> index ff455c724775..f8705138bf4a 100644
>> --- a/drivers/gpu/drm/i915/intel_audio.c
>> +++ b/drivers/gpu/drm/i915/intel_audio.c
>> @@ -704,7 +704,7 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>>   	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>>   		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
>>   		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
>> -	} else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
>> +	} else if (IS_HASWELL(dev_priv) || IS_GEN_GTE(dev_priv, 8)) {
>>   		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
>>   		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
>>   	} else if (HAS_PCH_SPLIT(dev_priv)) {
>> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
>> index aab6d1538fff..b13fb999340c 100644
>> --- a/drivers/gpu/drm/i915/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
>> @@ -1895,7 +1895,7 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
>>   static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
>>   				     int pixel_rate)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 10)
>> +	if (IS_GEN_GTE(dev_priv, 10))
>>   		return DIV_ROUND_UP(pixel_rate, 2);
>>   	else if (IS_GEMINILAKE(dev_priv))
>>   		/*
>> @@ -1950,7 +1950,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>>   	/* According to BSpec, "The CD clock frequency must be at least twice
>>   	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
>>   	 */
>> -	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
>> +	if (crtc_state->has_audio && IS_GEN_GTE(dev_priv, 9))
>>   		min_cdclk = max(2 * 96000, min_cdclk);
>>   
>>   	/*
>> @@ -2220,7 +2220,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>>   {
>>   	int max_cdclk_freq = dev_priv->max_cdclk_freq;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10)
>> +	if (IS_GEN_GTE(dev_priv, 10))
>>   		return 2 * max_cdclk_freq;
>>   	else if (IS_GEMINILAKE(dev_priv))
>>   		/*
>> @@ -2233,7 +2233,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>>   		return max_cdclk_freq;
>>   	else if (IS_CHERRYVIEW(dev_priv))
>>   		return max_cdclk_freq*95/100;
>> -	else if (INTEL_GEN(dev_priv) < 4)
>> +	else if (IS_GEN_LT(dev_priv, 4))
>>   		return 2*max_cdclk_freq*90/100;
>>   	else
>>   		return max_cdclk_freq*90/100;
>> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>> index aa66e952a95d..31c9a5b62297 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -222,7 +222,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
>>   	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
>>   	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
>>   
>> -	if (INTEL_GEN(dev_priv) > 6) {
>> +	if (IS_GEN_GT(dev_priv, 6)) {
>>   		uint16_t postoff = 0;
>>   
>>   		if (intel_crtc_state->limited_color_range)
>> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
>> index 1cd4a7c22bd5..871576790668 100644
>> --- a/drivers/gpu/drm/i915/intel_crt.c
>> +++ b/drivers/gpu/drm/i915/intel_crt.c
>> @@ -154,7 +154,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
>>   	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
>>   	u32 adpa;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 5)
>> +	if (IS_GEN_GTE(dev_priv, 5))
>>   		adpa = ADPA_HOTPLUG_BITS;
>>   	else
>>   		adpa = 0;
>> @@ -799,7 +799,7 @@ intel_crt_detect(struct drm_connector *connector,
>>   	if (ret > 0) {
>>   		if (intel_crt_detect_ddc(connector))
>>   			status = connector_status_connected;
>> -		else if (INTEL_GEN(dev_priv) < 4)
>> +		else if (IS_GEN_LT(dev_priv, 4))
>>   			status = intel_crt_load_detect(crt,
>>   				to_intel_crtc(connector->state->crtc)->pipe);
>>   		else if (i915_modparams.load_detect_test)
>> @@ -854,7 +854,7 @@ void intel_crt_reset(struct drm_encoder *encoder)
>>   	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
>>   	struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
>>   
>> -	if (INTEL_GEN(dev_priv) >= 5) {
>> +	if (IS_GEN_GTE(dev_priv, 5)) {
>>   		u32 adpa;
>>   
>>   		adpa = I915_READ(crt->adpa_reg);
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 8ca376aca8bd..5ae9cd02cd39 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -1458,7 +1458,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
>>   {
>>   	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>   
>> -	if (INTEL_GEN(dev_priv) <= 8)
>> +	if (IS_GEN_LTE(dev_priv, 8))
>>   		hsw_ddi_clock_get(encoder, pipe_config);
>>   	else if (IS_GEN9_BC(dev_priv))
>>   		skl_ddi_clock_get(encoder, pipe_config);
>> @@ -2152,7 +2152,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>>   
>>   		I915_WRITE(DPLL_CTRL2, val);
>>   
>> -	} else if (INTEL_GEN(dev_priv) < 9) {
>> +	} else if (IS_GEN_LT(dev_priv, 9)) {
>>   		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
>>   	}
>>   
>> @@ -2170,7 +2170,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
>>   	else if (IS_GEN9_BC(dev_priv))
>>   		I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
>>   			   DPLL_CTRL2_DDI_CLK_OFF(port));
>> -	else if (INTEL_GEN(dev_priv) < 9)
>> +	else if (IS_GEN_LT(dev_priv, 9))
>>   		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
>>   }
>>   
>> @@ -2207,7 +2207,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>>   	if (!is_mst)
>>   		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>>   	intel_dp_start_link_train(intel_dp);
>> -	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
>> +	if (port != PORT_A || IS_GEN_GTE(dev_priv, 9))
>>   		intel_dp_stop_link_train(intel_dp);
>>   }
>>   
>> @@ -2409,7 +2409,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
>>   	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>>   	enum port port = encoder->port;
>>   
>> -	if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
>> +	if (port == PORT_A && IS_GEN_LT(dev_priv, 9))
>>   		intel_dp_stop_link_train(intel_dp);
>>   
>>   	intel_edp_backlight_on(crtc_state, conn_state);
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index ae6f5b7b7978..068705c91332 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -380,7 +380,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>>   	u32 f19_2_mhz = 19200;
>>   	u32 f24_mhz = 24000;
>>   
>> -	if (INTEL_GEN(dev_priv) <= 4) {
>> +	if (IS_GEN_LTE(dev_priv, 4)) {
>>   		/* PRMs say:
>>   		 *
>>   		 *     "The value in this register increments once every 16
>> @@ -388,7 +388,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>>   		 *      (“CLKCFG”) MCHBAR register)
>>   		 */
>>   		return dev_priv->rawclk_freq / 16;
>> -	} else if (INTEL_GEN(dev_priv) <= 8) {
>> +	} else if (IS_GEN_LTE(dev_priv, 8)) {
>>   		/* PRMs say:
>>   		 *
>>   		 *     "The PCU TSC counts 10ns increments; this timestamp
>> @@ -396,7 +396,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>>   		 *      rolling over every 1.5 hours).
>>   		 */
>>   		return f12_5_mhz;
>> -	} else if (INTEL_GEN(dev_priv) <= 9) {
>> +	} else if (IS_GEN_LTE(dev_priv, 9)) {
>>   		u32 ctc_reg = I915_READ(CTC_MODE);
>>   		u32 freq = 0;
>>   
>> @@ -414,7 +414,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>>   		}
>>   
>>   		return freq;
>> -	} else if (INTEL_GEN(dev_priv) <= 10) {
>> +	} else if (IS_GEN_LTE(dev_priv, 10)) {
>>   		u32 ctc_reg = I915_READ(CTC_MODE);
>>   		u32 freq = 0;
>>   		u32 rpm_config_reg = 0;
>> @@ -480,7 +480,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>>   		container_of(info, struct drm_i915_private, info);
>>   	enum pipe pipe;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10) {
>> +	if (IS_GEN_GTE(dev_priv, 10)) {
>>   		for_each_pipe(dev_priv, pipe)
>>   			info->num_scalers[pipe] = 2;
>>   	} else if (IS_GEN9(dev_priv)) {
>> @@ -507,7 +507,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>>   	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>>   		for_each_pipe(dev_priv, pipe)
>>   			info->num_sprites[pipe] = 2;
>> -	} else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
>> +	} else if (IS_GEN_GTE(dev_priv, 5) || IS_G4X(dev_priv)) {
>>   		for_each_pipe(dev_priv, pipe)
>>   			info->num_sprites[pipe] = 1;
>>   	}
>> @@ -580,7 +580,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>>   		broadwell_sseu_info_init(dev_priv);
>>   	else if (IS_GEN9(dev_priv))
>>   		gen9_sseu_info_init(dev_priv);
>> -	else if (INTEL_GEN(dev_priv) >= 10)
>> +	else if (IS_GEN_GTE(dev_priv, 10))
>>   		gen10_sseu_info_init(dev_priv);
>>   
>>   	/* Initialize command stream timestamp frequency */
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 0d5207dbfdac..00efc4e6b7ce 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -1044,7 +1044,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
>>   	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
>>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4) {
>> +	if (IS_GEN_GTE(dev_priv, 4)) {
>>   		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>>   		i915_reg_t reg = PIPECONF(cpu_transcoder);
>>   
>> @@ -1542,7 +1542,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
>>   	POSTING_READ(reg);
>>   	udelay(150);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4) {
>> +	if (IS_GEN_GTE(dev_priv, 4)) {
>>   		I915_WRITE(DPLL_MD(crtc->pipe),
>>   			   crtc_state->dpll_hw_state.dpll_md);
>>   	} else {
>> @@ -2029,12 +2029,12 @@ static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_pr
>>   
>>   static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		return 256 * 1024;
>>   	else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
>>   		 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>   		return 128 * 1024;
>> -	else if (INTEL_GEN(dev_priv) >= 4)
>> +	else if (IS_GEN_GTE(dev_priv, 4))
>>   		return 4 * 1024;
>>   	else
>>   		return 0;
>> @@ -2053,7 +2053,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>>   	case DRM_FORMAT_MOD_LINEAR:
>>   		return intel_linear_alignment(dev_priv);
>>   	case I915_FORMAT_MOD_X_TILED:
>> -		if (INTEL_GEN(dev_priv) >= 9)
>> +		if (IS_GEN_GTE(dev_priv, 9))
>>   			return 256 * 1024;
>>   		return 0;
>>   	case I915_FORMAT_MOD_Y_TILED_CCS:
>> @@ -3163,7 +3163,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
>>   	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>>   		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>>   
>> -	if (INTEL_GEN(dev_priv) < 4)
>> +	if (IS_GEN_LT(dev_priv, 4))
>>   		dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
>>   
>>   	switch (fb->format->format) {
>> @@ -3193,7 +3193,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
>>   		return 0;
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4 &&
>> +	if (IS_GEN_GTE(dev_priv, 4) &&
>>   	    fb->modifier == I915_FORMAT_MOD_X_TILED)
>>   		dspcntr |= DISPPLANE_TILED;
>>   
>> @@ -3216,7 +3216,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
>>   
>>   	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		offset = intel_compute_tile_offset(&src_x, &src_y,
>>   						   plane_state, 0);
>>   	else
>> @@ -3260,14 +3260,14 @@ static void i9xx_update_plane(struct intel_plane *plane,
>>   
>>   	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		dspaddr_offset = plane_state->main.offset;
>>   	else
>>   		dspaddr_offset = linear_offset;
>>   
>>   	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>>   
>> -	if (INTEL_GEN(dev_priv) < 4) {
>> +	if (IS_GEN_LT(dev_priv, 4)) {
>>   		/* pipesrc and dspsize control the size that is scaled from,
>>   		 * which should always be the user's requested size.
>>   		 */
>> @@ -3291,7 +3291,7 @@ static void i9xx_update_plane(struct intel_plane *plane,
>>   			      intel_plane_ggtt_offset(plane_state) +
>>   			      dspaddr_offset);
>>   		I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x);
>> -	} else if (INTEL_GEN(dev_priv) >= 4) {
>> +	} else if (IS_GEN_GTE(dev_priv, 4)) {
>>   		I915_WRITE_FW(DSPSURF(i9xx_plane),
>>   			      intel_plane_ggtt_offset(plane_state) +
>>   			      dspaddr_offset);
>> @@ -3317,7 +3317,7 @@ static void i9xx_disable_plane(struct intel_plane *plane,
>>   	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>>   
>>   	I915_WRITE_FW(DSPCNTR(i9xx_plane), 0);
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		I915_WRITE_FW(DSPSURF(i9xx_plane), 0);
>>   	else
>>   		I915_WRITE_FW(DSPADDR(i9xx_plane), 0);
>> @@ -3538,7 +3538,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>>   
>>   	plane_ctl = PLANE_CTL_ENABLE;
>>   
>> -	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
>> +	if (IS_GEN_LT(dev_priv, 10) && !IS_GEMINILAKE(dev_priv)) {
>>   		plane_ctl |= skl_plane_ctl_alpha(fb->format->format);
>>   		plane_ctl |=
>>   			PLANE_CTL_PIPE_GAMMA_ENABLE |
>> @@ -3550,7 +3550,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>>   	plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
>>   	plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10)
>> +	if (IS_GEN_GTE(dev_priv, 10))
>>   		plane_ctl |= cnl_plane_ctl_flip(rotation &
>>   						DRM_MODE_REFLECT_MASK);
>>   
>> @@ -3618,7 +3618,7 @@ __intel_display_resume(struct drm_device *dev,
>>   static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
>>   {
>>   	return intel_has_gpu_reset(dev_priv) &&
>> -		INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
>> +		IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv);
>>   }
>>   
>>   void intel_prepare_reset(struct drm_i915_private *dev_priv)
>> @@ -3757,7 +3757,7 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
>>   		   (new_crtc_state->pipe_src_h - 1));
>>   
>>   	/* on skylake this is done by detaching scalers */
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		skl_detach_scalers(crtc);
>>   
>>   		if (new_crtc_state->pch_pfit.enabled)
>> @@ -4683,7 +4683,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>>   	 * Once NV12 is enabled, handle it here while allocating scaler
>>   	 * for NV12.
>>   	 */
>> -	if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
>> +	if (IS_GEN_GTE(dev_priv, 9) && crtc_state->base.enable &&
>>   	    need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
>>   		DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n");
>>   		return -EINVAL;
>> @@ -5477,7 +5477,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>>   	if (psl_clkgate_wa)
>>   		glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		skylake_pfit_enable(intel_crtc);
>>   	else
>>   		ironlake_pfit_enable(intel_crtc);
>> @@ -5623,7 +5623,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
>>   	if (!transcoder_is_dsi(cpu_transcoder))
>>   		intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		skylake_scaler_disable(intel_crtc);
>>   	else
>>   		ironlake_pfit_disable(intel_crtc, false);
>> @@ -6307,7 +6307,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
>>   	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>   
>>   	/* GDG double wide on either pipe, otherwise pipe A only */
>> -	return INTEL_GEN(dev_priv) < 4 &&
>> +	return IS_GEN_LT(dev_priv, 4) &&
>>   		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
>>   }
>>   
>> @@ -6367,7 +6367,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>>   	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
>>   	int clock_limit = dev_priv->max_dotclk_freq;
>>   
>> -	if (INTEL_GEN(dev_priv) < 4) {
>> +	if (IS_GEN_LT(dev_priv, 4)) {
>>   		clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
>>   
>>   		/*
>> @@ -6420,7 +6420,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>>   	/* Cantiga+ cannot handle modes with a hsync front porch of 0.
>>   	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
>>   	 */
>> -	if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
>> +	if ((IS_GEN_GT(dev_priv, 4) || IS_G4X(dev_priv)) &&
>>   		adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
>>   		return -EINVAL;
>>   
>> @@ -6577,7 +6577,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>>   	int pipe = crtc->pipe;
>>   	enum transcoder transcoder = crtc->config->cpu_transcoder;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 5) {
>> +	if (IS_GEN_GTE(dev_priv, 5)) {
>>   		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
>>   		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
>>   		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
>> @@ -6587,7 +6587,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
>>   		 * registers are not unnecessarily accessed).
>>   		 */
>>   		if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
>> -		    INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
>> +		    IS_GEN_LT(dev_priv, 8)) && crtc->config->has_drrs) {
>>   			I915_WRITE(PIPE_DATA_M2(transcoder),
>>   					TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
>>   			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
>> @@ -6971,7 +6971,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
>>   		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
>>   		break;
>>   	}
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
>>   
>>   	if (crtc_state->sdvo_tv_clock)
>> @@ -6985,7 +6985,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
>>   	dpll |= DPLL_VCO_ENABLE;
>>   	crtc_state->dpll_hw_state.dpll = dpll;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4) {
>> +	if (IS_GEN_GTE(dev_priv, 4)) {
>>   		u32 dpll_md = (crtc_state->pixel_multiplier - 1)
>>   			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
>>   		crtc_state->dpll_hw_state.dpll_md = dpll_md;
>> @@ -7058,7 +7058,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
>>   			vsyncshift += adjusted_mode->crtc_htotal;
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) > 3)
>> +	if (IS_GEN_GT(dev_priv, 3))
>>   		I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
>>   
>>   	I915_WRITE(HTOTAL(cpu_transcoder),
>> @@ -7217,7 +7217,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>>   	}
>>   
>>   	if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
>> -		if (INTEL_GEN(dev_priv) < 4 ||
>> +		if (IS_GEN_LT(dev_priv, 4) ||
>>   		    intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
>>   			pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
>>   		else
>> @@ -7428,7 +7428,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
>>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>   	uint32_t tmp;
>>   
>> -	if (INTEL_GEN(dev_priv) <= 3 &&
>> +	if (IS_GEN_LTE(dev_priv, 3) &&
>>   	    (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
>>   		return;
>>   
>> @@ -7437,7 +7437,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
>>   		return;
>>   
>>   	/* Check whether the pfit is attached to our pipe. */
>> -	if (INTEL_GEN(dev_priv) < 4) {
>> +	if (IS_GEN_LT(dev_priv, 4)) {
>>   		if (crtc->pipe != PIPE_B)
>>   			return;
>>   	} else {
>> @@ -7506,7 +7506,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>>   
>>   	val = I915_READ(DSPCNTR(i9xx_plane));
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4) {
>> +	if (IS_GEN_GTE(dev_priv, 4)) {
>>   		if (val & DISPPLANE_TILED) {
>>   			plane_config->tiling = I915_TILING_X;
>>   			fb->modifier = I915_FORMAT_MOD_X_TILED;
>> @@ -7520,7 +7520,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>>   	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>>   		offset = I915_READ(DSPOFFSET(i9xx_plane));
>>   		base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000;
>> -	} else if (INTEL_GEN(dev_priv) >= 4) {
>> +	} else if (IS_GEN_GTE(dev_priv, 4)) {
>>   		if (plane_config->tiling)
>>   			offset = I915_READ(DSPTILEOFF(i9xx_plane));
>>   		else
>> @@ -7626,7 +7626,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>>   	    (tmp & PIPECONF_COLOR_RANGE_SELECT))
>>   		pipe_config->limited_color_range = true;
>>   
>> -	if (INTEL_GEN(dev_priv) < 4)
>> +	if (IS_GEN_LT(dev_priv, 4))
>>   		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
>>   
>>   	intel_get_pipe_timings(crtc, pipe_config);
>> @@ -7634,7 +7634,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>>   
>>   	i9xx_get_pfit_config(crtc, pipe_config);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4) {
>> +	if (IS_GEN_GTE(dev_priv, 4)) {
>>   		/* No way to read it out on pipes B and C */
>>   		if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
>>   			tmp = dev_priv->chv_dpll_md[crtc->pipe];
>> @@ -8194,7 +8194,7 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
>>   	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>   	struct intel_crtc_state *config = intel_crtc->config;
>>   
>> -	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_BROADWELL(dev_priv) || IS_GEN_GTE(dev_priv, 9)) {
>>   		u32 val = 0;
>>   
>>   		switch (intel_crtc->config->pipe_bpp) {
>> @@ -8425,7 +8425,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
>>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>   	enum pipe pipe = crtc->pipe;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 5) {
>> +	if (IS_GEN_GTE(dev_priv, 5)) {
>>   		m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
>>   		m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
>>   		m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
>> @@ -8437,7 +8437,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
>>   		 * gen < 8) and if DRRS is supported (to make sure the
>>   		 * registers are not unnecessarily read).
>>   		 */
>> -		if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
>> +		if (m2_n2 && IS_GEN_LT(dev_priv, 8) &&
>>   			crtc->config->has_drrs) {
>>   			m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
>>   			m2_n2->link_n =	I915_READ(PIPE_LINK_N2(transcoder));
>> @@ -8536,12 +8536,12 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>>   
>>   	val = I915_READ(PLANE_CTL(pipe, plane_id));
>>   
>> -	if (INTEL_GEN(dev_priv) >= 11)
>> +	if (IS_GEN_GTE(dev_priv, 11))
>>   		pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
>>   	else
>>   		pixel_format = val & PLANE_CTL_FORMAT_MASK;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>> +	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) {
>>   		alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
>>   		alpha &= PLANE_COLOR_ALPHA_MASK;
>>   	} else {
>> @@ -9188,7 +9188,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>>   	 * DDI E. So just check whether this pipe is wired to DDI E and whether
>>   	 * the PCH transcoder is on.
>>   	 */
>> -	if (INTEL_GEN(dev_priv) < 9 &&
>> +	if (IS_GEN_LT(dev_priv, 9) &&
>>   	    (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
>>   		pipe_config->has_pch_encoder = true;
>>   
>> @@ -9238,11 +9238,11 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>>   	pipe_config->gamma_mode =
>>   		I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
>>   
>> -	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_BROADWELL(dev_priv) || IS_GEN_GTE(dev_priv, 9)) {
>>   		u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
>>   		bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;
>>   
>> -		if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
>> +		if (IS_GEMINILAKE(dev_priv) || IS_GEN_GTE(dev_priv, 10)) {
>>   			bool blend_mode_420 = tmp &
>>   					      PIPEMISC_YUV420_MODE_FULL_BLEND;
>>   
>> @@ -9258,7 +9258,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>>   	power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
>>   	if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
>>   		power_domain_mask |= BIT_ULL(power_domain);
>> -		if (INTEL_GEN(dev_priv) >= 9)
>> +		if (IS_GEN_GTE(dev_priv, 9))
>>   			skylake_get_pfit_config(crtc, pipe_config);
>>   		else
>>   			ironlake_get_pfit_config(crtc, pipe_config);
>> @@ -10227,7 +10227,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
>>   	struct drm_framebuffer *fb = plane_state->fb;
>>   	int ret;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
>> +	if (IS_GEN_GTE(dev_priv, 9) && plane->id != PLANE_CURSOR) {
>>   		ret = skl_update_scaler_plane(
>>   			to_intel_crtc_state(crtc_state),
>>   			to_intel_plane_state(plane_state));
>> @@ -10276,21 +10276,21 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
>>   			 turn_off, turn_on, mode_changed);
>>   
>>   	if (turn_on) {
>> -		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
>> +		if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv))
>>   			pipe_config->update_wm_pre = true;
>>   
>>   		/* must disable cxsr around plane enable/disable */
>>   		if (plane->id != PLANE_CURSOR)
>>   			pipe_config->disable_cxsr = true;
>>   	} else if (turn_off) {
>> -		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
>> +		if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv))
>>   			pipe_config->update_wm_post = true;
>>   
>>   		/* must disable cxsr around plane enable/disable */
>>   		if (plane->id != PLANE_CURSOR)
>>   			pipe_config->disable_cxsr = true;
>>   	} else if (intel_wm_need_update(&plane->base, plane_state)) {
>> -		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
>> +		if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv)) {
>>   			/* FIXME bollocks */
>>   			pipe_config->update_wm_pre = true;
>>   			pipe_config->update_wm_post = true;
>> @@ -10407,11 +10407,11 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
>>   			return ret;
>>   		}
>>   	} else if (dev_priv->display.compute_intermediate_wm) {
>> -		if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
>> +		if (HAS_PCH_SPLIT(dev_priv) && IS_GEN_LT(dev_priv, 9))
>>   			pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		if (mode_changed)
>>   			ret = skl_update_scaler_crtc(pipe_config);
>>   
>> @@ -10499,7 +10499,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
>>   	if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
>>   	    IS_CHERRYVIEW(dev_priv)))
>>   		bpp = 10*3;
>> -	else if (INTEL_GEN(dev_priv) >= 5)
>> +	else if (IS_GEN_GTE(dev_priv, 5))
>>   		bpp = 12*3;
>>   	else
>>   		bpp = 8*3;
>> @@ -10641,7 +10641,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
>>   		      pipe_config->pipe_src_w, pipe_config->pipe_src_h,
>>   		      pipe_config->pixel_rate);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
>>   			      crtc->num_scalers,
>>   			      pipe_config->scaler_state.scaler_users,
>> @@ -10682,7 +10682,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
>>   			      plane->base.id, plane->name,
>>   			      fb->base.id, fb->width, fb->height,
>>   			      drm_get_format_name(fb->format->format, &format_name));
>> -		if (INTEL_GEN(dev_priv) >= 9)
>> +		if (IS_GEN_GTE(dev_priv, 9))
>>   			DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
>>   				      state->scaler_id,
>>   				      state->base.src.x1 >> 16,
>> @@ -11167,7 +11167,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>>   	PIPE_CONF_CHECK_I(lane_count);
>>   	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
>>   
>> -	if (INTEL_GEN(dev_priv) < 8) {
>> +	if (IS_GEN_LT(dev_priv, 8)) {
>>   		PIPE_CONF_CHECK_M_N(dp_m_n);
>>   
>>   		if (current_config->has_drrs)
>> @@ -11193,7 +11193,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>>   
>>   	PIPE_CONF_CHECK_I(pixel_multiplier);
>>   	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
>> -	if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
>> +	if ((IS_GEN_LT(dev_priv, 8) && !IS_HASWELL(dev_priv)) ||
>>   	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>   		PIPE_CONF_CHECK_BOOL(limited_color_range);
>>   
>> @@ -11220,7 +11220,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>>   
>>   	PIPE_CONF_CHECK_X(gmch_pfit.control);
>>   	/* pfit ratios are autocomputed by the hw on gen4+ */
>> -	if (INTEL_GEN(dev_priv) < 4)
>> +	if (IS_GEN_LT(dev_priv, 4))
>>   		PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
>>   	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
>>   
>> @@ -11266,7 +11266,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>>   	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
>>   	PIPE_CONF_CHECK_X(dsi_pll.div);
>>   
>> -	if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
>> +	if (IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5))
>>   		PIPE_CONF_CHECK_I(pipe_bpp);
>>   
>>   	PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
>> @@ -11316,7 +11316,7 @@ static void verify_wm_state(struct drm_crtc *crtc,
>>   	const enum pipe pipe = intel_crtc->pipe;
>>   	int plane, level, max_level = ilk_wm_max_level(dev_priv);
>>   
>> -	if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
>> +	if (IS_GEN_LT(dev_priv, 9) || !new_state->active)
>>   		return;
>>   
>>   	skl_pipe_wm_get_hw_state(crtc, &hw_wm);
>> @@ -12293,7 +12293,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
>>   				 *
>>   				 * No clue what this is supposed to achieve.
>>   				 */
>> -				if (INTEL_GEN(dev_priv) >= 9)
>> +				if (IS_GEN_GTE(dev_priv, 9))
>>   					dev_priv->display.initial_watermarks(intel_state,
>>   									     to_intel_crtc_state(new_crtc_state));
>>   			}
>> @@ -12485,7 +12485,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>>   	 * FIXME doing watermarks and fb cleanup from a vblank worker
>>   	 * (assuming we had any) would solve these problems.
>>   	 */
>> -	if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
>> +	if (IS_GEN_LT(dev_priv, 9) && state->legacy_cursor_update) {
>>   		struct intel_crtc_state *new_crtc_state;
>>   		struct intel_crtc *crtc;
>>   		int i;
>> @@ -12592,7 +12592,7 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
>>   	if (!dma_fence_is_i915(fence))
>>   		return;
>>   
>> -	if (INTEL_GEN(to_i915(crtc->dev)) < 6)
>> +	if (IS_GEN_LT(to_i915(crtc->dev), 6))
>>   		return;
>>   
>>   	if (drm_crtc_vblank_get(crtc))
>> @@ -12770,7 +12770,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
>>   	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
>>   	max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
>>   
>> -	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>> +	if (IS_GEMINILAKE(dev_priv) || IS_GEN_GTE(dev_priv, 10))
>>   		max_dotclk *= 2;
>>   
>>   	if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
>> @@ -12801,7 +12801,7 @@ intel_check_primary_plane(struct intel_plane *plane,
>>   	struct drm_rect clip = {};
>>   	int ret;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		/* use scaler when colorkey is not required */
>>   		if (!state->ckey.flags) {
>>   			min_scale = 1;
>> @@ -12825,7 +12825,7 @@ intel_check_primary_plane(struct intel_plane *plane,
>>   	if (!state->base.fb)
>>   		return 0;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		ret = skl_check_plane_surface(crtc_state, state);
>>   		if (ret)
>>   			return ret;
>> @@ -12839,7 +12839,7 @@ intel_check_primary_plane(struct intel_plane *plane,
>>   		state->ctl = i9xx_plane_ctl(crtc_state, state);
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> +	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
>>   		state->color_ctl = glk_plane_color_ctl(crtc_state, state);
>>   
>>   	return 0;
>> @@ -12874,7 +12874,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
>>   
>>   	if (intel_cstate->update_pipe)
>>   		intel_update_pipe_config(old_intel_cstate, intel_cstate);
>> -	else if (INTEL_GEN(dev_priv) >= 9)
>> +	else if (IS_GEN_GTE(dev_priv, 9))
>>   		skl_detach_scalers(intel_crtc);
>>   
>>   out:
>> @@ -12998,9 +12998,9 @@ static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane,
>>   	    modifier != DRM_FORMAT_MOD_LINEAR)
>>   		return false;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		return skl_mod_supported(format, modifier);
>> -	else if (INTEL_GEN(dev_priv) >= 4)
>> +	else if (IS_GEN_GTE(dev_priv, 4))
>>   		return i965_mod_supported(format, modifier);
>>   	else
>>   		return i8xx_mod_supported(format, modifier);
>> @@ -13197,7 +13197,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>>   
>>   	primary->can_scale = false;
>>   	primary->max_downscale = 1;
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		primary->can_scale = true;
>>   		state->scaler_id = -1;
>>   	}
>> @@ -13206,7 +13206,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>>   	 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
>>   	 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
>>   	 */
>> -	if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
>> +	if (HAS_FBC(dev_priv) && IS_GEN_LT(dev_priv, 4))
>>   		primary->i9xx_plane = (enum i9xx_plane_id) !pipe;
>>   	else
>>   		primary->i9xx_plane = (enum i9xx_plane_id) pipe;
>> @@ -13214,7 +13214,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>>   	primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
>>   	primary->check_plane = intel_check_primary_plane;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		intel_primary_formats = skl_primary_formats;
>>   		num_formats = ARRAY_SIZE(skl_primary_formats);
>>   
>> @@ -13226,7 +13226,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>>   		primary->update_plane = skl_update_plane;
>>   		primary->disable_plane = skl_disable_plane;
>>   		primary->get_hw_state = skl_plane_get_hw_state;
>> -	} else if (INTEL_GEN(dev_priv) >= 4) {
>> +	} else if (IS_GEN_GTE(dev_priv, 4)) {
>>   		intel_primary_formats = i965_primary_formats;
>>   		num_formats = ARRAY_SIZE(i965_primary_formats);
>>   		modifiers = i9xx_format_modifiers;
>> @@ -13244,14 +13244,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>>   		primary->get_hw_state = i9xx_plane_get_hw_state;
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
>>   					       0, &intel_plane_funcs,
>>   					       intel_primary_formats, num_formats,
>>   					       modifiers,
>>   					       DRM_PLANE_TYPE_PRIMARY,
>>   					       "plane 1%c", pipe_name(pipe));
>> -	else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
>> +	else if (IS_GEN_GTE(dev_priv, 5) || IS_G4X(dev_priv))
>>   		ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
>>   					       0, &intel_plane_funcs,
>>   					       intel_primary_formats, num_formats,
>> @@ -13269,12 +13269,12 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>>   	if (ret)
>>   		goto fail;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10) {
>> +	if (IS_GEN_GTE(dev_priv, 10)) {
>>   		supported_rotations =
>>   			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
>>   			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270 |
>>   			DRM_MODE_REFLECT_X;
>> -	} else if (INTEL_GEN(dev_priv) >= 9) {
>> +	} else if (IS_GEN_GTE(dev_priv, 9)) {
>>   		supported_rotations =
>>   			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
>>   			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
>> @@ -13282,14 +13282,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>>   		supported_rotations =
>>   			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
>>   			DRM_MODE_REFLECT_X;
>> -	} else if (INTEL_GEN(dev_priv) >= 4) {
>> +	} else if (IS_GEN_GTE(dev_priv, 4)) {
>>   		supported_rotations =
>>   			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
>>   	} else {
>>   		supported_rotations = DRM_MODE_ROTATE_0;
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		drm_plane_create_rotation_property(&primary->base,
>>   						   DRM_MODE_ROTATE_0,
>>   						   supported_rotations);
>> @@ -13362,13 +13362,13 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
>>   	if (ret)
>>   		goto fail;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		drm_plane_create_rotation_property(&cursor->base,
>>   						   DRM_MODE_ROTATE_0,
>>   						   DRM_MODE_ROTATE_0 |
>>   						   DRM_MODE_ROTATE_180);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		state->scaler_id = -1;
>>   
>>   	drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
>> @@ -13548,7 +13548,7 @@ static bool has_edp_a(struct drm_i915_private *dev_priv)
>>   
>>   static bool intel_crt_present(struct drm_i915_private *dev_priv)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		return false;
>>   
>>   	if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
>> @@ -13929,7 +13929,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>>   		/* fall through */
>>   	case I915_FORMAT_MOD_Y_TILED:
>>   	case I915_FORMAT_MOD_Yf_TILED:
>> -		if (INTEL_GEN(dev_priv) < 9) {
>> +		if (IS_GEN_LT(dev_priv, 9)) {
>>   			DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
>>   				      mode_cmd->modifier[0]);
>>   			goto err;
>> @@ -13947,7 +13947,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>>   	 * gen2/3 display engine uses the fence if present,
>>   	 * so the tiling mode must match the fb modifier exactly.
>>   	 */
>> -	if (INTEL_GEN(dev_priv) < 4 &&
>> +	if (IS_GEN_LT(dev_priv, 4) &&
>>   	    tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
>>   		DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
>>   		goto err;
>> @@ -13981,7 +13981,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>>   	case DRM_FORMAT_ARGB8888:
>>   		break;
>>   	case DRM_FORMAT_XRGB1555:
>> -		if (INTEL_GEN(dev_priv) > 3) {
>> +		if (IS_GEN_GT(dev_priv, 3)) {
>>   			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>>   				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
>>   			goto err;
>> @@ -13989,7 +13989,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>>   		break;
>>   	case DRM_FORMAT_ABGR8888:
>>   		if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
>> -		    INTEL_GEN(dev_priv) < 9) {
>> +		    IS_GEN_LT(dev_priv, 9)) {
>>   			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>>   				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
>>   			goto err;
>> @@ -13998,7 +13998,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>>   	case DRM_FORMAT_XBGR8888:
>>   	case DRM_FORMAT_XRGB2101010:
>>   	case DRM_FORMAT_XBGR2101010:
>> -		if (INTEL_GEN(dev_priv) < 4) {
>> +		if (IS_GEN_LT(dev_priv, 4)) {
>>   			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>>   				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
>>   			goto err;
>> @@ -14015,7 +14015,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>>   	case DRM_FORMAT_UYVY:
>>   	case DRM_FORMAT_YVYU:
>>   	case DRM_FORMAT_VYUY:
>> -		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
>> +		if (IS_GEN_LT(dev_priv, 5) && !IS_G4X(dev_priv)) {
>>   			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>>   				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
>>   			goto err;
>> @@ -14162,7 +14162,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>>   {
>>   	intel_init_cdclk_hooks(dev_priv);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
>>   		dev_priv->display.get_initial_plane_config =
>>   			skylake_get_initial_plane_config;
>> @@ -14241,7 +14241,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>>   		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		dev_priv->display.update_crtcs = skl_update_crtcs;
>>   	else
>>   		dev_priv->display.update_crtcs = intel_update_crtcs;
>> @@ -14774,7 +14774,7 @@ intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
>>   {
>>   	struct intel_crtc *crtc;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		return;
>>   
>>   	for_each_intel_crtc(&dev_priv->drm, crtc) {
>> @@ -15210,7 +15210,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
>>   	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>>   		vlv_wm_get_hw_state(dev);
>>   		vlv_wm_sanitize(dev_priv);
>> -	} else if (INTEL_GEN(dev_priv) >= 9) {
>> +	} else if (IS_GEN_GTE(dev_priv, 9)) {
>>   		skl_wm_get_hw_state(dev);
>>   	} else if (HAS_PCH_SPLIT(dev_priv)) {
>>   		ilk_wm_get_hw_state(dev);
>> @@ -15361,7 +15361,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector,
>>    */
>>   int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
>>   {
>> -	unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
>> +	unsigned reg = IS_GEN_GTE(dev_priv, 6) ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
>>   	u16 gmch_ctrl;
>>   
>>   	if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
>> @@ -15467,13 +15467,13 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
>>   
>>   		error->plane[i].control = I915_READ(DSPCNTR(i));
>>   		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
>> -		if (INTEL_GEN(dev_priv) <= 3) {
>> +		if (IS_GEN_LTE(dev_priv, 3)) {
>>   			error->plane[i].size = I915_READ(DSPSIZE(i));
>>   			error->plane[i].pos = I915_READ(DSPPOS(i));
>>   		}
>> -		if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
>> +		if (IS_GEN_LTE(dev_priv, 7) && !IS_HASWELL(dev_priv))
>>   			error->plane[i].addr = I915_READ(DSPADDR(i));
>> -		if (INTEL_GEN(dev_priv) >= 4) {
>> +		if (IS_GEN_GTE(dev_priv, 4)) {
>>   			error->plane[i].surface = I915_READ(DSPSURF(i));
>>   			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
>>   		}
>> @@ -15538,13 +15538,13 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
>>   		err_printf(m, "Plane [%d]:\n", i);
>>   		err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
>>   		err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
>> -		if (INTEL_GEN(dev_priv) <= 3) {
>> +		if (IS_GEN_LTE(dev_priv, 3)) {
>>   			err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
>>   			err_printf(m, "  POS: %08x\n", error->plane[i].pos);
>>   		}
>> -		if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
>> +		if (IS_GEN_LTE(dev_priv, 7) && !IS_HASWELL(dev_priv))
>>   			err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
>> -		if (INTEL_GEN(dev_priv) >= 4) {
>> +		if (IS_GEN_GTE(dev_priv, 4)) {
>>   			err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
>>   			err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
>>   		}
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index abbe1e4e0af5..319d0d00f4ca 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1467,7 +1467,7 @@ static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
>>   static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
>>   				    enum port port)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		return skl_aux_ctl_reg(dev_priv, port);
>>   	else if (HAS_PCH_SPLIT(dev_priv))
>>   		return ilk_aux_ctl_reg(dev_priv, port);
>> @@ -1478,7 +1478,7 @@ static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
>>   static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
>>   				     enum port port, int index)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		return skl_aux_data_reg(dev_priv, port, index);
>>   	else if (HAS_PCH_SPLIT(dev_priv))
>>   		return ilk_aux_data_reg(dev_priv, port, index);
>> @@ -1726,7 +1726,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>>   
>>   		intel_fixed_panel_mode(panel_mode, adjusted_mode);
>>   
>> -		if (INTEL_GEN(dev_priv) >= 9) {
>> +		if (IS_GEN_GTE(dev_priv, 9)) {
>>   			int ret;
>>   			ret = skl_update_scaler_crtc(pipe_config);
>>   			if (ret)
>> @@ -3208,7 +3208,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>>   	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>>   	enum port port = dp_to_dig_port(intel_dp)->base.port;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
>>   		return intel_ddi_dp_voltage_max(encoder);
>>   	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> @@ -3227,7 +3227,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
>>   	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>>   	enum port port = dp_to_dig_port(intel_dp)->base.port;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
>>   		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
>>   			return DP_TRAIN_PRE_EMPH_LEVEL_3;
>> @@ -3760,7 +3760,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>>   		DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9 &&
>> +	if (IS_GEN_GTE(dev_priv, 9) &&
>>   	    (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
>>   		uint8_t frame_sync_cap;
>>   
>> @@ -5468,10 +5468,10 @@ bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
>>   	 * eDP not supported on g4x. so bail out early just
>>   	 * for a bit extra safety in case the VBT is bonkers.
>>   	 */
>> -	if (INTEL_GEN(dev_priv) < 5)
>> +	if (IS_GEN_LT(dev_priv, 5))
>>   		return false;
>>   
>> -	if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
>> +	if (IS_GEN_LT(dev_priv, 9) && port == PORT_A)
>>   		return true;
>>   
>>   	return intel_bios_is_port_edp(dev_priv, port);
>> @@ -5830,7 +5830,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
>>   		return;
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
>> +	if (IS_GEN_GTE(dev_priv, 8) && !IS_CHERRYVIEW(dev_priv)) {
>>   		switch (index) {
>>   		case DRRS_HIGH_RR:
>>   			intel_dp_set_m_n(intel_crtc, M1_N1);
>> @@ -5842,7 +5842,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
>>   		default:
>>   			DRM_ERROR("Unsupported refreshrate type\n");
>>   		}
>> -	} else if (INTEL_GEN(dev_priv) > 6) {
>> +	} else if (IS_GEN_GT(dev_priv, 6)) {
>>   		i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
>>   		u32 val;
>>   
>> @@ -6115,7 +6115,7 @@ intel_dp_drrs_init(struct intel_connector *connector,
>>   	INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
>>   	mutex_init(&dev_priv->drrs.mutex);
>>   
>> -	if (INTEL_GEN(dev_priv) <= 6) {
>> +	if (IS_GEN_LTE(dev_priv, 6)) {
>>   		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
>>   		return NULL;
>>   	}
>> @@ -6353,7 +6353,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>>   	intel_dp->active_pipe = INVALID_PIPE;
>>   
>>   	/* intel_dp vfuncs */
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
>>   	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>>   		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
>> @@ -6362,7 +6362,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>>   	else
>>   		intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
>>   	else
>>   		intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
>> @@ -6501,7 +6501,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
>>   		intel_encoder->enable = vlv_enable_dp;
>>   		intel_encoder->disable = vlv_disable_dp;
>>   		intel_encoder->post_disable = vlv_post_disable_dp;
>> -	} else if (INTEL_GEN(dev_priv) >= 5) {
>> +	} else if (IS_GEN_GTE(dev_priv, 5)) {
>>   		intel_encoder->pre_enable = g4x_pre_enable_dp;
>>   		intel_encoder->enable = g4x_enable_dp;
>>   		intel_encoder->disable = ilk_disable_dp;
>> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> index 51c5ae4e9116..7bde6b9853e3 100644
>> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> @@ -210,7 +210,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
>>   	unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
>>   
>>   	/* PCH only available on ILK+ */
>> -	if (INTEL_GEN(dev_priv) < 5)
>> +	if (IS_GEN_LT(dev_priv, 5))
>>   		return;
>>   
>>   	if (pll == NULL)
>> @@ -1860,7 +1860,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
>>   {
>>   	struct drm_i915_private *dev_priv = to_i915(dev);
>>   
>> -	if (INTEL_GEN(dev_priv) < 9) {
>> +	if (IS_GEN_LT(dev_priv, 9)) {
>>   		uint32_t val = I915_READ(LCPLL_CTL);
>>   
>>   		/*
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index 7eebfbb95e89..9706bd8d9e77 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -193,7 +193,7 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
>>   	case VIDEO_DECODE_CLASS:
>>   	case VIDEO_ENHANCEMENT_CLASS:
>>   	case COPY_ENGINE_CLASS:
>> -		if (INTEL_GEN(dev_priv) < 8)
>> +		if (IS_GEN_LT(dev_priv, 8))
>>   			return 0;
>>   		return GEN8_LR_CONTEXT_OTHER_SIZE;
>>   	}
>> @@ -696,10 +696,10 @@ u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
>>   	struct drm_i915_private *dev_priv = engine->i915;
>>   	u64 acthd;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> +	if (IS_GEN_GTE(dev_priv, 8))
>>   		acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
>>   					 RING_ACTHD_UDW(engine->mmio_base));
>> -	else if (INTEL_GEN(dev_priv) >= 4)
>> +	else if (IS_GEN_GTE(dev_priv, 4))
>>   		acthd = I915_READ(RING_ACTHD(engine->mmio_base));
>>   	else
>>   		acthd = I915_READ(ACTHD);
>> @@ -712,7 +712,7 @@ u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine)
>>   	struct drm_i915_private *dev_priv = engine->i915;
>>   	u64 bbaddr;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> +	if (IS_GEN_GTE(dev_priv, 8))
>>   		bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
>>   					  RING_BBADDR_UDW(engine->mmio_base));
>>   	else
>> @@ -1472,7 +1472,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
>>   		idle = false;
>>   
>>   	/* No bit for gen2, so assume the CS parser is idle */
>> -	if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE))
>> +	if (IS_GEN_GT(dev_priv, 2) && !(I915_READ_MODE(engine) & MODE_IDLE))
>>   		idle = false;
>>   
>>   	intel_runtime_pm_put(dev_priv);
>> @@ -1777,7 +1777,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>>   	drm_printf(m, "\tRING_CTL:   0x%08x%s\n",
>>   		   I915_READ(RING_CTL(engine->mmio_base)),
>>   		   I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
>> -	if (INTEL_GEN(engine->i915) > 2) {
>> +	if (IS_GEN_GT(engine->i915, 2)) {
>>   		drm_printf(m, "\tRING_MODE:  0x%08x%s\n",
>>   			   I915_READ(RING_MI_MODE(engine->mmio_base)),
>>   			   I915_READ(RING_MI_MODE(engine->mmio_base)) & (MODE_IDLE) ? " [idle]" : "");
>> @@ -1800,16 +1800,16 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>>   	addr = intel_engine_get_last_batch_head(engine);
>>   	drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
>>   		   upper_32_bits(addr), lower_32_bits(addr));
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> +	if (IS_GEN_GTE(dev_priv, 8))
>>   		addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
>>   					RING_DMA_FADD_UDW(engine->mmio_base));
>> -	else if (INTEL_GEN(dev_priv) >= 4)
>> +	else if (IS_GEN_GTE(dev_priv, 4))
>>   		addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
>>   	else
>>   		addr = I915_READ(DMA_FADD_I8XX);
>>   	drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
>>   		   upper_32_bits(addr), lower_32_bits(addr));
>> -	if (INTEL_GEN(dev_priv) >= 4) {
>> +	if (IS_GEN_GTE(dev_priv, 4)) {
>>   		drm_printf(m, "\tIPEIR: 0x%08x\n",
>>   			   I915_READ(RING_IPEIR(engine->mmio_base)));
>>   		drm_printf(m, "\tIPEHR: 0x%08x\n",
>> @@ -1869,7 +1869,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>>   		}
>>   		drm_printf(m, "\t\tHW active? 0x%x\n", execlists->active);
>>   		rcu_read_unlock();
>> -	} else if (INTEL_GEN(dev_priv) > 6) {
>> +	} else if (IS_GEN_GT(dev_priv, 6)) {
>>   		drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
>>   			   I915_READ(RING_PP_DIR_BASE(engine)));
>>   		drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
>> @@ -1899,7 +1899,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>>   	}
>>   	spin_unlock_irq(&b->rb_lock);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +	if (IS_GEN_GTE(dev_priv, 6)) {
>>   		drm_printf(m, "\tRING_IMR: %08x\n", I915_READ_IMR(engine));
>>   	}
>>   
>> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
>> index 0ad854095c38..30da6085f84e 100644
>> --- a/drivers/gpu/drm/i915/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/intel_fbc.c
>> @@ -48,17 +48,17 @@ static inline bool fbc_supported(struct drm_i915_private *dev_priv)
>>   
>>   static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
>>   {
>> -	return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
>> +	return IS_HASWELL(dev_priv) || IS_GEN_GTE(dev_priv, 8);
>>   }
>>   
>>   static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
>>   {
>> -	return INTEL_GEN(dev_priv) < 4;
>> +	return IS_GEN_LT(dev_priv, 4);
>>   }
>>   
>>   static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
>>   {
>> -	return INTEL_GEN(dev_priv) <= 3;
>> +	return IS_GEN_LTE(dev_priv, 3);
>>   }
>>   
>>   /*
>> @@ -96,7 +96,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
>>   	intel_fbc_get_plane_source_size(cache, NULL, &lines);
>>   	if (IS_GEN7(dev_priv))
>>   		lines = min(lines, 2048);
>> -	else if (INTEL_GEN(dev_priv) >= 8)
>> +	else if (IS_GEN_GTE(dev_priv, 8))
>>   		lines = min(lines, 2560);
>>   
>>   	/* Hardware needs the full buffer stride, not just the active area. */
>> @@ -357,7 +357,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>>   
>>   static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 5)
>> +	if (IS_GEN_GTE(dev_priv, 5))
>>   		return ilk_fbc_is_active(dev_priv);
>>   	else if (IS_GM45(dev_priv))
>>   		return g4x_fbc_is_active(dev_priv);
>> @@ -371,9 +371,9 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
>>   
>>   	fbc->active = true;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 7)
>> +	if (IS_GEN_GTE(dev_priv, 7))
>>   		gen7_fbc_activate(dev_priv);
>> -	else if (INTEL_GEN(dev_priv) >= 5)
>> +	else if (IS_GEN_GTE(dev_priv, 5))
>>   		ilk_fbc_activate(dev_priv);
>>   	else if (IS_GM45(dev_priv))
>>   		g4x_fbc_activate(dev_priv);
>> @@ -387,7 +387,7 @@ static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
>>   
>>   	fbc->active = false;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 5)
>> +	if (IS_GEN_GTE(dev_priv, 5))
>>   		ilk_fbc_deactivate(dev_priv);
>>   	else if (IS_GM45(dev_priv))
>>   		g4x_fbc_deactivate(dev_priv);
>> @@ -568,7 +568,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
>>   
>>   	ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
>>   						   4096, 0, end);
>> -	if (ret && INTEL_GEN(dev_priv) <= 4) {
>> +	if (ret && IS_GEN_LTE(dev_priv, 4)) {
>>   		return 0;
>>   	} else if (ret) {
>>   		compression_threshold <<= 1;
>> @@ -601,7 +601,7 @@ static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
>>   
>>   	fbc->threshold = ret;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 5)
>> +	if (IS_GEN_GTE(dev_priv, 5))
>>   		I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
>>   	else if (IS_GM45(dev_priv)) {
>>   		I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
>> @@ -724,10 +724,10 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
>>   	struct intel_fbc *fbc = &dev_priv->fbc;
>>   	unsigned int effective_w, effective_h, max_w, max_h;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
>> +	if (IS_GEN_GTE(dev_priv, 8) || IS_HASWELL(dev_priv)) {
>>   		max_w = 4096;
>>   		max_h = 4096;
>> -	} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
>> +	} else if (IS_G4X(dev_priv) || IS_GEN_GTE(dev_priv, 5)) {
>>   		max_w = 4096;
>>   		max_h = 2048;
>>   	} else {
>> @@ -820,7 +820,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
>>   		fbc->no_fbc_reason = "framebuffer not tiled or fenced";
>>   		return false;
>>   	}
>> -	if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
>> +	if (IS_GEN_LTE(dev_priv, 4) && !IS_G4X(dev_priv) &&
>>   	    cache->plane.rotation != DRM_MODE_ROTATE_0) {
>>   		fbc->no_fbc_reason = "rotation unsupported";
>>   		return false;
>> @@ -1325,7 +1325,7 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
>>   	if (!HAS_FBC(dev_priv))
>>   		return 0;
>>   
>> -	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_BROADWELL(dev_priv) || IS_GEN_GTE(dev_priv, 9))
>>   		return 1;
>>   
>>   	return 0;
>> @@ -1382,7 +1382,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
>>   	}
>>   
>>   	/* This value was pulled out of someone's hat */
>> -	if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
>> +	if (IS_GEN_LTE(dev_priv, 4) && !IS_GM45(dev_priv))
>>   		I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
>>   
>>   	/* We still don't have any sort of hardware state readout for FBC, so
>> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
>> index 77c123cc8817..0521208041ab 100644
>> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
>> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
>> @@ -264,7 +264,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
>>   		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
>>   	else if (IS_GEN7(dev_priv))
>>   		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
>> -	else if (INTEL_GEN(dev_priv) >= 8)
>> +	else if (IS_GEN_GTE(dev_priv, 8))
>>   		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
>>   
>>   	return old;
>> diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
>> index 42e45ae87393..3e4db1c0329d 100644
>> --- a/drivers/gpu/drm/i915/intel_hangcheck.c
>> +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
>> @@ -97,7 +97,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
>>   	 * ringbuffer itself.
>>   	 */
>>   	head = I915_READ_HEAD(engine) & HEAD_ADDR;
>> -	backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
>> +	backwards = (IS_GEN_GTE(dev_priv, 8)) ? 5 : 4;
>>   	vaddr = (void __iomem *)engine->buffer->vaddr;
>>   
>>   	for (i = backwards; i; --i) {
>> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
>> index 14ca5d3057a7..9c5ee2dae9fa 100644
>> --- a/drivers/gpu/drm/i915/intel_hdcp.c
>> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
>> @@ -651,7 +651,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
>>   bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
>>   {
>>   	/* PORT E doesn't have HDCP, and PORT F is disabled */
>> -	return ((INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
>> +	return ((IS_GEN_GTE(dev_priv, 8) || IS_HASWELL(dev_priv)) &&
>>   		!IS_CHERRYVIEW(dev_priv) && port < PORT_E);
>>   }
>>   
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
>> index f5d7bfb43006..ea64df508052 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -1481,11 +1481,11 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
>>   		&dev_priv->vbt.ddi_port_info[encoder->port];
>>   	int max_tmds_clock;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> +	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
>>   		max_tmds_clock = 594000;
>> -	else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
>> +	else if (IS_GEN_GTE(dev_priv, 8) || IS_HASWELL(dev_priv))
>>   		max_tmds_clock = 300000;
>> -	else if (INTEL_GEN(dev_priv) >= 5)
>> +	else if (IS_GEN_GTE(dev_priv, 5))
>>   		max_tmds_clock = 225000;
>>   	else
>>   		max_tmds_clock = 165000;
>> @@ -1754,7 +1754,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
>>   
>>   	pipe_config->lane_count = 4;
>>   
>> -	if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
>> +	if (scdc->scrambling.supported && (IS_GEN_GTE(dev_priv, 10) ||
>>   					   IS_GEMINILAKE(dev_priv))) {
>>   		if (scdc->scrambling.low_rates)
>>   			pipe_config->hdmi_scrambling = true;
>> @@ -2324,7 +2324,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>>   	connector->doublescan_allowed = 0;
>>   	connector->stereo_allowed = 1;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> +	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
>>   		connector->ycbcr_420_allowed = true;
>>   
>>   	intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index 380c0838d8b3..1a08f6bdaf50 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1488,7 +1488,7 @@ static void enable_execlists(struct intel_engine_cs *engine)
>>   	 * deeper FIFO it's not needed and it's not worth adding
>>   	 * more statements to the irq handler to support it.
>>   	 */
>> -	if (INTEL_GEN(dev_priv) >= 11)
>> +	if (IS_GEN_GTE(dev_priv, 11))
>>   		I915_WRITE(RING_MODE_GEN7(engine),
>>   			   _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
>>   	else
>> @@ -2057,7 +2057,7 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
>>   		engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
>>   
>>   	/* Override some for render ring. */
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		engine->init_hw = gen9_init_render_ring;
>>   	else
>>   		engine->init_hw = gen8_init_render_ring;
>> @@ -2100,7 +2100,7 @@ make_rpcs(struct drm_i915_private *dev_priv)
>>   	 * No explicit RPCS request is needed to ensure full
>>   	 * slice/subslice/EU enablement prior to Gen9.
>>   	*/
>> -	if (INTEL_GEN(dev_priv) < 9)
>> +	if (IS_GEN_LT(dev_priv, 9))
>>   		return 0;
>>   
>>   	/*
>> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
>> index 4677ac0b10d7..577385cb3c8d 100644
>> --- a/drivers/gpu/drm/i915/intel_lvds.c
>> +++ b/drivers/gpu/drm/i915/intel_lvds.c
>> @@ -139,12 +139,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
>>   
>>   	pipe_config->base.adjusted_mode.flags |= flags;
>>   
>> -	if (INTEL_GEN(dev_priv) < 5)
>> +	if (IS_GEN_LT(dev_priv, 5))
>>   		pipe_config->gmch_pfit.lvds_border_bits =
>>   			tmp & LVDS_BORDER_ENABLE;
>>   
>>   	/* gen2/3 store dither state in pfit control, needs to match */
>> -	if (INTEL_GEN(dev_priv) < 4) {
>> +	if (IS_GEN_LT(dev_priv, 4)) {
>>   		tmp = I915_READ(PFIT_CONTROL);
>>   
>>   		pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
>> @@ -189,7 +189,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
>>   	/* Convert from 100ms to 100us units */
>>   	pps->t4 = val * 1000;
>>   
>> -	if (INTEL_GEN(dev_priv) <= 4 &&
>> +	if (IS_GEN_LTE(dev_priv, 4) &&
>>   	    pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
>>   		DRM_DEBUG_KMS("Panel power timings uninitialized, "
>>   			      "setting defaults\n");
>> @@ -396,7 +396,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
>>   	unsigned int lvds_bpp;
>>   
>>   	/* Should never happen!! */
>> -	if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
>> +	if (IS_GEN_LT(dev_priv, 4) && intel_crtc->pipe == 0) {
>>   		DRM_ERROR("Can't support LVDS on pipe A\n");
>>   		return false;
>>   	}
>> @@ -914,7 +914,7 @@ static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
>>   
>>   	/* Otherwise LVDS was only attached to mobile products,
>>   	 * except for the inglorious 830gm */
>> -	if (INTEL_GEN(dev_priv) <= 4 &&
>> +	if (IS_GEN_LTE(dev_priv, 4) &&
>>   	    IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
>>   		return true;
>>   
>> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
>> index abb7a8c1e340..02b2768b556e 100644
>> --- a/drivers/gpu/drm/i915/intel_mocs.c
>> +++ b/drivers/gpu/drm/i915/intel_mocs.c
>> @@ -187,7 +187,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
>>   		table->table = broxton_mocs_table;
>>   		result = true;
>>   	} else {
>> -		WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
>> +		WARN_ONCE(IS_GEN_GTE(dev_priv, 9),
>>   			  "Platform that should have a MOCS table does not.\n");
>>   	}
>>   
>> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
>> index 41e9465d44a8..752085a2a2d0 100644
>> --- a/drivers/gpu/drm/i915/intel_overlay.c
>> +++ b/drivers/gpu/drm/i915/intel_overlay.c
>> @@ -945,7 +945,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
>>   	/* XXX: This is not the same logic as in the xorg driver, but more in
>>   	 * line with the intel documentation for the i965
>>   	 */
>> -	if (INTEL_GEN(dev_priv) >= 4) {
>> +	if (IS_GEN_GTE(dev_priv, 4)) {
>>   		/* on i965 use the PGM reg to read out the autoscaler values */
>>   		ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
>>   	} else {
>> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
>> index 78a53c8b1789..557249583f8e 100644
>> --- a/drivers/gpu/drm/i915/intel_panel.c
>> +++ b/drivers/gpu/drm/i915/intel_panel.c
>> @@ -326,7 +326,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
>>   		break;
>>   	case DRM_MODE_SCALE_ASPECT:
>>   		/* Scale but preserve the aspect ratio */
>> -		if (INTEL_GEN(dev_priv) >= 4)
>> +		if (IS_GEN_GTE(dev_priv, 4))
>>   			i965_scale_aspect(pipe_config, &pfit_control);
>>   		else
>>   			i9xx_scale_aspect(pipe_config, &pfit_control,
>> @@ -340,7 +340,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
>>   		if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay ||
>>   		    pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
>>   			pfit_control |= PFIT_ENABLE;
>> -			if (INTEL_GEN(dev_priv) >= 4)
>> +			if (IS_GEN_GTE(dev_priv, 4))
>>   				pfit_control |= PFIT_SCALING_AUTO;
>>   			else
>>   				pfit_control |= (VERT_AUTO_SCALE |
>> @@ -356,7 +356,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
>>   
>>   	/* 965+ wants fuzzy fitting */
>>   	/* FIXME: handle multiple panels by failing gracefully */
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
>>   				 PFIT_FILTER_FUZZY);
>>   
>> @@ -367,7 +367,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
>>   	}
>>   
>>   	/* Make sure pre-965 set dither correctly for 18bpp panels. */
>> -	if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18)
>> +	if (IS_GEN_LT(dev_priv, 4) && pipe_config->pipe_bpp == 18)
>>   		pfit_control |= PANEL_8TO6_DITHER_ENABLE;
>>   
>>   	pipe_config->gmch_pfit.control = pfit_control;
>> @@ -497,7 +497,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector)
>>   	u32 val;
>>   
>>   	val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
>> -	if (INTEL_GEN(dev_priv) < 4)
>> +	if (IS_GEN_LT(dev_priv, 4))
>>   		val >>= 1;
>>   
>>   	if (panel->backlight.combination_mode) {
>> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
>> index 1f5cd572a7ff..017bd2602c99 100644
>> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
>> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
>> @@ -604,7 +604,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
>>   {
>>   	if (IS_GEN2(dev_priv))
>>   		return i8xx_pipe_crc_ctl_reg(source, val);
>> -	else if (INTEL_GEN(dev_priv) < 5)
>> +	else if (IS_GEN_LT(dev_priv, 5))
>>   		return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
>>   	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>   		return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 7a112d075c24..37421fe4c0a3 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -2571,9 +2571,9 @@ static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
>>   static unsigned int
>>   ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> +	if (IS_GEN_GTE(dev_priv, 8))
>>   		return 3072;
>> -	else if (INTEL_GEN(dev_priv) >= 7)
>> +	else if (IS_GEN_GTE(dev_priv, 7))
>>   		return 768;
>>   	else
>>   		return 512;
>> @@ -2583,10 +2583,10 @@ static unsigned int
>>   ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
>>   		     int level, bool is_sprite)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> +	if (IS_GEN_GTE(dev_priv, 8))
>>   		/* BDW primary/sprite plane watermarks */
>>   		return level == 0 ? 255 : 2047;
>> -	else if (INTEL_GEN(dev_priv) >= 7)
>> +	else if (IS_GEN_GTE(dev_priv, 7))
>>   		/* IVB/HSW primary/sprite plane watermarks */
>>   		return level == 0 ? 127 : 1023;
>>   	else if (!is_sprite)
>> @@ -2600,7 +2600,7 @@ ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
>>   static unsigned int
>>   ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 7)
>> +	if (IS_GEN_GTE(dev_priv, 7))
>>   		return level == 0 ? 63 : 255;
>>   	else
>>   		return level == 0 ? 31 : 63;
>> @@ -2608,7 +2608,7 @@ ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
>>   
>>   static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> +	if (IS_GEN_GTE(dev_priv, 8))
>>   		return 31;
>>   	else
>>   		return 15;
>> @@ -2637,7 +2637,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
>>   		 * FIFO size is only half of the self
>>   		 * refresh FIFO size on ILK/SNB.
>>   		 */
>> -		if (INTEL_GEN(dev_priv) <= 6)
>> +		if (IS_GEN_LTE(dev_priv, 6))
>>   			fifo_size /= 2;
>>   	}
>>   
>> @@ -2798,7 +2798,7 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
>>   static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>>   				  uint16_t wm[8])
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		uint32_t val;
>>   		int ret, i;
>>   		int level, max_level = ilk_wm_max_level(dev_priv);
>> @@ -2883,14 +2883,14 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>>   		wm[2] = (sskpd >> 12) & 0xFF;
>>   		wm[3] = (sskpd >> 20) & 0x1FF;
>>   		wm[4] = (sskpd >> 32) & 0x1FF;
>> -	} else if (INTEL_GEN(dev_priv) >= 6) {
>> +	} else if (IS_GEN_GTE(dev_priv, 6)) {
>>   		uint32_t sskpd = I915_READ(MCH_SSKPD);
>>   
>>   		wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
>>   		wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
>>   		wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
>>   		wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
>> -	} else if (INTEL_GEN(dev_priv) >= 5) {
>> +	} else if (IS_GEN_GTE(dev_priv, 5)) {
>>   		uint32_t mltr = I915_READ(MLTR_ILK);
>>   
>>   		/* ILK primary LP0 latency is 700 ns */
>> @@ -2925,11 +2925,11 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
>>   int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
>>   {
>>   	/* how many WM levels are we expecting */
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		return 7;
>>   	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>>   		return 4;
>> -	else if (INTEL_GEN(dev_priv) >= 6)
>> +	else if (IS_GEN_GTE(dev_priv, 6))
>>   		return 3;
>>   	else
>>   		return 2;
>> @@ -2954,7 +2954,7 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
>>   		 * - latencies are in us on gen9.
>>   		 * - before then, WM1+ latency values are in 0.5us units
>>   		 */
>> -		if (INTEL_GEN(dev_priv) >= 9)
>> +		if (IS_GEN_GTE(dev_priv, 9))
>>   			latency *= 10;
>>   		else if (level > 0)
>>   			latency *= 5;
>> @@ -3090,7 +3090,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
>>   	usable_level = max_level;
>>   
>>   	/* ILK/SNB: LP2+ watermarks only w/o sprites */
>> -	if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
>> +	if (IS_GEN_LTE(dev_priv, 6) && pipe_wm->sprites_enabled)
>>   		usable_level = 1;
>>   
>>   	/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
>> @@ -3235,12 +3235,12 @@ static void ilk_wm_merge(struct drm_device *dev,
>>   	int last_enabled_level = max_level;
>>   
>>   	/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
>> -	if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
>> +	if ((IS_GEN_LTE(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) &&
>>   	    config->num_pipes_active > 1)
>>   		last_enabled_level = 0;
>>   
>>   	/* ILK: FBC WM must be disabled always */
>> -	merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
>> +	merged->fbc_wm_enabled = IS_GEN_GTE(dev_priv, 6);
>>   
>>   	/* merge each WM1+ level */
>>   	for (level = 1; level <= max_level; level++) {
>> @@ -3330,7 +3330,7 @@ static void ilk_compute_wm_results(struct drm_device *dev,
>>   		if (r->enable)
>>   			results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
>>   
>> -		if (INTEL_GEN(dev_priv) >= 8)
>> +		if (IS_GEN_GTE(dev_priv, 8))
>>   			results->wm_lp[wm_lp - 1] |=
>>   				r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
>>   		else
>> @@ -3341,7 +3341,7 @@ static void ilk_compute_wm_results(struct drm_device *dev,
>>   		 * Always set WM1S_LP_EN when spr_val != 0, even if the
>>   		 * level is disabled. Doing otherwise could cause underruns.
>>   		 */
>> -		if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
>> +		if (IS_GEN_LTE(dev_priv, 6) && r->spr_val) {
>>   			WARN_ON(wm_lp != 1);
>>   			results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
>>   		} else
>> @@ -3546,7 +3546,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
>>   	    previous->wm_lp_spr[0] != results->wm_lp_spr[0])
>>   		I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 7) {
>> +	if (IS_GEN_GTE(dev_priv, 7)) {
>>   		if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
>>   			I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
>>   		if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
>> @@ -3785,7 +3785,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
>>   	ddb_size = INTEL_INFO(dev_priv)->ddb_size;
>>   	WARN_ON(ddb_size == 0);
>>   
>> -	if (INTEL_GEN(dev_priv) < 11)
>> +	if (IS_GEN_LT(dev_priv, 11))
>>   		ddb_size -= 4; /* 4 blocks for bypass path allocation */
>>   
>>   	/*
>> @@ -3996,7 +3996,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>>   	crtc_clock = crtc_state->adjusted_mode.crtc_clock;
>>   	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
>>   
>> -	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>> +	if (IS_GEMINILAKE(dev_priv) || IS_GEN_GTE(dev_priv, 10))
>>   		dotclk *= 2;
>>   
>>   	pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
>> @@ -4330,7 +4330,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
>>   	wm_intermediate_val = latency * pixel_rate * cpp;
>>   	ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10)
>> +	if (IS_GEN_GTE(dev_priv, 10))
>>   		ret = add_fixed16_u32(ret, 1);
>>   
>>   	return ret;
>> @@ -4438,7 +4438,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>>   	wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
>>   							     intel_pstate);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 11 &&
>> +	if (IS_GEN_GTE(dev_priv, 11) &&
>>   	    fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
>>   		wp->dbuf_block_size = 256;
>>   	else
>> @@ -4473,7 +4473,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>>   					   wp->y_min_scanlines,
>>   					   wp->dbuf_block_size);
>>   
>> -		if (INTEL_GEN(dev_priv) >= 10)
>> +		if (IS_GEN_GTE(dev_priv, 10))
>>   			interm_pbpl++;
>>   
>>   		wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
>> @@ -4573,7 +4573,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>>   		}
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 11) {
>> +	if (IS_GEN_GTE(dev_priv, 11)) {
>>   		if (wp->y_tiled) {
>>   			uint32_t extra_lines;
>>   			uint_fixed_16_16_t fp_min_disp_buf_needed;
>> @@ -4705,14 +4705,14 @@ static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
>>   		goto exit;
>>   
>>   	/* Transition WM are not recommended by HW team for GEN9 */
>> -	if (INTEL_GEN(dev_priv) <= 9)
>> +	if (IS_GEN_LTE(dev_priv, 9))
>>   		goto exit;
>>   
>>   	/* Transition WM don't make any sense if ipc is disabled */
>>   	if (!dev_priv->ipc_enabled)
>>   		goto exit;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10)
>> +	if (IS_GEN_GTE(dev_priv, 10))
>>   		trans_min = 4;
>>   
>>   	trans_offset_b = trans_min + trans_amount;
>> @@ -4835,7 +4835,7 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
>>   
>>   	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
>>   			    &ddb->plane[pipe][plane_id]);
>> -	if (INTEL_GEN(dev_priv) < 11)
>> +	if (IS_GEN_LT(dev_priv, 11))
>>   		skl_ddb_entry_write(dev_priv,
>>   				    PLANE_NV12_BUF_CFG(pipe, plane_id),
>>   				    &ddb->y_plane[pipe][plane_id]);
>> @@ -5249,7 +5249,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
>>   	ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
>>   
>>   	/* 5/6 split only in single pipe config on IVB+ */
>> -	if (INTEL_GEN(dev_priv) >= 7 &&
>> +	if (IS_GEN_GTE(dev_priv, 7) &&
>>   	    config.num_pipes_active == 1 && config.sprites_enabled) {
>>   		ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
>>   		ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
>> @@ -5848,7 +5848,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
>>   	hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
>>   
>>   	hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
>> -	if (INTEL_GEN(dev_priv) >= 7) {
>> +	if (IS_GEN_GTE(dev_priv, 7)) {
>>   		hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
>>   		hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
>>   	}
>> @@ -6076,7 +6076,7 @@ static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
>>   	 * the hw runs at the minimal clock before selecting the desired
>>   	 * frequency, if the down threshold expires in that window we will not
>>   	 * receive a down interrupt. */
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		limits = (rps->max_freq_softlimit) << 23;
>>   		if (val <= rps->min_freq_softlimit)
>>   			limits |= (rps->min_freq_softlimit) << 14;
>> @@ -6222,7 +6222,7 @@ static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
>>   	if (val != rps->cur_freq) {
>>   		gen6_set_rps_thresholds(dev_priv, val);
>>   
>> -		if (INTEL_GEN(dev_priv) >= 9)
>> +		if (IS_GEN_GTE(dev_priv, 9))
>>   			I915_WRITE(GEN6_RPNSWREQ,
>>   				   GEN9_FREQUENCY(val));
>>   		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>> @@ -6650,7 +6650,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
>>   	I915_WRITE(GEN6_RC_CONTROL, 0);
>>   
>>   	/* 2b: Program RC6 thresholds.*/
>> -	if (INTEL_GEN(dev_priv) >= 10) {
>> +	if (IS_GEN_GTE(dev_priv, 10)) {
>>   		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
>>   		I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>>   	} else if (IS_SKYLAKE(dev_priv)) {
>> @@ -6940,7 +6940,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
>>   			 * No floor required for ring frequency on SKL.
>>   			 */
>>   			ring_freq = gpu_freq;
>> -		} else if (INTEL_GEN(dev_priv) >= 8) {
>> +		} else if (IS_GEN_GTE(dev_priv, 8)) {
>>   			/* max(2 * GT, DDR). NB: GT is 50MHz units */
>>   			ring_freq = max(min_ring_freq, gpu_freq);
>>   		} else if (IS_HASWELL(dev_priv)) {
>> @@ -7957,7 +7957,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>>   		cherryview_init_gt_powersave(dev_priv);
>>   	else if (IS_VALLEYVIEW(dev_priv))
>>   		valleyview_init_gt_powersave(dev_priv);
>> -	else if (INTEL_GEN(dev_priv) >= 6)
>> +	else if (IS_GEN_GTE(dev_priv, 6))
>>   		gen6_init_rps_frequencies(dev_priv);
>>   
>>   	/* Derive initial user preferences/limits from the hardware limits */
>> @@ -8012,7 +8012,7 @@ void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
>>    */
>>   void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
>>   {
>> -	if (INTEL_GEN(dev_priv) < 6)
>> +	if (IS_GEN_LT(dev_priv, 6))
>>   		return;
>>   
>>   	/* gen6_rps_idle() will be called later to disable interrupts */
>> @@ -8046,13 +8046,13 @@ static void intel_disable_rc6(struct drm_i915_private *dev_priv)
>>   	if (!dev_priv->gt_pm.rc6.enabled)
>>   		return;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		gen9_disable_rc6(dev_priv);
>>   	else if (IS_CHERRYVIEW(dev_priv))
>>   		cherryview_disable_rc6(dev_priv);
>>   	else if (IS_VALLEYVIEW(dev_priv))
>>   		valleyview_disable_rc6(dev_priv);
>> -	else if (INTEL_GEN(dev_priv) >= 6)
>> +	else if (IS_GEN_GTE(dev_priv, 6))
>>   		gen6_disable_rc6(dev_priv);
>>   
>>   	dev_priv->gt_pm.rc6.enabled = false;
>> @@ -8065,13 +8065,13 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv)
>>   	if (!dev_priv->gt_pm.rps.enabled)
>>   		return;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		gen9_disable_rps(dev_priv);
>>   	else if (IS_CHERRYVIEW(dev_priv))
>>   		cherryview_disable_rps(dev_priv);
>>   	else if (IS_VALLEYVIEW(dev_priv))
>>   		valleyview_disable_rps(dev_priv);
>> -	else if (INTEL_GEN(dev_priv) >= 6)
>> +	else if (IS_GEN_GTE(dev_priv, 6))
>>   		gen6_disable_rps(dev_priv);
>>   	else if (IS_IRONLAKE_M(dev_priv))
>>   		ironlake_disable_drps(dev_priv);
>> @@ -8114,11 +8114,11 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv)
>>   		cherryview_enable_rc6(dev_priv);
>>   	else if (IS_VALLEYVIEW(dev_priv))
>>   		valleyview_enable_rc6(dev_priv);
>> -	else if (INTEL_GEN(dev_priv) >= 9)
>> +	else if (IS_GEN_GTE(dev_priv, 9))
>>   		gen9_enable_rc6(dev_priv);
>>   	else if (IS_BROADWELL(dev_priv))
>>   		gen8_enable_rc6(dev_priv);
>> -	else if (INTEL_GEN(dev_priv) >= 6)
>> +	else if (IS_GEN_GTE(dev_priv, 6))
>>   		gen6_enable_rc6(dev_priv);
>>   
>>   	dev_priv->gt_pm.rc6.enabled = true;
>> @@ -8137,11 +8137,11 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
>>   		cherryview_enable_rps(dev_priv);
>>   	} else if (IS_VALLEYVIEW(dev_priv)) {
>>   		valleyview_enable_rps(dev_priv);
>> -	} else if (INTEL_GEN(dev_priv) >= 9) {
>> +	} else if (IS_GEN_GTE(dev_priv, 9)) {
>>   		gen9_enable_rps(dev_priv);
>>   	} else if (IS_BROADWELL(dev_priv)) {
>>   		gen8_enable_rps(dev_priv);
>> -	} else if (INTEL_GEN(dev_priv) >= 6) {
>> +	} else if (IS_GEN_GTE(dev_priv, 6)) {
>>   		gen6_enable_rps(dev_priv);
>>   	} else if (IS_IRONLAKE_M(dev_priv)) {
>>   		ironlake_enable_drps(dev_priv);
>> @@ -9056,7 +9056,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>>   		i915_ironlake_get_mem_freq(dev_priv);
>>   
>>   	/* For FIFO watermark updates */
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		skl_setup_wm_latency(dev_priv);
>>   		dev_priv->display.initial_watermarks = skl_initial_wm;
>>   		dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
>> @@ -9202,7 +9202,7 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val
>>   	*val = I915_READ_FW(GEN6_PCODE_DATA);
>>   	I915_WRITE_FW(GEN6_PCODE_DATA, 0);
>>   
>> -	if (INTEL_GEN(dev_priv) > 6)
>> +	if (IS_GEN_GT(dev_priv, 6))
>>   		status = gen7_check_mailbox_status(dev_priv);
>>   	else
>>   		status = gen6_check_mailbox_status(dev_priv);
>> @@ -9250,7 +9250,7 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
>>   
>>   	I915_WRITE_FW(GEN6_PCODE_DATA, 0);
>>   
>> -	if (INTEL_GEN(dev_priv) > 6)
>> +	if (IS_GEN_GT(dev_priv, 6))
>>   		status = gen7_check_mailbox_status(dev_priv);
>>   	else
>>   		status = gen6_check_mailbox_status(dev_priv);
>> @@ -9379,7 +9379,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
>>   
>>   int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
>>   					 GEN9_FREQ_SCALER);
>>   	else if (IS_CHERRYVIEW(dev_priv))
>> @@ -9392,7 +9392,7 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
>>   
>>   int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
>>   					 GT_FREQUENCY_MULTIPLIER);
>>   	else if (IS_CHERRYVIEW(dev_priv))
>> @@ -9537,7 +9537,7 @@ u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)
>>   {
>>   	u32 cagf;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
>>   	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>>   		cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 2ef374f936b9..116cce194ac9 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -126,7 +126,7 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
>>   static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
>>   				       enum port port)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		return DP_AUX_CH_CTL(port);
>>   	else
>>   		return EDP_PSR_AUX_CTL;
>> @@ -135,7 +135,7 @@ static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
>>   static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
>>   					enum port port, int index)
>>   {
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		return DP_AUX_CH_DATA(port, index);
>>   	else
>>   		return EDP_PSR_AUX_DATA(index);
>> @@ -521,7 +521,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>>   	dev_priv->psr.enable_source(intel_dp, crtc_state);
>>   	dev_priv->psr.enabled = intel_dp;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		intel_psr_activate(intel_dp);
>>   	} else {
>>   		/*
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index c91d7106fbcf..2c4ad89d9d57 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -346,7 +346,7 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
>>   	u32 addr;
>>   
>>   	addr = dev_priv->status_page_dmah->busaddr;
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
>>   	I915_WRITE(HWS_PGA, addr);
>>   }
>> @@ -386,7 +386,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>>   		mmio = RING_HWS_PGA(engine->mmio_base);
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6)
>> +	if (IS_GEN_GTE(dev_priv, 6))
>>   		I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
>>   
>>   	I915_WRITE(mmio, engine->status_page.ggtt_offset);
>> @@ -414,7 +414,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
>>   {
>>   	struct drm_i915_private *dev_priv = engine->i915;
>>   
>> -	if (INTEL_GEN(dev_priv) > 2) {
>> +	if (IS_GEN_GT(dev_priv, 2)) {
>>   		I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
>>   		if (intel_wait_for_register(dev_priv,
>>   					    RING_MI_MODE(engine->mmio_base),
>> @@ -521,7 +521,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
>>   
>>   	intel_engine_init_hangcheck(engine);
>>   
>> -	if (INTEL_GEN(dev_priv) > 2)
>> +	if (IS_GEN_GT(dev_priv, 2))
>>   		I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
>>   
>>   out:
>> @@ -655,7 +655,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
>>   	if (IS_GEN(dev_priv, 6, 7))
>>   		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6)
>> +	if (IS_GEN_GTE(dev_priv, 6))
>>   		I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
>>   
>>   	return init_workarounds_ring(engine);
>> @@ -1360,7 +1360,7 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
>>   {
>>   	struct drm_i915_private *dev_priv = engine->i915;
>>   
>> -	WARN_ON(INTEL_GEN(dev_priv) > 2 &&
>> +	WARN_ON(IS_GEN_GT(dev_priv, 2) &&
>>   		(I915_READ_MODE(engine) & MODE_IDLE) == 0);
>>   
>>   	intel_ring_unpin(engine->buffer);
>> @@ -1900,7 +1900,7 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
>>   	if (!HAS_LEGACY_SEMAPHORES(dev_priv))
>>   		return;
>>   
>> -	GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
>> +	GEM_BUG_ON(IS_GEN_LT(dev_priv, 6));
>>   	engine->semaphore.sync_to = gen6_ring_sync_to;
>>   	engine->semaphore.signal = gen6_signal;
>>   
>> @@ -1957,15 +1957,15 @@ static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
>>   {
>>   	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +	if (IS_GEN_GTE(dev_priv, 6)) {
>>   		engine->irq_enable = gen6_irq_enable;
>>   		engine->irq_disable = gen6_irq_disable;
>>   		engine->irq_seqno_barrier = gen6_seqno_barrier;
>> -	} else if (INTEL_GEN(dev_priv) >= 5) {
>> +	} else if (IS_GEN_GTE(dev_priv, 5)) {
>>   		engine->irq_enable = gen5_irq_enable;
>>   		engine->irq_disable = gen5_irq_disable;
>>   		engine->irq_seqno_barrier = gen5_seqno_barrier;
>> -	} else if (INTEL_GEN(dev_priv) >= 3) {
>> +	} else if (IS_GEN_GTE(dev_priv, 3)) {
>>   		engine->irq_enable = i9xx_irq_enable;
>>   		engine->irq_disable = i9xx_irq_disable;
>>   	} else {
>> @@ -1993,7 +1993,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
>>   				      struct intel_engine_cs *engine)
>>   {
>>   	/* gen8+ are only supported with execlists */
>> -	GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
>> +	GEM_BUG_ON(IS_GEN_GTE(dev_priv, 8));
>>   
>>   	intel_ring_init_irq(dev_priv, engine);
>>   	intel_ring_init_semaphores(dev_priv, engine);
>> @@ -2021,9 +2021,9 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
>>   
>>   	engine->set_default_submission = i9xx_set_default_submission;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6)
>> +	if (IS_GEN_GTE(dev_priv, 6))
>>   		engine->emit_bb_start = gen6_emit_bb_start;
>> -	else if (INTEL_GEN(dev_priv) >= 4)
>> +	else if (IS_GEN_GTE(dev_priv, 4))
>>   		engine->emit_bb_start = i965_emit_bb_start;
>>   	else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
>>   		engine->emit_bb_start = i830_emit_bb_start;
>> @@ -2041,7 +2041,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
>>   	if (HAS_L3_DPF(dev_priv))
>>   		engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +	if (IS_GEN_GTE(dev_priv, 6)) {
>>   		engine->init_context = intel_rcs_ctx_init;
>>   		engine->emit_flush = gen7_render_ring_flush;
>>   		if (IS_GEN6(dev_priv))
>> @@ -2049,7 +2049,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
>>   	} else if (IS_GEN5(dev_priv)) {
>>   		engine->emit_flush = gen4_render_ring_flush;
>>   	} else {
>> -		if (INTEL_GEN(dev_priv) < 4)
>> +		if (IS_GEN_LT(dev_priv, 4))
>>   			engine->emit_flush = gen2_render_ring_flush;
>>   		else
>>   			engine->emit_flush = gen4_render_ring_flush;
>> @@ -2065,7 +2065,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
>>   	if (ret)
>>   		return ret;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +	if (IS_GEN_GTE(dev_priv, 6)) {
>>   		ret = intel_engine_create_scratch(engine, PAGE_SIZE);
>>   		if (ret)
>>   			return ret;
>> @@ -2084,7 +2084,7 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
>>   
>>   	intel_ring_default_vfuncs(dev_priv, engine);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +	if (IS_GEN_GTE(dev_priv, 6)) {
>>   		/* gen6 bsd needs a special wa for tail updates */
>>   		if (IS_GEN6(dev_priv))
>>   			engine->set_default_submission = gen6_bsd_set_default_submission;
>> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
>> index 0bf97ed5ffac..3dd5f2c244d9 100644
>> --- a/drivers/gpu/drm/i915/intel_sdvo.c
>> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
>> @@ -1335,13 +1335,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
>>   		return;
>>   
>>   	/* Set the SDVO control regs. */
>> -	if (INTEL_GEN(dev_priv) >= 4) {
>> +	if (IS_GEN_GTE(dev_priv, 4)) {
>>   		/* The real mode polarity is set by the SDVO commands, using
>>   		 * struct intel_sdvo_dtd. */
>>   		sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
>>   		if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
>>   			sdvox |= HDMI_COLOR_RANGE_16_235;
>> -		if (INTEL_GEN(dev_priv) < 5)
>> +		if (IS_GEN_LT(dev_priv, 5))
>>   			sdvox |= SDVO_BORDER_ENABLE;
>>   	} else {
>>   		sdvox = I915_READ(intel_sdvo->sdvo_reg);
>> @@ -1358,11 +1358,11 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
>>   		sdvox |= SDVO_PIPE_SEL(crtc->pipe);
>>   
>>   	if (crtc_state->has_audio) {
>> -		WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4);
>> +		WARN_ON_ONCE(IS_GEN_LT(dev_priv, 4));
>>   		sdvox |= SDVO_AUDIO_ENABLE;
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4) {
>> +	if (IS_GEN_GTE(dev_priv, 4)) {
>>   		/* done in crtc_mode_set as the dpll_md reg must be written early */
>>   	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
>>   		   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
>> @@ -1373,7 +1373,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
>>   	}
>>   
>>   	if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
>> -	    INTEL_GEN(dev_priv) < 5)
>> +	    IS_GEN_LT(dev_priv, 5))
>>   		sdvox |= SDVO_STALL_SELECT;
>>   	intel_sdvo_write_sdvox(intel_sdvo, sdvox);
>>   }
>> @@ -2433,7 +2433,7 @@ intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
>>   	struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
>>   
>>   	intel_attach_force_audio_property(&connector->base.base);
>> -	if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
>> +	if (IS_GEN_GTE(dev_priv, 4) && IS_MOBILE(dev_priv)) {
>>   		intel_attach_broadcast_rgb_property(&connector->base.base);
>>   	}
>>   	intel_attach_aspect_ratio_property(&connector->base.base);
>> @@ -2502,7 +2502,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
>>   	connector->connector_type = DRM_MODE_CONNECTOR_DVID;
>>   
>>   	/* gen3 doesn't do the hdmi bits in the SDVO register */
>> -	if (INTEL_GEN(dev_priv) >= 4 &&
>> +	if (IS_GEN_GTE(dev_priv, 4) &&
>>   	    intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
>>   		connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
>>   		intel_sdvo->is_hdmi = true;
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> index 3be22c0fcfb5..a28c5f83fa02 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -263,7 +263,7 @@ skl_update_plane(struct intel_plane *plane,
>>   
>>   	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> +	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
>>   		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
>>   			      plane_state->color_ctl);
>>   	if (key->flags) {
>> @@ -865,7 +865,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>>   	struct drm_rect *src = &state->base.src;
>>   	struct drm_rect *dst = &state->base.dst;
>>   	struct drm_rect clip = {};
>> -	int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
>> +	int max_stride = IS_GEN_GTE(dev_priv, 9) ? 32768 : 16384;
>>   	int hscale, vscale;
>>   	int max_scale, min_scale;
>>   	bool can_scale;
>> @@ -892,7 +892,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>>   	}
>>   
>>   	/* setup can_scale, min_scale, max_scale */
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		/* use scaler when colorkey is not required */
>>   		if (!state->ckey.flags) {
>>   			can_scale = 1;
>> @@ -1012,8 +1012,8 @@ intel_check_sprite_plane(struct intel_plane *plane,
>>   
>>   		width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
>>   
>> -		if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
>> -		    width_bytes > 4096 || fb->pitches[0] > 4096)) {
>> +		if (IS_GEN_LT(dev_priv, 9) && (src_w > 2048 || src_h > 2048 ||
>> +					       width_bytes > 4096 || fb->pitches[0] > 4096)) {
>>   			DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
>>   			return -EINVAL;
>>   		}
>> @@ -1031,7 +1031,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>>   	dst->y1 = crtc_y;
>>   	dst->y2 = crtc_y + crtc_h;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		ret = skl_check_plane_surface(crtc_state, state);
>>   		if (ret)
>>   			return ret;
>> @@ -1043,7 +1043,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>>   			return ret;
>>   
>>   		state->ctl = vlv_sprite_ctl(crtc_state, state);
>> -	} else if (INTEL_GEN(dev_priv) >= 7) {
>> +	} else if (IS_GEN_GTE(dev_priv, 7)) {
>>   		ret = i9xx_check_plane_surface(state);
>>   		if (ret)
>>   			return ret;
>> @@ -1057,7 +1057,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>>   		state->ctl = g4x_sprite_ctl(crtc_state, state);
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> +	if (IS_GEN_GTE(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
>>   		state->color_ctl = glk_plane_color_ctl(crtc_state, state);
>>   
>>   	return 0;
>> @@ -1290,11 +1290,11 @@ static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
>>   	    modifier != DRM_FORMAT_MOD_LINEAR)
>>   		return false;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		return skl_mod_supported(format, modifier);
>>   	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>>   		return vlv_mod_supported(format, modifier);
>> -	else if (INTEL_GEN(dev_priv) >= 6)
>> +	else if (IS_GEN_GTE(dev_priv, 6))
>>   		return snb_mod_supported(format, modifier);
>>   	else
>>   		return g4x_mod_supported(format, modifier);
>> @@ -1317,7 +1317,7 @@ bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
>>   	if (plane_id == PLANE_CURSOR)
>>   		return false;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 10)
>> +	if (IS_GEN_GTE(dev_priv, 10))
>>   		return true;
>>   
>>   	if (IS_GEMINILAKE(dev_priv))
>> @@ -1354,7 +1354,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>>   	}
>>   	intel_plane->base.state = &state->base;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		intel_plane->can_scale = true;
>>   		state->scaler_id = -1;
>>   
>> @@ -1380,7 +1380,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>>   		plane_formats = vlv_plane_formats;
>>   		num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
>>   		modifiers = i9xx_plane_format_modifiers;
>> -	} else if (INTEL_GEN(dev_priv) >= 7) {
>> +	} else if (IS_GEN_GTE(dev_priv, 7)) {
>>   		if (IS_IVYBRIDGE(dev_priv)) {
>>   			intel_plane->can_scale = true;
>>   			intel_plane->max_downscale = 2;
>> @@ -1414,7 +1414,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>>   		}
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		supported_rotations =
>>   			DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
>>   			DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
>> @@ -1435,7 +1435,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>>   
>>   	possible_crtcs = (1 << pipe);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9)
>> +	if (IS_GEN_GTE(dev_priv, 9))
>>   		ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
>>   					       possible_crtcs, &intel_sprite_plane_funcs,
>>   					       plane_formats, num_plane_formats,
>> diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
>> index b3dabc219e6a..e9bed89cc1f7 100644
>> --- a/drivers/gpu/drm/i915/intel_tv.c
>> +++ b/drivers/gpu/drm/i915/intel_tv.c
>> @@ -1067,7 +1067,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
>>   
>>   	set_color_conversion(dev_priv, color_conversion);
>>   
>> -	if (INTEL_GEN(dev_priv) >= 4)
>> +	if (IS_GEN_GTE(dev_priv, 4))
>>   		I915_WRITE(TV_CLR_KNOBS, 0x00404000);
>>   	else
>>   		I915_WRITE(TV_CLR_KNOBS, 0x00606000);
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index 73959ae56241..4ae72c2f1921 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -435,7 +435,7 @@ u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
>>   	/* The needed capability bits for size calculation
>>   	 * are not there with pre gen9 so return 128MB always.
>>   	 */
>> -	if (INTEL_GEN(dev_priv) < 9)
>> +	if (IS_GEN_LT(dev_priv, 9))
>>   		return 128 * 1024 * 1024;
>>   
>>   	return gen9_edram_size(dev_priv);
>> @@ -445,7 +445,7 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
>>   {
>>   	if (IS_HASWELL(dev_priv) ||
>>   	    IS_BROADWELL(dev_priv) ||
>> -	    INTEL_GEN(dev_priv) >= 9) {
>> +	    IS_GEN_GTE(dev_priv, 9)) {
>>   		dev_priv->edram_cap = __raw_i915_read32(dev_priv,
>>   							HSW_EDRAM_CAP);
>>   
>> @@ -837,7 +837,7 @@ find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
>>   	{ .start = (s), .end = (e), .domains = (d) }
>>   
>>   #define HAS_FWTABLE(dev_priv) \
>> -	(INTEL_GEN(dev_priv) >= 9 || \
>> +	(IS_GEN_GTE(dev_priv, 9) || \
>>   	 IS_CHERRYVIEW(dev_priv) || \
>>   	 IS_VALLEYVIEW(dev_priv))
>>   
>> @@ -1253,7 +1253,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
>>   
>>   static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>>   {
>> -	if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
>> +	if (IS_GEN_LTE(dev_priv, 5) || intel_vgpu_active(dev_priv))
>>   		return;
>>   
>>   	if (IS_GEN6(dev_priv)) {
>> @@ -1267,7 +1267,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>>   		dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
>>   	}
>>   
>> -	if (INTEL_GEN(dev_priv) >= 9) {
>> +	if (IS_GEN_GTE(dev_priv, 9)) {
>>   		dev_priv->uncore.funcs.force_wake_get =
>>   			fw_domains_get_with_fallback;
>>   		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
>> @@ -1541,7 +1541,7 @@ static void i915_stop_engines(struct drm_i915_private *dev_priv,
>>   	struct intel_engine_cs *engine;
>>   	enum intel_engine_id id;
>>   
>> -	if (INTEL_GEN(dev_priv) < 3)
>> +	if (IS_GEN_LT(dev_priv, 3))
>>   		return;
>>   
>>   	for_each_engine_masked(engine, dev_priv, engine_mask, id)
>> @@ -1874,9 +1874,9 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
>>   	if (!i915_modparams.reset)
>>   		return NULL;
>>   
>> -	if (INTEL_GEN(dev_priv) >= 8)
>> +	if (IS_GEN_GTE(dev_priv, 8))
>>   		return gen8_reset_engines;
>> -	else if (INTEL_GEN(dev_priv) >= 6)
>> +	else if (IS_GEN_GTE(dev_priv, 6))
>>   		return gen6_reset_engines;
>>   	else if (IS_GEN5(dev_priv))
>>   		return ironlake_do_reset;
>> @@ -1884,7 +1884,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
>>   		return g4x_do_reset;
>>   	else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
>>   		return g33_do_reset;
>> -	else if (INTEL_GEN(dev_priv) >= 3)
>> +	else if (IS_GEN_GTE(dev_priv, 3))
>>   		return i915_do_reset;
>>   	else
>>   		return NULL;
>> @@ -1987,7 +1987,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
>>   
>>   	if (HAS_FWTABLE(dev_priv)) {
>>   		fw_domains = __fwtable_reg_read_fw_domains(offset);
>> -	} else if (INTEL_GEN(dev_priv) >= 6) {
>> +	} else if (IS_GEN_GTE(dev_priv, 6)) {
>>   		fw_domains = __gen6_reg_read_fw_domains(offset);
>>   	} else {
>>   		WARN_ON(!IS_GEN(dev_priv, 2, 5));
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
>> index 7a0d1e17c1ad..8deed5569b7a 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
>> @@ -204,12 +204,12 @@ static int gpu_set(struct drm_i915_gem_object *obj,
>>   		return PTR_ERR(cs);
>>   	}
>>   
>> -	if (INTEL_GEN(i915) >= 8) {
>> +	if (IS_GEN_GTE(i915, 8)) {
>>   		*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
>>   		*cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset);
>>   		*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
>>   		*cs++ = v;
>> -	} else if (INTEL_GEN(i915) >= 4) {
>> +	} else if (IS_GEN_GTE(i915, 4)) {
>>   		*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
>>   		*cs++ = 0;
>>   		*cs++ = i915_ggtt_offset(vma) + offset;
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
>> index 56a803d11916..12ec7b39ce77 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
>> @@ -159,7 +159,7 @@ static int gpu_fill(struct drm_i915_gem_object *obj,
>>   	}
>>   
>>   	flags = 0;
>> -	if (INTEL_GEN(vm->i915) <= 5)
>> +	if (IS_GEN_LTE(vm->i915, 5))
>>   		flags |= I915_DISPATCH_SECURE;
>>   
>>   	err = engine->emit_bb_start(rq,
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
>> index f32aa6bb79e2..2c8f500ed7f7 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
>> @@ -355,7 +355,7 @@ static int igt_partial_tiling(void *arg)
>>   		    tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17)
>>   			continue;
>>   
>> -		if (INTEL_GEN(i915) <= 2) {
>> +		if (IS_GEN_LTE(i915, 2)) {
>>   			tile.height = 16;
>>   			tile.width = 128;
>>   			tile.size = 11;
>> @@ -370,9 +370,9 @@ static int igt_partial_tiling(void *arg)
>>   			tile.size = 12;
>>   		}
>>   
>> -		if (INTEL_GEN(i915) < 4)
>> +		if (IS_GEN_LT(i915, 4))
>>   			max_pitch = 8192 / tile.width;
>> -		else if (INTEL_GEN(i915) < 7)
>> +		else if (IS_GEN_LT(i915, 7))
>>   			max_pitch = 128 * I965_FENCE_MAX_PITCH_VAL / tile.width;
>>   		else
>>   			max_pitch = 128 * GEN7_FENCE_MAX_PITCH_VAL / tile.width;
>> @@ -385,7 +385,7 @@ static int igt_partial_tiling(void *arg)
>>   			if (err)
>>   				goto out_unlock;
>>   
>> -			if (pitch > 2 && INTEL_GEN(i915) >= 4) {
>> +			if (pitch > 2 && IS_GEN_GTE(i915, 4)) {
>>   				tile.stride = tile.width * (pitch - 1);
>>   				err = check_partial_mapping(obj, &tile, end);
>>   				if (err == -EINTR)
>> @@ -394,7 +394,7 @@ static int igt_partial_tiling(void *arg)
>>   					goto out_unlock;
>>   			}
>>   
>> -			if (pitch < max_pitch && INTEL_GEN(i915) >= 4) {
>> +			if (pitch < max_pitch && IS_GEN_GTE(i915, 4)) {
>>   				tile.stride = tile.width * (pitch + 1);
>>   				err = check_partial_mapping(obj, &tile, end);
>>   				if (err == -EINTR)
>> @@ -404,7 +404,7 @@ static int igt_partial_tiling(void *arg)
>>   			}
>>   		}
>>   
>> -		if (INTEL_GEN(i915) >= 4) {
>> +		if (IS_GEN_GTE(i915, 4)) {
>>   			for_each_prime_number(pitch, max_pitch) {
>>   				tile.stride = tile.width * pitch;
>>   				err = check_partial_mapping(obj, &tile, end);
>> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
>> index d1d2c2456f69..92bc059a78f4 100644
>> --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
>> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
>> @@ -136,7 +136,7 @@ static int emit_recurse_batch(struct hang *h,
>>   	}
>>   
>>   	batch = h->batch;
>> -	if (INTEL_GEN(i915) >= 8) {
>> +	if (IS_GEN_GTE(i915, 8)) {
>>   		*batch++ = MI_STORE_DWORD_IMM_GEN4;
>>   		*batch++ = lower_32_bits(hws_address(hws, rq));
>>   		*batch++ = upper_32_bits(hws_address(hws, rq));
>> @@ -150,7 +150,7 @@ static int emit_recurse_batch(struct hang *h,
>>   		*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
>>   		*batch++ = lower_32_bits(vma->node.start);
>>   		*batch++ = upper_32_bits(vma->node.start);
>> -	} else if (INTEL_GEN(i915) >= 6) {
>> +	} else if (IS_GEN_GTE(i915, 6)) {
>>   		*batch++ = MI_STORE_DWORD_IMM_GEN4;
>>   		*batch++ = 0;
>>   		*batch++ = lower_32_bits(hws_address(hws, rq));
>> @@ -163,7 +163,7 @@ static int emit_recurse_batch(struct hang *h,
>>   		*batch++ = MI_ARB_CHECK;
>>   		*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
>>   		*batch++ = lower_32_bits(vma->node.start);
>> -	} else if (INTEL_GEN(i915) >= 4) {
>> +	} else if (IS_GEN_GTE(i915, 4)) {
>>   		*batch++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
>>   		*batch++ = 0;
>>   		*batch++ = lower_32_bits(hws_address(hws, rq));
>> @@ -193,7 +193,7 @@ static int emit_recurse_batch(struct hang *h,
>>   	i915_gem_chipset_flush(h->i915);
>>   
>>   	flags = 0;
>> -	if (INTEL_GEN(vm->i915) <= 5)
>> +	if (IS_GEN_LTE(vm->i915, 5))
>>   		flags |= I915_DISPATCH_SECURE;
>>   
>>   	err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
>> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
>> index 2f6367643171..7177f97e72ef 100644
>> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
>> @@ -173,7 +173,7 @@ int intel_uncore_live_selftests(struct drm_i915_private *i915)
>>   	/* Confirm the table we load is still valid */
>>   	err = intel_fw_table_check(i915->uncore.fw_domains_table,
>>   				   i915->uncore.fw_domains_table_entries,
>> -				   INTEL_GEN(i915) >= 9);
>> +				   IS_GEN_GTE(i915, 9));
>>   	if (err)
>>   		return err;
>>   
>> -- 
>> 2.14.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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Re: [RFC 14/15] drm/i915: Use new IS_GEN range helpers

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-08 14:34:38)
> 
> On 08/02/2018 14:22, Ville Syrjälä wrote:
> > On Thu, Feb 08, 2018 at 01:06:05PM +0000, Tvrtko Ursulin wrote:
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> Coccinelle transformation:
> >>
> >>   @@
> >>   expression p, g;
> >>   @@
> >>   (
> >>   -INTEL_GEN(p) > g
> >>   +IS_GEN_GT(p, g)
> > 
> > I think this stuff makes the code pretty close to illegible.
> > In this particular case even more so because "GT" actually
> > means something very different to us.
> 
> Oh how true! And I did not realize it at all while writing it! :)
> 
> Anyway, something like this, regardless of a name, is needed if people 
> want this to be effective. Since the checks have to be moved to known at 
> compile time. Or a completely different approach will be needed.

IS_GEN_RANGE() doesn't cut it?

I think that people find it inconvenient to use, so some sugar is still
required.
-Chris
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Re: [RFC 14/15] drm/i915: Use new IS_GEN range helpers

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Tvrtko Ursulin (2018-02-08 14:34:38)
>> 
>> On 08/02/2018 14:22, Ville Syrjälä wrote:
>> > On Thu, Feb 08, 2018 at 01:06:05PM +0000, Tvrtko Ursulin wrote:
>> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> >>
>> >> Coccinelle transformation:
>> >>
>> >>   @@
>> >>   expression p, g;
>> >>   @@
>> >>   (
>> >>   -INTEL_GEN(p) > g
>> >>   +IS_GEN_GT(p, g)
>> > 
>> > I think this stuff makes the code pretty close to illegible.
>> > In this particular case even more so because "GT" actually
>> > means something very different to us.
>> 
>> Oh how true! And I did not realize it at all while writing it! :)
>> 
>> Anyway, something like this, regardless of a name, is needed if people 
>> want this to be effective. Since the checks have to be moved to known at 
>> compile time. Or a completely different approach will be needed.
>
> IS_GEN_RANGE() doesn't cut it?
>

IS_GEN_RANGE(8,9);

short and readable

and

IS_GEN_RANGE(6, ANY);

?

-Mika

> I think that people find it inconvenient to use, so some sugar is still
> required.
> -Chris
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Re: [RFC 14/15] drm/i915: Use new IS_GEN range helpers

[Ville Syrjälä]

On Thu, Feb 08, 2018 at 05:13:02PM +0200, Mika Kuoppala wrote:
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > Quoting Tvrtko Ursulin (2018-02-08 14:34:38)
> >> 
> >> On 08/02/2018 14:22, Ville Syrjälä wrote:
> >> > On Thu, Feb 08, 2018 at 01:06:05PM +0000, Tvrtko Ursulin wrote:
> >> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> >>
> >> >> Coccinelle transformation:
> >> >>
> >> >>   @@
> >> >>   expression p, g;
> >> >>   @@
> >> >>   (
> >> >>   -INTEL_GEN(p) > g
> >> >>   +IS_GEN_GT(p, g)
> >> > 
> >> > I think this stuff makes the code pretty close to illegible.
> >> > In this particular case even more so because "GT" actually
> >> > means something very different to us.
> >> 
> >> Oh how true! And I did not realize it at all while writing it! :)
> >> 
> >> Anyway, something like this, regardless of a name, is needed if people 
> >> want this to be effective. Since the checks have to be moved to known at 
> >> compile time. Or a completely different approach will be needed.
> >
> > IS_GEN_RANGE() doesn't cut it?
> >
> 
> IS_GEN_RANGE(8,9);
> 
> short and readable

'if (IS_GEN_RANGE(...))' reads funny. IS_GEN_IN_RANGE() would be more
englishy perhaps, but it looks a bit off to me for whatever reason.

And it still doesn't tell you anything about inclusive vs. exlusive.
So it just forces you to waste brain cells on mundane details when
reading the code. IMO that's a fairly bad tradeoff.

-- 
Ville Syrjälä
Intel OTC
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Re: [RFC 14/15] drm/i915: Use new IS_GEN range helpers

[Jani Nikula]

On Thu, 08 Feb 2018, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Feb 08, 2018 at 05:13:02PM +0200, Mika Kuoppala wrote:
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>> 
>> > Quoting Tvrtko Ursulin (2018-02-08 14:34:38)
>> >> 
>> >> On 08/02/2018 14:22, Ville Syrjälä wrote:
>> >> > On Thu, Feb 08, 2018 at 01:06:05PM +0000, Tvrtko Ursulin wrote:
>> >> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> >> >>
>> >> >> Coccinelle transformation:
>> >> >>
>> >> >>   @@
>> >> >>   expression p, g;
>> >> >>   @@
>> >> >>   (
>> >> >>   -INTEL_GEN(p) > g
>> >> >>   +IS_GEN_GT(p, g)
>> >> > 
>> >> > I think this stuff makes the code pretty close to illegible.
>> >> > In this particular case even more so because "GT" actually
>> >> > means something very different to us.
>> >> 
>> >> Oh how true! And I did not realize it at all while writing it! :)
>> >> 
>> >> Anyway, something like this, regardless of a name, is needed if people 
>> >> want this to be effective. Since the checks have to be moved to known at 
>> >> compile time. Or a completely different approach will be needed.
>> >
>> > IS_GEN_RANGE() doesn't cut it?
>> >
>> 
>> IS_GEN_RANGE(8,9);
>> 
>> short and readable
>
> 'if (IS_GEN_RANGE(...))' reads funny. IS_GEN_IN_RANGE() would be more
> englishy perhaps, but it looks a bit off to me for whatever reason.

We already have IS_GEN(dev_priv, start, end) for inclusive ranges with
GEN_FOREVER as unbound start/end. There's no need to bikeshed the naming
further. (Except perhaps the GEN_FOREVER part.)

With some macro vararg hacking, we could probably make that work for
IS_GEN(dev_priv, exact) too, to replace say IS_GEN5() with one macro if
we like. Just to make more code use similar constructs.

> And it still doesn't tell you anything about inclusive vs. exlusive.
> So it just forces you to waste brain cells on mundane details when
> reading the code. IMO that's a fairly bad tradeoff.

Agreed. I think this patch is by far the worst part in the
series. Especially the _GT, _GTE, _LT, _LTE macros are IMO unacceptable.

Quick greping shows that we have much more inclusive than exclusive
range checks. We could help our brains a bit by switching, uh,
exclusively to inclusive ranges. That's not perfect, by far, as some
checks naturally work better with < and >, but I think I'd rather have
that with IS_GEN() than a bunch of macros you have to stop to think
about.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [RFC 14/15] drm/i915: Use new IS_GEN range helpers

[Ville Syrjälä]

On Fri, Feb 09, 2018 at 01:18:49PM +0200, Jani Nikula wrote:
> On Thu, 08 Feb 2018, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Thu, Feb 08, 2018 at 05:13:02PM +0200, Mika Kuoppala wrote:
> >> Chris Wilson <chris@chris-wilson.co.uk> writes:
> >> 
> >> > Quoting Tvrtko Ursulin (2018-02-08 14:34:38)
> >> >> 
> >> >> On 08/02/2018 14:22, Ville Syrjälä wrote:
> >> >> > On Thu, Feb 08, 2018 at 01:06:05PM +0000, Tvrtko Ursulin wrote:
> >> >> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> >> >>
> >> >> >> Coccinelle transformation:
> >> >> >>
> >> >> >>   @@
> >> >> >>   expression p, g;
> >> >> >>   @@
> >> >> >>   (
> >> >> >>   -INTEL_GEN(p) > g
> >> >> >>   +IS_GEN_GT(p, g)
> >> >> > 
> >> >> > I think this stuff makes the code pretty close to illegible.
> >> >> > In this particular case even more so because "GT" actually
> >> >> > means something very different to us.
> >> >> 
> >> >> Oh how true! And I did not realize it at all while writing it! :)
> >> >> 
> >> >> Anyway, something like this, regardless of a name, is needed if people 
> >> >> want this to be effective. Since the checks have to be moved to known at 
> >> >> compile time. Or a completely different approach will be needed.
> >> >
> >> > IS_GEN_RANGE() doesn't cut it?
> >> >
> >> 
> >> IS_GEN_RANGE(8,9);
> >> 
> >> short and readable
> >
> > 'if (IS_GEN_RANGE(...))' reads funny. IS_GEN_IN_RANGE() would be more
> > englishy perhaps, but it looks a bit off to me for whatever reason.
> 
> We already have IS_GEN(dev_priv, start, end) for inclusive ranges with
> GEN_FOREVER as unbound start/end. There's no need to bikeshed the naming
> further. (Except perhaps the GEN_FOREVER part.)
> 
> With some macro vararg hacking, we could probably make that work for
> IS_GEN(dev_priv, exact) too, to replace say IS_GEN5() with one macro if
> we like. Just to make more code use similar constructs.
> 
> > And it still doesn't tell you anything about inclusive vs. exlusive.
> > So it just forces you to waste brain cells on mundane details when
> > reading the code. IMO that's a fairly bad tradeoff.
> 
> Agreed. I think this patch is by far the worst part in the
> series. Especially the _GT, _GTE, _LT, _LTE macros are IMO unacceptable.
> 
> Quick greping shows that we have much more inclusive than exclusive
> range checks.

I think the usual pattern has been inclusive start, exclusive end. That
can help you think in terms of "this is when the feature appeared, and
this is when it disappeared". But if it's hidden in a macro then I
think exclusive might end up being rather confusing.

> We could help our brains a bit by switching, uh,
> exclusively to inclusive ranges. That's not perfect, by far, as some
> checks naturally work better with < and >, but I think I'd rather have
> that with IS_GEN() than a bunch of macros you have to stop to think
> about.

If only the compiler would be smart and be able to see that something
like

#define INTEL_GEN(dev_priv) (ilog2((dev_priv)->gen_mask & CONFIG_GEN_MASK))

if (INTEL_GEN(dev_priv) < 8)
	...

can never be true...

Not sure it can't actually. But I assume people have actually tried
that.

-- 
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Intel OTC
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Re: [RFC 14/15] drm/i915: Use new IS_GEN range helpers

[Chris Wilson]

Quoting Ville Syrjälä (2018-02-09 14:48:43)
> If only the compiler would be smart and be able to see that something
> like
> 
> #define INTEL_GEN(dev_priv) (ilog2((dev_priv)->gen_mask & CONFIG_GEN_MASK))
> 
> if (INTEL_GEN(dev_priv) < 8)
>         ...
> 
> can never be true...
> 
> Not sure it can't actually. But I assume people have actually tried
> that.

gcc-7 doesn't appear to be that smart. :(
add/remove: 5/6 grow/shrink: 246/26 up/down: 10387/-3793 (6594)
-Chris
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Re: [RFC 14/15] drm/i915: Use new IS_GEN range helpers

[Ville Syrjälä]

On Fri, Feb 09, 2018 at 04:48:43PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 09, 2018 at 01:18:49PM +0200, Jani Nikula wrote:
> > On Thu, 08 Feb 2018, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > > On Thu, Feb 08, 2018 at 05:13:02PM +0200, Mika Kuoppala wrote:
> > >> Chris Wilson <chris@chris-wilson.co.uk> writes:
> > >> 
> > >> > Quoting Tvrtko Ursulin (2018-02-08 14:34:38)
> > >> >> 
> > >> >> On 08/02/2018 14:22, Ville Syrjälä wrote:
> > >> >> > On Thu, Feb 08, 2018 at 01:06:05PM +0000, Tvrtko Ursulin wrote:
> > >> >> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > >> >> >>
> > >> >> >> Coccinelle transformation:
> > >> >> >>
> > >> >> >>   @@
> > >> >> >>   expression p, g;
> > >> >> >>   @@
> > >> >> >>   (
> > >> >> >>   -INTEL_GEN(p) > g
> > >> >> >>   +IS_GEN_GT(p, g)
> > >> >> > 
> > >> >> > I think this stuff makes the code pretty close to illegible.
> > >> >> > In this particular case even more so because "GT" actually
> > >> >> > means something very different to us.
> > >> >> 
> > >> >> Oh how true! And I did not realize it at all while writing it! :)
> > >> >> 
> > >> >> Anyway, something like this, regardless of a name, is needed if people 
> > >> >> want this to be effective. Since the checks have to be moved to known at 
> > >> >> compile time. Or a completely different approach will be needed.
> > >> >
> > >> > IS_GEN_RANGE() doesn't cut it?
> > >> >
> > >> 
> > >> IS_GEN_RANGE(8,9);
> > >> 
> > >> short and readable
> > >
> > > 'if (IS_GEN_RANGE(...))' reads funny. IS_GEN_IN_RANGE() would be more
> > > englishy perhaps, but it looks a bit off to me for whatever reason.
> > 
> > We already have IS_GEN(dev_priv, start, end) for inclusive ranges with
> > GEN_FOREVER as unbound start/end. There's no need to bikeshed the naming
> > further. (Except perhaps the GEN_FOREVER part.)
> > 
> > With some macro vararg hacking, we could probably make that work for
> > IS_GEN(dev_priv, exact) too, to replace say IS_GEN5() with one macro if
> > we like. Just to make more code use similar constructs.
> > 
> > > And it still doesn't tell you anything about inclusive vs. exlusive.
> > > So it just forces you to waste brain cells on mundane details when
> > > reading the code. IMO that's a fairly bad tradeoff.
> > 
> > Agreed. I think this patch is by far the worst part in the
> > series. Especially the _GT, _GTE, _LT, _LTE macros are IMO unacceptable.
> > 
> > Quick greping shows that we have much more inclusive than exclusive
> > range checks.
> 
> I think the usual pattern has been inclusive start, exclusive end. That
> can help you think in terms of "this is when the feature appeared, and
> this is when it disappeared". But if it's hidden in a macro then I
> think exclusive might end up being rather confusing.
> 
> > We could help our brains a bit by switching, uh,
> > exclusively to inclusive ranges. That's not perfect, by far, as some
> > checks naturally work better with < and >, but I think I'd rather have
> > that with IS_GEN() than a bunch of macros you have to stop to think
> > about.
> 
> If only the compiler would be smart and be able to see that something
> like
> 
> #define INTEL_GEN(dev_priv) (ilog2((dev_priv)->gen_mask & CONFIG_GEN_MASK))
> 
> if (INTEL_GEN(dev_priv) < 8)
> 	...
> 
> can never be true...
> 
> Not sure it can't actually. But I assume people have actually tried
> that.

Hmm...

#define IS_GEN(dev_priv, expr) ((ilog2(GEN_MASK) expr) && \
                                (ilog2((dev_priv)->gen_mask expr)))

if (IS_GEN(dev_priv, >= 8))
	...

Would something like that actually work?

-- 
Ville Syrjälä
Intel OTC
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Re: [RFC 14/15] drm/i915: Use new IS_GEN range helpers

[Chris Wilson]

Quoting Ville Syrjälä (2018-02-09 15:12:58)
> On Fri, Feb 09, 2018 at 04:48:43PM +0200, Ville Syrjälä wrote:
> > On Fri, Feb 09, 2018 at 01:18:49PM +0200, Jani Nikula wrote:
> > > On Thu, 08 Feb 2018, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > > > On Thu, Feb 08, 2018 at 05:13:02PM +0200, Mika Kuoppala wrote:
> > > >> Chris Wilson <chris@chris-wilson.co.uk> writes:
> > > >> 
> > > >> > Quoting Tvrtko Ursulin (2018-02-08 14:34:38)
> > > >> >> 
> > > >> >> On 08/02/2018 14:22, Ville Syrjälä wrote:
> > > >> >> > On Thu, Feb 08, 2018 at 01:06:05PM +0000, Tvrtko Ursulin wrote:
> > > >> >> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > >> >> >>
> > > >> >> >> Coccinelle transformation:
> > > >> >> >>
> > > >> >> >>   @@
> > > >> >> >>   expression p, g;
> > > >> >> >>   @@
> > > >> >> >>   (
> > > >> >> >>   -INTEL_GEN(p) > g
> > > >> >> >>   +IS_GEN_GT(p, g)
> > > >> >> > 
> > > >> >> > I think this stuff makes the code pretty close to illegible.
> > > >> >> > In this particular case even more so because "GT" actually
> > > >> >> > means something very different to us.
> > > >> >> 
> > > >> >> Oh how true! And I did not realize it at all while writing it! :)
> > > >> >> 
> > > >> >> Anyway, something like this, regardless of a name, is needed if people 
> > > >> >> want this to be effective. Since the checks have to be moved to known at 
> > > >> >> compile time. Or a completely different approach will be needed.
> > > >> >
> > > >> > IS_GEN_RANGE() doesn't cut it?
> > > >> >
> > > >> 
> > > >> IS_GEN_RANGE(8,9);
> > > >> 
> > > >> short and readable
> > > >
> > > > 'if (IS_GEN_RANGE(...))' reads funny. IS_GEN_IN_RANGE() would be more
> > > > englishy perhaps, but it looks a bit off to me for whatever reason.
> > > 
> > > We already have IS_GEN(dev_priv, start, end) for inclusive ranges with
> > > GEN_FOREVER as unbound start/end. There's no need to bikeshed the naming
> > > further. (Except perhaps the GEN_FOREVER part.)
> > > 
> > > With some macro vararg hacking, we could probably make that work for
> > > IS_GEN(dev_priv, exact) too, to replace say IS_GEN5() with one macro if
> > > we like. Just to make more code use similar constructs.
> > > 
> > > > And it still doesn't tell you anything about inclusive vs. exlusive.
> > > > So it just forces you to waste brain cells on mundane details when
> > > > reading the code. IMO that's a fairly bad tradeoff.
> > > 
> > > Agreed. I think this patch is by far the worst part in the
> > > series. Especially the _GT, _GTE, _LT, _LTE macros are IMO unacceptable.
> > > 
> > > Quick greping shows that we have much more inclusive than exclusive
> > > range checks.
> > 
> > I think the usual pattern has been inclusive start, exclusive end. That
> > can help you think in terms of "this is when the feature appeared, and
> > this is when it disappeared". But if it's hidden in a macro then I
> > think exclusive might end up being rather confusing.
> > 
> > > We could help our brains a bit by switching, uh,
> > > exclusively to inclusive ranges. That's not perfect, by far, as some
> > > checks naturally work better with < and >, but I think I'd rather have
> > > that with IS_GEN() than a bunch of macros you have to stop to think
> > > about.
> > 
> > If only the compiler would be smart and be able to see that something
> > like
> > 
> > #define INTEL_GEN(dev_priv) (ilog2((dev_priv)->gen_mask & CONFIG_GEN_MASK))
> > 
> > if (INTEL_GEN(dev_priv) < 8)
> >       ...
> > 
> > can never be true...
> > 
> > Not sure it can't actually. But I assume people have actually tried
> > that.
> 
> Hmm...
> 
> #define IS_GEN(dev_priv, expr) ((ilog2(GEN_MASK) expr) && \
>                                 (ilog2((dev_priv)->gen_mask expr)))
> 
> if (IS_GEN(dev_priv, >= 8))
>         ...
> 
> Would something like that actually work?

There are a few ways in which we could map gen to 0 if the platform
wasn't enabled at build time, but I haven't a better approach than
Tvrtko's replacement of INTEL_GEN() with IS_GENx() or IS_GEN(x, y). The
biggest problem with just mapping gen to 0 comes in then we need to add
the 0 case to many if-else chains and switches (it makes writing
IS_GEN(i915, < 8) hard as well) but worse it's hard to do it in a way
that doesn't result in the compiler emitting instructions rather than
resolving it at compile time.

Still doesn't look pretty, and we need some more surgery (some static
tables pulling in function references need pruning) and LTO.

Doing build tests is easy enough, I hope we can get CI to do
per-platform builds (as I think those are more likely to show errors).
-Chris
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[RFC 15/15] drm/i915: Replace some negative Gen checks

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Instead of INTEL_GEN != x use !IS_GENx for more optimisation
opportunities.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 37421fe4c0a3..41674aedbd2a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7551,7 +7551,7 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
 {
 	unsigned long val;
 
-	if (INTEL_GEN(dev_priv) != 5)
+	if (!IS_GEN5(dev_priv))
 		return 0;
 
 	spin_lock_irq(&mchdev_lock);
@@ -7635,7 +7635,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
 
 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) != 5)
+	if (!IS_GEN5(dev_priv))
 		return;
 
 	spin_lock_irq(&mchdev_lock);
@@ -7686,7 +7686,7 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
 {
 	unsigned long val;
 
-	if (INTEL_GEN(dev_priv) != 5)
+	if (!IS_GEN5(dev_priv))
 		return 0;
 
 	spin_lock_irq(&mchdev_lock);
-- 
2.14.1

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Re: [RFC 15/15] drm/i915: Replace some negative Gen checks

[Jani Nikula]

On Thu, 08 Feb 2018, Tvrtko Ursulin <tursulin@ursulin.net> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Instead of INTEL_GEN != x use !IS_GENx for more optimisation
> opportunities.

This could be upstreamed outside of this series.

BR,
Jani.

>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 37421fe4c0a3..41674aedbd2a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7551,7 +7551,7 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
>  {
>  	unsigned long val;
>  
> -	if (INTEL_GEN(dev_priv) != 5)
> +	if (!IS_GEN5(dev_priv))
>  		return 0;
>  
>  	spin_lock_irq(&mchdev_lock);
> @@ -7635,7 +7635,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
>  
>  void i915_update_gfx_val(struct drm_i915_private *dev_priv)
>  {
> -	if (INTEL_GEN(dev_priv) != 5)
> +	if (!IS_GEN5(dev_priv))
>  		return;
>  
>  	spin_lock_irq(&mchdev_lock);
> @@ -7686,7 +7686,7 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
>  {
>  	unsigned long val;
>  
> -	if (INTEL_GEN(dev_priv) != 5)
> +	if (!IS_GEN5(dev_priv))
>  		return 0;
>  
>  	spin_lock_irq(&mchdev_lock);

-- 
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Re: [RFC 15/15] drm/i915: Replace some negative Gen checks

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-08 13:06:06)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Instead of INTEL_GEN != x use !IS_GENx for more optimisation
> opportunities.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [RFC 00/15] Selectable platform support

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-08 13:05:51)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> For Joonas basically. :)
> 
> Rough goal - add Kconfig options to turn off supported platforms and count on
> compiler DCE to make the driver smaller.
> 
> Tested as so much that it boots and renders on Skylake with all platforms/gens
> older than Gen8 turned off.
> 
>    text    data     bss     dec     hex filename
> 1502847   54223    2888 1559958  17cd96 i915.ko.original
> 1375647   51939    2888 1430474  15d3ca i915.ko.gen8+
> 
> So only ~124kiB saving. Or ~8.5%. Perhaps once GCC LTO support lands it would be
> better than this?

Did you get to the point where the compiler was complaining about unused
functions?
 
> Starts with smaller patches to show the idea step by step on Gen2, then proceeds
> in larger chunks, to finish with some invasive Coccinelle works to enable the
> last few kilo-bytes of savings.

So, if we want to support this, how do we test it?

Do a per-platform build and check modinfo for pci ids?

Limit the CI builds to be per-platform and check they work?
-Chris
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Re: [RFC 00/15] Selectable platform support

[Tvrtko Ursulin]

On 08/02/2018 13:26, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-02-08 13:05:51)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> For Joonas basically. :)
>>
>> Rough goal - add Kconfig options to turn off supported platforms and count on
>> compiler DCE to make the driver smaller.
>>
>> Tested as so much that it boots and renders on Skylake with all platforms/gens
>> older than Gen8 turned off.
>>
>>     text    data     bss     dec     hex filename
>> 1502847   54223    2888 1559958  17cd96 i915.ko.original
>> 1375647   51939    2888 1430474  15d3ca i915.ko.gen8+
>>
>> So only ~124kiB saving. Or ~8.5%. Perhaps once GCC LTO support lands it would be
>> better than this?
> 
> Did you get to the point where the compiler was complaining about unused
> functions?

No, but on a random check it seems that it is removing some. For 
instance i965_emit_bb_start and i830_emit_bb_start are not in my build.

Doesn't mean I haven't made some other mistake which is preventing more 
savings.

>> Starts with smaller patches to show the idea step by step on Gen2, then proceeds
>> in larger chunks, to finish with some invasive Coccinelle works to enable the
>> last few kilo-bytes of savings.
> 
> So, if we want to support this, how do we test it?
> 
> Do a per-platform build and check modinfo for pci ids?
> 
> Limit the CI builds to be per-platform and check they work?

Extensively. :) Which will probably be a problem. PCI ids is not enough, 
I think it would actually need functional testing so a growth of number 
of builds we would need to test.

Regards,

Tvrtko
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Re: [RFC 00/15] Selectable platform support

[Joonas Lahtinen]

Quoting Tvrtko Ursulin (2018-02-08 16:06:41)
> 
> On 08/02/2018 13:26, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-02-08 13:05:51)
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> For Joonas basically. :)
> >>
> >> Rough goal - add Kconfig options to turn off supported platforms and count on
> >> compiler DCE to make the driver smaller.
> >>
> >> Tested as so much that it boots and renders on Skylake with all platforms/gens
> >> older than Gen8 turned off.
> >>
> >>     text    data     bss     dec     hex filename
> >> 1502847   54223    2888 1559958  17cd96 i915.ko.original
> >> 1375647   51939    2888 1430474  15d3ca i915.ko.gen8+
> >>
> >> So only ~124kiB saving. Or ~8.5%. Perhaps once GCC LTO support lands it would be
> >> better than this?
> > 
> > Did you get to the point where the compiler was complaining about unused
> > functions?
> 
> No, but on a random check it seems that it is removing some. For 
> instance i965_emit_bb_start and i830_emit_bb_start are not in my build.
> 
> Doesn't mean I haven't made some other mistake which is preventing more 
> savings.
> 
> >> Starts with smaller patches to show the idea step by step on Gen2, then proceeds
> >> in larger chunks, to finish with some invasive Coccinelle works to enable the
> >> last few kilo-bytes of savings.
> > 
> > So, if we want to support this, how do we test it?
> > 
> > Do a per-platform build and check modinfo for pci ids?
> > 
> > Limit the CI builds to be per-platform and check they work?
> 
> Extensively. :) Which will probably be a problem. PCI ids is not enough, 
> I think it would actually need functional testing so a growth of number 
> of builds we would need to test.

My original suggestion was to be able to "pre-select the PCI ID" and let
the compiler do the magic with LTO to get rid of the dead code. You
would test by comparing the "include all" and "one PCI ID" kernel
operation on same system. I'm assuming that the feature would be a
useful non-default to opt-in to similarly to a "targeted" initrd.

Regards, Joonas

> 
> Regards,
> 
> Tvrtko
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [RFC 00/15] Selectable platform support

[Jani Nikula]

On Thu, 08 Feb 2018, Joonas Lahtinen <joonas.lahtinen@linux.intel.com> wrote:
> Quoting Tvrtko Ursulin (2018-02-08 16:06:41)
>> 
>> On 08/02/2018 13:26, Chris Wilson wrote:
>> > Quoting Tvrtko Ursulin (2018-02-08 13:05:51)
>> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> >>
>> >> For Joonas basically. :)
>> >>
>> >> Rough goal - add Kconfig options to turn off supported platforms
>> >> and count on compiler DCE to make the driver smaller.
>> >>
>> >> Tested as so much that it boots and renders on Skylake with all
>> >> platforms/gens older than Gen8 turned off.
>> >>
>> >>     text    data     bss     dec     hex filename
>> >> 1502847   54223    2888 1559958  17cd96 i915.ko.original
>> >> 1375647   51939    2888 1430474  15d3ca i915.ko.gen8+
>> >>
>> >> So only ~124kiB saving. Or ~8.5%. Perhaps once GCC LTO support
>> >> lands it would be better than this?
>> > 
>> > Did you get to the point where the compiler was complaining about
>> > unused functions?
>> 
>> No, but on a random check it seems that it is removing some. For
>> instance i965_emit_bb_start and i830_emit_bb_start are not in my
>> build.
>> 
>> Doesn't mean I haven't made some other mistake which is preventing
>> more savings.
>> 
>> >> Starts with smaller patches to show the idea step by step on Gen2,
>> >> then proceeds in larger chunks, to finish with some invasive
>> >> Coccinelle works to enable the last few kilo-bytes of savings.
>> > 
>> > So, if we want to support this, how do we test it?
>> > 
>> > Do a per-platform build and check modinfo for pci ids?
>> > 
>> > Limit the CI builds to be per-platform and check they work?
>> 
>> Extensively. :) Which will probably be a problem. PCI ids is not
>> enough, I think it would actually need functional testing so a growth
>> of number of builds we would need to test.
>
> My original suggestion was to be able to "pre-select the PCI ID" and
> let the compiler do the magic with LTO to get rid of the dead
> code. You would test by comparing the "include all" and "one PCI ID"
> kernel operation on same system. I'm assuming that the feature would
> be a useful non-default to opt-in to similarly to a "targeted" initrd.

So I can imagine someone shipping a specific product with a specific
platform (or even PCI ID) could use this. Beyond that, who would use
this? Some rare enthusiasts?

Is there any way a general purpose distro could use it? I guess only by
building several drivers with different options (and names) that would
have different PCI ID matches.

The increased testing requirements are not to be taken lightly. We need
to have pretty good rationale for the CI team before just dropping this
on them to test.


BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [RFC 00/15] Selectable platform support

[Chris Wilson]

Quoting Jani Nikula (2018-02-09 11:49:16)
> On Thu, 08 Feb 2018, Joonas Lahtinen <joonas.lahtinen@linux.intel.com> wrote:
> > Quoting Tvrtko Ursulin (2018-02-08 16:06:41)
> >> 
> >> On 08/02/2018 13:26, Chris Wilson wrote:
> >> > Quoting Tvrtko Ursulin (2018-02-08 13:05:51)
> >> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> >>
> >> >> For Joonas basically. :)
> >> >>
> >> >> Rough goal - add Kconfig options to turn off supported platforms
> >> >> and count on compiler DCE to make the driver smaller.
> >> >>
> >> >> Tested as so much that it boots and renders on Skylake with all
> >> >> platforms/gens older than Gen8 turned off.
> >> >>
> >> >>     text    data     bss     dec     hex filename
> >> >> 1502847   54223    2888 1559958  17cd96 i915.ko.original
> >> >> 1375647   51939    2888 1430474  15d3ca i915.ko.gen8+
> >> >>
> >> >> So only ~124kiB saving. Or ~8.5%. Perhaps once GCC LTO support
> >> >> lands it would be better than this?
> >> > 
> >> > Did you get to the point where the compiler was complaining about
> >> > unused functions?
> >> 
> >> No, but on a random check it seems that it is removing some. For
> >> instance i965_emit_bb_start and i830_emit_bb_start are not in my
> >> build.
> >> 
> >> Doesn't mean I haven't made some other mistake which is preventing
> >> more savings.
> >> 
> >> >> Starts with smaller patches to show the idea step by step on Gen2,
> >> >> then proceeds in larger chunks, to finish with some invasive
> >> >> Coccinelle works to enable the last few kilo-bytes of savings.
> >> > 
> >> > So, if we want to support this, how do we test it?
> >> > 
> >> > Do a per-platform build and check modinfo for pci ids?
> >> > 
> >> > Limit the CI builds to be per-platform and check they work?
> >> 
> >> Extensively. :) Which will probably be a problem. PCI ids is not
> >> enough, I think it would actually need functional testing so a growth
> >> of number of builds we would need to test.
> >
> > My original suggestion was to be able to "pre-select the PCI ID" and
> > let the compiler do the magic with LTO to get rid of the dead
> > code. You would test by comparing the "include all" and "one PCI ID"
> > kernel operation on same system. I'm assuming that the feature would
> > be a useful non-default to opt-in to similarly to a "targeted" initrd.
> 
> So I can imagine someone shipping a specific product with a specific
> platform (or even PCI ID) could use this. Beyond that, who would use
> this? Some rare enthusiasts?
> 
> Is there any way a general purpose distro could use it? I guess only by
> building several drivers with different options (and names) that would
> have different PCI ID matches.

The way I see this effort scaling to general purpose distros is
basically with a flock of modules (or a fat module with disposable
.sections). I'm a few steps sort of $profit.
-Chris
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✗ Fi.CI.BAT: failure for Selectable platform support

[Patchwork]

== Series Details ==

Series: Selectable platform support
URL   : https://patchwork.freedesktop.org/series/37912/
State : failure

== Summary ==

Applying: drm/i915: Make I830 platform support optional
Applying: drm/i915: Make I845G platform support optional
Applying: drm/i915: Make I85X platform support optional
Applying: drm/i915: Make I865G platform support optional
Applying: drm/i915: Make GEN2 support optional
Applying: drm/i915: Make Gen3 platforms support optional
Applying: drm/i915: Make Gen4 platforms support optional
Applying: drm/i915: Make Ironlake/Gen5 platforms support optional
Applying: drm/i915: Make Sandybridge/Gen6 platforms support optional
Applying: drm/i915: Make Gen7/7.5 platform support optional
Applying: drm/i915: Use INTEL_GEN everywhere
Applying: drm/i915: Favour IS_GENx
Applying: drm/i915: IS_GEN range helpers
Applying: drm/i915: Use new IS_GEN range helpers
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_drv.h).
error: could not build fake ancestor
Patch failed at 0014 drm/i915: Use new IS_GEN range helpers
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [RFC 00/15] Selectable platform support

[Tvrtko Ursulin]

On 08/02/2018 13:05, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> For Joonas basically. :)
> 
> Rough goal - add Kconfig options to turn off supported platforms and count on
> compiler DCE to make the driver smaller.
> 
> Tested as so much that it boots and renders on Skylake with all platforms/gens
> older than Gen8 turned off.
> 
>     text    data     bss     dec     hex filename
> 1502847   54223    2888 1559958  17cd96 i915.ko.original
> 1375647   51939    2888 1430474  15d3ca i915.ko.gen8+

I've finished this today (all platforms plus some more details and 
changes) but wont' post it again. Instead who is interested can see it 
in my freedesktop git repo - people.freedesktop.org/~tursulin/drm-intel 
platform-kconfig - but for some reason it is not showing in GitWeb any 
longer.

Anyway.. with the latest build the i915.ko size goes from 15600073 to 
1256697 when I enable only Skylake via Kconfig. This is 296kiB and close 
to 20% saving.

Regards,

Tvrtko
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Re: [RFC 00/15] Selectable platform support

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-09 10:48:23)
> 
> On 08/02/2018 13:05, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > 
> > For Joonas basically. :)
> > 
> > Rough goal - add Kconfig options to turn off supported platforms and count on
> > compiler DCE to make the driver smaller.
> > 
> > Tested as so much that it boots and renders on Skylake with all platforms/gens
> > older than Gen8 turned off.
> > 
> >     text    data     bss     dec     hex filename
> > 1502847   54223    2888 1559958  17cd96 i915.ko.original
> > 1375647   51939    2888 1430474  15d3ca i915.ko.gen8+
> 
> I've finished this today (all platforms plus some more details and 
> changes) but wont' post it again. Instead who is interested can see it 
> in my freedesktop git repo - people.freedesktop.org/~tursulin/drm-intel 
> platform-kconfig - but for some reason it is not showing in GitWeb any 
> longer.
> 
> Anyway.. with the latest build the i915.ko size goes from 15600073 to 
> 1256697 when I enable only Skylake via Kconfig. This is 296kiB and close 
> to 20% saving.

Could you post ./scripts/bloat-o-meter?
-Chris
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Re: [RFC 00/15] Selectable platform support

[Tvrtko Ursulin]

On 09/02/18 10:50, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-02-09 10:48:23)
>>
>> On 08/02/2018 13:05, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>> For Joonas basically. :)
>>>
>>> Rough goal - add Kconfig options to turn off supported platforms and count on
>>> compiler DCE to make the driver smaller.
>>>
>>> Tested as so much that it boots and renders on Skylake with all platforms/gens
>>> older than Gen8 turned off.
>>>
>>>      text    data     bss     dec     hex filename
>>> 1502847   54223    2888 1559958  17cd96 i915.ko.original
>>> 1375647   51939    2888 1430474  15d3ca i915.ko.gen8+
>>
>> I've finished this today (all platforms plus some more details and
>> changes) but wont' post it again. Instead who is interested can see it
>> in my freedesktop git repo - people.freedesktop.org/~tursulin/drm-intel
>> platform-kconfig - but for some reason it is not showing in GitWeb any
>> longer.
>>
>> Anyway.. with the latest build the i915.ko size goes from 15600073 to
>> 1256697 when I enable only Skylake via Kconfig. This is 296kiB and close
>> to 20% saving.
> 
> Could you post ./scripts/bloat-o-meter?

It's big:

add/remove: 20/813 grow/shrink: 119/355 up/down: 20178/-247867 (-227689)
Function                                     old     new   delta
vlv_wm_sanitize                              419    1752   +1333
vlv_force_pll_on                             340    1465   +1125
cnl_set_cdclk.isra                             -     956    +956
i9xx_crtc_compute_clock                      237    1174    +937
g4x_wm_sanitize                              389    1283    +894
bxt_set_cdclk.isra                             -     853    +853
gen6_set_rps                                 406    1172    +766
i915_read_mch_val                             73     783    +710
broadwell_load_luts                          490    1116    +626
intel_set_pipe_timings.isra                    -     573    +573
gen8_irq_reset                               704    1260    +556
g4x_pre_enable_dp                            399     925    +526
ironlake_crtc_compute_clock                  902    1413    +511
intel_dp_init_panel_power_sequencer_registers.constprop       -     492    +492
bxt_find_best_dpll                            25     491    +466
g4x_enable_dp                                 31     480    +449
intel_cpu_transcoder_get_m_n.isra              -     397    +397
i965_irq_handler                             503     898    +395
i965_write_fence_reg.isra                      -     350    +350
intel_cpu_transcoder_set_m_n.isra              -     349    +349
ilk_wm_merge.isra                              -     348    +348
intel_dp_set_drrs_state.isra                   -     344    +344
__intel_adjust_tile_offset.constprop           -     309    +309
skl_init_clock_gating                        116     410    +294
_intel_compute_tile_offset.isra                -     273    +273
i9xx_update_cursor                           611     862    +251
gen8_check_and_clear_faults                    -     235    +235
ironlake_irq_reset                           236     453    +217
i9xx_check_cursor                            497     708    +211
intel_tile_width_bytes.isra                    -     201    +201
intel_hdmi_pre_enable                        124     314    +190
gen9_init_indirectctx_bb                     368     554    +186
gen8_oa_read                                1196    1378    +182
ironlake_irq_postinstall                     221     400    +179
ilk_compute_wm_level.isra                    651     827    +176
valleyview_enable_display_irqs                49     221    +172
intel_setup_gmbus                            729     897    +168
i915_gem_restore_gtt_mappings                494     654    +160
hdmi_port_clock_limit                          -     149    +149
skl_modeset_calc_cdclk                       292     429    +137
vlv_force_pll_off                             24     157    +133
intel_atomic_check                          4471    4602    +131
gen8_reset_engines                           280     405    +125
i8xx_fbc_deactivate                            -     121    +121
intel_PLL_is_valid.isra                        -     118    +118
hsw_fdi_link_train                           972    1087    +115
gen8_irq_handler                            1566    1676    +110
bxt_signal_levels                             97     203    +106
intel_engine_cleanup_cmd_parser               20     124    +104
i915_gem_init_swizzling.part                   -     101    +101
skl_ddi_set_iboost                           452     552    +100
intel_teardown_gmbus                          63     154     +91
intel_gmbus_get_adapter                       74     165     +91
i9xx_crtc_enable                            1041    1120     +79
gen8_irq_postinstall                         837     911     +74
ilk_fbc_deactivate                             -      62     +62
ilk_hpd_irq_setup                            430     487     +57
intel_hdmi_mode_valid                        237     291     +54
i915_gem_object_pin_pages                      -      53     +53
check_for_unclaimed_mmio.part                  -      49     +49
intel_fbc_deactivate                          85     128     +43
execlists_submission_tasklet                3601    3639     +38
intel_update_crtc                            127     164     +37
hsw_disable_pc8                              699     734     +35
skl_plane_stride                             104     131     +27
i9xx_pipe_crc_irq_handler                    344     370     +26
ilk_compute_wm_maximums                      150     174     +24
i915_pmu_event_init                          252     275     +23
intel_fb_align_height                         32      54     +22
intel_uncore_arm_unclaimed_mmio_detection      90     111     +21
intel_gpu_reset                              475     493     +18
snb_update_pm_irq                            163     179     +16
skl_get_buf_trans_dp                          92     107     +15
intel_has_gpu_reset                           17      30     +13
intel_uncore_unclaimed_mmio                   10      22     +12
i965_irq_postinstall                         269     281     +12
i915_gem_render_state_emit                  1676    1688     +12
__unclaimed_reg_debug                         83      93     +10
intel_disable_shared_dpll                    277     286      +9
gen6_disable_pm_irq                           71      80      +9
intel_modeset_vga_set_state                  201     209      +8
intel_dump_pipe_config                      1606    1614      +8
intel_dp_get_config                          645     653      +8
intel_crt_set_dpms                           253     261      +8
i915_gem_restore_fences                      271     279      +8
gen9_enable_guc_interrupts                   254     262      +8
gen6_reset_pm_iir                             90      98      +8
gen6_enable_rps_interrupts                   201     209      +8
gen6_enable_pm_irq                            67      75      +8
fence_update                                 612     620      +8
skl_set_cdclk                               1214    1221      +7
intel_edp_drrs_invalidate                    161     168      +7
intel_edp_drrs_flush                         229     236      +7
intel_edp_drrs_downclock_work                111     118      +7
i915_llc                                     127     134      +7
hsw_psr_enable_sink                          477     483      +6
ironlake_get_pipe_config                     729     734      +5
intel_edp_drrs_disable                       153     158      +5
intel_dp_get_m_n                             221     226      +5
spr_wm_latency_write                          44      48      +4
spr_wm_latency_show                           40      44      +4
pri_wm_latency_write                          44      48      +4
pri_wm_latency_show                           40      44      +4
intel_engine_is_idle                         287     291      +4
intel_begin_crtc_commit                      402     406      +4
haswell_crtc_disable                         312     316      +4
cur_wm_latency_write                          44      48      +4
cur_wm_latency_show                           40      44      +4
cnl_uninit_cdclk                              88      92      +4
intel_guc_init_params                        933     936      +3
stop_ring                                    337     339      +2
skl_update_scaler                            473     475      +2
sandybridge_pcode_write_timeout              537     539      +2
sandybridge_pcode_read                       538     540      +2
lspcon_init                                  467     469      +2
ironlake_enable_vblank                        99     101      +2
ironlake_disable_vblank                       96      98      +2
intel_psr_enable                             326     328      +2
intel_pin_and_fence_fb_obj                   326     328      +2
intel_engine_get_last_batch_head             169     171      +2
intel_engine_cleanup                         141     143      +2
intel_crt_reset                              138     140      +2
intel_bios_is_lspcon_present                 123     125      +2
i9xx_load_csc_matrix                        1534    1536      +2
i9xx_disable_plane                           195     197      +2
i915_rps_boost_info                          865     867      +2
i915_gem_sanitize                            116     118      +2
i915_gem_reset                               215     217      +2
i915_gem_request_alloc                      1478    1480      +2
i915_gem_object_wait_fence                   254     256      +2
i915_gem_idle_work_handler                   531     533      +2
i915_gem_fence_alignment                      54      56      +2
gmbus_wait_idle                              206     208      +2
gmbus_wait                                   550     552      +2
gen8_init_common_ring                        237     239      +2
gen6_rps_irq_handler                         211     213      +2
display_pipe_crc_irq_handler                 509     511      +2
bxt_uninit_cdclk                              89      91      +2
i915_gem_suspend_gtt_mappings                 59      60      +1
intel_uncore_forcewake_user_put              131     130      -1
haswell_crtc_enable                         1980    1979      -1
gen9_enable_dc5                              406     405      -1
vlv_pipe_to_channel.part                       2       -      -2
verify_wm_state                             1050    1048      -2
gen8_enable_metric_set                       184     182      -2
skl_init_cdclk                               373     370      -3
intel_hdmi_compute_config                   1091    1088      -3
intel_sdvo_dvi_init                          499     495      -4
vlv_enable_hdmi                                6       -      -6
skl_plane_ctl                                737     731      -6
skl_check_pipe_max_pixel_rate                881     875      -6
lpe_audio_irq_unmask                           6       -      -6
lpe_audio_irq_mask                             6       -      -6
div_4800                                       6       -      -6
skl_plane_has_ccs                             50      43      -7
skl_max_scale.part                           137     130      -7
show_media_rc6_ms                              7       -      -7
intel_gmbus_is_valid_pin                     130     123      -7
pineview_display_wm                            8       -      -8
pineview_display_hplloff_wm                    8       -      -8
pineview_cursor_wm                             8       -      -8
pineview_cursor_hplloff_wm                     8       -      -8
intel_prepare_reset                          298     290      -8
intel_dsi_host_detach                          8       -      -8
intel_dsi_host_attach                          8       -      -8
i945_wm_info                                   8       -      -8
i915_wm_info                                   8       -      -8
i845_wm_info                                   8       -      -8
i830_bc_wm_info                                8       -      -8
i830_a_wm_info                                 8       -      -8
skl_disable_dc6                              112     103      -9
intel_dp_set_m_n                             256     247      -9
i9xx_check_plane_surface                     217     208      -9
i915_forcewake_release                        42      33      -9
i915_forcewake_open                           42      33      -9
i915_fbc_false_color_set                     131     122      -9
i915_fbc_false_color_get                      42      33      -9
i915_disable_vga                             118     109      -9
i915_audio_component_codec_wake_override     200     191      -9
div_5333                                       9       -      -9
div_4000                                       9       -      -9
div_3200                                       9       -      -9
vlv_post_disable_dp                           10       -     -10
vlv_hdmi_post_disable                         10       -     -10
i915_gmch_remove                              10       -     -10
i915_gem_fence_size                          175     165     -10
gmch_ggtt_invalidate                          10       -     -10
gen7_mm_switch                                10       -     -10
chv_hdmi_post_pll_disable                     10       -     -10
chv_dp_post_pll_disable                       10       -     -10
vlv_pipe_any                                  11       -     -11
intel_crt_get_modes                          137     126     -11
i9xx_get_backlight                           111     100     -11
vlv_power_well_disable                        12       -     -12
fixed_450mhz_get_cdclk                        12       -     -12
fixed_400mhz_get_cdclk                        12       -     -12
fixed_333mhz_get_cdclk                        12       -     -12
fixed_266mhz_get_cdclk                        12       -     -12
fixed_200mhz_get_cdclk                        12       -     -12
bxt_stepping_info                             12       -     -12
add_rps_boost_after_vblank                   189     177     -12
set_data                                     118     105     -13
set_clock                                    112      99     -13
intel_overlay_attrs_ioctl                   1002     989     -13
intel_finish_crtc_commit                     170     157     -13
i915_gem_execbuffer                          650     637     -13
bxt_dpio_cmn_power_well_enabled               13       -     -13
bxt_dpio_cmn_power_well_enable                13       -     -13
bxt_dpio_cmn_power_well_disable               13       -     -13
i915_redisable_vga_power_on                  102      88     -14
i845_disable_cursor                           14       -     -14
vlv_power_well_enable                         15       -     -15
intel_uncore_edram_size                       37      22     -15
i915_min_freq_get                             45      30     -15
i915_max_freq_get                             45      30     -15
gen6_pm_rps_work                             712     697     -15
assert_pipe                                  336     321     -15
snb_b_fdi_train_param                         16       -     -16
media_rc6_attrs                               16       -     -16
intel_tv_pre_enable                         1804    1788     -16
intel_set_rps                                110      93     -17
intel_get_cagf                                46      29     -17
intel_engine_get_active_head                 178     161     -17
bxt_ddi_pre_pll_enable                        17       -     -17
__intel_get_crtc_scanline                    452     434     -18
is_hdcp_supported                             45      26     -19
i9xx_set_backlight                           209     190     -19
i915_drrs_ctl_set                            429     410     -19
get_data                                     133     114     -19
get_clock                                    133     114     -19
gen5_irq_enable                               19       -     -19
gen5_irq_disable                              19       -     -19
ddi_signal_levels                            102      83     -19
bxt_hz_to_pwm                                 19       -     -19
skl_update_plane                            1058    1038     -20
intel_gmch_panel_fitting                     656     636     -20
intel_crt_init                               744     724     -20
i915_pipestat_enable_mask                    246     226     -20
gen8_null_state_relocs                        20       -     -20
gen7_null_state_relocs                        20       -     -20
gen5_seqno_barrier                            20       -     -20
__warned                                      92      72     -20
i915_ddb_info                                312     291     -21
chv_private_pat_match                         21       -     -21
bxt_ddi_phy_verify_state                     498     477     -21
ilk_wm_max_level                              51      29     -22
bxt_ddi_phy_init                             116      94     -22
intel_ring_context_pin                       813     790     -23
intel_hpd_pin_default                         99      76     -23
i915_energy_uJ                               220     197     -23
fw_domains_get_with_thread_status             23       -     -23
edp_have_panel_vdd                            85      62     -23
edp_have_panel_power                          82      59     -23
cnl_init_cdclk                               366     343     -23
snb_plane_formats                             24       -     -24
intel_plane_disable_noatomic                 251     227     -24
intel_gpio_pre_xfer                           85      61     -24
intel_dsi_host_ops                            24       -     -24
i965_primary_formats                          24       -     -24
i915_ggtt_enable_hw                           32       8     -24
i915_ggtt_clear_range                         24       -     -24
hsw_master_regs                               24       -     -24
gen8_null_state                               24       -     -24
gen7_null_state                               24       -     -24
gen6_null_state_relocs                        24       -     -24
gen6_null_state                               24       -     -24
cnl_pll_mgr                                   24       -     -24
bxt_pll_mgr                                   24       -     -24
broxton_mocs_table                            24       -     -24
vlv_get_backlight                             25       -     -25
intel_print_wm_latency                       228     203     -25
intel_engine_create_ring                     378     353     -25
gen7_oa_hw_tail_read                          25       -     -25
gen7_oa_disable                               26       -     -26
reloc_gpu_flush                              251     224     -27
pri_wm_latency_open                           57      30     -27
intel_ddi_enable_transcoder_func             393     366     -27
i915_min_freq_set                            232     205     -27
i915_max_freq_set                            232     205     -27
intel_hdmi_init                              555     527     -28
intel_dp_is_port_edp                          38      10     -28
intel_ddi_compute_min_voltage_level           34       6     -28
bxt_rates                                     28       -     -28
vlv_pipe_has_pp_on                            29       -     -29
intel_sprite_set_colorkey                    334     305     -29
intel_hdmi_get_hw_state                      180     151     -29
intel_dsi_enable_nop                          29       -     -29
ilk_plane_wm_max                             227     198     -29
i830_init_clock_gating                        29       -     -29
execlists_init_reg_state.isra               1291    1262     -29
wait_for_pipe_scanline_moving                373     343     -30
intel_tv_detect                             1214    1184     -30
intel_overlay_off_tail                        77      47     -30
ilk_compute_intermediate_wm                  497     467     -30
i830_pipes_power_well_disable                 30       -     -30
bxt_ddi_phy_uninit                           194     164     -30
assert_pch_dp_disabled                       284     254     -30
__intel_uncore_early_sanitize                109      79     -30
vlv_hdmi_pre_pll_enable                       31       -     -31
vlv_dp_pre_pll_enable                         31       -     -31
gen6_sema_emit_breadcrumb                     31       -     -31
g4x_plane_fifo_size.part                      31       -     -31
chv_hdmi_pre_pll_enable                       31       -     -31
chv_dp_pre_pll_enable                         31       -     -31
vlv_dpio_power_well_ops                       32       -     -32
vlv_dpio_cmn_power_well_ops                   32       -     -32
vlv_display_power_well_ops                    32       -     -32
pnv_vco                                       32       -     -32
ivb_render_reg_tables                         32       -     -32
ivb_blt_reg_tables                            32       -     -32
intel_legacy_cursor_update                  1273    1241     -32
intel_dsi_funcs                               32       -     -32
i915_perf_add_config_ioctl                  1131    1099     -32
i830_pipes_power_well_ops                     32       -     -32
hsw_vebox_cmds                                32       -     -32
hsw_blt_reg_tables                            32       -     -32
gen9_sanitize_dc_state                       105      73     -32
gen7_video_cmds                               32       -     -32
gen7_render_cmds                              32       -     -32
gen7_blt_cmds                                 32       -     -32
elk_vco                                       32       -     -32
dev_attr_vlv_rpe_freq_mhz                     32       -     -32
dev_attr_media_rc6_residency_ms               32       -     -32
ctg_vco                                       32       -     -32
cnl_rates                                     32       -     -32
cnl_ddi_pll_funcs                             32       -     -32
cl_vco                                        32       -     -32
chv_pipe_power_well_ops                       32       -     -32
chv_dpio_cmn_power_well_ops                   32       -     -32
bxt_dpio_cmn_power_well_ops                   32       -     -32
bxt_ddi_pll_funcs                             32       -     -32
blb_vco                                       32       -     -32
vlv_display_irq_reset                        337     304     -33
intel_guc_wopcm_size                          44      11     -33
i9xx_hz_to_pwm                                65      32     -33
i915_ggtt_insert_page                         33       -     -33
hsw_pte_encode                                33       -     -33
intel_gpio_post_xfer                          67      33     -34
bxt_ddi_phy_is_enabled                       284     250     -34
vlv_pipe_has_vdd_on                           35       -     -35
intel_plane_atomic_check_with_state          506     471     -35
intel_enable_sagv                            262     227     -35
intel_dsi_encoder_destroy                     35       -     -35
intel_disable_sagv                           270     235     -35
intel_crtc_set_crc_source                    484     449     -35
cnl_ddi_translations_hdmi_0_85V               35       -     -35
ilk_audio_codec_disable                      313     277     -36
hpd_status_g4x                                36       -     -36
hpd_bxt                                       36       -     -36
cnl_dump_hw_state                             36       -     -36
intel_engine_can_store_dword                  48      11     -37
intel_csr_load_program                       475     438     -37
intel_init_bsd_ring_buffer                   142     104     -38
intel_dp_mst_compute_config                  416     378     -38
i915_teardown_sysfs                          149     111     -38
i915_gem_object_pin_to_display_plane         288     250     -38
gen10_is_valid_mux_addr                       38       -     -38
assert_pch_hdmi_disabled                     252     214     -38
intel_uncore_forcewake_reset                 565     526     -39
media_rc6_attr_group                          40       -     -40
i915_gem_object_create.part                  391     351     -40
hsw_read_dcomp                                40       -     -40
vlv_pre_enable_dp                             41       -     -41
ironlake_pfit_enable                         189     148     -41
intel_prepare_plane_fb                      1026     985     -41
intel_crt_mode_valid                         139      98     -41
i915_ggtt_insert_entries                      41       -     -41
i915_getparam                                605     564     -41
i915_gem_object_get_pages_phys               634     593     -41
gt_act_freq_mhz_show                         179     138     -41
skl_pipe_wm_get_hw_state                     491     449     -42
pwm_get_backlight                             42       -     -42
intel_pps_readout_hw_state                   327     285     -42
intel_atomic_commit_tail                    3242    3200     -42
i915_pmu_register                           1441    1399     -42
i915_driver_cleanup_mmio                     206     164     -42
i830_pipes_power_well_sync_hw                 42       -     -42
gen6_initialize_pt.isra                       42       -     -42
intel_surf_alignment.isra                    154     111     -43
intel_enable_ddi                             651     608     -43
intel_dsi_vbt_init                          2228    2185     -43
intel_dp_voltage_max                         108      65     -43
vlv_plane_formats                             44       -     -44
i915_get_crtc_scanoutpos                     564     520     -44
i915_gem_set_caching_ioctl                   495     451     -44
guc_fw_xfer                                 1093    1049     -44
gen4_render_ring_flush                       147     103     -44
byt_pte_encode                                44       -     -44
bxt_vtd_ggtt_insert_entries__BKL              44       -     -44
__UNIQUE_ID_alias99                           44       -     -44
__UNIQUE_ID_alias98                           44       -     -44
__UNIQUE_ID_alias97                           44       -     -44
__UNIQUE_ID_alias96                           44       -     -44
__UNIQUE_ID_alias95                           44       -     -44
__UNIQUE_ID_alias94                           44       -     -44
__UNIQUE_ID_alias93                           44       -     -44
__UNIQUE_ID_alias92                           44       -     -44
__UNIQUE_ID_alias91                           44       -     -44
__UNIQUE_ID_alias90                           44       -     -44
__UNIQUE_ID_alias89                           44       -     -44
__UNIQUE_ID_alias88                           44       -     -44
__UNIQUE_ID_alias87                           44       -     -44
__UNIQUE_ID_alias86                           44       -     -44
__UNIQUE_ID_alias85                           44       -     -44
__UNIQUE_ID_alias84                           44       -     -44
__UNIQUE_ID_alias83                           44       -     -44
__UNIQUE_ID_alias82                           44       -     -44
__UNIQUE_ID_alias81                           44       -     -44
__UNIQUE_ID_alias80                           44       -     -44
__UNIQUE_ID_alias79                           44       -     -44
__UNIQUE_ID_alias78                           44       -     -44
__UNIQUE_ID_alias77                           44       -     -44
__UNIQUE_ID_alias76                           44       -     -44
__UNIQUE_ID_alias75                           44       -     -44
__UNIQUE_ID_alias74                           44       -     -44
__UNIQUE_ID_alias73                           44       -     -44
__UNIQUE_ID_alias72                           44       -     -44
__UNIQUE_ID_alias71                           44       -     -44
__UNIQUE_ID_alias70                           44       -     -44
__UNIQUE_ID_alias69                           44       -     -44
__UNIQUE_ID_alias68                           44       -     -44
__UNIQUE_ID_alias67                           44       -     -44
__UNIQUE_ID_alias66                           44       -     -44
__UNIQUE_ID_alias65                           44       -     -44
__UNIQUE_ID_alias64                           44       -     -44
__UNIQUE_ID_alias63                           44       -     -44
__UNIQUE_ID_alias62                           44       -     -44
__UNIQUE_ID_alias61                           44       -     -44
__UNIQUE_ID_alias60                           44       -     -44
__UNIQUE_ID_alias59                           44       -     -44
__UNIQUE_ID_alias58                           44       -     -44
__UNIQUE_ID_alias57                           44       -     -44
__UNIQUE_ID_alias56                           44       -     -44
__UNIQUE_ID_alias55                           44       -     -44
__UNIQUE_ID_alias54                           44       -     -44
__UNIQUE_ID_alias53                           44       -     -44
__UNIQUE_ID_alias52                           44       -     -44
__UNIQUE_ID_alias51                           44       -     -44
__UNIQUE_ID_alias49                           44       -     -44
__UNIQUE_ID_alias48                           44       -     -44
__UNIQUE_ID_alias47                           44       -     -44
__UNIQUE_ID_alias46                           44       -     -44
__UNIQUE_ID_alias45                           44       -     -44
__UNIQUE_ID_alias44                           44       -     -44
__UNIQUE_ID_alias43                           44       -     -44
__UNIQUE_ID_alias42                           44       -     -44
__UNIQUE_ID_alias41                           44       -     -44
__UNIQUE_ID_alias40                           44       -     -44
__UNIQUE_ID_alias39                           44       -     -44
__UNIQUE_ID_alias38                           44       -     -44
__UNIQUE_ID_alias37                           44       -     -44
__UNIQUE_ID_alias36                           44       -     -44
__UNIQUE_ID_alias35                           44       -     -44
__UNIQUE_ID_alias34                           44       -     -44
__UNIQUE_ID_alias231                          44       -     -44
__UNIQUE_ID_alias230                          44       -     -44
__UNIQUE_ID_alias229                          44       -     -44
__UNIQUE_ID_alias228                          44       -     -44
__UNIQUE_ID_alias227                          44       -     -44
__UNIQUE_ID_alias226                          44       -     -44
__UNIQUE_ID_alias225                          44       -     -44
__UNIQUE_ID_alias224                          44       -     -44
__UNIQUE_ID_alias223                          44       -     -44
__UNIQUE_ID_alias222                          44       -     -44
__UNIQUE_ID_alias221                          44       -     -44
__UNIQUE_ID_alias220                          44       -     -44
__UNIQUE_ID_alias219                          44       -     -44
__UNIQUE_ID_alias218                          44       -     -44
__UNIQUE_ID_alias217                          44       -     -44
__UNIQUE_ID_alias216                          44       -     -44
__UNIQUE_ID_alias215                          44       -     -44
__UNIQUE_ID_alias214                          44       -     -44
__UNIQUE_ID_alias213                          44       -     -44
__UNIQUE_ID_alias212                          44       -     -44
__UNIQUE_ID_alias211                          44       -     -44
__UNIQUE_ID_alias210                          44       -     -44
__UNIQUE_ID_alias209                          44       -     -44
__UNIQUE_ID_alias208                          44       -     -44
__UNIQUE_ID_alias207                          44       -     -44
__UNIQUE_ID_alias206                          44       -     -44
__UNIQUE_ID_alias205                          44       -     -44
__UNIQUE_ID_alias204                          44       -     -44
__UNIQUE_ID_alias203                          44       -     -44
__UNIQUE_ID_alias202                          44       -     -44
__UNIQUE_ID_alias201                          44       -     -44
__UNIQUE_ID_alias200                          44       -     -44
__UNIQUE_ID_alias199                          44       -     -44
__UNIQUE_ID_alias198                          44       -     -44
__UNIQUE_ID_alias197                          44       -     -44
__UNIQUE_ID_alias196                          44       -     -44
__UNIQUE_ID_alias195                          44       -     -44
__UNIQUE_ID_alias194                          44       -     -44
__UNIQUE_ID_alias193                          44       -     -44
__UNIQUE_ID_alias192                          44       -     -44
__UNIQUE_ID_alias191                          44       -     -44
__UNIQUE_ID_alias190                          44       -     -44
__UNIQUE_ID_alias189                          44       -     -44
__UNIQUE_ID_alias188                          44       -     -44
__UNIQUE_ID_alias187                          44       -     -44
__UNIQUE_ID_alias186                          44       -     -44
__UNIQUE_ID_alias185                          44       -     -44
__UNIQUE_ID_alias184                          44       -     -44
__UNIQUE_ID_alias183                          44       -     -44
__UNIQUE_ID_alias182                          44       -     -44
__UNIQUE_ID_alias181                          44       -     -44
__UNIQUE_ID_alias180                          44       -     -44
__UNIQUE_ID_alias179                          44       -     -44
__UNIQUE_ID_alias178                          44       -     -44
__UNIQUE_ID_alias177                          44       -     -44
__UNIQUE_ID_alias176                          44       -     -44
__UNIQUE_ID_alias175                          44       -     -44
__UNIQUE_ID_alias174                          44       -     -44
__UNIQUE_ID_alias173                          44       -     -44
__UNIQUE_ID_alias172                          44       -     -44
__UNIQUE_ID_alias171                          44       -     -44
__UNIQUE_ID_alias170                          44       -     -44
__UNIQUE_ID_alias169                          44       -     -44
__UNIQUE_ID_alias168                          44       -     -44
__UNIQUE_ID_alias167                          44       -     -44
__UNIQUE_ID_alias166                          44       -     -44
__UNIQUE_ID_alias165                          44       -     -44
__UNIQUE_ID_alias164                          44       -     -44
__UNIQUE_ID_alias163                          44       -     -44
__UNIQUE_ID_alias162                          44       -     -44
__UNIQUE_ID_alias161                          44       -     -44
__UNIQUE_ID_alias160                          44       -     -44
__UNIQUE_ID_alias159                          44       -     -44
__UNIQUE_ID_alias158                          44       -     -44
__UNIQUE_ID_alias157                          44       -     -44
__UNIQUE_ID_alias156                          44       -     -44
__UNIQUE_ID_alias155                          44       -     -44
__UNIQUE_ID_alias154                          44       -     -44
__UNIQUE_ID_alias153                          44       -     -44
__UNIQUE_ID_alias152                          44       -     -44
__UNIQUE_ID_alias151                          44       -     -44
__UNIQUE_ID_alias150                          44       -     -44
__UNIQUE_ID_alias149                          44       -     -44
__UNIQUE_ID_alias148                          44       -     -44
__UNIQUE_ID_alias147                          44       -     -44
__UNIQUE_ID_alias146                          44       -     -44
__UNIQUE_ID_alias145                          44       -     -44
__UNIQUE_ID_alias144                          44       -     -44
__UNIQUE_ID_alias143                          44       -     -44
__UNIQUE_ID_alias142                          44       -     -44
__UNIQUE_ID_alias141                          44       -     -44
__UNIQUE_ID_alias140                          44       -     -44
__UNIQUE_ID_alias139                          44       -     -44
__UNIQUE_ID_alias138                          44       -     -44
__UNIQUE_ID_alias137                          44       -     -44
__UNIQUE_ID_alias136                          44       -     -44
__UNIQUE_ID_alias135                          44       -     -44
__UNIQUE_ID_alias134                          44       -     -44
__UNIQUE_ID_alias133                          44       -     -44
__UNIQUE_ID_alias132                          44       -     -44
__UNIQUE_ID_alias131                          44       -     -44
__UNIQUE_ID_alias130                          44       -     -44
__UNIQUE_ID_alias129                          44       -     -44
__UNIQUE_ID_alias128                          44       -     -44
__UNIQUE_ID_alias127                          44       -     -44
__UNIQUE_ID_alias126                          44       -     -44
__UNIQUE_ID_alias125                          44       -     -44
__UNIQUE_ID_alias124                          44       -     -44
__UNIQUE_ID_alias123                          44       -     -44
__UNIQUE_ID_alias122                          44       -     -44
__UNIQUE_ID_alias121                          44       -     -44
__UNIQUE_ID_alias120                          44       -     -44
__UNIQUE_ID_alias119                          44       -     -44
__UNIQUE_ID_alias118                          44       -     -44
__UNIQUE_ID_alias117                          44       -     -44
__UNIQUE_ID_alias116                          44       -     -44
__UNIQUE_ID_alias115                          44       -     -44
__UNIQUE_ID_alias114                          44       -     -44
__UNIQUE_ID_alias113                          44       -     -44
__UNIQUE_ID_alias112                          44       -     -44
__UNIQUE_ID_alias111                          44       -     -44
__UNIQUE_ID_alias110                          44       -     -44
__UNIQUE_ID_alias109                          44       -     -44
__UNIQUE_ID_alias108                          44       -     -44
__UNIQUE_ID_alias107                          44       -     -44
__UNIQUE_ID_alias106                          44       -     -44
__UNIQUE_ID_alias105                          44       -     -44
__UNIQUE_ID_alias104                          44       -     -44
__UNIQUE_ID_alias103                          44       -     -44
__UNIQUE_ID_alias102                          44       -     -44
__UNIQUE_ID_alias101                          44       -     -44
__UNIQUE_ID_alias100                          44       -     -44
iris_pte_encode                               45       -     -45
cnl_ddi_translations_edp_1_05V                45       -     -45
cnl_ddi_translations_edp_0_85V                45       -     -45
bxt_vtd_ggtt_clear_range__BKL                 45       -     -45
_intel_hdcp_enable                           704     659     -45
vlv_psr_enable_sink                           46       -     -46
intel_pps_unlock_regs_wa.part                111      65     -46
i915_update_gfx_val                           52       6     -46
i915_hpd_irq_setup                           240     194     -46
gpu_reset_clobbers_display                    46       -     -46
intel_init_audio_hooks                       119      72     -47
gen6_free_scratch                             47       -     -47
vlv_gpio_table                                48       -     -48
intel_pre_enable_lvds                        625     577     -48
intel_huc_init_early                         157     109     -48
intel_guc_fw_init_early                      157     109     -48
intel_dsi_connector_helper_funcs              48       -     -48
hsw_render_ring_cmds                          48       -     -48
hsw_render_reg_tables                         48       -     -48
hsw_blt_ring_cmds                             48       -     -48
assert_bpp_mismatch                           48       -     -48
vlv_psr_enable_source                         49       -     -49
intel_hpd_irq_handler                        837     788     -49
intel_fbc_init                               510     461     -49
i9xx_irq_disable                              49       -     -49
chv_pre_enable_dp                             49       -     -49
bxt_vtd_ggtt_insert_page__BKL                 49       -     -49
bxt_port_hotplug_long_detect                  49       -     -49
wm_latency_write.isra                        343     293     -50
intel_hpd_pin_to_port                         76      26     -50
i915_tiling_ok.isra                          163     113     -50
gen6_bsd_set_default_submission               50       -     -50
g4x_plane_fifo_size                           50       -     -50
cnl_ddi_translations_edp_0_95V                50       -     -50
cnl_ddi_translations_dp_1_05V                 50       -     -50
cnl_ddi_translations_dp_0_95V                 50       -     -50
cnl_ddi_translations_dp_0_85V                 50       -     -50
intel_enable_pipe                            500     449     -51
ilk_audio_codec_enable                       595     544     -51
intel_tile_height.part                        52       -     -52
intel_atomic_setup_scalers                   766     713     -53
cnl_ddi_translations_hdmi_1_05V               55       -     -55
cnl_ddi_translations_hdmi_0_95V               55       -     -55
bxt_vtd_ggtt_clear_range__cb                  55       -     -55
bxt_port_to_phy_channel                      146      91     -55
i9xx_select_p2_div                            56       -     -56
gen7_setup_fixed_func_scheduler               56       -     -56
bxt_vtd_ggtt_insert_entries__cb               56       -     -56
skl_atomic_update_crtc_wm                    825     768     -57
i915_edp_psr_status                          911     854     -57
gen9_set_dc_state                            447     390     -57
vlv_rpe_freq_mhz_show                         58       -     -58
ironlake_get_pfit_config.isra                180     122     -58
intel_fbc_choose_crtc                        392     334     -58
gen7_blt_get_cmd_length_mask                  58       -     -58
gen6_check_mch_setup                          58       -     -58
__UNIQUE_ID_alias50                           58       -     -58
wm_latency_show                              229     170     -59
reset_rps                                     60       -     -60
ivb_master_regs                               60       -     -60
cnl_procmon_values                            60       -     -60
g4x_get_aux_send_ctl                          97      36     -61
chv_hdmi_post_disable                         61       -     -61
bxt_vtd_ggtt_insert_page__cb                  61       -     -61
intel_dsi_connector_destroy                   62       -     -62
i9xx_get_initial_plane_config                839     777     -62
i915_handle_error                            948     886     -62
hsw_enable_pc8                              1796    1734     -62
_intel_adjust_tile_offset                    416     354     -62
logical_render_ring_init                     964     901     -63
ivybridge_parity_work                        780     717     -63
intel_crt_ddc_get_modes                       63       -     -63
intel_compute_tile_offset                    194     131     -63
i915_gfx_val                                  71       8     -63
i915_chipset_val                              71       8     -63
get_mocs_settings                            248     185     -63
gmbus_pins_bxt                                64       -     -64
i915_perf_open_ioctl                        3096    3031     -65
_vlv_get_backlight                            65       -     -65
intel_update_cdclk                            84      18     -66
intel_lvds_get_config                        154      88     -66
intel_ddi_dp_voltage_max                     205     139     -66
chv_post_disable_dp                           66       -     -66
bxt_gmbus_clock_gating                        66       -     -66
CSWTCH                                       646     580     -66
vlv_init_gpll_ref_freq                        67       -     -67
intel_set_memory_cxsr                        100      33     -67
intel_ddi_get_hw_state                       498     431     -67
assert_panel_unlocked                        334     267     -67
intel_dp_get_hw_state                        424     356     -68
i965_hz_to_pwm                                68       -     -68
i8xx_disable_vblank                           68       -     -68
cnp_init_clock_gating                         68       -     -68
intel_sdvo_get_config                        484     415     -69
i915_gem_load_init_fences                    221     152     -69
i915_fbc_status                              388     318     -70
gen10_disable_metric_set                      70       -     -70
i915_ring_freq_table                         398     327     -71
i8xx_enable_vblank                            71       -     -71
intel_ddi_get_buf_trans_dp                   149      77     -72
i9xx_irq_enable                               72       -     -72
i9xx_hpd_irq_ack                              72       -     -72
i915_gem_pread_ioctl                        1207    1135     -72
i915_cache_sharing_get                        83      11     -72
glk_pipe_scaler_clock_gating_wa               72       -     -72
glk_de_pll_vco.part                           72       -     -72
glk_ddi_phy_info                              72       -     -72
get_gmbus_pin.part                            72       -     -72
display_crc_ctl_write                       1471    1398     -73
chv_pipe_power_well_disable                   73       -     -73
i915_gem_object_get_pages_internal           651     576     -75
csr_load_work_fn                            1117    1042     -75
intel_limits_vlv                              76       -     -76
intel_limits_pineview_sdvo                    76       -     -76
intel_limits_pineview_lvds                    76       -     -76
intel_limits_i8xx_lvds                        76       -     -76
intel_limits_i8xx_dvo                         76       -     -76
intel_limits_i8xx_dac                         76       -     -76
intel_limits_g4x_single_channel_lvds          76       -     -76
intel_limits_g4x_sdvo                         76       -     -76
intel_limits_g4x_hdmi                         76       -     -76
intel_limits_g4x_dual_channel_lvds            76       -     -76
intel_limits_chv                              76       -     -76
intel_disable_pipe                           366     290     -76
i915_gem_gtt_pwrite_fast                    1215    1139     -76
gen7_render_get_cmd_length_mask               76       -     -76
chv_pipe_power_well_enable                    76       -     -76
cfl_init_clock_gating                         76       -     -76
skylake_get_initial_plane_config            1015     938     -77
i9xx_enable_backlight                        303     226     -77
i845_cursor_get_hw_state                      77       -     -77
bxt_dump_hw_state                             77       -     -77
i9xx_setup_backlight                         259     181     -78
i915_gem_gtt_pread                          1104    1026     -78
i845_get_fifo_size                            78       -     -78
intel_freq_opcode                            186     107     -79
i9xx_update_pll_dividers.isra.constprop       79       -     -79
vlv_dpll                                      80       -     -80
vlv_attrs                                     80       -     -80
gen4_dpll                                     80       -     -80
dma_set_coherent_mask                         80       -     -80
vlv_display_power_well_disable                81       -     -81
do_gmbus_xfer                               1143    1062     -81
intel_hdmi_set_gcp_infoframe.isra            410     328     -82
intel_cleanup_gt_powersave                   102      20     -82
i85x_init_clock_gating                        82       -     -82
hsw_pll_to_ddi_pll_sel.isra                   82       -     -82
vlv_check_no_gt_access                        83       -     -83
i965_disable_backlight                        83       -     -83
vlv_display_power_well_enable                 84       -     -84
intel_can_enable_sagv                        470     386     -84
i830_pipes_power_well_enabled                 84       -     -84
gen7_blt_regs                                 84       -     -84
gen10_init_indirectctx_bb                     84       -     -84
chv_is_valid_mux_addr                         84       -     -84
__vlv_fw_ranges                               84       -     -84
vlv_psr_activate                              85       -     -85
snb_pte_encode                                85       -     -85
pnv_gmbus_clock_gating                        85       -     -85
intel_update_rawclk                          326     241     -85
vlv_display_power_well_deinit                 86       -     -86
intel_lvds_compute_config                    298     212     -86
single_enabled_crtc                           87       -     -87
i915_enable_asle_pipestat.part                87       -     -87
intel_pre_plane_update                       410     322     -88
intel_pipe_update_start                      679     591     -88
hsw_oa_formats                                88       -     -88
intel_dp_encoder_reset                       396     307     -89
vlv_psr_setup_vsc                             90       -     -90
intel_infoframe_init                         218     128     -90
init_unused_ring                              90       -     -90
hsw_enable_ips                               233     143     -90
intel_dp_program_link_training_pattern       516     425     -91
i945gm_get_cdclk                              91       -     -91
i915gm_get_cdclk                              91       -     -91
ivb_plane_get_hw_state                        92       -     -92
i9xx_get_fifo_size                            92       -     -92
g4x_raw_crtc_wm_is_valid.part                 93       -     -93
valleyview_irq_reset                          94       -     -94
intel_atomic_commit                          758     664     -94
i915_gem_pwrite_ioctl                       1582    1488     -94
gen7_bsd_get_cmd_length_mask                  94       -     -94
pwm_enable_backlight                          95       -     -95
ivb_pte_encode                                95       -     -95
intel_engine_init_global_seqno               228     133     -95
intel_tile_dims                               96       -     -96
intel_dp_pre_emphasis_max                    156      60     -96
i830_power_wells                              96       -     -96
hsw_power_wells                               96       -     -96
cpt_digital_port_connected.isra               96       -     -96
bdw_power_wells                               96       -     -96
atom_hdaudio_ids                              96       -     -96
__gen6_gt_wait_for_thread_c0                  96       -     -96
i915_instdone_info                           369     272     -97
gen2_render_ring_flush                        97       -     -97
gen6_rps_idle                                200     101     -99
vlv_set_backlight                            100       -    -100
vlv_disable_backlight                        100       -    -100
valleyview_irq_postinstall                   100       -    -100
i830_get_fifo_size                           100       -    -100
config_status                                100       -    -100
cherryview_irq_postinstall                   100       -    -100
pwm_set_backlight                            101       -    -101
i915_dmc_info                                470     369    -101
gen6_ppgtt_cleanup                           101       -    -101
gen6_ggtt_insert_page                        101       -    -101
intel_csr_ucode_init                         276     174    -102
intel_dsi_mode_valid                         103       -    -103
i965g_init_clock_gating                      103       -    -103
intel_ddi_compute_config                     159      55    -104
vlv_plane_get_hw_state                       105       -    -105
update_scanline_offset                       105       -    -105
intel_init_render_ring_buffer                256     151    -105
i830_pipes_power_well_enable                 105       -    -105
engine_stuck                                 485     380    -105
intel_prepare_dp_ddi_buffers.isra            354     247    -107
intel_fbc_pre_update                         392     285    -107
i915_gem_create_context                     1031     924    -107
kbl_y_ddi_translations_dp                    108       -    -108
kbl_u_ddi_translations_dp                    108       -    -108
kbl_ddi_translations_dp                      108       -    -108
intel_check_primary_plane                    810     702    -108
hsw_is_valid_mux_addr                        108       -    -108
hsw_ddi_translations_fdi                     108       -    -108
hsw_ddi_translations_dp                      108       -    -108
bdw_ddi_translations_fdi                     108       -    -108
bdw_ddi_translations_edp                     108       -    -108
bdw_ddi_translations_dp                      108       -    -108
hsw_get_aux_clock_divider                    109       -    -109
vlv_initial_pps_pipe                         111       -    -111
intel_primary_plane_format_mod_supported     468     357    -111
intel_encoders_pre_pll_enable.isra           111       -    -111
hsw_ddi_calc_wrpll_link                      111       -    -111
g4x_initial_watermarks                       111       -    -111
bxt_hpd_irq_setup                            111       -    -111
intel_dsi_connector_funcs                    112       -    -112
i965_emit_bb_start                           112       -    -112
gmbus_pins_bdw                               112       -    -112
vlv_enable_dp                                114       -    -114
fini_hash_table                              114       -    -114
vlv_disable_plane                            115       -    -115
vlv_disable_dp                               115       -    -115
intel_get_gpu_reset                          115       -    -115
cnl_cdclk_pll_vco.part                       115       -    -115
intel_fbc_init_pipe_state                    122       6    -116
ilk_increase_wm_latency.constprop            116       -    -116
bxt_de_pll_vco.part                          117       -    -117
vlv_undo_pipe_scramble_reset                 118       -    -118
vlv_hz_to_pwm                                118       -    -118
gen6_mm_switch                               118       -    -118
kbl_get_buf_trans_dp                         119       -    -119
hsw_crtc_state_ips_capable                   127       8    -119
gen6_signal                                  120       -    -120
eb_relocate_entry                           3246    3126    -120
chv_dpll                                     120       -    -120
bdw_ddi_translations_hdmi                    120       -    -120
intel_ddi_clk_disable.isra                   202      81    -121
g4x_optimize_watermarks                      122       -    -122
intel_sdvo_pre_enable                       1696    1573    -123
cnl_get_buf_trans_hdmi                       124       -    -124
cnl_get_buf_trans_dp                         124       -    -124
lpt_init_clock_gating                        125       -    -125
intel_modeset_setup_hw_state                3870    3745    -125
hsw_emit_bb_start                            125       -    -125
intel_sanitize_enable_ppgtt                  262     136    -126
i915_cache_sharing_set                       137      11    -126
g4x_infoframe_enabled                        127       -    -127
sem_data                                     128       -    -128
intel_color_init                             237     109    -128
gen6_write_page_range.constprop              128       -    -128
edp_panel_on                                 370     242    -128
cnl_plls                                     128       -    -128
bxt_plls                                     128       -    -128
intel_dsi_disable                            131       -    -131
intel_ddi_get_buf_trans_hdmi                 131       -    -131
vlv_get_cdclk                                132       -    -132
ivb_disable_plane                            132       -    -132
intel_valleyview_info                        132       -    -132
intel_sandybridge_m_gt2_info                 132       -    -132
intel_sandybridge_m_gt1_info                 132       -    -132
intel_sandybridge_d_gt2_info                 132       -    -132
intel_sandybridge_d_gt1_info                 132       -    -132
intel_pineview_info                          132       -    -132
intel_kabylake_gt3_info                      132       -    -132
intel_kabylake_gt2_info                      132       -    -132
intel_kabylake_gt1_info                      132       -    -132
intel_ivybridge_q_info                       132       -    -132
intel_ivybridge_m_gt2_info                   132       -    -132
intel_ivybridge_m_gt1_info                   132       -    -132
intel_ivybridge_d_gt2_info                   132       -    -132
intel_ivybridge_d_gt1_info                   132       -    -132
intel_ironlake_m_info                        132       -    -132
intel_ironlake_d_info                        132       -    -132
intel_i965gm_info                            132       -    -132
intel_i965g_info                             132       -    -132
intel_i945gm_info                            132       -    -132
intel_i945g_info                             132       -    -132
intel_i915gm_info                            132       -    -132
intel_i915g_info                             132       -    -132
intel_i865g_info                             132       -    -132
intel_i85x_info                              132       -    -132
intel_i845g_info                             132       -    -132
intel_i830_info                              132       -    -132
intel_haswell_gt3_info                       132       -    -132
intel_haswell_gt2_info                       132       -    -132
intel_haswell_gt1_info                       132       -    -132
intel_gm45_info                              132       -    -132
intel_geminilake_info                        132       -    -132
intel_g45_info                               132       -    -132
intel_g33_info                               132       -    -132
intel_dsi_get_modes                          132       -    -132
intel_coffeelake_gt3_info                    132       -    -132
intel_coffeelake_gt2_info                    132       -    -132
intel_coffeelake_gt1_info                    132       -    -132
intel_cherryview_info                        132       -    -132
intel_cannonlake_info                        132       -    -132
intel_broxton_info                           132       -    -132
intel_broadwell_rsvd_info                    132       -    -132
intel_broadwell_gt3_info                     132       -    -132
intel_broadwell_gt2_info                     132       -    -132
intel_broadwell_gt1_info                     132       -    -132
i85x_get_cdclk                               132       -    -132
gen6_reset_engines                           132       -    -132
g4x_audio_codec_disable                      134       -    -134
vlv_dpio_cmn_power_well_enable               135       -    -135
intel_ddi_get_buf_trans_edp                  349     214    -135
glk_init_clock_gating                        135       -    -135
bxt_init_cdclk                               473     335    -138
intel_get_cxsr_latency.part                  140       -    -140
intel_fbc_enable                            1437    1297    -140
ddi_dotclock_get                             140       -    -140
intel_engine_dump                           3103    2962    -141
intel_dsi_pll_is_enabled                     177      36    -141
i915_error_state_to_str                     4590    4449    -141
hsw_ddi_translations_hdmi                    144       -    -144
intel_gpu_freq                               206      60    -146
hsw_power_well_enable                        412     265    -147
hsw_get_cdclk                                147       -    -147
gen7_oa_enable                               147       -    -147
hsw_disable_metric_set                       148       -    -148
g4x_undo_pipe_scramble_reset                 148       -    -148
hsw_disable_ips                              228      79    -149
append_oa_sample.isra                        149       -    -149
intel_dp_link_down.isra                      776     626    -150
skl_check_plane_surface                     1833    1682    -151
bxt_disable_backlight                        151       -    -151
__i915_update_gfx_val                        152       -    -152
__gen6_gt_wait_for_fifo                      152       -    -152
intel_psr_single_frame_update                160       6    -154
intel_ddi_init                              1128     974    -154
ilk_compute_fbc_wm                           154       -    -154
vlv_initial_watermarks                       155       -    -155
intel_psr_compute_config                     483     328    -155
i830_overlay_clock_gating                    155       -    -155
chv_pipe_power_well_enabled                  155       -    -155
i915_swizzle_info                            579     423    -156
hsw_write_dcomp                              156       -    -156
vlv_disable_pll                              157       -    -157
cnl_get_buf_trans_edp                        157       -    -157
i915_sr_status                               339     181    -158
gen6_bsd_submit_request                      159       -    -159
vlv_power_well_enabled                       160       -    -160
valleyview_pipestat_irq_handler              160       -    -160
bxt_init_clock_gating                        160       -    -160
pwm_disable_backlight                        161       -    -161
vlv_dpio_cmn_power_well_disable              163       -    -163
intel_pps_get_registers                      269     105    -164
intel_compute_min_cdclk                      164       -    -164
bdw_update_port_irq                          164       -    -164
vlv_optimize_watermarks                      166       -    -166
intel_bios_is_port_hpd_inverted              214      48    -166
gen6_ring_sync_to                            166       -    -166
gen8_set_l3sqc_credits.constprop             167       -    -167
vlv_PLL_is_optimal.isra                      168       -    -168
pnv_calc_dpll_params                         169       -    -169
bdw_modeset_calc_cdclk                       171       -    -171
intel_dsi_get_pclk                           590     417    -173
i965gm_init_clock_gating                     173       -    -173
bxt_ddi_vswing_sequence.isra                 173       -    -173
bdw_get_cdclk                                173       -    -173
intel_calculate_wm                           175       -    -175
intel_finish_reset                           341     165    -176
intel_display_print_error_state              895     719    -176
i845_update_wm                               176       -    -176
hsw_blt_cmds                                 176       -    -176
vlv_allow_gt_wake                            177       -    -177
hsw_mm_switch                                177       -    -177
gen6_ggtt_clear_range                        178       -    -178
vlv_steal_power_sequencer                    179       -    -179
intel_shared_dpll_init                       493     314    -179
i915_pm_resume_early                         390     211    -179
vlv_program_pfi_credits                      180       -    -180
pnv_get_cdclk                                182       -    -182
gen3_init_clock_gating                       182       -    -182
chv_crtc_compute_clock                       182       -    -182
i915_setup_sysfs                             508     325    -183
i8xx_irq_reset                               183       -    -183
g4x_init_clock_gating                        183       -    -183
bxt_ddi_hdmi_pll_dividers.isra               183       -    -183
intel_lvds_init                             1943    1759    -184
dividers                                     216      32    -184
gen8_gt_irq_ack                              185       -    -185
i915_emon_status                             197      11    -186
vlv_infoframe_enabled                        187       -    -187
intel_runtime_suspend                        589     402    -187
i965gm_get_cdclk                             188       -    -188
chv_hdmi_pre_enable                          188       -    -188
vlv_hdmi_pre_enable                          189       -    -189
haswell_load_luts                            189       -    -189
vlv_wait_for_pw_status                       190       -    -190
cnl_ddi_pll_get_hw_state                     190       -    -190
vlv_calc_dpll_params.constprop               191       -    -191
gm45_get_cdclk                               191       -    -191
chv_power_wells                              192       -    -192
__chv_fw_ranges                              192       -    -192
intel_hpll_vco                               194       -    -194
intel_engines_init_mmio                     1143     945    -198
gen8_init_workarounds.isra                   198       -    -198
i915_ips_status                              211      11    -200
g33_do_reset                                 202       -    -202
intel_runtime_resume                         528     323    -205
ilk_wm_get_hw_state                         1074     868    -206
g33_get_cdclk                                208       -    -208
i9xx_hpd_irq_handler                         209       -    -209
__bxt_hpd_detection_setup                    211       -    -211
vlv_detach_power_sequencer                   212       -    -212
intel_PLL_is_valid                           212       -    -212
chv_init_clock_gating                        212       -    -212
i845_check_cursor                            214       -    -214
i915_gem_init_swizzling                      237      21    -216
intel_psr_init                               568     350    -218
intel_power_domains_suspend                  406     188    -218
vlv_psr_disable                              219       -    -219
kbl_init_clock_gating                        219       -    -219
intel_hdmi_prepare                           219       -    -219
ggtt_probe_common                            219       -    -219
i915_drpc_info                              2033    1812    -221
intel_dp_pps_init                            222       -    -222
intel_dsi_compute_config                     223       -    -223
bxt_dp_clk_val                               224       -    -224
init_render_ring                             303      77    -226
hsw_enable_metric_set                        227       -    -227
intel_fbc_hw_deactivate                      228       -    -228
edp_notify_handler                           230       -    -230
i915_drm_suspend_late                        352     121    -231
check_for_unclaimed_mmio                     231       -    -231
vlv_display_irq_postinstall                  233       -    -233
ironlake_do_reset                            233       -    -233
ironlake_crtc_enable                        3071    2838    -233
cherryview_irq_reset                         235       -    -235
intel_check_cpu_fifo_underruns               626     388    -238
i915_irq_postinstall                         238       -    -238
intel_cursor_base                            240       -    -240
intel_dp_init                                628     384    -244
i9xx_pfit_enable                             244       -    -244
skl_compute_wm                              6504    6259    -245
intel_power_sequencer_reset                  272      27    -245
i915_gem_detect_bit_6_swizzle                484     238    -246
i965_setup_backlight                         247       -    -247
cpt_init_clock_gating                        248       -    -248
chv_dpio_cmn_power_well_disable              249       -    -249
cpt_set_fdi_bc_bifurcation                   251       -    -251
intel_overlay_put_image_ioctl               4473    4219    -254
intel_engine_get_instdone                    972     717    -255
cnl_init_clock_gating                        255       -    -255
intel_read_wm_latency                        703     447    -256
gen8_gt_irq_handler                          258       -    -258
intel_disable_dsi_pll                        266       6    -260
intel_sprite_plane_format_mod_supported      634     373    -261
g4x_disable_trickle_feed                     261       -    -261
i915_perf_init                               681     419    -262
cnl_get_cdclk                                262       -    -262
intel_display_capture_error_state           1345    1082    -263
intel_dp_compute_config                     2411    2145    -266
i915_irq_reset                               266       -    -266
gen8_emit_flush_render                       663     397    -266
intel_ddi_clk_select.isra                    459     192    -267
intel_panel_init                             661     392    -269
i9xx_pipe_crc_auto_source                    270       -    -270
cnl_ddi_pll_disable                          270       -    -270
vlv_setup_backlight                          271       -    -271
i9xx_compute_dpll.isra.constprop             271       -    -271
lpe_audio_irqchip                            272       -    -272
i9xx_pipestat_irq_ack                        276       -    -276
ilk_program_watermarks                      2090    1812    -278
bxt_ddi_pll_disable                          279       -    -279
bxt_ddi_set_dpll_hw_state                    282       -    -282
chv_disable_pll                              283       -    -283
gen5_write32                                 284       -    -284
gen5_gt_irq_postinstall                      284       -    -284
gen5_write8                                  285       -    -285
intel_crtc_compute_min_cdclk                 517     231    -286
gen5_write16                                 286       -    -286
bxt_power_wells                              288       -    -288
gen5_read64                                  289       -    -289
bxt_setup_backlight                          289       -    -289
intel_uncore_forcewake_for_reg               745     455    -290
i915_gem_do_execbuffer                      4625    4333    -292
i8xx_irq_postinstall                         294       -    -294
gen6_ppgtt_clear_range                       294       -    -294
gen5_read32                                  294       -    -294
gen5_read8                                   295       -    -295
gen5_read16                                  296       -    -296
intel_set_cpu_fifo_underrun_reporting        630     332    -298
intel_tile_width_bytes                       300       -    -300
init_ring_common                            1717    1417    -300
intel_ring_default_vfuncs                    556     254    -302
ilk_compute_pipe_wm                         1022     720    -302
gen8_init_indirectctx_bb                     303       -    -303
gen5_gt_irq_reset                            307       -    -307
glk_load_luts                                308       -    -308
_intel_compute_tile_offset                   311       -    -311
__i915_chipset_val                           312       -    -312
g4x_write_infoframe                          314       -    -314
vlv_set_power_well                           315       -    -315
intel_check_cursor                           316       -    -316
intel_rc6_residency_ns                       356      39    -317
gen9_init_clock_gating                       317       -    -317
__intel_adjust_tile_offset                   317       -    -317
valleyview_set_rps                           318       -    -318
g4x_crtc_compute_clock                       318       -    -318
__i915_gfx_val                               320       -    -320
gen6_ggtt_insert_entries                     321       -    -321
i915_gem_init_hw                             715     392    -323
hsw_init_clock_gating                        323       -    -323
snb_gt_irq_handler                           325       -    -325
hsw_pipe_A_crc_wa                            326       -    -326
i8xx_irq_handler                             334       -    -334
vlv_power_wells                              336       -    -336
gen7_init_oa_buffer                          336       -    -336
intel_digital_port_connected                 578     241    -337
vlv_enable_backlight                         338       -    -338
intel_sprite_plane_create                    888     549    -339
i9xx_set_pipeconf                            341       -    -341
__intel_fbc_post_update                     1417    1076    -341
intel_init_display_hooks                     645     297    -348
i965_enable_backlight                        348       -    -348
chv_set_cdclk                                348       -    -348
i9xx_crtc_clock_get.isra                     608     259    -349
chv_set_pipe_power_well.constprop            351       -    -351
hdmi_port_clock_valid                        352       -    -352
dpi_send_cmd.constprop                       357       -    -357
intel_hdmi_init_connector                   1042     684    -358
i915_perf_register                           588     230    -358
pwm_setup_backlight                          359       -    -359
intel_crtc_atomic_check                      836     475    -361
gen9_dc_off_power_well_enable                531     167    -364
i9xx_find_best_dpll.constprop                366       -    -366
gen8_gt_irq_postinstall                      372       -    -372
g4x_find_best_dpll.isra                      376       -    -376
bxt_get_cdclk                                379       -    -379
i915_ppgtt_info                              877     496    -381
cnl_ddi_pll_enable                           386       -    -386
i915_restore_state                           616     229    -387
vlv_modeset_calc_cdclk                       388       -    -388
intel_power_domains_init                     908     515    -393
i845_update_cursor                           394       -    -394
i915_save_state                              596     199    -397
gen6_write32                                 401       -    -401
vlv_init_clock_gating                        402       -    -402
gen6_write8                                  402       -    -402
gen6_write16                                 403       -    -403
i9xx_crtc_disable                            965     561    -404
hsw_render_regs                              408       -    -408
i915_do_reset                                410       -    -410
intel_init_clock_gating_hooks                483      71    -412
intel_dsi_reset_clocks                       418       6    -412
cxsr_latency_table                           420       -    -420
vlv_write_infoframe                          431       -    -431
intel_irq_init                              1019     585    -434
ilk_init_clock_gating                        436       -    -436
semaphore_passed                             440       -    -440
vlv_enable_pll.isra                          442       -    -442
gen8_emit_flush_coherentl3_wa.isra           442       -    -442
intel_plane_atomic_calc_changes             1347     902    -445
cherryview_irq_handler                       445       -    -445
i915_irq_handler                             447       -    -447
gen6_read64                                  447       -    -447
intel_framebuffer_init                      2982    2533    -449
gen6_read32                                  450       -    -450
gen6_read8                                   451       -    -451
gen6_read16                                  452       -    -452
ironlake_irq_handler                        2626    2171    -455
cherryview_load_csc_matrix                   455       -    -455
gen6_init_clock_gating                       459       -    -459
fw_domains_get                               477       -    -477
bdw_init_clock_gating                        477       -    -477
valleyview_crtc_enable                       480       -    -480
chv_find_best_dpll.isra.constprop            480       -    -480
g4x_set_infoframes                           482       -    -482
intel_dp_set_drrs_state                      490       -    -490
i915_check_and_clear_faults                  515      22    -493
ring_request_alloc                          1640    1145    -495
i915_ppgtt_init_hw                           758     261    -497
chv_dpio_cmn_power_well_enable               498       -    -498
bxt_enable_backlight                         498       -    -498
vlv_set_infoframes                           499       -    -499
i965_update_wm                               500       -    -500
cnl_get_dpll                                 500       -    -500
i8xx_crtc_compute_clock                      503       -    -503
ilk_wm_merge                                 504       -    -504
cnl_modeset_calc_cdclk                       507       -    -507
intel_disable_gt_powersave                   690     182    -508
gen6_ppgtt_insert_entries                    509       -    -509
intel_update_max_cdclk                       807     296    -511
bxt_modeset_calc_cdclk                       512       -    -512
valleyview_irq_handler                       516       -    -516
g4x_audio_codec_enable                       523       -    -523
vecs_cmds                                    528       -    -528
blt_cmds                                     528       -    -528
g4x_do_reset                                 546       -    -546
gen6_render_ring_flush                       548       -    -548
intel_pipe_config_compare                   4794    4244    -550
vlv_display_power_well_init                  556       -    -556
i9xx_update_plane                           1325     766    -559
vlv_wm_get_hw_state                         2403    1841    -562
pnv_crtc_compute_clock                       565       -    -565
i830_emit_bb_start                           566       -    -566
ivb_init_clock_gating                        567       -    -567
gen8_gt_irq_reset                            574       -    -574
vlv_compute_intermediate_wm                  581       -    -581
gen6_dump_ppgtt                              586       -    -586
intel_ddi_pre_enable                        2013    1425    -588
gen8_write32                                 591       -    -591
gen8_write8                                  592       -    -592
gen8_write16                                 593       -    -593
__func__                                    2126    1529    -597
capture                                     5493    4893    -600
mipi_exec_gpio                               810     208    -602
intel_init_cdclk_hooks                       694      79    -615
vlv_crtc_compute_clock                       616       -    -616
video_cmds                                   616       -    -616
_intel_set_memory_cxsr                       617       -    -617
intel_cpu_transcoder_set_m_n                 622       -    -622
bdw_load_gamma_lut.isra                      622       -    -622
glk_power_wells                              624       -    -624
intel_dsi_get_hw_state                       625       -    -625
chv_enable_pll                               649       -    -649
i915_sseu_status                            1633     977    -656
pineview_update_wm                           661       -    -661
cnl_power_wells                              672       -    -672
cherryview_load_luts                         687       -    -687
vlv_set_cdclk                                692       -    -692
intel_dp_prepare                             693       -    -693
chv_prepare_pll.isra                         693       -    -693
bxt_get_dpll                                 697       -    -697
vlv_atomic_update_fifo                       698       -    -698
cnl_ddi_hdmi_pll_dividers.isra               706       -    -706
intel_bios_init                             9033    8316    -717
intel_cpu_transcoder_get_m_n                 718       -    -718
clear_intel_crtc_state                       718       -    -718
intel_set_pipe_timings                       726       -    -726
intel_dp_init_panel_power_sequencer_registers     726       -    -726
ironlake_fdi_link_train                      767       -    -767
intel_uncore_init                           1356     582    -774
gen7_render_regs                             792       -    -792
ivb_update_plane                             794       -    -794
intel_check_sprite_plane                    2824    2024    -800
get_new_crc_ctl_reg                          812       -    -812
intel_dsi_host_transfer                      836       -    -836
vlv_prepare_pll                              858       -    -858
gen9_init_workarounds                        867       -    -867
intel_compute_dsi_pll                        883      11    -872
intel_lpe_audio_init                         893      11    -882
bxt_set_cdclk                                888       -    -888
intel_fbc_work_fn                           1804     912    -892
haswell_get_pipe_config                     2572    1658    -914
intel_enable_dp                              934       -    -934
g4x_program_watermarks                       935       -    -935
init_workarounds_ring                       2220    1277    -943
i9xx_get_pipe_config                        1587     632    -955
gen6_set_rps_thresholds                      956       -    -956
cnl_set_cdclk                                957       -    -957
bdw_set_cdclk                                959       -    -959
gen7_null_state_batch                        960       -    -960
g4x_compute_intermediate_wm                  978       -    -978
i9xx_update_wm                               983       -    -983
ivb_manual_fdi_link_train                    998       -    -998
bxt_ddi_pll_get_hw_state                    1000       -   -1000
intel_ddi_get_config                        2433    1432   -1001
intel_dp_set_signal_levels                  1348     335   -1013
fence_write                                 1017       -   -1017
i915_ppgtt_create                           2774    1754   -1020
gen6_fdi_link_train                         1020       -   -1020
vlv_update_plane                            1031       -   -1031
intel_enable_dsi_pll                        1039       6   -1033
cnl_ddi_vswing_sequence                     1047       -   -1047
common_cmds                                 1056       -   -1056
cnl_ddi_vswing_program.isra                 1064       -   -1064
i915_gem_init_stolen                        1868     785   -1083
i915_driver_load                            5255    4167   -1088
vlv_power_sequencer_pipe                    1092       -   -1092
gen6_null_state_batch                       1100       -   -1100
intel_engine_init_cmd_parser                1127       6   -1121
gen7_oa_read                                1132       -   -1132
i915_frequency_info                         3198    2050   -1148
intel_dp_init_connector                     5321    4168   -1153
intel_dsi_init                              1324      81   -1243
i915_interrupt_info                         2690    1437   -1253
intel_device_info_runtime_init              2402    1107   -1295
i915_ggtt_probe_hw                          3137    1819   -1318
vlv_resume_prepare                          1359       -   -1359
intel_power_domains_init_hw                 1838     477   -1361
vlv_suspend_complete                        1394       -   -1394
intel_crt_detect                            2330     935   -1395
intel_init_pm                               1879     399   -1480
hsw_render_cmds                             1584       -   -1584
vlv_program_watermarks                      1586       -   -1586
intel_modeset_init                          6474    4855   -1619
intel_dsi_get_config                        1737       -   -1737
render_cmds                                 1760       -   -1760
g4x_compute_pipe_wm                         1929       -   -1929
vlv_compute_pipe_wm                         2032       -   -2032
bxt_ddi_pll_enable                          2255       -   -2255
intel_init_gt_powersave                     3073     444   -2629
intel_dsi_post_disable                      2767       -   -2767
intel_dsi_prepare                           3622       -   -3622
gen8_null_state_batch                       3776       -   -3776
intel_enable_gt_powersave                   6039    1474   -4565
intel_dsi_pre_enable                        4570       -   -4570
pciidlist                                   7072     736   -6336
Total: Before=1012894, After=785205, chg -22.48%
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Re: [RFC 00/15] Selectable platform support

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-09 11:01:08)
> 
> On 09/02/18 10:50, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-02-09 10:48:23)
> >>
> >> On 08/02/2018 13:05, Tvrtko Ursulin wrote:
> >>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>>
> >>> For Joonas basically. :)
> >>>
> >>> Rough goal - add Kconfig options to turn off supported platforms and count on
> >>> compiler DCE to make the driver smaller.
> >>>
> >>> Tested as so much that it boots and renders on Skylake with all platforms/gens
> >>> older than Gen8 turned off.
> >>>
> >>>      text    data     bss     dec     hex filename
> >>> 1502847   54223    2888 1559958  17cd96 i915.ko.original
> >>> 1375647   51939    2888 1430474  15d3ca i915.ko.gen8+
> >>
> >> I've finished this today (all platforms plus some more details and
> >> changes) but wont' post it again. Instead who is interested can see it
> >> in my freedesktop git repo - people.freedesktop.org/~tursulin/drm-intel
> >> platform-kconfig - but for some reason it is not showing in GitWeb any
> >> longer.
> >>
> >> Anyway.. with the latest build the i915.ko size goes from 15600073 to
> >> 1256697 when I enable only Skylake via Kconfig. This is 296kiB and close
> >> to 20% saving.
> > 
> > Could you post ./scripts/bloat-o-meter?
> 
> It's big:

Ok. Looking at some examples in intel_ringbuffer.c,

> i965_emit_bb_start                           112       -    -112
> ring_request_alloc                          1640    1145    -495

It can prune away the vfuncs with the local tests, but it can't
determine that the majority of intel_ringbuffer.c isn't used. Other
than LTO for cross compilation unit, one problem will be

#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
                ((dev_priv)->info.has_logical_ring_contexts)
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
                ((dev_priv)->info.has_logical_ring_preemption)

#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)

where we are strongly advocating using static GEN lists rather than
describing capabilities.

Ideas? A long time ago, we wanted a static INTEL_INFO. I think now we
have driver_caps, we try to kill off mkwrite_intel_info() and where
need be use INTEL_INFO() && DRIVER_CAPS().

Tvrtko, how easy do you think it will be to go from Kconfig to

#define INTEL_INFO(dev_priv) (&platform_info)
?
-Chris
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Re: [RFC 00/15] Selectable platform support

[Chris Wilson]

Quoting Chris Wilson (2018-02-09 11:19:44)
> Ideas? A long time ago, we wanted a static INTEL_INFO. I think now we
> have driver_caps, we try to kill off mkwrite_intel_info() and where
> need be use INTEL_INFO() && DRIVER_CAPS().
> 
> Tvrtko, how easy do you think it will be to go from Kconfig to
> 
> #define INTEL_INFO(dev_priv) (&platform_info)
> ?

Fwiw, I've been playing around with getting INTEL_INFO() back to being a
static blob, but the DCE elimination for a single platform_info does
require LTO. (And no, I can't build Andi Keen's lto-415-2 branch either.)

--- ctl.h ---
#include <stdbool.h>

struct control {
	bool exists;
};

--- ctl.c ---
#include "ctl.h"

const struct control ctl = {
	.exists = false,
};

--- test.c ---
#include "ctl.h"

static void unwanted(int *x)
{
	*x = 0;
}

extern const struct control ctl;

int main(void)
{
	if (ctl.exists)
		unwanted(0);

	return 0;
}

Without LTO, gcc -Wall -g test.c ctl.c -O2
Dump of assembler code for function main:
   0x00000000004003e0 <+0>:	cmpb   $0x0,0x1ad(%rip)        # 0x400594 <ctl>
   0x00000000004003e7 <+7>:	je     0x400400 <main+32>
   0x00000000004003e9 <+9>:	movl   $0x0,0x0
   0x00000000004003f4 <+20>:	ud2    
   0x00000000004003f6 <+22>:	nopw   %cs:0x0(%rax,%rax,1)
   0x0000000000400400 <+32>:	xor    %eax,%eax
   0x0000000000400402 <+34>:	retq   

With LTO, gcc -Wall -g test.c ctl.c -flto -O2
Dump of assembler code for function main:
   0x00000000004003e0 <+0>:	xor    %eax,%eax
   0x00000000004003e2 <+2>:	retq   

Let's hope that magic scales!
-Chris
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Re: [RFC 00/15] Selectable platform support

[Jani Nikula]

On Fri, 09 Feb 2018, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> Anyway.. with the latest build the i915.ko size goes from 15600073 to 
> 1256697 when I enable only Skylake via Kconfig. This is 296kiB and close 
> to 20% saving.

Those numbers look like 90+% saving to me. ;)

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Technology Center
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✗ Fi.CI.BAT: failure for Selectable platform support (rev2)

[Patchwork]

== Series Details ==

Series: Selectable platform support (rev2)
URL   : https://patchwork.freedesktop.org/series/37912/
State : failure

== Summary ==

Applying: drm/i915: Make I830 platform support optional
Applying: drm/i915: Make I845G platform support optional
Applying: drm/i915: Make I85X platform support optional
Applying: drm/i915: Make I865G platform support optional
Applying: drm/i915: Make GEN2 support optional
Applying: drm/i915: Make Gen3 platforms support optional
Applying: drm/i915: Make Gen4 platforms support optional
Applying: drm/i915: Make Ironlake/Gen5 platforms support optional
Applying: drm/i915: Make Sandybridge/Gen6 platforms support optional
Applying: drm/i915: Make Gen7/7.5 platform support optional
Applying: __gen__
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_drv.h).
error: could not build fake ancestor
Patch failed at 0011 __gen__
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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