From: niklas.cassel@axis.com (Niklas Cassel)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/8] ARM: dts: artpec: add and utilize artpec6 pin controller
Date: Tue, 20 Feb 2018 18:00:46 +0100 [thread overview]
Message-ID: <20180220170049.22809-6-niklas.cassel@axis.com> (raw)
In-Reply-To: <20180220170049.22809-1-niklas.cassel@axis.com>
Add node for the pin controller used in the artpec6 SoC,
and start using it for the exising UARTs.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
---
arch/arm/boot/dts/artpec6.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 981aecd27b0b..7a6d8f39823a 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -180,6 +180,32 @@
status = "disabled";
};
+ pinctrl: pinctrl at f801d000 {
+ compatible = "axis,artpec6-pinctrl";
+ reg = <0xf801d000 0x400>;
+
+ pinctrl_uart0: uart0grp {
+ function = "uart0";
+ groups = "uart0grp2";
+ bias-pull-up;
+ };
+ pinctrl_uart1: uart1grp {
+ function = "uart1";
+ groups = "uart1grp0";
+ bias-pull-up;
+ };
+ pinctrl_uart2: uart2grp {
+ function = "uart2";
+ groups = "uart2grp1";
+ bias-pull-up;
+ };
+ pinctrl_uart3: uart3grp {
+ function = "uart3";
+ groups = "uart3grp0";
+ bias-pull-up;
+ };
+ };
+
amba at 0 {
compatible = "simple-bus";
#address-cells = <0x1>;
@@ -238,6 +264,8 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
status = "disabled";
};
uart1: serial at f8037000 {
@@ -247,6 +275,8 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
status = "disabled";
};
uart2: serial at f8038000 {
@@ -256,6 +286,8 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
status = "disabled";
};
uart3: serial at f8039000 {
@@ -265,6 +297,8 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
status = "disabled";
};
};
--
2.14.2
WARNING: multiple messages have this Message-ID (diff)
From: Niklas Cassel <niklas.cassel@axis.com>
To: arm@kernel.org, Jesper Nilsson <jespern@axis.com>,
Lars Persson <larper@axis.com>, Niklas Cassel <niklass@axis.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Russell King <linux@armlinux.org.uk>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-arm-kernel@axis.com, linux-kernel@vger.kernel.org
Subject: [PATCH 5/8] ARM: dts: artpec: add and utilize artpec6 pin controller
Date: Tue, 20 Feb 2018 18:00:46 +0100 [thread overview]
Message-ID: <20180220170049.22809-6-niklas.cassel@axis.com> (raw)
In-Reply-To: <20180220170049.22809-1-niklas.cassel@axis.com>
Add node for the pin controller used in the artpec6 SoC,
and start using it for the exising UARTs.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
---
arch/arm/boot/dts/artpec6.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 981aecd27b0b..7a6d8f39823a 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -180,6 +180,32 @@
status = "disabled";
};
+ pinctrl: pinctrl@f801d000 {
+ compatible = "axis,artpec6-pinctrl";
+ reg = <0xf801d000 0x400>;
+
+ pinctrl_uart0: uart0grp {
+ function = "uart0";
+ groups = "uart0grp2";
+ bias-pull-up;
+ };
+ pinctrl_uart1: uart1grp {
+ function = "uart1";
+ groups = "uart1grp0";
+ bias-pull-up;
+ };
+ pinctrl_uart2: uart2grp {
+ function = "uart2";
+ groups = "uart2grp1";
+ bias-pull-up;
+ };
+ pinctrl_uart3: uart3grp {
+ function = "uart3";
+ groups = "uart3grp0";
+ bias-pull-up;
+ };
+ };
+
amba@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
@@ -238,6 +264,8 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
status = "disabled";
};
uart1: serial@f8037000 {
@@ -247,6 +275,8 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
status = "disabled";
};
uart2: serial@f8038000 {
@@ -256,6 +286,8 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
status = "disabled";
};
uart3: serial@f8039000 {
@@ -265,6 +297,8 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
status = "disabled";
};
};
--
2.14.2
WARNING: multiple messages have this Message-ID (diff)
From: Niklas Cassel <niklas.cassel@axis.com>
To: arm@kernel.org, Jesper Nilsson <jespern@axis.com>,
Lars Persson <larper@axis.com>, Niklas Cassel <niklass@axis.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Russell King <linux@armlinux.org.uk>
Cc: linux-arm-kernel@axis.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 5/8] ARM: dts: artpec: add and utilize artpec6 pin controller
Date: Tue, 20 Feb 2018 18:00:46 +0100 [thread overview]
Message-ID: <20180220170049.22809-6-niklas.cassel@axis.com> (raw)
In-Reply-To: <20180220170049.22809-1-niklas.cassel@axis.com>
Add node for the pin controller used in the artpec6 SoC,
and start using it for the exising UARTs.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
---
arch/arm/boot/dts/artpec6.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 981aecd27b0b..7a6d8f39823a 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -180,6 +180,32 @@
status = "disabled";
};
+ pinctrl: pinctrl@f801d000 {
+ compatible = "axis,artpec6-pinctrl";
+ reg = <0xf801d000 0x400>;
+
+ pinctrl_uart0: uart0grp {
+ function = "uart0";
+ groups = "uart0grp2";
+ bias-pull-up;
+ };
+ pinctrl_uart1: uart1grp {
+ function = "uart1";
+ groups = "uart1grp0";
+ bias-pull-up;
+ };
+ pinctrl_uart2: uart2grp {
+ function = "uart2";
+ groups = "uart2grp1";
+ bias-pull-up;
+ };
+ pinctrl_uart3: uart3grp {
+ function = "uart3";
+ groups = "uart3grp0";
+ bias-pull-up;
+ };
+ };
+
amba@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
@@ -238,6 +264,8 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
status = "disabled";
};
uart1: serial@f8037000 {
@@ -247,6 +275,8 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
status = "disabled";
};
uart2: serial@f8038000 {
@@ -256,6 +286,8 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
status = "disabled";
};
uart3: serial@f8039000 {
@@ -265,6 +297,8 @@
clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
<&clkctrl ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
status = "disabled";
};
};
--
2.14.2
next prev parent reply other threads:[~2018-02-20 17:00 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-20 17:00 [PATCH 0/8] ARTPEC-6 ARM SoC device tree updates Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` [PATCH 1/8] ARM: dts: artpec: disable Accelerator Coherency Port Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` [PATCH 2/8] ARM: dts: artpec: use 1 GiB RAM Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` [PATCH 3/8] ARM: dts: artpec: remove 0x prefix from clkctrl unit address Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` [PATCH 4/8] ARM: dts: artpec: migrate ethernet to stmmac binding Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel [this message]
2018-02-20 17:00 ` [PATCH 5/8] ARM: dts: artpec: add and utilize artpec6 pin controller Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` [PATCH 6/8] ARM: dts: artpec: add and utilize nbpfaxi DMA controllers Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` [PATCH 7/8] ARM: dts: artpec: add disabled node for PCIe endpoint mode Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 21:29 ` Niklas Cassel
2018-02-20 21:29 ` Niklas Cassel
2018-02-20 21:29 ` Niklas Cassel
2018-02-20 17:00 ` [PATCH 8/8] ARM: dts: artpec: add node for hardware crypto accelerator Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
2018-02-20 17:00 ` Niklas Cassel
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