[PATCH v3 0/2] Add HiSilicon INNO USB2 PHY driver support

[PATCH v3 0/2] Add HiSilicon INNO USB2 PHY driver support

[Shawn Guo]

It adds device tree bindings and driver support for HiSilicon INNO USB2
PHY device, which can be found on HiSilicon STB SoC Hi3798cv200.

Changes for v3:
 - Make combphy device be child of peripheral controller and use 'reg'
   property for mapping combphy configuration register.

Changes for v2:
 - Move DT bindings into a separate patch.
 - Rename hisi_inno_phy_start() to hisi_inno_phy_init() for aligning
   name with .init hook.

Pengcheng Li (2):
  dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY
  phy: add inno-usb2-phy driver for hi3798cv200 SoC

 .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt |  52 +++++
 drivers/phy/hisilicon/Kconfig                      |  10 +
 drivers/phy/hisilicon/Makefile                     |   1 +
 drivers/phy/hisilicon/phy-hisi-inno-usb2.c         | 218 +++++++++++++++++++++
 4 files changed, 281 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
 create mode 100644 drivers/phy/hisilicon/phy-hisi-inno-usb2.c

-- 
1.9.1

[PATCH v3 1/2] dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY

[Shawn Guo]

From: Pengcheng Li <lpc.li@hisilicon.com>

It adds device tree bindings document for HiSilicon INNO USB2 PHY.

Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 52 ++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
new file mode 100644
index 000000000000..b563cf54ca7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
@@ -0,0 +1,52 @@
+HiSilicon INNO USB2 PHY
+
+Required properties:
+- compatible: Should be one of the following strings:
+	"hisilicon,inno-usb2-phy",
+	"hisilicon,hi3798cv200-usb2-phy".
+- reg: Should be the address space for PHY configuration register in peripheral
+  controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798cv200 SoC.
+- #phy-cells: Should be 1. The specifier is the index of the PHY port to
+  reference.
+- clocks: The phandle and clock specifier pair for reference clock utmi_refclk.
+- resets: The list of phandle and reset specifier pairs for each reset signal
+  in reset-names.
+- reset-names: Should contain "power_on", "utmi0" and "utmi1". The "utmi1"
+  should exist only if the device has two PHY port.
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties
+
+Note: the device node should be a child of peripheral controller that contains
+the PHY configuration register.
+
+Example:
+
+perictrl: peripheral-controller@8a20000 {
+	compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
+		     "simple-mfd";
+	reg = <0x8a20000 0x1000>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x0 0x8a20000 0x1000>;
+
+	usb2_phy1: phy@120 {
+		compatible = "hisilicon,hi3798cv200-usb2-phy";
+		reg = <0x120 0x4>;
+		#phy-cells = <1>;
+		clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
+		resets = <&crg 0xbc 4>,
+			 <&crg 0xbc 8>,
+			 <&crg 0xbc 9>;
+		reset-names = "power_on", "utmi0", "utmi1";
+	};
+
+	usb2_phy2: phy@124 {
+		compatible = "hisilicon,hi3798cv200-usb2-phy";
+		reg = <0x124 0x4>;
+		#phy-cells = <1>;
+		clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
+		resets = <&crg 0xbc 6>,
+			 <&crg 0xbc 10>;
+		reset-names = "power_on", "utmi0";
+	};
+};
-- 
1.9.1

Re: [PATCH v3 1/2] dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY

[Kishon Vijay Abraham I]

On Thursday 01 March 2018 12:52 PM, Shawn Guo wrote:
> From: Pengcheng Li <lpc.li@hisilicon.com>
> 
> It adds device tree bindings document for HiSilicon INNO USB2 PHY.
> 
> Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
>  .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 52 ++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> new file mode 100644
> index 000000000000..b563cf54ca7b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> @@ -0,0 +1,52 @@
> +HiSilicon INNO USB2 PHY
> +
> +Required properties:
> +- compatible: Should be one of the following strings:
> +	"hisilicon,inno-usb2-phy",
> +	"hisilicon,hi3798cv200-usb2-phy".
> +- reg: Should be the address space for PHY configuration register in peripheral
> +  controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798cv200 SoC.
> +- #phy-cells: Should be 1. The specifier is the index of the PHY port to
> +  reference.

This can be '0' if the consumers directly use phandle to the subnodes.

Thanks
Kishon

Re: [PATCH v3 1/2] dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY

[Kishon Vijay Abraham I]

On Thursday 01 March 2018 12:52 PM, Shawn Guo wrote:
> From: Pengcheng Li <lpc.li@hisilicon.com>
> 
> It adds device tree bindings document for HiSilicon INNO USB2 PHY.
> 
> Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> ---
>  .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 52 ++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> new file mode 100644
> index 000000000000..b563cf54ca7b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> @@ -0,0 +1,52 @@
> +HiSilicon INNO USB2 PHY
> +
> +Required properties:
> +- compatible: Should be one of the following strings:
> +	"hisilicon,inno-usb2-phy",
> +	"hisilicon,hi3798cv200-usb2-phy".
> +- reg: Should be the address space for PHY configuration register in peripheral
> +  controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798cv200 SoC.
> +- #phy-cells: Should be 1. The specifier is the index of the PHY port to
> +  reference.

This can be '0' if the consumers directly use phandle to the subnodes.

Thanks
Kishon

Re: [PATCH v3 1/2] dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY

[Shawn Guo]

Hi Kishon,

On Fri, Mar 02, 2018 at 11:55:57AM +0530, Kishon Vijay Abraham I wrote:
> On Thursday 01 March 2018 12:52 PM, Shawn Guo wrote:
> > From: Pengcheng Li <lpc.li@hisilicon.com>
> > 
> > It adds device tree bindings document for HiSilicon INNO USB2 PHY.
> > 
> > Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
> > Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
> > Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> > ---
> >  .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 52 ++++++++++++++++++++++
> >  1 file changed, 52 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> > new file mode 100644
> > index 000000000000..b563cf54ca7b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> > @@ -0,0 +1,52 @@
> > +HiSilicon INNO USB2 PHY
> > +
> > +Required properties:
> > +- compatible: Should be one of the following strings:
> > +	"hisilicon,inno-usb2-phy",
> > +	"hisilicon,hi3798cv200-usb2-phy".
> > +- reg: Should be the address space for PHY configuration register in peripheral
> > +  controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798cv200 SoC.
> > +- #phy-cells: Should be 1. The specifier is the index of the PHY port to
> > +  reference.
> 
> This can be '0' if the consumers directly use phandle to the subnodes.

Yes, I understand that for most of PHY devices #phy-cells is just 0, and
consumers simply use the phandle without any cell number.  But for this
inno-usb2-phy, every single device contains two PHY ports, and each port
can be connected to different USB controller.  That said, for each
inno-usb2-phy device, we need to create two phy devices and register
them to PHY core system.  And the phy-cell number is used by consumers
to specify the PHY port id.

Shawn

Re: [PATCH v3 1/2] dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY

[Kishon Vijay Abraham I]

Hi,

On Friday 02 March 2018 01:07 PM, Shawn Guo wrote:
> Hi Kishon,
> 
> On Fri, Mar 02, 2018 at 11:55:57AM +0530, Kishon Vijay Abraham I wrote:
>> On Thursday 01 March 2018 12:52 PM, Shawn Guo wrote:
>>> From: Pengcheng Li <lpc.li@hisilicon.com>
>>>
>>> It adds device tree bindings document for HiSilicon INNO USB2 PHY.
>>>
>>> Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
>>> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
>>> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
>>> ---
>>>  .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 52 ++++++++++++++++++++++
>>>  1 file changed, 52 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
>>> new file mode 100644
>>> index 000000000000..b563cf54ca7b
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
>>> @@ -0,0 +1,52 @@
>>> +HiSilicon INNO USB2 PHY
>>> +
>>> +Required properties:
>>> +- compatible: Should be one of the following strings:
>>> +	"hisilicon,inno-usb2-phy",
>>> +	"hisilicon,hi3798cv200-usb2-phy".
>>> +- reg: Should be the address space for PHY configuration register in peripheral
>>> +  controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798cv200 SoC.
>>> +- #phy-cells: Should be 1. The specifier is the index of the PHY port to
>>> +  reference.
>>
>> This can be '0' if the consumers directly use phandle to the subnodes.
> 
> Yes, I understand that for most of PHY devices #phy-cells is just 0, and
> consumers simply use the phandle without any cell number.  But for this
> inno-usb2-phy, every single device contains two PHY ports, and each port

Why not have a separate sub-node for each phy port? Then you can just use
phandle to the subnode in the controller node.

Thanks
Kishon

Re: [PATCH v3 1/2] dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY

[Kishon Vijay Abraham I]

Hi,

On Friday 02 March 2018 01:07 PM, Shawn Guo wrote:
> Hi Kishon,
> 
> On Fri, Mar 02, 2018 at 11:55:57AM +0530, Kishon Vijay Abraham I wrote:
>> On Thursday 01 March 2018 12:52 PM, Shawn Guo wrote:
>>> From: Pengcheng Li <lpc.li@hisilicon.com>
>>>
>>> It adds device tree bindings document for HiSilicon INNO USB2 PHY.
>>>
>>> Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
>>> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
>>> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
>>> ---
>>>  .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 52 ++++++++++++++++++++++
>>>  1 file changed, 52 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
>>> new file mode 100644
>>> index 000000000000..b563cf54ca7b
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
>>> @@ -0,0 +1,52 @@
>>> +HiSilicon INNO USB2 PHY
>>> +
>>> +Required properties:
>>> +- compatible: Should be one of the following strings:
>>> +	"hisilicon,inno-usb2-phy",
>>> +	"hisilicon,hi3798cv200-usb2-phy".
>>> +- reg: Should be the address space for PHY configuration register in peripheral
>>> +  controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798cv200 SoC.
>>> +- #phy-cells: Should be 1. The specifier is the index of the PHY port to
>>> +  reference.
>>
>> This can be '0' if the consumers directly use phandle to the subnodes.
> 
> Yes, I understand that for most of PHY devices #phy-cells is just 0, and
> consumers simply use the phandle without any cell number.  But for this
> inno-usb2-phy, every single device contains two PHY ports, and each port

Why not have a separate sub-node for each phy port? Then you can just use
phandle to the subnode in the controller node.

Thanks
Kishon

Re: [PATCH v3 1/2] dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY

[Shawn Guo]

On Fri, Mar 02, 2018 at 01:35:43PM +0530, Kishon Vijay Abraham I wrote:
> >>> diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> >>> new file mode 100644
> >>> index 000000000000..b563cf54ca7b
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt
> >>> @@ -0,0 +1,52 @@
> >>> +HiSilicon INNO USB2 PHY
> >>> +
> >>> +Required properties:
> >>> +- compatible: Should be one of the following strings:
> >>> +	"hisilicon,inno-usb2-phy",
> >>> +	"hisilicon,hi3798cv200-usb2-phy".
> >>> +- reg: Should be the address space for PHY configuration register in peripheral
> >>> +  controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798cv200 SoC.
> >>> +- #phy-cells: Should be 1. The specifier is the index of the PHY port to
> >>> +  reference.
> >>
> >> This can be '0' if the consumers directly use phandle to the subnodes.
> > 
> > Yes, I understand that for most of PHY devices #phy-cells is just 0, and
> > consumers simply use the phandle without any cell number.  But for this
> > inno-usb2-phy, every single device contains two PHY ports, and each port
> 
> Why not have a separate sub-node for each phy port? Then you can just use
> phandle to the subnode in the controller node.

It sounds like a sensible suggestion.  I will try to implement that and
see how it goes.  Thanks.

Shawn

[PATCH v3 2/2] phy: add inno-usb2-phy driver for hi3798cv200 SoC

[Shawn Guo]

From: Pengcheng Li <lpc.li@hisilicon.com>

It adds inno-usb2-phy driver for hi3798cv200 SoC USB 2.0 support.  One
inno-usb2-phy device can support up to two PHY ports.  While there is
device level reference clock and power reset to be controlled, each PHY
port has its own utmi reset that needs to assert/de-assert as needed.

Hi3798cv200 needs to access PHY port0 register via particular peripheral
syscon controller register to control PHY, like turning on PHY clock.

Signed-off-by: Pengcheng Li <lpc.li@hisilicon.com>
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
 drivers/phy/hisilicon/Kconfig              |  10 ++
 drivers/phy/hisilicon/Makefile             |   1 +
 drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 218 +++++++++++++++++++++++++++++
 3 files changed, 229 insertions(+)
 create mode 100644 drivers/phy/hisilicon/phy-hisi-inno-usb2.c

diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig
index 6164c4cd0f65..c21470eb7fba 100644
--- a/drivers/phy/hisilicon/Kconfig
+++ b/drivers/phy/hisilicon/Kconfig
@@ -11,6 +11,16 @@ config PHY_HI6220_USB
 
 	  To compile this driver as a module, choose M here.
 
+config PHY_HISI_INNO_USB2
+       tristate "HiSilicon INNO USB2 PHY support"
+       depends on (ARCH_HISI && ARM64) || COMPILE_TEST
+       select GENERIC_PHY
+       select MFD_SYSCON
+       help
+         Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports
+         USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It supports one
+         USB host port to accept one USB device.
+
 config PHY_HIX5HD2_SATA
 	tristate "HIX5HD2 SATA PHY Driver"
 	depends on ARCH_HIX5HD2 && OF && HAS_IOMEM
diff --git a/drivers/phy/hisilicon/Makefile b/drivers/phy/hisilicon/Makefile
index 541b348187a8..e6c979458d3b 100644
--- a/drivers/phy/hisilicon/Makefile
+++ b/drivers/phy/hisilicon/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_PHY_HI6220_USB)		+= phy-hi6220-usb.o
+obj-$(CONFIG_PHY_HISI_INNO_USB2)	+= phy-hisi-inno-usb2.o
 obj-$(CONFIG_PHY_HIX5HD2_SATA)		+= phy-hix5hd2-sata.o
diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
new file mode 100644
index 000000000000..4b6b6fd43682
--- /dev/null
+++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
@@ -0,0 +1,218 @@
+/*
+ * HiSilicon INNO USB2 PHY Driver.
+ *
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/reset.h>
+
+#define INNO_PHY_PORT_NUM	2
+#define REF_CLK_STABLE_TIME	100	/* unit:us */
+#define UTMI_CLK_STABLE_TIME	200	/* unit:us */
+#define TEST_CLK_STABLE_TIME	2	/* unit:ms */
+#define PHY_CLK_STABLE_TIME	2	/* unit:ms */
+#define UTMI_RST_COMPLETE_TIME	2	/* unit:ms */
+#define POR_RST_COMPLETE_TIME	300	/* unit:us */
+#define PHY_TEST_DATA		GENMASK(7, 0)
+#define PHY_TEST_ADDR		GENMASK(15, 8)
+#define PHY_TEST_PORT		GENMASK(18, 16)
+#define PHY_TEST_WREN		BIT(21)
+#define PHY_TEST_CLK		BIT(22)	/* rising edge active */
+#define PHY_TEST_RST		BIT(23)	/* low active */
+#define PHY_CLK_ENABLE		BIT(2)
+
+struct hisi_inno_phy_port {
+	struct phy *phy;
+	struct device *dev;
+	struct reset_control *utmi_rst;
+};
+
+struct hisi_inno_phy_priv {
+	void __iomem *mmio;
+	struct clk *ref_clk;
+	struct reset_control *por_rst;
+	struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM];
+	u32 port_num;
+};
+
+static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv,
+				    u8 port, u32 addr, u32 data)
+{
+	void __iomem *reg = priv->mmio;
+	u32 val;
+
+	val = (data & PHY_TEST_DATA) |
+	      ((addr << 8) & PHY_TEST_ADDR) |
+	      ((port << 16) & PHY_TEST_PORT) |
+	      PHY_TEST_WREN | PHY_TEST_RST;
+	writel(val, reg);
+
+	val |= PHY_TEST_CLK;
+	writel(val, reg);
+
+	val &= ~PHY_TEST_CLK;
+	writel(val, reg);
+}
+
+static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
+{
+	/* The phy clk is controlled by the port0 register 0x06. */
+	hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE);
+	msleep(PHY_CLK_STABLE_TIME);
+}
+
+static int hisi_inno_phy_init(struct phy *phy)
+{
+	struct hisi_inno_phy_port *port = phy_get_drvdata(phy);
+	struct hisi_inno_phy_priv *priv = dev_get_drvdata(port->dev);
+	int ret;
+
+	ret = clk_prepare_enable(priv->ref_clk);
+	if (ret)
+		return ret;
+	udelay(REF_CLK_STABLE_TIME);
+
+	reset_control_deassert(priv->por_rst);
+	udelay(POR_RST_COMPLETE_TIME);
+
+	/* Set up phy registers */
+	hisi_inno_phy_setup(priv);
+
+	reset_control_deassert(port->utmi_rst);
+	udelay(UTMI_RST_COMPLETE_TIME);
+
+	return 0;
+}
+
+static int hisi_inno_phy_exit(struct phy *phy)
+{
+	struct hisi_inno_phy_port *port = phy_get_drvdata(phy);
+	struct hisi_inno_phy_priv *priv = dev_get_drvdata(port->dev);
+
+	reset_control_assert(port->utmi_rst);
+	reset_control_assert(priv->por_rst);
+	clk_disable_unprepare(priv->ref_clk);
+
+	return 0;
+}
+
+static const struct phy_ops hisi_inno_phy_ops = {
+	.init = hisi_inno_phy_init,
+	.exit = hisi_inno_phy_exit,
+	.owner = THIS_MODULE,
+};
+
+static struct phy *hisi_inno_phy_xlate(struct device *dev,
+				       struct of_phandle_args *args)
+{
+	struct hisi_inno_phy_priv *priv = dev_get_drvdata(dev);
+	int id = args->args[0];
+
+	if (id >= priv->port_num)
+		return ERR_PTR(-ENODEV);
+
+	return priv->ports[id].phy;
+}
+
+static int hisi_inno_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct hisi_inno_phy_priv *priv;
+	struct phy_provider *provider;
+	struct resource *res;
+	int ret, i;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->mmio = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->mmio)) {
+		ret = PTR_ERR(priv->mmio);
+		return ret;
+	}
+
+	priv->ref_clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->ref_clk))
+		return PTR_ERR(priv->ref_clk);
+
+	priv->port_num = of_count_phandle_with_args(np, "resets",
+						    "#reset-cells");
+	/* Do not count power_on reset */
+	priv->port_num--;
+
+	if (priv->port_num <= 0 || priv->port_num > INNO_PHY_PORT_NUM) {
+		dev_err(dev, "Invalid port number %d\n", priv->port_num);
+		return -EINVAL;
+	}
+
+	priv->por_rst = devm_reset_control_get_shared(dev, "power_on");
+	if (IS_ERR(priv->por_rst))
+		return PTR_ERR(priv->por_rst);
+
+	for (i = 0; i < priv->port_num; i++) {
+		struct reset_control *rst;
+		struct phy *phy;
+		char id[6];
+
+		snprintf(id, 6, "utmi%1d", i);
+		rst = devm_reset_control_get_exclusive(dev, id);
+		if (IS_ERR(rst))
+			return PTR_ERR(rst);
+		priv->ports[i].utmi_rst = rst;
+
+		phy = devm_phy_create(dev, NULL, &hisi_inno_phy_ops);
+		if (IS_ERR(phy))
+			return PTR_ERR(phy);
+
+		priv->ports[i].phy = phy;
+		priv->ports[i].dev = dev;
+		phy_set_bus_width(phy, 8);
+		phy_set_drvdata(phy, &priv->ports[i]);
+	}
+
+	dev_set_drvdata(dev, priv);
+
+	provider = devm_of_phy_provider_register(dev, hisi_inno_phy_xlate);
+	return PTR_ERR_OR_ZERO(provider);
+}
+
+static const struct of_device_id hisi_inno_phy_of_match[] = {
+	{ .compatible = "hisilicon,inno-usb2-phy", },
+	{ .compatible = "hisilicon,hi3798cv200-usb2-phy", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match);
+
+static struct platform_driver hisi_inno_phy_driver = {
+	.probe	= hisi_inno_phy_probe,
+	.driver = {
+		.name	= "hisi-inno-phy",
+		.of_match_table	= hisi_inno_phy_of_match,
+	}
+};
+module_platform_driver(hisi_inno_phy_driver);
+
+MODULE_DESCRIPTION("HiSilicon INNO USB2 PHY Driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1